JP4880199B2 - トレンチのエッチングおよび反対にドープされたポリシリコンの領域からの拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力mosfet - Google Patents
トレンチのエッチングおよび反対にドープされたポリシリコンの領域からの拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力mosfet Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 56
- 229920005591 polysilicon Polymers 0.000 title claims description 54
- 238000009792 diffusion process Methods 0.000 title claims description 13
- 238000005530 etching Methods 0.000 title claims description 11
- 239000002019 doping agent Substances 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 34
- 210000000746 body region Anatomy 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 9
- 230000000873 masking effect Effects 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 239000012808 vapor phase Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
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Description
本発明によれば、電力半導体装置を形成する方法が提供される。本方法では、最初に第1または第2の導電型の基板が設けられ、続いて、基板上に電圧維持領域が形成される。電圧維持領域は、基板上に第1の導電型のエピタキシャル層が堆積され、少なくとも1つのトレンチがエピタキシャル層に形成されることで形成される。第2の導電型の第2のドーパントを有するポリシリコンの第1の層がトレンチに堆積される。第2のドーパントが拡散されてトレンチに隣接し、エピタキシャル層においてドープエピタキシャル領域を形成する。第1の導電型の第1のドーパントを有するポリシリコンの第2の層がその後トレンチに堆積される。ポリシリコンの第1および第2の層において電気的補償を実現するようポリシリコンの第2および第1の層にそれぞれ位置する第1および第2のドーパントが相互に拡散される。最後に、間に接合を画定するよう第2の導電型の少なくとも1つの領域が電圧維持領域上に形成される。
Claims (46)
- 電力半導体装置を形成する方法であって、
A.第1又は第2の導電型の基板を用意する工程と;
B.
1.前記基板上に前記第1の導電型を有するエピタキシャル層を堆積し、
2.前記エピタキシャル層に少なくとも1つのトレンチを形成し、
3.前記第2の導電型の第2のドーパントを有する材料の第1の層を前記トレンチに堆積し、
4.前記第2のドーパントを拡散して前記トレンチに隣接し、前記エピタキシャル層においてドープエピタキシャル領域を形成し、
5.前記第1の導電型の第1のドーパントを有する材料の第2の層を前記トレンチに堆積し、
6.前記材料の第2および第1の層にそれぞれ位置する前記第1および第2のドーパントを相互拡散して前記材料の第1および第2の層において前記材料の第1および第2の層において電荷の中立性を実質的に実現するように電気的補償を行う、
工程によって前記基板上の前記エピタキシャルの一部分内に電圧維持領域を形成する工程と;
C.接合を間に画成するよう前記電圧維持領域上に第2の導電型の少なくとも1つの領域を形成する工程と;
を備える方法。 - 前記電気的補償は、前記材料の第1および第2の層において電荷の中立性を実質的に実現するに十分である、請求項1記載の方法。
- 前記第2の層は前記トレンチを実質的に充填する、請求項1記載の方法。
- 前記工程Cは、
ドリフト領域を間に画成するよう前記エピタキシャル層に、第2の導電型を有する第1および第2のボディ領域を形成する工程と、
前記第1および第2のボディ領域の上方のゲート誘電体領域の上にゲート電極を形成する工程と、
前記第1および前記第2のボディ領域それぞれに前記第1の導電型の第1および第2のソース領域を形成する工程とを更に備える請求項1記載の方法。 - 前記第2のドーパントはホウ素である、請求項1記載の方法。
- 前記第1のドーパントはリンを含む、請求項1記載の方法。
- 前記第1のドーパントはヒ素を含む、請求項1記載の方法。
- 前記第1のドーパントはリンおよびヒ素を含む、請求項1記載の方法。
- 前記ボディ領域は深いボディ領域を含む、請求項4記載の方法。
- 前記トレンチは、少なくとも1つのトレンチを画成するマスキング層を設け、前記マスキング層によって画成された前記トレンチをエッチングすることで形成される、請求項1記載の方法。
- 前記ボディ領域は前記基板にドーパントを注入し拡散することで形成される、請求項4記載の方法。
- 前記電力半導体装置は、縦型DMOS、V溝DMOSおよびトレンチDMOS MOSFET、IGBT、ダイオード、および、バイポーラトランジスタからなる群から選択される、請求項1記載の方法。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項1記載の方法。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項2記載の方法。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項3記載の方法。
- 前記材料の第1のおよび第2の層は、ポリシリコンの層である、請求項4記載の方法。
- 前記ドープエピタキシャル領域の電荷を調節するよう前記第1のドーパントの一部分を前記ドープエピタキシャル領域中に拡散する工程を更に備える、請求項1記載の方法。
- 請求項1記載の方法により形成される電力半導体装置。
- 請求項16記載の方法により形成される電力半導体装置。
- 請求項12記載の方法により形成される電力半導体装置。
- 第1又は第2の導電型の基板と、
前記基板上に配置される電圧維持領域とを備え、
前記電圧維持領域は、
第1の導電型を有するエピタキシャル層と、
前記エピタキシャル層に位置する少なくとも1つのトレンチと、
前記トレンチに位置する材料の第1の層と、
ポリシリコンの前記第1の層の上に位置する材料の第2の層と、
前記トレンチに隣接し前記エピタキシャル層に位置する少なくとも1つのドープカラムであって、前記少なくとも1つのドープカラムが前記第2の導電型のドーパントを有し、前記少なくとも1つのドープカラムが前記材料の第1の層から前記エピタキシャル層への前記第2の導電型のドーパントの拡散によって形成される、ドープカラムと、
接合を間に画成するよう前記電圧維持領域上に形成される前記第2の導電型の少なくとも1つの領域をと含み、前記基板上の前記エピタキシャルの一部分内に前記電圧維持領域が形成され、前記材料の第1のおよび第2の層は実質的に電気的に中立であり、前記材料の第1および第2の層において電気的中立性を実現するよう前記第2の層から前記第1の層に拡散される前記第1の導電型のドーパントを更に備える、電力半導体装置。 - 前記第1の導電型のドーパントはヒ素を含む、請求項21記載の装置。
- 前記第1の導電型のドーパントはリンを含む、請求項21記載の装置。
- 前記第1の導電型のドーパントはリンおよびヒ素を含む、請求項21記載の装置。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項21記載の装置。
- 電力半導体装置を形成する方法であって、
A.第1又は第2の導電型の基板を用意する工程と;
B.
1.前記基板上に第1の導電型を有するエピタキシャル層を堆積し、
2.前記エピタキシャル層に少なくとも1つのトレンチを形成し、
3.前記第2の導電型の第2のドーパントを有する材料の第1の層を前記トレンチに形成し、
4.前記第2のドーパントを拡散して前記トレンチに隣接し、前記エピタキシャル層中にドープエピタキシャル領域を形成し、
5.前記第1の導電型の第1のドーパントを有する材料の第2の層を前記トレンチに形成し、
6.前記材料の第1のおよび第2の層において電気的補償を実現するよう前記材料の第2のおよび第1の層にそれぞれ位置する前記第1および第2のドーパントを相互拡散する、
工程によって前記基板上の前記エピタキシャルの一部分内に電圧維持領域を形成する工程と;
C.接合を間に画成するよう前記電圧維持領域上に第2の導電型の少なくとも1つの領域を形成する工程と;
を備える方法。 - 前記電気的補償は、前記材料の第1のおよび第2の層において電荷の中立性を実質的に実現するに十分である、請求項26記載の方法。
- 前記第2の層は前記トレンチを実質的に充填する、請求項26記載の方法。
- 前記工程Cは、
ドリフト領域を間に画成するよう前記エピタキシャル層に第2の導電型を有する第1のおよび第2のボディ領域を形成する工程と、
前記第1および第2のボディ領域の上方のゲート誘電体領域の上にゲート電極を形成する工程と、
前記第1および前記第2のボディ領域それぞれに前記第1の導電型の第1および第2のソース領域を形成する工程とを更に含む請求項26記載の方法。 - 前記第2のドーパントはホウ素である、請求項26記載の方法。
- 前記第1のドーパントはリンを含む、請求項26記載の方法。
- 前記第1のドーパントはヒ素を含む、請求項26記載の方法。
- 前記第1のドーパントはリンおよびヒ素を含む、請求項26記載の方法。
- 前記ボディ領域は深いボディ領域を含む、請求項29記載の方法。
- 前記トレンチは、少なくとも1つのトレンチを画成するマスキング層を設け、前記マスキング層によって画成される前記トレンチをエッチングすることで形成される、請求項26記載の方法。
- 前記ボディ領域は前記基板にドーパントを注入し拡散することで形成される、請求項29記載の方法。
- 前記電力半導体装置は、縦型DMOS、V溝DMOSおよびトレンチDMOS MOSFET、IGBT、ダイオード、および、バイポーラトランジスタからなる群から選択される、請求項26記載の方法。
- 前記材料の第1の層を設ける工程は、材料の第1の層を堆積し、気相ドーピングを用いて前記第2のドーパントで前記材料の第1の層をドーピングする工程を含む、請求項26記載の方法。
- 前記材料の第2の層を設ける工程は、材料の第2の層を堆積し、気相ドーピングを用いて前記第1のドーパントで前記材料の第2の層をドーピングする工程を含む、請求項26記載の方法。
- 前記トレンチを誘電体材料で充填する工程を更に備える、請求項39記載の方法。
- 前記トレンチをノンドープのポリシリコンで充填する工程を更に備える請求項39記載の方法。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項38記載の方法。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項39記載の方法。
- 前記材料の第1および第2の層は、ポリシリコンの層である、請求項40記載の方法。
- 前記ドープエピタキシャル領域の電荷を調節するよう前記第1のドーパントの一部分を前記ドープエピタキシャル領域に拡散する工程を更に備える請求項26記載の方法。
- 電力半導体装置を形成する方法であって、
A.第1又は第2の導電型の基板を用意する工程と;
B.
1.前記基板上に第1の導電型を有するエピタキシャル層を堆積し、
2.前記エピタキシャル層に少なくとも1つのトレンチを形成し、
3.前記第2の導電型の第2のドーパントを有する材料の第1の層を前記トレンチに
設け、
4.前記第2のドーパントを拡散して前記トレンチに隣接し、前記エピタキシャル層中にドープエピタキシャル領域を形成し、
5.前記材料の第1の層に前記第1の導電型の第1のドーパントを拡散して、前記材料の第1の層において電荷の中立性を実質的に実現するように電気的補償を行う、
工程によって前記基板上に電圧維持領域を形成する工程と;
C.前記電圧維持領域上に第2の導電型の少なくとも1つの領域を形成して接合を間に画成する工程と;
を備える方法。
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US10/039,241 | 2001-12-31 | ||
US10/039,241 US6576516B1 (en) | 2001-12-31 | 2001-12-31 | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon |
PCT/US2002/041809 WO2003058684A2 (en) | 2001-12-31 | 2002-12-30 | High voltage power mosfet having a voltage sustaining region and diffusion from regions of oppositely doped polysilicon |
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JP4880199B2 true JP4880199B2 (ja) | 2012-02-22 |
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US (3) | US6576516B1 (ja) |
EP (1) | EP1476894B1 (ja) |
JP (1) | JP4880199B2 (ja) |
KR (1) | KR100952538B1 (ja) |
CN (1) | CN100355086C (ja) |
AU (1) | AU2002359889A1 (ja) |
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JP2003536261A (ja) * | 2000-06-02 | 2003-12-02 | ゼネラル セミコンダクター,インク. | パワー金属酸化膜半導体電界効果トランジスタの製造方法 |
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EP1476894A2 (en) | 2004-11-17 |
KR20040069213A (ko) | 2004-08-04 |
CN1610974A (zh) | 2005-04-27 |
WO2003058684A3 (en) | 2003-10-02 |
WO2003058684A2 (en) | 2003-07-17 |
US20050042830A1 (en) | 2005-02-24 |
CN100355086C (zh) | 2007-12-12 |
KR100952538B1 (ko) | 2010-04-12 |
US6794251B2 (en) | 2004-09-21 |
EP1476894A4 (en) | 2009-02-18 |
US20030203552A1 (en) | 2003-10-30 |
AU2002359889A1 (en) | 2003-07-24 |
TW200302575A (en) | 2003-08-01 |
TWI270208B (en) | 2007-01-01 |
JP2005514787A (ja) | 2005-05-19 |
US6576516B1 (en) | 2003-06-10 |
US7224027B2 (en) | 2007-05-29 |
EP1476894B1 (en) | 2016-06-22 |
AU2002359889A8 (en) | 2003-07-24 |
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