JP4786872B2 - 単一のイオン注入工程によって形成されたドープされたコラムを含む電圧維持領域を有するパワー半導体デバイス及びそれらの製造方法 - Google Patents
単一のイオン注入工程によって形成されたドープされたコラムを含む電圧維持領域を有するパワー半導体デバイス及びそれらの製造方法 Download PDFInfo
- Publication number
- JP4786872B2 JP4786872B2 JP2003579265A JP2003579265A JP4786872B2 JP 4786872 B2 JP4786872 B2 JP 4786872B2 JP 2003579265 A JP2003579265 A JP 2003579265A JP 2003579265 A JP2003579265 A JP 2003579265A JP 4786872 B2 JP4786872 B2 JP 4786872B2
- Authority
- JP
- Japan
- Prior art keywords
- trench
- power device
- semiconductor power
- region
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 62
- 238000000034 method Methods 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 230000008569 process Effects 0.000 title description 20
- 238000005468 ion implantation Methods 0.000 title description 9
- 210000000746 body region Anatomy 0.000 claims description 39
- 239000012535 impurity Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 238000012423 maintenance Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 239000000945 filler Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (32)
- A.第1の伝導型の基板を準備する工程と、
B.1.上記基板上に、第1の伝導型又は第2の伝導型のエピタキシャル層を成長させる工程と、
2.上記エピタキシャル層内に、最下層の部分がトレンチ底面を画定し、隣接する部分の間にそれぞれ1つの環状の棚を画定し、それぞれ幅が異なる、当該雛壇状のトレンチを形成する複数の部分を有する少なくとも1つの雛壇状のトレンチを形成する工程と、
3.上記雛壇状のトレンチの壁、上記環状の棚及び上記トレンチ底面に沿ってバリア材を堆積させる工程と、
4.上記エピタキシャル層とは逆の伝導型の不純物を、上記環状の棚及び上記トレンチ底面に堆積されたバリア層を通して、該エピタキシャル層の上記雛壇状のトレンチに隣接した領域にイオン注入して、少なくとも1つの環状のドープ領域及び他のドープ領域を形成する工程と、
5.上記少なくとも1つの環状のドープ領域及び他のドープ領域で上記不純物を拡散させて、該環状のドープ領域と該他のドープ領域とが互いに重なり合うようにし、上記エピタキシャル層内に連続してドープされたコラムを形成する工程と、
6.上記雛壇状のトレンチにフィラ材料を堆積して、該雛壇状のトレンチを埋め込む工程とによって、上記基板上に電圧維持領域を形成する工程と、
C.上記電圧維持領域上に、上記エピタキシャル層の伝導型とは逆の伝導型の少なくとも1つの領域を形成して、該領域と該エピタキシャル層との間に接合を画定する工程とを有する半導体パワーデバイスの製造方法。 - 上記少なくとも1つの雛壇状のトレンチを形成する工程は、上記雛壇状のトレンチの複数の部分のうちの最も幅広の部分から最も幅狭の部分の順に、該雛壇状のトレンチの複数の部分を順次エッチングする工程を有することを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記最も幅狭の部分は、上記エピタキシャル層内において、上記最も幅広の部分よりも上記基板に近い深さに位置することを特徴とする請求項2記載の半導体パワーデバイスの製造方法。
- 上記雛壇状のトレンチの複数の部分は、互いに共通の中心軸を有するように配置されていることを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記工程Cは、
ゲート誘電体領域上にゲート導電層を形成する工程と、
上記エピタキシャル層内に、該エピタキシャル層とは逆の伝導型の第1及び第2のボディ領域を形成して、該第1及び第2のボディ領域間にドリフト領域を画定する工程と、
上記第1及び第2のボディ領域内に、上記エピタキシャル層と同じ伝導型の第1及び第2のソース領域をそれぞれ形成する工程とを更に有することを特徴とする請求項1記載の半導体パワーデバイスの製造方法。 - 上記バリア材は、酸化物材料であることを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記酸化物材料は、二酸化シリコンであることを特徴とする請求項6記載の半導体パワーデバイスの製造方法。
- xを上記電圧維持領域に形成する環状のドープ領域の所定の数として、上記エピタキシャル層のうち、上記接合と、該エピタキシャル層の上記基板面との所定の距離の1/(x+1)だけ上記雛壇状のトレンチの第1の部分をエッチングする工程を更に有し、
上記所定の数の環状のドープ領域は、全体で上記連続してドープされたコラムを画定することを特徴とする請求項1記載の半導体パワーデバイスの製造方法。 - 上記雛壇状のトレンチに埋め込む材料は、誘電体材料であることを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記誘電体材料は、二酸化シリコンであることを特徴とする請求項9記載の半導体パワーデバイスの製造方法。
- 上記誘電体材料は、窒化シリコンであることを特徴とする請求項9記載の半導体パワーデバイスの製造方法。
- 上記不純物は、ホウ素であることを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記ボディ領域は、深いボディ領域を有することを特徴とする請求項5記載の半導体パワーデバイスの製造方法。
- 上記雛壇状のトレンチは、該雛壇状のトレンチの複数の部分のうちの第1の部分を画定するマスク層を設け、該マスク層によって画定される該雛壇状のトレンチの第1の部分をエッチングすることによって形成されることを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記雛壇状のトレンチの第1の部分の壁に沿って、所定の厚さの酸化物層を堆積させる工程を更に有する請求項14記載の半導体パワーデバイスの製造方法。
- 上記酸化物層は、第2のマスク層として機能し、
上記雛壇状のトレンチは、該雛壇状のトレンチの第1の部分の底面を貫通して、上記第2のマスク層によって画定される該雛壇状のトレンチの第2の部分をエッチングすることによって形成される工程を更に有する請求項15記載の半導体パワーデバイスの製造方法。 - 上記酸化物層の所定の厚さは、上記環状の棚の表面積と、上記トレンチ底面の表面積とが互いに等しくなるように選択されることを特徴とする請求項16記載の半導体パワーデバイスの製造方法。
- 上記ボディ領域は、上記基板に不純物を注入して、拡散させることによって形成されることを特徴とする請求項5記載の半導体パワーデバイスの製造方法。
- 上記半導体パワーデバイスは、縦型二重拡散金属酸化膜半導体、V溝二重拡散金属酸化膜半導体、トレンチ二重拡散金属酸化膜半導体電界効果トランジスタ、絶縁ゲートバイポーラトランジスタ及びバイポーラトランジスタからなるグループから選択されることを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 上記各棚は、上記トレンチ底面の面積に等しい面積を有し、隣り合う棚間の距離は、該トレンチ底面と、最下位の棚との間の距離に等しいことを特徴とする請求項1記載の半導体パワーデバイスの製造方法。
- 第1の伝導型の基板と、
上記基板上に形成された電圧維持領域とを備え、
上記電圧維持領域は、
第1の伝導型又は第2の伝導型のエピタキシャル層と、
上記エピタキシャル層内に位置し、最下層の部分がトレンチ底面を画定し、隣接する部分の間にそれぞれ1つの環状の棚を画定し、それぞれ幅が異なる、当該雛壇状のトレンチを形成する複数の部分を有する少なくとも1つの雛壇状のトレンチと、
上記エピタキシャル層内の上記環状の棚及び上記トレンチ底面の下方に及びこれらに隣接して位置し、該エピタキシャル層とは逆の伝導型の不純物を含む少なくとも1つの環状のドープ領域及び他のドープ領域から形成された上記エピタキシャル層とは逆の伝導型の不純物を含む、該環状のドープ領域と該他のドープ領域とが互いに重なりあうように形成された少なくとも1つのコラムと、
上記雛壇状のトレンチに埋め込まれたフィラ材料と、
上記エピタキシャル層とは逆の伝導型を有し、上記電圧維持領域上に堆積され、該エピタキシャル層との間に接合を画定する少なくとも1つの活性領域とを有することを特徴とする半導体パワーデバイス。 - 上記雛壇状のトレンチの複数の部分は、上記雛壇状のトレンチの複数の部分のうちの、最も幅狭の部分と、最も幅広の部分とを含み、該最も幅狭の部分は、上記エピタキシャル層内において、該最も幅広の部分よりも上記基板に近い深さに位置することを特徴とする請求項21記載の半導体パワーデバイス。
- 上記雛壇状のトレンチの複数の部分は、互いに共通の中心軸を有するように配置されていることを特徴とする請求項22記載の半導体パワーデバイス。
- xを上記電圧維持領域に形成する環状のドープ領域の所定の数として、上記雛壇状のトレンチは、上記エピタキシャル層のうち、上記接合と、該エピタキシャル層の上記基板面との所定の距離の1/(x+1)だけエッチングされて形成された第1の部分を有することを特徴とする請求項21記載の半導体パワーデバイス。
- 上記トレンチに埋め込む材料は、誘電体材料であることを特徴とする請求項21記載の半導体パワーデバイス。
- 上記誘電体材料は、二酸化シリコンであることを特徴とする請求項25記載の半導体パワーデバイス。
- 上記誘電体材料は、窒化シリコンであることを特徴とする請求項25記載の半導体パワーデバイス。
- 上記不純物は、ホウ素であることを特徴とする請求項21記載の半導体パワーデバイス。
- 上記少なくとも1つの活性領域は、
ゲート誘電体及び該ゲート誘電体上に形成されたゲート導電層と、
上記エピタキシャル層内に位置し、第2の伝導型を有し、それらの間にドリフト領域を画定する第1及び第2のボディ領域と、
上記第1及び第2のボディ領域内にそれぞれ形成された第1及び第2のソース領域とを有することを特徴とする請求項21記載の半導体パワーデバイス。 - 上記ボディ領域は、深いボディ領域を有することを特徴とする請求項29記載の半導体パワーデバイス。
- 上記雛壇状のトレンチは、円形の断面を有することを特徴とする請求項21記載の半導体パワーデバイス。
- 上記雛壇状のトレンチは、正方形、長方形、八角形、及び六角形からなるグループから選択される断面形状を有することを特徴とする請求項21記載の半導体パワーデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/103,674 | 2002-03-21 | ||
US10/103,674 US6686244B2 (en) | 2002-03-21 | 2002-03-21 | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
PCT/US2003/008588 WO2003081642A2 (en) | 2002-03-21 | 2003-03-21 | Power semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005521259A JP2005521259A (ja) | 2005-07-14 |
JP4786872B2 true JP4786872B2 (ja) | 2011-10-05 |
Family
ID=28040452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003579265A Expired - Fee Related JP4786872B2 (ja) | 2002-03-21 | 2003-03-21 | 単一のイオン注入工程によって形成されたドープされたコラムを含む電圧維持領域を有するパワー半導体デバイス及びそれらの製造方法 |
Country Status (6)
Country | Link |
---|---|
US (3) | US6686244B2 (ja) |
EP (1) | EP1485945B1 (ja) |
JP (1) | JP4786872B2 (ja) |
AU (1) | AU2003230699A1 (ja) |
TW (1) | TW200305970A (ja) |
WO (1) | WO2003081642A2 (ja) |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7736976B2 (en) * | 2001-10-04 | 2010-06-15 | Vishay General Semiconductor Llc | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands |
US6649477B2 (en) * | 2001-10-04 | 2003-11-18 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands |
US6686244B2 (en) * | 2002-03-21 | 2004-02-03 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
US7015104B1 (en) | 2003-05-29 | 2006-03-21 | Third Dimension Semiconductor, Inc. | Technique for forming the deep doped columns in superjunction |
US7087472B2 (en) * | 2003-07-18 | 2006-08-08 | Semiconductor Components Industries, L.L.C. | Method of making a vertical compound semiconductor field effect transistor device |
JP4500530B2 (ja) * | 2003-11-05 | 2010-07-14 | トヨタ自動車株式会社 | 絶縁ゲート型半導体装置およびその製造方法 |
DE102004015921B4 (de) * | 2004-03-31 | 2006-06-14 | Infineon Technologies Ag | Rückwärts sperrendes Halbleiterbauelement mit Ladungskompensation |
US7400014B2 (en) * | 2004-04-20 | 2008-07-15 | International Rectifier Corporation | ACCUFET with schottky source contact |
US7465986B2 (en) * | 2004-08-27 | 2008-12-16 | International Rectifier Corporation | Power semiconductor device including insulated source electrodes inside trenches |
JP4491307B2 (ja) * | 2004-09-21 | 2010-06-30 | トヨタ自動車株式会社 | 半導体装置およびその製造方法 |
CN101189710B (zh) * | 2005-04-22 | 2011-05-04 | 艾斯莫斯技术公司 | 具有氧化物衬里沟槽的超结器件和制造具有氧化物衬里沟槽的超结器件的方法 |
US20070012983A1 (en) * | 2005-07-15 | 2007-01-18 | Yang Robert K | Terminations for semiconductor devices with floating vertical series capacitive structures |
US7446018B2 (en) | 2005-08-22 | 2008-11-04 | Icemos Technology Corporation | Bonded-wafer superjunction semiconductor device |
US7554137B2 (en) * | 2005-10-25 | 2009-06-30 | Infineon Technologies Austria Ag | Power semiconductor component with charge compensation structure and method for the fabrication thereof |
US7768064B2 (en) * | 2006-01-05 | 2010-08-03 | Fairchild Semiconductor Corporation | Structure and method for improving shielded gate field effect transistors |
CN100517592C (zh) * | 2006-04-30 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | 改进浅沟槽隔离间隙填充工艺的方法 |
US8659074B2 (en) * | 2007-01-09 | 2014-02-25 | Maxpower Semiconductor, Inc. | Semiconductor device |
US8564057B1 (en) | 2007-01-09 | 2013-10-22 | Maxpower Semiconductor, Inc. | Power devices, structures, components, and methods using lateral drift, fixed net charge, and shield |
US7723172B2 (en) | 2007-04-23 | 2010-05-25 | Icemos Technology Ltd. | Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material |
US8580651B2 (en) * | 2007-04-23 | 2013-11-12 | Icemos Technology Ltd. | Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material |
US20090053869A1 (en) * | 2007-08-22 | 2009-02-26 | Infineon Technologies Austria Ag | Method for producing an integrated circuit including a trench transistor and integrated circuit |
US8012806B2 (en) | 2007-09-28 | 2011-09-06 | Icemos Technology Ltd. | Multi-directional trenching of a die in manufacturing superjunction devices |
EP2081233A1 (de) * | 2007-12-21 | 2009-07-22 | SEMIKRON Elektronik GmbH & Co. KG | Leistungsdiode mit grabenförmigen Anodenkontaktbereich |
CN101510557B (zh) | 2008-01-11 | 2013-08-14 | 艾斯莫斯技术有限公司 | 具有电介质终止的超结半导体器件及制造该器件的方法 |
US7795045B2 (en) * | 2008-02-13 | 2010-09-14 | Icemos Technology Ltd. | Trench depth monitor for semiconductor manufacturing |
US7846821B2 (en) * | 2008-02-13 | 2010-12-07 | Icemos Technology Ltd. | Multi-angle rotation for ion implantation of trenches in superjunction devices |
CN102318045B (zh) * | 2008-02-14 | 2014-08-06 | 马克斯半导体股份有限公司 | 改良式击穿电压的边缘端点 |
JP2011512677A (ja) | 2008-02-14 | 2011-04-21 | マックスパワー・セミコンダクター・インコーポレイテッド | 半導体素子構造及び関連プロセス |
US8030133B2 (en) | 2008-03-28 | 2011-10-04 | Icemos Technology Ltd. | Method of fabricating a bonded wafer substrate for use in MEMS structures |
US7911021B2 (en) * | 2008-06-02 | 2011-03-22 | Maxpower Semiconductor Inc. | Edge termination for semiconductor devices |
US7910439B2 (en) * | 2008-06-11 | 2011-03-22 | Maxpower Semiconductor Inc. | Super self-aligned trench MOSFET devices, methods, and systems |
WO2009154882A2 (en) * | 2008-06-20 | 2009-12-23 | Maxpower Semiconductor Inc. | Semiconductor power switches having trench gates |
US7807576B2 (en) * | 2008-06-20 | 2010-10-05 | Fairchild Semiconductor Corporation | Structure and method for forming a thick bottom dielectric (TBD) for trench-gate devices |
US8829624B2 (en) * | 2008-06-30 | 2014-09-09 | Fairchild Semiconductor Corporation | Power device with monolithically integrated RC snubber |
US8310001B2 (en) | 2008-07-15 | 2012-11-13 | Maxpower Semiconductor Inc. | MOSFET switch with embedded electrostatic charge |
WO2010014281A1 (en) * | 2008-07-30 | 2010-02-04 | Maxpower Semiconductor Inc. | Semiconductor on insulator devices containing permanent charge |
WO2010014283A1 (en) * | 2008-07-30 | 2010-02-04 | Max Power Semiconductor Inc. | Lateral devices containing permanent charge |
US7960783B2 (en) * | 2008-08-25 | 2011-06-14 | Maxpower Semiconductor Inc. | Devices containing permanent charge |
EP2330617A4 (en) | 2008-09-01 | 2012-01-25 | Rohm Co Ltd | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR |
WO2010065428A2 (en) * | 2008-12-01 | 2010-06-10 | Maxpower Semiconductor Inc. | Mos-gated power devices, methods, and integrated circuits |
US7989293B2 (en) * | 2009-02-24 | 2011-08-02 | Maxpower Semiconductor, Inc. | Trench device structure and fabrication |
US8319278B1 (en) | 2009-03-31 | 2012-11-27 | Maxpower Semiconductor, Inc. | Power device structures and methods using empty space zones |
WO2010120704A2 (en) * | 2009-04-13 | 2010-10-21 | Maxpower Semiconductor Inc. | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges |
US8847307B2 (en) | 2010-04-13 | 2014-09-30 | Maxpower Semiconductor, Inc. | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges |
JP2010272758A (ja) * | 2009-05-22 | 2010-12-02 | Hitachi High-Technologies Corp | 被エッチング材のプラズマエッチング方法 |
US20110084332A1 (en) * | 2009-10-08 | 2011-04-14 | Vishay General Semiconductor, Llc. | Trench termination structure |
DE102009060072B4 (de) * | 2009-12-22 | 2017-05-11 | Infineon Technologies Ag | Halbleiterbauelement und Verfahren zu seiner Herstellung |
CN102403256B (zh) * | 2010-09-08 | 2014-02-26 | 上海华虹宏力半导体制造有限公司 | 赝埋层及制造方法、深孔接触及三极管 |
US8629020B2 (en) | 2010-10-25 | 2014-01-14 | Electronics & Telecommunications Research Institute | Semiconductor device and method of fabricating the same |
KR101106535B1 (ko) * | 2011-04-15 | 2012-01-20 | 페어차일드코리아반도체 주식회사 | 전력용 반도체 소자 및 그 제조방법 |
US8680607B2 (en) * | 2011-06-20 | 2014-03-25 | Maxpower Semiconductor, Inc. | Trench gated power device with multiple trench width and its fabrication process |
US8946814B2 (en) | 2012-04-05 | 2015-02-03 | Icemos Technology Ltd. | Superjunction devices having narrow surface layout of terminal structures, buried contact regions and trench gates |
US8765609B2 (en) * | 2012-07-25 | 2014-07-01 | Power Integrations, Inc. | Deposit/etch for tapered oxide |
KR101832334B1 (ko) * | 2013-03-05 | 2018-02-27 | 매그나칩 반도체 유한회사 | 반도체소자 및 그 제조방법 |
US9741851B2 (en) * | 2013-05-13 | 2017-08-22 | Alpha And Omega Semiconductor Incorporated | Trench junction barrier controlled Schottky |
CN104183494B (zh) * | 2013-05-24 | 2017-04-12 | 帅群微电子股份有限公司 | 沟渠式功率金属氧化物半导体结构与其形成方法 |
TWI512887B (zh) * | 2013-05-24 | 2015-12-11 | Super Group Semiconductor Co Ltd | Gutter type power gold - oxygen semiconductor structure and its forming method |
KR101514537B1 (ko) | 2013-08-09 | 2015-04-22 | 삼성전기주식회사 | 전력 반도체 소자 및 그 제조 방법 |
DE102013217768A1 (de) * | 2013-09-05 | 2015-03-05 | Robert Bosch Gmbh | Verfahren zur Herstellung eines Substrats, Substrat, Metall-Oxid-Halbleiter-Feldeffekttransistor mit einem Substrat, mikroelektromechanisches System mit einem Substrat, und Kraftfahrzeug |
JP6563639B2 (ja) * | 2014-11-17 | 2019-08-21 | トヨタ自動車株式会社 | 半導体装置及び半導体装置の製造方法 |
CN109713041B (zh) * | 2018-12-27 | 2022-05-24 | 四川立泰电子有限公司 | 一种适用于超结dmos器件的改良结构 |
DE102019119020A1 (de) * | 2019-07-12 | 2021-01-14 | Infineon Technologies Ag | Siliziumcarbid-vorrichtung mit kompensationsschicht und verfahren zur herstellung |
CN115188804B (zh) * | 2022-09-14 | 2022-11-15 | 江苏长晶科技股份有限公司 | 一种超结半导体器件及其制造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4914058A (en) * | 1987-12-29 | 1990-04-03 | Siliconix Incorporated | Grooved DMOS process with varying gate dielectric thickness |
US6376878B1 (en) * | 2000-02-11 | 2002-04-23 | Fairchild Semiconductor Corporation | MOS-gated devices with alternating zones of conductivity |
JP2002353447A (ja) * | 2001-05-30 | 2002-12-06 | Fuji Electric Co Ltd | 半導体装置 |
US6576516B1 (en) * | 2001-12-31 | 2003-06-10 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4140558A (en) | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
US4593302B1 (en) * | 1980-08-18 | 1998-02-03 | Int Rectifier Corp | Process for manufacture of high power mosfet laterally distributed high carrier density beneath the gate oxide |
GB2089119A (en) * | 1980-12-10 | 1982-06-16 | Philips Electronic Associated | High voltage semiconductor devices |
US4419150A (en) | 1980-12-29 | 1983-12-06 | Rockwell International Corporation | Method of forming lateral bipolar transistors |
US4569701A (en) | 1984-04-05 | 1986-02-11 | At&T Bell Laboratories | Technique for doping from a polysilicon transfer layer |
USH204H (en) | 1984-11-29 | 1987-02-03 | At&T Bell Laboratories | Method for implanting the sidewalls of isolation trenches |
US4711017A (en) | 1986-03-03 | 1987-12-08 | Trw Inc. | Formation of buried diffusion devices |
US4719185A (en) * | 1986-04-28 | 1988-01-12 | International Business Machines Corporation | Method of making shallow junction complementary vertical bipolar transistor pair |
US4893160A (en) | 1987-11-13 | 1990-01-09 | Siliconix Incorporated | Method for increasing the performance of trenched devices and the resulting structure |
JPH01136369A (ja) * | 1987-11-21 | 1989-05-29 | Toshiba Corp | 過電圧保護機能付半導体装置の製造方法 |
JP2733271B2 (ja) | 1988-12-23 | 1998-03-30 | シャープ株式会社 | 半導体装置の製造方法 |
CN1019720B (zh) | 1991-03-19 | 1992-12-30 | 电子科技大学 | 半导体功率器件 |
US5488236A (en) * | 1994-05-26 | 1996-01-30 | North Carolina State University | Latch-up resistant bipolar transistor with trench IGFET and buried collector |
US6228719B1 (en) * | 1995-11-06 | 2001-05-08 | Stmicroelectronics S.R.L. | MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
US5719409A (en) * | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
US6097076A (en) * | 1997-03-25 | 2000-08-01 | Micron Technology, Inc. | Self-aligned isolation trench |
US5981332A (en) * | 1997-09-30 | 1999-11-09 | Siemens Aktiengesellschaft | Reduced parasitic leakage in semiconductor devices |
DE19843959B4 (de) * | 1998-09-24 | 2004-02-12 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiterbauelements mit einem sperrenden pn-Übergang |
US6194741B1 (en) * | 1998-11-03 | 2001-02-27 | International Rectifier Corp. | MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance |
US6291856B1 (en) * | 1998-11-12 | 2001-09-18 | Fuji Electric Co., Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
DE19854915C2 (de) * | 1998-11-27 | 2002-09-05 | Infineon Technologies Ag | MOS-Feldeffekttransistor mit Hilfselektrode |
US6380569B1 (en) * | 1999-08-10 | 2002-04-30 | Rockwell Science Center, Llc | High power unipolar FET switch |
DE19943143B4 (de) | 1999-09-09 | 2008-04-24 | Infineon Technologies Ag | Halbleiterbauelement für hohe Sperrspannungen bei gleichzeitig niedrigem Einschaltwiderstand und Verfahren zu dessen Herstellung |
DE19947020B4 (de) * | 1999-09-30 | 2006-02-23 | Infineon Technologies Ag | Kompensationsbauelement mit variabler Ladungsbilanz und dessen Herstellungsverfahren |
US6475864B1 (en) * | 1999-10-21 | 2002-11-05 | Fuji Electric Co., Ltd. | Method of manufacturing a super-junction semiconductor device with an conductivity type layer |
JP4371521B2 (ja) | 2000-03-06 | 2009-11-25 | 株式会社東芝 | 電力用半導体素子およびその製造方法 |
IT1320016B1 (it) * | 2000-04-04 | 2003-11-12 | St Microelectronics Srl | Procedimento per la fabbricazione di strutture di giunzione a saccheprofonde. |
JP4965756B2 (ja) * | 2000-04-12 | 2012-07-04 | 株式会社東芝 | 半導体装置 |
GB0010041D0 (en) | 2000-04-26 | 2000-06-14 | Koninkl Philips Electronics Nv | Trench semiconductor device manufacture |
US6509240B2 (en) * | 2000-05-15 | 2003-01-21 | International Rectifier Corporation | Angle implant process for cellular deep trench sidewall doping |
US6468847B1 (en) | 2000-11-27 | 2002-10-22 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
US6509220B2 (en) * | 2000-11-27 | 2003-01-21 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
US6608350B2 (en) * | 2000-12-07 | 2003-08-19 | International Rectifier Corporation | High voltage vertical conduction superjunction semiconductor device |
EP1267415A3 (en) * | 2001-06-11 | 2009-04-15 | Kabushiki Kaisha Toshiba | Power semiconductor device having resurf layer |
US6649477B2 (en) * | 2001-10-04 | 2003-11-18 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands |
US6465304B1 (en) * | 2001-10-04 | 2002-10-15 | General Semiconductor, Inc. | Method for fabricating a power semiconductor device having a floating island voltage sustaining layer |
US6656797B2 (en) | 2001-12-31 | 2003-12-02 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and ion implantation |
US6566201B1 (en) | 2001-12-31 | 2003-05-20 | General Semiconductor, Inc. | Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion |
US6750104B2 (en) * | 2001-12-31 | 2004-06-15 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source |
US6686244B2 (en) | 2002-03-21 | 2004-02-03 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
-
2002
- 2002-03-21 US US10/103,674 patent/US6686244B2/en not_active Expired - Lifetime
-
2003
- 2003-03-18 TW TW092105928A patent/TW200305970A/zh unknown
- 2003-03-21 JP JP2003579265A patent/JP4786872B2/ja not_active Expired - Fee Related
- 2003-03-21 EP EP03723789.8A patent/EP1485945B1/en not_active Expired - Fee Related
- 2003-03-21 AU AU2003230699A patent/AU2003230699A1/en not_active Abandoned
- 2003-03-21 WO PCT/US2003/008588 patent/WO2003081642A2/en active Application Filing
-
2004
- 2004-02-02 US US10/770,045 patent/US7084455B2/en not_active Expired - Fee Related
-
2006
- 2006-07-31 US US11/496,233 patent/US7586148B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4914058A (en) * | 1987-12-29 | 1990-04-03 | Siliconix Incorporated | Grooved DMOS process with varying gate dielectric thickness |
US6376878B1 (en) * | 2000-02-11 | 2002-04-23 | Fairchild Semiconductor Corporation | MOS-gated devices with alternating zones of conductivity |
JP2002353447A (ja) * | 2001-05-30 | 2002-12-06 | Fuji Electric Co Ltd | 半導体装置 |
US6576516B1 (en) * | 2001-12-31 | 2003-06-10 | General Semiconductor, Inc. | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon |
Also Published As
Publication number | Publication date |
---|---|
EP1485945A2 (en) | 2004-12-15 |
US20040157384A1 (en) | 2004-08-12 |
AU2003230699A1 (en) | 2003-10-08 |
US7084455B2 (en) | 2006-08-01 |
TW200305970A (en) | 2003-11-01 |
EP1485945A4 (en) | 2009-03-11 |
US7586148B2 (en) | 2009-09-08 |
EP1485945B1 (en) | 2013-08-07 |
WO2003081642A3 (en) | 2004-02-26 |
AU2003230699A8 (en) | 2003-10-08 |
US20030181010A1 (en) | 2003-09-25 |
US20060267083A1 (en) | 2006-11-30 |
JP2005521259A (ja) | 2005-07-14 |
WO2003081642A2 (en) | 2003-10-02 |
US6686244B2 (en) | 2004-02-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4786872B2 (ja) | 単一のイオン注入工程によって形成されたドープされたコラムを含む電圧維持領域を有するパワー半導体デバイス及びそれらの製造方法 | |
JP4743744B2 (ja) | フローティングアイランド電圧維持層を有する半導体パワーデバイス | |
JP4833517B2 (ja) | 迅速な拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力mosfetを製造する方法 | |
JP4741187B2 (ja) | ドープカラムを含む高電圧電力mosfet | |
JP4615217B2 (ja) | フローティングアイランドを形成するための雛壇状のトレンチを有する電圧維持層を備える半導体パワーデバイスの製造方法 | |
US7736976B2 (en) | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands | |
JP4880199B2 (ja) | トレンチのエッチングおよび反対にドープされたポリシリコンの領域からの拡散によって形成されるドープカラムを含む電圧維持領域を有する高電圧電力mosfet | |
US6750104B2 (en) | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060306 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100209 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20100510 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20100517 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100531 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100622 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101022 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20101101 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101214 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110314 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110325 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110414 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110421 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110512 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110614 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110714 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140722 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |