CN102403256B - 赝埋层及制造方法、深孔接触及三极管 - Google Patents

赝埋层及制造方法、深孔接触及三极管 Download PDF

Info

Publication number
CN102403256B
CN102403256B CN201010275532.8A CN201010275532A CN102403256B CN 102403256 B CN102403256 B CN 102403256B CN 201010275532 A CN201010275532 A CN 201010275532A CN 102403256 B CN102403256 B CN 102403256B
Authority
CN
China
Prior art keywords
shallow trench
impurities district
district
arsenic
implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010275532.8A
Other languages
English (en)
Other versions
CN102403256A (zh
Inventor
刘冬华
钱文生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201010275532.8A priority Critical patent/CN102403256B/zh
Priority to US13/227,387 priority patent/US8592870B2/en
Publication of CN102403256A publication Critical patent/CN102403256A/zh
Application granted granted Critical
Publication of CN102403256B publication Critical patent/CN102403256B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821Collector regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708Emitter or collector electrodes for bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • H01L29/7378Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Abstract

本发明公开了一种赝埋层的制造方法,包括如下步骤:在硅衬底上刻蚀形成有源区和浅沟槽;在浅沟槽底部表面进行磷离子注入形成磷杂质区;在所述浅沟槽底部表面进行砷离子注入形成砷杂质区;进行热退火。本发明还公开了一种赝埋层。本发明还公开一种深孔接触;本发明还公开一种三极管。本发明方法的赝埋层注入通过采用具有快速热扩散特性的磷注入和具有慢速热扩散特性的砷注入,能提高赝埋层表面的杂质浓度、能减少赝埋层的方块电阻、能使赝埋层和深孔接触形成良好的欧姆接触并减少接触电阻,还能提高三极管器件的频率特性和电流输出能力。

Description

赝埋层及制造方法、深孔接触及三极管
技术领域
本发明涉及半导体集成电路制造领域,特别是涉及一种锗硅双极CMOS工艺中的赝埋层的制造方法;本发明还涉及一种赝埋层;本发明还涉及一种深孔接触;本发明还涉及一种三极管。
背景技术
在锗硅双极CMOS(SiGe BiCMOS)工艺中采用深孔接触工艺和赝埋层(Pseudo Buried Layer),能使得器件具有面积小、成本低等特点。如图1所示,为现有N型赝埋层的结构示意图。在硅衬底上形成有浅沟槽隔离(STI)和有源区,所述浅沟槽隔离也即为浅沟槽场氧是通过在硅衬底上刻蚀出浅沟槽并填入氧化硅形成;现有N型赝埋层由形成于所述浅沟槽隔离的底部硅衬底中磷杂质区组成,所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成。通过热退火,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中。
现有深孔接触是通过在现有赝埋层顶部的浅沟槽场氧即所述浅沟槽隔离中开一深孔并在所述深孔中淀积钛/氮化钛阻挡金属层后、再填入钨形成。现有深孔接触的特点的金属是直接与所述浅沟槽底部的硅即赝埋层接触,无法引入金属硅化物工艺。同时现有锗硅双极CMOS(SiGe BiCMOS)工艺中,为了满足异质结双极晶体管(HBT,hetero junction bipolartransistor)的性能需求,现有N型赝埋层必须要具有一定量的横向和纵向扩散,因此现有N型赝埋层的注入杂质必须使用具有快速横向扩散特性的磷。由于现有N型赝埋层的注入发生在工艺流程的开始阶段,基本上承受了所有的热过程,这样虽然达到了现有N型赝埋层的横向扩散的要求,但也造成了现有N型赝埋层表面的杂质浓度过低,从而使得现有N型赝埋层与深接触孔的接触电阻过大,某些情况下甚至无法形成有效的欧姆接触;浓度的降低也会造成现有N型赝埋层本身的方块电阻增加。
发明内容
本发明所要解决的技术问题是提供一种赝埋层的制造方法,能提高赝埋层表面的杂质浓度、能减少赝埋层的方块电阻、能使赝埋层和深孔接触形成良好的欧姆接触并减少接触电阻;为此,本发明还提供一种赝埋层;本发明还提供一种深孔接触;本发明还提供一种三极管,能提高器件的频率特性和电流输出能力。
为解决上述技术问题,本发明提供的赝埋层的制造方法包括如下步骤:
步骤一、在硅衬底上刻蚀形成有源区和浅沟槽。
步骤二、在所述浅沟槽底部表面进行磷离子注入形成磷杂质区。所述磷离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV。
步骤三、在所述浅沟槽底部表面进行砷离子注入形成砷杂质区。所述砷离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
步骤四、对所述磷杂质区和砷杂质区进行热退火。由于磷离子具有快速热扩散特性,而砷离子具有慢速热扩散特性,热退火过程中所述磷离子扩散速率会远大于所述砷离子的扩散速率,热退火后,所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区保留在所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂区的浓度。
为解决上述技术问题,本发明提供一种赝埋层,所述赝埋层形成于浅沟槽底部的硅衬底中,包括一磷杂质区和一砷杂质区。所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区处于所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂区的浓度。所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成,所述砷杂质区通过在所述浅沟槽底部进行砷离子注入并进行热退火形成。所述磷杂质离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;所述砷杂质离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
为解决上述技术问题,本发明提供一种深孔接触,所述深孔接触由形成于赝埋层顶部的浅沟槽场氧的深孔中并和所述赝埋层相接触的金属组成,所述深孔接触的金属包括形成于所述深孔内壁和底部的钛/氮化钛阻挡金属层、以及形成于所述钛/氮化钛阻挡金属层上并填满所述深孔的钨。所述赝埋层形成于浅沟槽底部的硅衬底中,所述赝埋层包括一磷杂质区和一砷杂质区;所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区处于所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂区的浓度;所述深孔接触的金属和所述砷杂质区形成欧姆接触。所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成,所述砷杂质区通过在所述浅沟槽底部进行砷离子注入并进行热退火形成。所述磷杂质离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;所述砷杂质离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
为解决上述技术问题,本发明提供一种三极管,所述三极管的N型区形成于硅衬底上的有源区中,所述N型区和一赝埋层相连并通过一深孔接触引出。所述赝埋层形成于和所述有源区相邻的浅沟槽底部的硅衬底中,所述赝埋层包括一磷杂质区和一砷杂质区。所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区处于所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂区的浓度。所述N型区和所述磷杂质区相连接。所述深孔接触由形成于所述赝埋层顶部的浅沟槽场氧的深孔中并和所述赝埋层相接触的金属组成;所述深孔接触的金属和所述砷杂质区形成欧姆接触。所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成,所述砷杂质区通过在所述浅沟槽底部进行砷离子注入并进行热退火形成。所述磷杂质离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;所述砷杂质离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
其中,所述三极管能为锗硅NPN异质结三极管,所述NPN锗硅异质结三极管的集电区为所述N型区。或者,所述三极管为锗硅工艺中的寄生PNP三极管,所述锗硅工艺中的寄生PNP三极管的基区为所述N型区。
本发明赝埋层的制造方法能提高赝埋层表面的杂质浓度、能减少赝埋层的方块电阻、能使赝埋层和深孔接触形成良好的欧姆接触并减少接触电阻。本发明三极管能保证在器件的电流增益系数不受影响的条件下,提高器件的频率特性和改善器件的电流输出能力,也能提高器件的功率增益。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明:
图1是现有N型赝埋层的结构示意图;
图2-图4是本发明实施例赝埋层的制造方法中的器件结构示意图;
图5是本发明实施例三极管的器件结构示意图;
图6是现有N型赝埋层和本发明赝埋层的杂质分布图。
具体实施方式
如图2至图4所示,是本发明实施例赝埋层的制造方法中的器件结构示意图。本发明实施例赝埋层的制造方法包括如下步骤:
步骤一、如图2所示,在硅衬底101上刻蚀形成有源区和浅沟槽。在所述有源区表面形成第一层氧化硅层102、第二层氮化硅层103、第三层氧化硅层104;同时在所述浅沟槽侧壁和底部分布形成侧壁氧化硅层105和底部氧化硅层106。各氧化硅层和氮化硅层用以在后续的浅沟槽底部的离子注入时作为所述有源区的保护层,防止离子注入到所述有源区中。
步骤二、如图2所示,在所述浅沟槽底部表面进行磷离子注入形成磷杂质区301。所述磷离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV。
步骤三、如图3所示,在所述浅沟槽底部表面进行砷离子注入形成砷杂质区302。所述砷离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。如图4所示,去除所述有源区表面的第一层氧化硅层102、第二层氮化硅层103、第三层氧化硅层104和所述浅沟槽表面的侧壁氧化硅层105和底部氧化硅层106。
步骤四、如图4所示,在所述浅沟槽中填入氧化硅形成浅沟槽场氧也即浅沟槽隔离303。对所述磷杂质区301和砷杂质区302进行热退火。所述热退火可以单独进行,也可以利用后续工艺中本身的热过程进行。由于磷离子具有快速热扩散特性,而砷离子具有慢速热扩散特性,热退火过程中所述磷离子扩散速率会远大于所述砷离子的扩散速率,热退火后,所述磷杂质区301的区域范围大于所述砷杂质区302的区域范围,所述砷杂质区302保留在所述浅沟槽底部表面处,所述磷杂质区301横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底101中,且所述砷杂质区301的浓度大于所述磷杂区302的浓度。
经过上述步骤后最后形成本发明实施例赝埋层。
如图5所示,是本发明实施例三极管的器件结构示意图。本发明实施例三极管为为锗硅NPN异质结三极管。在上述四个步骤的基础上,采用现有的锗硅双极CMOS工艺流程能够形成如图5所示的锗硅NPN异质结三极管。本发明实施例三极管的集电区401形成于所述有源区中,所述集电区401和扩散进入所述有源区中的所述磷杂质区302形成接触连接。所述集电区401通过和所述赝埋层相连接的深孔接触408引出。所述深孔接触408由形成于所述赝埋层顶部的浅沟槽场氧即所述浅沟槽隔离303的深孔中并和所述赝埋层相接触的金属组成。所述深孔接触408的金属和所述砷杂质区302形成欧姆接触。所述深孔接触408的金属包括形成于所述深孔内壁和底部的钛/氮化钛阻挡金属层、以及形成于所述钛/氮化钛阻挡金属层上并填满所述深孔的钨。
如图5所示,本发明实施例三极管还包括一基区403和一发射区406。所述基区403由形成于所述有源区上的P型外延层组成,所述基区403和所述集电区401形成接触。所述基区403还和外基区404相连,通过金属接触409和所述外基区404相连引出所述基区403,所述外基区404和所述浅沟槽隔离303间隔有基区隔离场氧402。所述发射区406由形成在所述基区403上的N型多晶硅组成。所述发射区406和所述基区403形成接触。所述发射区406的上部区域往外延伸,所述发射区406的延伸部分和所述基区403间通过所述发射极多晶硅隔离氧化物405进行隔离。所述发射区406通过金属接触409引出。各金属接触409、深孔接触408最后和金属连线410相连实现器件的互连。
如图6所示,是现有N型赝埋层和本发明赝埋层的杂质分布图。图6中的横坐标表示所述赝埋层的纵向深度坐标,即从所述浅沟槽隔离底部表面处开始向所述硅衬底底面方向的纵向深度坐标,其中0.35微米表示所述浅沟槽隔离底部表面处的深度坐标。图6中的纵坐标为杂质浓度,所述杂质浓度表示所述赝埋层的各位置处的杂质浓度。如图6可知,本发明赝埋层的在处于所述浅沟槽隔离底部表面位置处的浓度得到了大幅度的提高。这个高浓度对于减小赝埋层本身的方块电阻和使其与深接触孔形成良好的欧姆接触提供良好的工艺保证。
以上通过具体实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。

Claims (11)

1.一种赝埋层的制造方法,其特征在于,包括如下步骤:
步骤一、采用浅沟槽隔离工艺在硅衬底上刻蚀形成有源区和浅沟槽,其中所述有源区由所述浅沟槽隔离出来的所述硅衬底组成,所述浅沟槽为所述浅沟槽隔离工艺中的浅沟槽场氧的填充区域;
步骤二、在所述浅沟槽底部表面进行磷离子注入形成磷杂质区;所述磷离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;
步骤三、在所述浅沟槽底部表面进行砷离子注入形成砷杂质区;所述砷离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV;
步骤四、对所述磷杂质区和砷杂质区进行热退火,由热退火后的所述磷杂质区和所述砷杂质区组成赝埋层,步骤二中的所述磷离子注入的注入剂量和注入能量以及步骤三中的所述砷离子注入的注入剂量和注入能量的工艺条件使所述赝埋层为导电层并和金属形成欧姆接触。
2.如权利要求1所述的方法,其特征在于:步骤四的热退火过程中所述磷离子扩散速率大于所述砷离子的扩散速率,热退火后,所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区保留在所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂质区的浓度。
3.一种赝埋层,其特征在于:形成于浅沟槽底部的硅衬底中,有源区由所述浅沟槽隔离出来的所述硅衬底组成,所述浅沟槽采用浅沟槽隔离工艺形成,所述浅沟槽为所述浅沟槽隔离工艺中的浅沟槽场氧的填充区域;所述赝埋层包括一磷杂质区和一砷杂质区;所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区处于所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂质区的浓度;所述磷杂质离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;所述砷杂质离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
4.如权利要求3所述的赝埋层,其特征在于:所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成,所述砷杂质区通过在所述浅沟槽底部进行砷离子注入并进行热退火形成。
5.一种深孔接触,其特征在于:所述深孔接触由形成于赝埋层顶部的浅沟槽场氧的深孔中并和所述赝埋层相接触的金属组成;所述赝埋层形成于浅沟槽底部的硅衬底中,有源区由所述浅沟槽隔离出来的所述硅衬底组成,所述浅沟槽场氧由填充于所述浅沟槽中的氧化硅组成;所述赝埋层包括一磷杂质区和一砷杂质区;所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区处于所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂质区的浓度;所述深孔接触的金属和所述砷杂质区形成欧姆接触;所述磷杂质离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;所述砷杂质离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
6.如权利要求5所述的深孔接触,其特征在于:所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成,所述砷杂质区通过在所述浅沟槽底部进行砷离子注入并进行热退火形成。
7.如权利要求5所述的深孔接触,其特征在于:所述深孔接触的金属包括形成于所述深孔内壁和底部的钛/氮化钛阻挡金属层、以及形成于所述钛/氮化钛阻挡金属层上并填满所述深孔的钨。
8.一种三极管,其特征在于:所述三极管的N型区形成于硅衬底上的有源区中,有源区由浅沟槽隔离出来的所述硅衬底组成,由填充于所述浅沟槽中的氧化硅组成浅沟槽场氧;所述N型区和一赝埋层相连并通过一深孔接触引出;所述赝埋层形成于和所述有源区相邻的浅沟槽底部的硅衬底中,所述赝埋层包括一磷杂质区和一砷杂质区;所述磷杂质区的区域范围大于所述砷杂质区的区域范围,所述砷杂质区处于所述浅沟槽底部表面处,所述磷杂质区横向和纵向扩散进入所述有源区和远离所述浅沟槽底部表面的硅衬底中,且所述砷杂质区的浓度大于所述磷杂质区的浓度;所述N型区和所述磷杂质区相连接;所述深孔接触由形成于所述赝埋层顶部的浅沟槽场氧的深孔中并和所述赝埋层相接触的金属组成;所述深孔接触的金属和所述砷杂质区形成欧姆接触;所述磷杂质离子注入的注入剂量为1e14cm-2~1e16cm-2、注入能量为3keV~30keV;所述砷杂质离子注入的注入剂量为1e15cm-2~1e16cm-2、注入能量为5keV~30keV。
9.如权利要求8所述的三极管,其特征在于:所述磷杂质区通过在所述浅沟槽底部进行磷离子注入并进行热退火形成,所述砷杂质区通过在所述浅沟槽底部进行砷离子注入并进行热退火形成。
10.如权利要求8所述的三极管,其特征在于:所述三极管为锗硅NPN异质结三极管,所述锗硅NPN异质结三极管的集电区为所述N型区。
11.如权利要求8所述的三极管,其特征在于:所述三极管为锗硅工艺中的寄生PNP三极管,所述寄生PNP三极管的基区为所述N型区。
CN201010275532.8A 2010-09-08 2010-09-08 赝埋层及制造方法、深孔接触及三极管 Active CN102403256B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201010275532.8A CN102403256B (zh) 2010-09-08 2010-09-08 赝埋层及制造方法、深孔接触及三极管
US13/227,387 US8592870B2 (en) 2010-09-08 2011-09-07 Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010275532.8A CN102403256B (zh) 2010-09-08 2010-09-08 赝埋层及制造方法、深孔接触及三极管

Publications (2)

Publication Number Publication Date
CN102403256A CN102403256A (zh) 2012-04-04
CN102403256B true CN102403256B (zh) 2014-02-26

Family

ID=45770065

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010275532.8A Active CN102403256B (zh) 2010-09-08 2010-09-08 赝埋层及制造方法、深孔接触及三极管

Country Status (2)

Country Link
US (1) US8592870B2 (zh)
CN (1) CN102403256B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035560A (zh) * 2012-01-31 2013-04-10 上海华虹Nec电子有限公司 抑制p型赝埋层中的硼杂质外扩的方法
CN103050521B (zh) * 2012-05-23 2015-02-04 上海华虹宏力半导体制造有限公司 锗硅hbt器件的集电区引出结构及其制造方法
US20150061010A1 (en) * 2013-08-27 2015-03-05 International Business Machines Corporation Structure for improved contact resistance and extension diffusion control
RU2688866C1 (ru) * 2018-03-12 2019-05-22 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления полупроводникового прибора

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770952B2 (en) * 2001-04-30 2004-08-03 Texas Instruments Incorporated Integrated process for high voltage and high performance silicon-on-insulator bipolar devices

Family Cites Families (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344081A (en) * 1980-04-14 1982-08-10 Supertex, Inc. Combined DMOS and a vertical bipolar transistor device and fabrication method therefor
US4729001A (en) * 1981-07-27 1988-03-01 Xerox Corporation Short-channel field effect transistor
JPS6072272A (ja) * 1983-09-28 1985-04-24 Toshiba Corp 半導体装置の製造方法
US4837173A (en) * 1987-07-13 1989-06-06 Motorola, Inc. N-channel MOS transistors having source/drain regions with germanium
US4963504A (en) * 1987-11-23 1990-10-16 Xerox Corporation Method for fabricating double implanted LDD transistor self-aligned with gate
JP2733271B2 (ja) * 1988-12-23 1998-03-30 シャープ株式会社 半導体装置の製造方法
US4975385A (en) * 1990-04-06 1990-12-04 Applied Materials, Inc. Method of constructing lightly doped drain (LDD) integrated circuit structure
MY107475A (en) * 1990-05-31 1995-12-30 Canon Kk Semiconductor device and method for producing the same.
US5102815A (en) * 1990-12-19 1992-04-07 Intel Corporation Method of fabricating a composite inverse T-gate metal oxide semiconductor device
US5223732A (en) * 1991-05-28 1993-06-29 Motorola, Inc. Insulated gate semiconductor device with reduced based-to-source electrode short
US5324973A (en) * 1993-05-03 1994-06-28 Motorola Inc. Semiconductor SRAM with trench transistors
US5424231A (en) * 1994-08-09 1995-06-13 United Microelectronics Corp. Method for manufacturing a VDMOS transistor
JP2586342B2 (ja) * 1994-08-27 1997-02-26 日本電気株式会社 半導体装置の製造方法
JP3303601B2 (ja) * 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0143459B1 (ko) * 1995-05-22 1998-07-01 한민구 모오스 게이트형 전력 트랜지스터
US5728613A (en) * 1996-03-27 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor
US5719409A (en) * 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5817564A (en) * 1996-06-28 1998-10-06 Harris Corporation Double diffused MOS device and method
US6100146A (en) * 1996-10-30 2000-08-08 Advanced Micro Devices, Inc. Method of forming trench transistor with insulative spacers
JP3397057B2 (ja) * 1996-11-01 2003-04-14 日産自動車株式会社 半導体装置
KR100221619B1 (ko) * 1996-12-28 1999-09-15 구본준 플래쉬 메모리 셀의 제조방법
US6570185B1 (en) * 1997-02-07 2003-05-27 Purdue Research Foundation Structure to reduce the on-resistance of power transistors
US5912493A (en) * 1997-11-14 1999-06-15 Gardner; Mark I. Enhanced oxidation for spacer formation integrated with LDD implantation
US5907168A (en) * 1998-01-23 1999-05-25 Tlc Precision Wafer Technology, Inc. Low noise Ge-JFETs
JP2000100829A (ja) * 1998-09-25 2000-04-07 Sony Corp 接合型電界効果トランジスタおよびその製造方法
JP2001168328A (ja) * 1999-12-10 2001-06-22 Nippon Precision Circuits Inc 耐圧性能を持つmos型半導体装置およびその製造方法
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
JP4004843B2 (ja) * 2002-04-24 2007-11-07 Necエレクトロニクス株式会社 縦型mosfetの製造方法
US7432136B2 (en) * 2002-05-06 2008-10-07 Advanced Micro Devices, Inc. Transistors with controllable threshold voltages, and various methods of making and operating same
KR100442881B1 (ko) * 2002-07-24 2004-08-02 삼성전자주식회사 고전압 종형 디모스 트랜지스터 및 그 제조방법
DE10260613B8 (de) * 2002-12-23 2010-03-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Feldeffekttransistors
US7235827B2 (en) * 2004-04-20 2007-06-26 Power-One, Inc. Vertical power JFET with low on-resistance for high voltage applications
JP5033305B2 (ja) * 2004-10-01 2012-09-26 株式会社日立製作所 炭化珪素半導体装置
JP2007005723A (ja) * 2005-06-27 2007-01-11 Toshiba Corp 半導体装置
US8338887B2 (en) * 2005-07-06 2012-12-25 Infineon Technologies Ag Buried gate transistor
US7868394B2 (en) * 2005-08-09 2011-01-11 United Microelectronics Corp. Metal-oxide-semiconductor transistor and method of manufacturing the same
KR100660881B1 (ko) * 2005-10-12 2006-12-26 삼성전자주식회사 수직 채널 트랜지스터를 구비한 반도체 소자 및 그 제조방법
US7705427B2 (en) * 2005-11-16 2010-04-27 Stmicroelectronics Sa Integrated circuit comprising a gradually doped bipolar transistor
US7687851B2 (en) * 2005-11-23 2010-03-30 M-Mos Semiconductor Sdn. Bhd. High density trench MOSFET with reduced on-resistance
JP5164333B2 (ja) * 2005-12-28 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体装置
KR100645221B1 (ko) * 2005-12-28 2006-11-10 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
JP4453671B2 (ja) * 2006-03-08 2010-04-21 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
US20080048186A1 (en) * 2006-03-30 2008-02-28 International Business Machines Corporation Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions
JP4935160B2 (ja) * 2006-04-11 2012-05-23 株式会社デンソー 炭化珪素半導体装置およびその製造方法
US7407875B2 (en) * 2006-09-06 2008-08-05 International Business Machines Corporation Low resistance contact structure and fabrication thereof
JP4501965B2 (ja) * 2006-10-16 2010-07-14 ソニー株式会社 半導体装置の製造方法
US7691734B2 (en) * 2007-03-01 2010-04-06 International Business Machines Corporation Deep trench based far subcollector reachthrough
US8178930B2 (en) * 2007-03-06 2012-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure to improve MOS transistor on-breakdown voltage
US20080217686A1 (en) * 2007-03-09 2008-09-11 International Business Machines Corporation Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extension
US8273633B2 (en) * 2007-03-26 2012-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of enhancing dopant activation without suffering additional dopant diffusion
US7718513B2 (en) * 2007-04-13 2010-05-18 International Business Machines Corporation Forming silicided gate and contacts from polysilicon germanium and structure formed
DE102007029121B3 (de) * 2007-06-25 2008-11-20 Infineon Technologies Austria Ag Verfahren zur Herstellung eines Halbleiterbauelements, sowie Halbleiterbauelement
US7948031B2 (en) * 2007-07-03 2011-05-24 Sanyo Electric Co., Ltd. Semiconductor device and method of fabricating semiconductor device
US7825465B2 (en) * 2007-12-13 2010-11-02 Fairchild Semiconductor Corporation Structure and method for forming field effect transistor with low resistance channel region
US7932541B2 (en) * 2008-01-14 2011-04-26 International Business Machines Corporation High performance collector-up bipolar transistor
US7973364B2 (en) * 2008-02-27 2011-07-05 Globalfoundries Inc. Method for forming a one-transistor memory cell and related structure
JP2010021176A (ja) * 2008-07-08 2010-01-28 Nec Electronics Corp 半導体装置および半導体装置の製造方法
US8847359B2 (en) * 2008-08-06 2014-09-30 Texas Instruments Incorporated High voltage bipolar transistor and method of fabrication
US8022474B2 (en) * 2008-09-30 2011-09-20 Infineon Technologies Austria Ag Semiconductor device
US8022471B2 (en) * 2008-12-31 2011-09-20 Force-Mos Technology Corp. Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures
US7875918B2 (en) * 2009-04-24 2011-01-25 Omnivision Technologies, Inc. Multilayer image sensor pixel structure for reducing crosstalk
US20110018608A1 (en) * 2009-07-24 2011-01-27 Semiconductor Manufacturing International (Shanghai) Corporation Bipolar Transistor, Band-Gap Reference Circuit and Virtual Ground Reference Circuit
US8159008B2 (en) * 2009-09-18 2012-04-17 International Business Machines Corporation Method of fabricating a trench-generated transistor structure
CN102097464B (zh) * 2009-12-15 2012-10-03 上海华虹Nec电子有限公司 高压双极晶体管
KR101096265B1 (ko) * 2009-12-29 2011-12-22 주식회사 하이닉스반도체 반도체 소자의 매립 게이트 및 그 형성방법
CN102117827B (zh) * 2009-12-31 2012-11-07 上海华虹Nec电子有限公司 BiCMOS工艺中的寄生垂直型PNP器件
US8264035B2 (en) * 2010-03-26 2012-09-11 Force Mos Technology Co., Ltd. Avalanche capability improvement in power semiconductor devices
US9331174B2 (en) * 2010-04-15 2016-05-03 Globalfoundries Inc. Method for improving device performance using epitaxially grown silicon carbon (SiC) or silicon-germanium (SiGe)
CN102254944A (zh) * 2010-05-21 2011-11-23 上海新进半导体制造有限公司 一种沟槽mosfet功率整流器件及制造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770952B2 (en) * 2001-04-30 2004-08-03 Texas Instruments Incorporated Integrated process for high voltage and high performance silicon-on-insulator bipolar devices

Also Published As

Publication number Publication date
US8592870B2 (en) 2013-11-26
CN102403256A (zh) 2012-04-04
US20120056247A1 (en) 2012-03-08

Similar Documents

Publication Publication Date Title
US8598678B2 (en) Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process
CN102110709B (zh) BiCMOS工艺中的寄生垂直型PNP三极管及其制造方法
US8673726B2 (en) Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the transistor
CN102487077B (zh) BiCMOS工艺中的垂直寄生型PNP器件及制造方法
CN102403256B (zh) 赝埋层及制造方法、深孔接触及三极管
CN102412274B (zh) 锗硅hbt工艺中垂直寄生型pnp器件及制造方法
CN102104064B (zh) SiGe HBT工艺中的寄生横向型PNP三极管及其制造方法
CN102412278B (zh) 锗硅BiCMOS工艺中垂直型PNP三极管及制造方法
CN102386218B (zh) BiCMOS工艺中的垂直寄生型PNP器件及其制造方法
CN102544079B (zh) 锗硅异质结npn晶体管及制造方法
CN102544081B (zh) 锗硅异质结npn三极管及制造方法
CN102569371B (zh) BiCMOS工艺中的垂直寄生型PNP三极管及制造方法
CN102544082B (zh) 锗硅异质结npn三极管器件及制造方法
CN102969349B (zh) 锗硅hbt工艺中的横向寄生型pnp器件及制造方法
CN103066115B (zh) 垂直寄生型pnp三极管及制造方法
CN102412279B (zh) 锗硅bicmos工艺中垂直寄生型pnp三极管及制造方法
CN102543727B (zh) 锗硅hbt结构、其赝埋层结构及其制造方法
CN102569370B (zh) BiCMOS工艺中垂直寄生型PNP器件及制造方法
CN102104065A (zh) SiGe HBT工艺中的寄生横向型PNP三极管
CN102403343B (zh) BiCMOS工艺中的垂直寄生型PNP器件及制造方法
CN103066056B (zh) BiCMOS工艺中的垂直寄生型PNP器件及其制造方法
CN103066057B (zh) BiCMOS工艺中的垂直寄生型PNP器件及其制造方法
CN103178100A (zh) 纵向pnp型三极管及其制造方法
CN104205336A (zh) 具有浅层向外扩散p+发射极区的锗化硅异质结双极晶体管
CN102412308A (zh) BiCMOS工艺中的寄生PIN器件及制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140103

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20140103

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201203, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Applicant before: Shanghai Huahong NEC Electronics Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant