CN102117827B - BiCMOS工艺中的寄生垂直型PNP器件 - Google Patents

BiCMOS工艺中的寄生垂直型PNP器件 Download PDF

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CN102117827B
CN102117827B CN2009102020672A CN200910202067A CN102117827B CN 102117827 B CN102117827 B CN 102117827B CN 2009102020672 A CN2009102020672 A CN 2009102020672A CN 200910202067 A CN200910202067 A CN 200910202067A CN 102117827 B CN102117827 B CN 102117827B
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CN102117827A (zh
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邱慈云
朱东园
钱文生
范永洁
刘冬华
胡君
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

本发明公开了一种BiCMOS工艺中的寄生垂直型PNP器件，有源区由浅槽场氧隔离，包括：一集电区，由形成于有源区中的一P型杂质离子注入层构成，所述集电区底部连接一P型埋层，所述P型埋层是通过离子注入形成于所述集电区两侧的浅槽底部，通过在所述P型埋层顶部对应的浅槽场氧中制作深孔接触引出集电极；一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层构成；一发射区，由形成于所述基区上部的一P型外延层构成，发射区直接通过一金属接触引出；所述基区上部的P型外延层部分反型为N型，用作所述基区的连接。本发明能用作BiCMOS高频电路中的输出器件，具有较小的面积和传导电阻。

Description

BiCMOS工艺中的寄生垂直型PNP器件
技术领域
本发明涉及一种半导体集成电路制造器件，特别是涉及一种BiCMOS工艺中的寄生垂直型PNP器件。
背景技术
在射频应用中，需要越来越高的器件特征频率。在BICMOS工艺技术中，NPN三极管，特别是锗硅异质结三极管(SiGe HBT)或者锗硅碳异质结三极管(SiGeC HBT)是超高频器件的很好选择。并且SiGe工艺基本与硅工艺相兼容，因此SiGe HBT已经成为超高频器件的主流之一。
现有的BiCMOS工艺中的垂直型寄生PNP三极管，集电极的引出通常需要经过浅槽隔离(STI)底下的埋层或者阱和与之相连的有源区来实现。这样的做法是由其器件的垂直结构特点所决定的。其缺点是器件面积大，集电极的连接电阻大。而且引出集电极的有源区的存在及其与PNP管的集电区之间必须有STI或者其他场氧来隔离，这也限制了器件尺寸的进一步缩小。
发明内容
本发明所要解决的技术问题是提供一种BiCMOS工艺中的寄生垂直型PNP器件，能用作BiCMOS高频电路中的输出器件，具有较小的面积和传导电阻。
为解决上述技术问题，本发明提供的BiCMOS工艺中的寄生垂直型PNP器件的有源区由浅槽场氧隔离，包括：
一集电区，由形成于有源区中的一P型杂质离子注入层构成，集电极是通过一深孔接触引出，所述集电区底部连接一P型埋层，所述P型埋层是通过离子注入形成于所述集电区两侧的浅槽底部，通过在所述P型埋层顶部对应的浅槽场氧中制作深孔并填入金属形成连接所述P型埋层的所述深孔接触；所述P型埋层离子注入的剂量为1e14～1e16cm-2的、能量为小于45keV。
一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层构成。
一发射区，由形成于所述基区上部的一P型外延层构成，所述发射区直接通过一金属接触引出。
所述基区上部的P型外延层部分反型为N型，用作所述基区的连接。
本发明能用作BiCMOS高频电路中的输出器件。另外本发明采用了先进的深孔接触工艺来与所述集电区的P型埋层直接接触从而引出本发明器件的集电极，使得本发明器件的面积与现有结构相比能够有效的减小；并且由于集电极的引出位置到集电区的距离缩短，寄生的电阻也随之减小，从而有助于提高器件的频率特性；而其他特性，比如电流增益，却不会受影响。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明实施例的BiCMOS工艺中的寄生垂直型PNP器件结构示意图；
图2A-图2F是本发明实施例的BiCMOS工艺中的寄生垂直型PNP器件在制造过程中的结构示意图。
如图1所示，为本发明实施例的BiCMOS工艺中的寄生垂直型PNP器件结构示意图，有源区由浅槽场氧隔离即图1中所示浅沟槽隔离，包括：
一集电区201，由形成于有源区中的一P型杂质离子注入层构成，该P型杂质离子注入层采用MOSFET中的P阱注入实现，也可以只采用P阱中的抗穿通注入和阈值调节注入；所述集电区201底部连接一P型埋层101，所述P型埋层101是通过离子注入形成于所述集电区201两侧的浅槽底部，该P型埋层离子注入的剂量为1e14～1e16cm-2的、能量为小于45keV；通过在所述P型埋层顶部对应的浅槽场氧中制作深孔接触引出所述集电区201，深孔接触顶部连接一金属连线形成集电极。
一基区301，由形成于所述集电区201上部并和所述集电区201连接的一N型杂质离子注入层构成，该离子注入采用NMOS管的NLDD注入来实现。
一发射区602，由形成于所述基区301上部的一P型外延层构成，该P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，该P型外延层采用P型掺杂的NPN三极管基区外延层工艺实现，为形成于有源区的具有单晶结构的外延层，形成后再通过P型杂质注入来进行重掺杂，所述发射区直接通过一金属接触引出。
所述基区301上部的P型外延层部分反型为N型用作所述基区的连接，最后形成N型的多晶硅层601并连接一金属接触引出所述基区。用于形成所述基区连接的所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，是通过P型掺杂的NPN三极管基区外延层工艺实现，为形成于场氧或者多晶硅上面具有多晶硅结构的外延层，所述P型外延层反型为N型的方法为：在所述P型外延层上面淀积一层多晶硅，该层多晶硅可以是N型在位掺杂，或者不掺杂；然后进行N型源漏的重型掺杂注入；并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，而使原来是P型硅外延层或者锗硅或者锗硅碳外延层反型为N型，实现与N型基区的连接。
如图2A-图2F所示，为本发明实施例的BiCMOS工艺中的寄生垂直型PNP器件在制造过程中的结构示意图，主要包括如下步骤：
工艺步骤1：如图2A所示，选用轻掺杂的P型衬底硅片，用浅沟槽刻蚀作隔离工艺。在浅沟槽刻蚀之后，进行P型杂质注入以形成低阻区101也即为埋层，注入的剂量为1e14～1e16cm-2。在本发明所设计的寄生垂直型PNP管中，低阻区101可以有效地实现集电区的低阻连接。
工艺步骤2：如图2B所示，在浅沟槽隔离和埋层101形成之后，进行P阱注入或其中的抗穿通注入和阈值调节注入形成集电区201。然后进行热退火，低阻区101在退火过程中的纵向和横向扩散将使两个注入区扩散进有源区，实现与有源区的有效连接，这有助于减少基区的连接电阻。
工艺步骤3：如图2C所示，对P型集电区201进行NLDD的注入，形成基区301，注入区的大小用光阻定义。
工艺步骤4：如图2D所示，淀积一层氧化膜404和多晶硅，多晶硅也可以不淀积，然后进行刻蚀将集电区201打开。在对硅表面进行预清洁之后进行硅外延层、锗硅外延层或者锗硅碳外延层的生长。在单晶硅表面外延生长的结果是形成硅单晶401；而在其他区域，外延生长所形成的是多晶硅402。
工艺步骤5：如图2E所示，淀积一层10～50纳米氧化层501和10～50纳米左右的氮化硅502，然后刻蚀。刻蚀之后，仅留下图2E中所示的氧化层501和氮化硅502所在区域，从而实现PNP管的发射区401与随后淀积的150～350纳米多晶硅503的隔离。氧化层501和氮化硅502所覆盖的区域可以与有源区201一样大小或者比有源区小，也可以比有源区大，但不能大太多。这层多晶硅材料可以是N型在位掺杂，所掺杂质为磷或者砷。也可以淀积时不搀杂，而是通过淀积好之后的N型注入来改变其形态和减小其电阻。图2E所示通过N型的注入来掺杂。此N型注入可以是单独的对此多晶硅的注入，也可以在NMOS的源漏注入时一起注入，或者两个注入都注入到这个多晶硅区域。掺杂区域可用光阻来定义；仅仅这个寄生垂直型PNP而言，也可以不用光阻，对这个区域进行普注。
工艺步骤6：如图2F所示，刻蚀多晶硅刻蚀和电介质层即氮化硅502和氧化层501，打开寄生垂直型PNP管的的发射区602，刻蚀后氮化硅502和氧化层501只保留发射区两边的区域部分即电介质层氮化硅603和氧化层604，实现其与多晶硅的隔离。刻蚀同时也保留了用于连接基极的多晶硅。刻蚀完成之后，光阻去除之前，进行通过P型注入来重掺杂，注入的杂质是硼，也可以是氟化硼及铟，这步注入可以采用NPN三极管的非本征基区注入工艺。之后进行热处理。这一步对实现基区的连接至关重要。这一步热处理必须通过多晶硅中杂质的快速扩散实现P型外延多晶硅即图2E中的多晶硅402的完全反型，并横向少量推进硅单晶外延层即图2E中的单晶硅401中，从而最终形成发射区602和完整的N型基区连接多晶硅601。这样就实现了N型多晶硅601和N型基区301的连接。同时由于工艺步骤3中的NLDD掺杂浓度比发射区的掺杂浓度淡，这样发射极/基极PN结在纵向推进到LDD区域。
工艺步骤7：如图1所示，形成基极、发射极的金属接触，形成集电极深孔接触，从而形成本发明所设计的寄生垂直型PNP管。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (2)

1.一种BiCMOS工艺中的寄生垂直型PNP器件，其特征在于，有源区由浅槽场氧隔离，包括：
一集电区，由形成于有源区中的一P型杂质离子注入层构成，集电极是通过一深孔接触引出，所述集电区底部连接一P型埋层，所述P型埋层是通过离子注入形成于所述集电区两侧的浅槽底部，所述P型埋层在退火过程中纵向和横向扩散进入到所述有源区中实现和所述集电区底部连接，所述P型赝埋层的顶部和所述浅槽场氧相接触，通过在所述P型埋层顶部对应的浅槽场氧中制作深孔并填入金属形成连接所述P型埋层的所述深孔接触；
一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层构成；该离子注入采用NMOS管的N型轻掺杂漏区注入来实现；
一发射区，由形成于所述基区上部的一P型外延层构成，所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，该P型外延层采用P型掺杂的NPN三极管基区外延层工艺实现，所述发射区直接通过一金属接触引出；
所述基区上部的P型外延层部分反型为N型，反型为N型的部分所述P型外延层形成N型外延层，该N型外延层用作所述基区的连接；在所述N型外延层上形成有N型的多晶硅层，该多晶硅层和一金属接触相连接引出所述基区；利用所述多晶硅层的N型杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，而使所述P型外延层反型为所述N型外延层。
2.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP器件，其特征在于：所述集电区的P型埋层离子注入的剂量为1e14～1e16cm-2的、能量为小于45keV。
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