CN102097465B - BiCMOS工艺中的寄生垂直型PNP三极管及其制造方法 - Google Patents
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000003672 processing method Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 238000005516 engineering process Methods 0.000 claims description 42
- 239000012535 impurity Substances 0.000 claims description 42
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L21/8248—Combination of bipolar and field-effect technology
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
Abstract
本发明公开了一种BiCMOS工艺中的寄生垂直型PNP三极管，包括：集电区、基区和发射区。集电区由有源区中的P型杂质离子注入层即NMOS的P阱构成，底部连接一形成于浅槽底部的P型导电区，通过P型导电区和集电区相邻的有源区的连接引出集电区。基区由集电区上部的N型杂质离子注入层即NMOS的NLDD构成，通过基区上部的N型多晶硅引出。发射区为形成于基区上部的P型外延层构成，并通过NPN管的非本征基区注入连接出去。本发明还公开了该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法。本发明器件能用作高速、高增益BiCMOS电路中的输出器件、为电路提供多一种器件选择；本发明还能降低生产成本。
Description
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种BiCMOS工艺中的寄生垂直型PNP三极管，本发明还涉及该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法。
背景技术
现有的Bipolar采用高掺杂的集电区埋层，以降低集电区电阻，采用高浓度高能量N型注入，连接集电区埋层，形成集电极引出端(collectorpick-up)。集电区埋层上外延中低掺杂的集电区，在位P型掺杂的外延形成基区，然后重N型掺杂多晶硅构成发射极，最终完成bipolar的制作。
发明内容
本发明所要解决的技术问题是提供一种BiCMOS工艺中的寄生垂直型PNP三极管，能用作高速、高增益BiCMOS电路中的输出器件，为电路提供多一种器件选择；本发明还提供该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，无须额外的工艺条件，能够降低生产成本。
为解决上述技术问题，本发明提供的BiCMOS工艺中的寄生垂直型PNP三极管的有源区由浅槽场氧隔离，包括：一集电区，由形成于有源区中的一P型杂质离子注入层构成，该P型杂质离子注入层采用P阱中的抗穿通注入和阈值调节注入；所述集电区底部连接一P型导电区，所述P型导电区为通过P型杂质离子注入形成于所述集电区两侧的浅槽底部的P型赝埋层，所述P型导电区离子注入剂量为1e14～1e16cm-2、能量为小于15keV、注入杂质为B、BF2或In，所述P型导电区还和第二个有源区相连，所述第二个有源区为和所述第一个有源区通过所述P型导电区所对应的沟槽相隔离的有源区，通过在所述第二个有源区形成P型杂质离子注入层并做金属接触引出所述集电区。一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层构成，所述基区的N型杂质离子注入层是采用NMOS管的NLDD注入形成，注入的杂质为磷或者砷、能量条件为1-100Kev、剂量为1e11-1e15Kev，注入深度和剂量以满足NMOS管的性能为要求。一发射区，由所述基区上部的P型外延层构成，该P型外延层采用NPN晶体管的基区外延层的生长工艺形成，厚度小于5000
掺杂杂质为硼、硼峰值浓度为1e17-1e20cm-2，其厚度以及杂质的分布的具体值由Bipolar的性能决定，直接通过一金属接触引出。所述基区是通过形成于其上部的N型重掺杂多晶硅进行连接，并通过所述多晶硅上做金属接触引出所述基区；所述基区上部的N型重掺杂多晶硅的形成方法为：先把所述基区上部的P型外延层中用于基区连接区域的外延层刻掉或减薄，也可以有硅的过刻蚀；在其上面淀积一层多晶硅、该多晶硅为N型在位掺杂或者不掺杂；然后进行N型源漏的重型掺杂注入；并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，实现与所述基区的连接。
本发明提供的BiCMOS工艺中的寄生垂直型PNP三极管的制造方法为：
在硅衬底上形成有源区和浅槽；
形成集电区的P型导电区，是通过在所述浅槽底部注入P型杂质离子形成的，所述导电区离子注入剂量为1e14～1e16cm-2、能量为小于15keV、注入杂质为B、BF2或In；
形成浅槽场氧；
形成集电区，通过在所述有源区中进行P型杂质离子注入形成，该注入采用P阱中的抗穿通注入和阈值调节注入，利用退火工艺使所述集电区的P型导电区横向扩散到所述有源区并和所述集电区相连接；
形成基区，通过在所述集电区上部进行N型杂质离子注入形成，采用NMOS管的NLDD注入，注入的杂质为磷或者砷，能量条件为1-100Kev、剂量为1e11-1e15Kev，注入深度和剂量的具体值以满足NMOS管的性能为要求；
形成发射区，通过在所述基区上部生长一P型外延层形成，形成该P型外延层采用NPN晶体管的基区外延层工艺，厚度小于5000掺杂杂质为硼、硼峰值浓度为1e17-1e20cm-2，其厚度以及杂质的分布的具体值由Bipolar的性能决定；
形成所述基区上部形成所述基区的重掺杂多晶硅连接，方法为：先把所述基区上部的P型外延层中用于基区连接区域的外延层刻掉或减薄，也可以有硅的过刻蚀；在其上面淀积一层多晶硅、该多晶硅为N型在位掺杂或者不掺杂；然后进行N型源漏的重型掺杂注入；并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，实现与所述基区的连接；
形成所述集电区、基区和发射区的金属接触。
本发明的BiCMOS工艺中的寄生垂直型PNP三极管，具有较大的电流放大系数和较好的频率特性，能用作高速、高增益BiCMOS电路中的输出器件，为电路提供多一种器件选择；由于本发明的BiCMOS工艺中的寄生垂直型PNP三极管的制造方法涉及BiCMOS工艺中的埋层作埋层，NLDD注入，基区外延层，源漏多晶硅和N型源漏注入，无须额外的工艺条件，本发明也避免了现有BiCMOS工艺中的寄生三极管中埋层工艺、集电区外延工艺、深槽隔离工艺，以上原因使得本发明能够降低成本。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明的BiCMOS工艺中的寄生垂直型PNP三极管的结构示意图；
图2A-图2G是本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管在制造过程中的结构示意图；
图3A是TCAD模拟的本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管的Gummel曲线；
图3B是TCAD模拟的本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管的增益曲线。
具体实施方式
如图1所述为本发明的BiCMOS工艺中的寄生垂直型PNP三极管的结构示意图，有源区由浅槽场氧隔离即图1中的浅沟槽隔离，包括：一集电区802、一基区803、一发射区804。
所述集电区803，由形成于有源区中的一P型杂质离子注入层构成，该P型杂质离子注入层采用P阱中的抗穿通注入和阈值调节注入；所述集电区底部连接一P型导电区801，所述P型导电区801为通过P型杂质离子注入形成于所述集电区802两侧的浅槽底部的P型赝埋层，所述P型导电区801离子注入剂量为1e14～1e16cm-2、能量为小于15keV、注入杂质为B、BF2或In，所述P型导电区801还和第二个有源区相连，所述第二个有源区为和所述第一个有源区通过所述P型导电区801所对应的沟槽相隔离的有源区，通过在所述第二个有源区形成P型杂质离子注入层802并做金属接触引出所述集电区802。
所述基区803，由形成于所述集电区802上部并和所述集电区802连接的一N型杂质离子注入层构成，所述基区803的N型杂质离子注入层是采用NMOS管的NLDD注入形成，注入的杂质为磷或者砷，注入深度和剂量以满足NMOS管的性能为要求。
所述发射区804，由所述基区803上部的P型外延层构成，所述发射区804的掺杂杂质为硼，其厚度以及杂质的分布情况由Bipolar的性能决定，直接通过一金属接触引出。
所述基区803是通过形成于其上部的N型重掺杂多晶硅807进行连接，并通过所述多晶硅807上做金属接触引出所述基区803；所述基区803上部的N型重掺杂多晶硅807的形成方法为：先把所述基区上部的P型外延层中用于基区连接区域的外延层刻掉或减薄，也可以有硅的过刻蚀，而对所述发射区则生长介质层氧化层805和氮化硅806进行保护；在其上面淀积一层多晶硅、该多晶硅为N型在位掺杂或者不掺杂；然后进行N型源漏的重型掺杂注入；并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，实现与所述基区的连接。
如图2A-图2G所示，为本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管在制造过程中的结构示意图，包括如下工艺步骤：
工艺步骤1、如图2A所示，选用轻掺杂的P型衬底硅片，用浅沟槽刻蚀作隔离工艺。在浅沟槽刻蚀之后，进行一道剂量为1e14～1e16cm-2、能量为小于15keV的P型杂质注入用以形成埋层即为导电区801。在本发明所设计的寄生垂直型PNP管中，埋层801可以有效地实现集电区的低阻连接。
工艺步骤2、如图2B所示，在浅沟槽隔离和埋层801形成之后，进行P阱注入中的抗穿通注入和阈值调节注入形成集电区802以及集电极引出区即与所述集电区通过所述浅槽相隔离的有源区802。然后进行热退火，埋层801在退火过程中的纵向和横向扩散进入到其两侧的有源区并和所述集电区802以及集电极引出端的有源区202相连接，这有助于减少集电区的连接电阻。
工艺步骤3、如图2C所示，对P型集电区802进行NLDD的注入，用于形成寄生垂直型PNP管的基区803，用合适的光阻定义注入区。
工艺步骤4、如图2D所示，淀积一层氧化膜和多晶硅(可选)，然后进行刻蚀将集电区打开。在对硅表面进行预清洁之后进行P型外延层的生长。在单晶硅表面外延生长的结果是形成硅单晶804；而在其他区域，外延生长所形成的是多晶硅805。
工艺步骤5、如图2E所示，将基区803连出区域的硅或多晶硅外延805刻蚀掉或者减薄，刻蚀后所剩区域为发射区804的硅单晶层，刻蚀厚度可以按工艺进行调整，以达到工艺稳定，并且保证基区803的连接.
工艺步骤6、如图2F所示，淀积一层20纳米氧化层805和30纳米左右的氮化硅806，然后刻蚀，留下所述发射区804上的氧化层805和氮化硅806，用于对所述发射区804的保护。采用淀积源漏多晶硅的工艺淀积一层多晶硅，这层多晶硅材料可以是N型在位搀杂，所掺杂质可选用磷或者砷。也可以淀积时不搀杂，而是通过淀积好之后的N型注入来改变其形态和减小其电阻，本实施例采用N型源漏的注入来搀杂。搀杂区域可用光阻来定义；对本实施例而言，也可以不用光阻，对这个区域进行普打。
工艺步骤7、如图2G所示，刻蚀多晶硅和电介质层(氮化硅806和氧化层805)，打开本实施例寄生垂直型PNP管的发射区804，同时保留发射区804两边的电介质层(氮化硅806和氧化层805)，实现其与多晶硅的隔离。刻蚀同时也保留了用于连接基极的多晶硅807。刻蚀完成之后，进行热处理，从而激活所述发射区804和基区803的引出多晶硅807。
工艺步骤8、如图1所示，采用现有的接触孔工艺和金属连线工艺实现对集电极，基极和发射极的连接，本发明实施例所设计的寄生垂直型PNP管最终形成。
如图3A和3B所示，分别为TCAD模拟的本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管的Gummel曲线和增益曲线，本发明实施例中所述发射区是用SiGe HBT的基区外延层形成、其外延掺杂是锗和硼。从曲线可以看出：通过浅槽低能量注入的埋层减少了集电极连接电阻；源漏多晶硅实现对N型基区的连接；外延层作为发射区，有效地与基区(NLDD注入区)形成发射区-基区结。器件的最大增益也实现了16以上。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。
Claims (12)
1.一种BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于，有源区由浅槽场氧隔离，包括：
一集电区，由形成于第一有源区中的一P型杂质离子注入层构成，该P型杂质离子注入层为CMOS工艺中的NMOS的P阱，所述集电区底部连接一P型导电区，所述P型导电区为通过P型杂质离子注入形成于所述集电区两侧的浅槽底部的P型埋层，所述P型导电区还和第二个有源区相连，所述第二个有源区为和所述第一个有源区通过所述P型导电区所对应的沟槽相隔离的有源区，通过在所述第二个有源区形成P型杂质离子注入层并做金属接触引出所述集电区；
一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层即NMOS的NLDD注入层构成；
一发射区，由所述基区上部的P型外延层即NPN晶体管的基区外延层构成，直接通过一金属接触引出；
所述基区是通过形成于其上部的N型重掺杂多晶硅进行连接，并通过所述多晶硅上做金属接触引出所述基区。
2.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述集电区的P型杂质离子注入层采用P阱中的抗穿通注入和阈值调节注入。
3.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述集电区的P型导电区离子注入剂量为1e14～1e16cm-2、能量为小于15keV、注入杂质为B、BF2或In。
4.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述基区的N型杂质离子注入层是采用NMOS管的NLDD注入形成，注入的杂质为磷或者砷、能量条件为1-100Kev、剂量为1e11-1e15Kev。
5.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述发射区的P型外延层采用NPN晶体管的基区外延层的生长工艺形成，厚度小于 
掺杂杂质为硼、硼峰值浓度为1e17-1e20cm-2。
6.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述基区上部的N型重掺杂多晶硅的形成方法为：先把所述基区上部的P型外延层中用于基区连接区域的外延层刻掉或减薄；在其上面淀积一层多晶硅、该多晶硅为N型在位掺杂或者不掺杂；然后进行N型源漏的重型掺杂注入；并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，实现与所述基区的连接。
7.一种BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，其特征在于：
在硅衬底上形成有源区和浅槽；
形成集电区的P型导电区，是通过在所述浅槽底部注入P型杂质离子形成的；
形成浅槽场氧，所述浅槽场氧由填充于所述浅槽中的氧化层构成；
形成集电区，通过在所述有源区中进行P型杂质离子注入形成，利用退火工艺使所述集电区的P型导电区横向扩散到所述有源区并和所述集电区相连接；
形成基区，通过在所述集电区上部进行N型杂质离子注入形成；
形成发射区，通过在所述基区上部生长一P型外延层形成；
形成所述基区上部形成所述基区的重掺杂多晶硅连接；
形成所述集电区、基区和发射区的金属接触。
8.如权利要求7所述的BiCMOS工艺中的PNP三极管的制造方法，其特征在于：所述集电区的P型杂质离子注入采用P阱中的抗穿通注入和阈值调节注入。
9.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述集电区的P型导电区离子注入剂量为1e14～1e16cm-2、能量为小于15keV、注入杂质为B、BF2或In。
10.如权利要求7所述的BiCMOS工艺中的PNP三极管的制造方法，其特征在于：所述基区的N型杂质离子注入采用NMOS管的NLDD注入，注入的杂质为磷或者砷，能量条件为1-100Kev、剂量为1e11-1e15Kev。
11.如权利要求7所述的BiCMOS工艺中的PNP三极管的制造方法，其特征在于：形成所述发射区的P型外延层采用NPN晶体管的基区外延层工艺，厚度小于 
掺杂杂质为硼、硼峰值浓度为1e17-1e20cm-2。
12.如权利要求7所述的BiCMOS工艺中的PNP三极管的制造方法，其特征在于：形成所述基区的重掺杂多晶硅连接的方法为：先把所述基区上部的P型外延层中用于基区连接区域的外延层刻掉或减薄；在其上面淀积一层多晶硅、该多晶硅为N型在位掺杂或者不掺杂；然后进行N型源漏的重型掺杂注入；并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，实现与所述基区的连接。
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| CN102403344B (zh) * | 2010-09-10 | 2013-09-11 | 上海华虹Nec电子有限公司 | 锗硅BiCMOS工艺中的寄生PNP双极晶体管 |
| CN102412272B (zh) * | 2011-07-28 | 2013-09-11 | 上海华虹Nec电子有限公司 | BiCMOS工艺中的垂直寄生型PNP器件 |
| CN102437056A (zh) * | 2011-09-08 | 2012-05-02 | 上海华力微电子有限公司 | 互补金属氧化物半导体工艺中寄生垂直型pnp管的方法 |
| CN103066101B (zh) * | 2011-10-24 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | 锗硅hbt器件及制造方法 |
| CN103094328B (zh) * | 2011-11-07 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | 一种SiGe BiCMOS工艺中的寄生PNP器件结构及其制造方法 |
| CN102437180B (zh) * | 2011-11-21 | 2013-09-11 | 上海华虹Nec电子有限公司 | 超高压锗硅hbt器件及其制造方法 |
| CN103178086B (zh) * | 2011-12-21 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | 一种SiGe HBT工艺中的VPNP器件及其制造方法 |
| CN103050520B (zh) * | 2012-01-09 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | 一种SiGe HBT器件及其制造方法 |
| CN103050521B (zh) | 2012-05-23 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | 锗硅hbt器件的集电区引出结构及其制造方法 |
| CN103035689B (zh) | 2012-05-23 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | 锗硅hbt的集电区引出结构及其制造方法 |
| US9324846B1 (en) | 2015-01-08 | 2016-04-26 | Globalfoundries Inc. | Field plate in heterojunction bipolar transistor with improved break-down voltage |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5547893A (en) * | 1995-12-27 | 1996-08-20 | Vanguard International Semiconductor Corp. | method for fabricating an embedded vertical bipolar transistor and a memory cell |
| CN1398432A (zh) * | 2000-05-23 | 2003-02-19 | 松下电器产业株式会社 | 双极晶体管及其制造方法 |
| US7297992B1 (en) * | 2004-11-23 | 2007-11-20 | Newport Fab, Llc | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4339767A (en) * | 1980-05-05 | 1982-07-13 | International Business Machines Corporation | High performance PNP and NPN transistor structure |
| US5175607A (en) * | 1990-04-26 | 1992-12-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US6225181B1 (en) * | 1999-04-19 | 2001-05-01 | National Semiconductor Corp. | Trench isolated bipolar transistor structure integrated with CMOS technology |
| US20050250289A1 (en) * | 2002-10-30 | 2005-11-10 | Babcock Jeffrey A | Control of dopant diffusion from buried layers in bipolar integrated circuits |
| DE10327709A1 (de) * | 2003-06-21 | 2005-01-13 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit npn- und pnp-Bipolartransistoren sowie Herstellungsverfahren |
| TW200620478A (en) * | 2004-08-20 | 2006-06-16 | Koninkl Philips Electronics Nv | Self-aligned epitaxially grown bipolar transistor |
| US8129234B2 (en) * | 2009-09-09 | 2012-03-06 | International Business Machines Corporation | Method of forming bipolar transistor integrated with metal gate CMOS devices |
-
2009
- 2009-12-15 CN CN2009102019478A patent/CN102097465B/zh active Active
-
2010
- 2010-12-08 US US12/963,242 patent/US8598678B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5547893A (en) * | 1995-12-27 | 1996-08-20 | Vanguard International Semiconductor Corp. | method for fabricating an embedded vertical bipolar transistor and a memory cell |
| CN1398432A (zh) * | 2000-05-23 | 2003-02-19 | 松下电器产业株式会社 | 双极晶体管及其制造方法 |
| US7297992B1 (en) * | 2004-11-23 | 2007-11-20 | Newport Fab, Llc | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平10-223785A 1998.08.21 |
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