CN102110709B - BiCMOS工艺中的寄生垂直型PNP三极管及其制造方法 - Google Patents
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Abstract
本发明公开了一种BiCMOS工艺中的寄生垂直型PNP三极管，包括：集电区、基区和发射区。集电区由有源区中的P型杂质离子注入层构成，底部连接一形成于浅槽底部的P型埋层，通过P型埋层和集电区相邻的有源区的连接引出集电区。基区由集电区上部的N型杂质离子注入层构成，通过基区上部的P型外延层反型后引出。发射区为基区上部的P型外延层进行重掺杂后形成。本发明还公开了该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法。本发明器件能用作高速、高增益BiCMOS电路中的输出器件、为电路提供多一种器件选择；本发明还能降低生产成本。
Description
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种BiCMOS工艺中的寄生垂直型PNP三极管，本发明还涉及该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法。
背景技术
现有BiCMOS工艺中的寄生三极管采用高掺杂的集电区埋层，以降低集电区电阻，同时需要高温和长时间的炉管退火，以驱动杂质扩散的更深以减小埋层与硅衬底间的电容；采用浓度大于1e15cm-2的高浓度N型注入，连接集电区埋层，形成集电极引出端(collector pick-up)。集电区埋层上外延中低掺杂的集电区，在位P型掺杂的硅或者锗硅外延形成基区，然后由N型重掺杂的多晶硅构成发射极，并且用深槽隔离工艺来实现器件与器件之间的隔离。现有BiCMOS工艺中的寄生三极管设计，通常具有制作工艺成熟可靠等优点，但也由以下主要缺点：1、埋层需要高温和长时间的炉管退火；2、集电区外延成本高；3、深槽隔离工艺复杂，而且成本较高。
发明内容
本发明所要解决的技术问题是提供一种BiCMOS工艺中的寄生垂直型PNP三极管，能用作高速、高增益BiCMOS电路中的输出器件，为电路提供多一种器件选择；本发明还提供该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，无须额外的工艺条件，能够降低生产成本。
为解决上述技术问题，本发明提供的BiCMOS工艺中的PNP三极管的有源区由浅槽场氧隔离，包括：一集电区，由形成于第一个有源区中的一P型杂质离子注入层构成，所述集电区底部连接一P型埋层，所述P型埋层形成于所述集电区两侧的浅槽底部的，所述P型埋层还和第二个有源区相连，所述第二个有源区为和所述第一个有源区通过所述P型埋层所对应的沟槽相隔离的有源区，通过在所述第二个有源区形成P型杂质离子注入层并做金属接触引出所述集电区；一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层构成；一发射区，由所述基区上部的P型外延层构成，所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，所述发射区直接通过一金属接触引出；所述基区上部的P型外延层部分反型为N型，用作所述基区的连接。
所述集电区的P型杂质离子注入层是利用MOSFET中P阱注入工艺实现，此注入分三步，注入杂质为硼，第一步注入的剂量为1e12～5e13cm-2、能量为200～300keV；第二步注入的剂量为5e11～5e13cm-2、能量为25～200keV；第三步注入的剂量为1e11～1e13cm-2、能量为5～25keV；或者所述P型杂质离子注入层仅取上述的第二步与第三步注入形成。
所述基区的N型杂质离子注入层是采用NMOS管的NLDD注入形成，注入的杂质为磷或者砷、剂量为5e12～1e15cm-2、能量为10～60keV。
所述基区上部的P型外延层为本征掺杂、掺入的杂质为硼、掺杂方法采用NPN三极管的P型的基区外延层工艺；形成所述发射区的P型外延层要在本征掺杂的基础上再通过NPN三极管的非本征基区注入进行P型重掺杂，注入杂质为硼、氟化硼或者铟、剂量为5e12～1e15cm-2、能量为5～60keV。
所述基区上部的P型外延层部分反型为N型的方法为：在其上面淀积一层多晶硅，然后进行N型源漏的重型掺杂注入，并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，而使原来是P型外延层反型为N型，实现与N型基区的连接；所述N型源漏的重型掺杂注入分为两步，第一步注入杂质为磷、剂量为1e12～1e14cm-2、能量为20～60keV，第二步注入杂质为磷或者砷、剂量为1e14～1e16cm-2、能量为5～50keV。
本发明提供的该BiCMOS工艺中的寄生垂直型PNP三极管的制造方法包括：在硅衬底上形成有源区和浅槽；形成集电区的P型埋层，是通过在所述浅槽底部注入剂量为1e14～1e16cm-2的P型杂质离子形成的；形成浅槽场氧；形成集电区，通过在所述有源区中进行P型杂质离子注入形成，所述P型杂质离子注入采用MOSFET中P阱注入工艺，利用退火工艺使所述集电区的P型埋层横向扩散到所述有源区并和所述集电区相连接；形成基区，通过在所述集电区上部进行N型杂质离子注入形成；在所述基区上部形成P型外延层，并进行本征掺杂、所掺入的杂质为硼，所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，使所述基区上部的P型外延层部分反型为N型形成所述基区的连接；形成发射区，所述基区上部的P型外延层注入高剂量的P型杂质进行重掺杂形成，所注入高剂量的P型杂质是硼、氟化硼或者铟；形成所述集电区、基区和发射区的金属接触。
本发明的BiCMOS工艺中的寄生垂直型PNP三极管，具有大于15的电 流放大系数和较好的频率特性，能用作高速、高增益BiCMOS电路中的输出器件，为电路提供多一种器件选择；由于本发明的BiCMOS工艺中的寄生垂直型PNP三极管的制造方法涉及BiCMOS工艺中P阱注入、NLDD注入、NPN三极管的基区外延层，无须额外的工艺条件，能够降低成本；本发明也避免了现有BiCMOS工艺中的寄生三极管中埋层工艺、集电区外延工艺、深槽隔离工艺，使成本进一步降低。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明的BiCMOS工艺中的寄生垂直型PNP三极管的结构示意图；
图2A-图2F是本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管在制造过程中的结构示意图；
图3A是TCAD模拟的本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管的Gummel曲线；
图3B是TCAD模拟的本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管的增益曲线。
具体实施方式
如图1所述为本发明的BiCMOS工艺中的寄生垂直型PNP三极管的结构示意图，有源区由浅槽场氧隔离也即为图1中的浅沟槽隔离，包括：一集电区201、一基区301、一发射区602。
所述集电区201由形成于第一个有源区中的一P型杂质离子注入层构成，所述集电区201的P型杂质离子注入层利用BiCMOS工艺中的MOSFET 工艺中的P阱注入工艺实现，此注入分三步，注入杂质为硼，第一步注入的剂量为1e12～5e13cm-2、能量为200～300keV；第二步注入的剂量为5e11～5e13cm-2、能量为25～200keV；第三步注入的剂量为1e11～1e13cm-2、能量为5～25keV；或者所述P型杂质离子注入层仅取上述的第二步与第三步注入形成。所述集电区201底部连接一P型埋层101，所述P型埋层101形成于所述集电区201两侧的浅槽底部的，所述集电区201的P型埋层101是在所述浅槽形成后、场氧填入前在所述浅槽底部注入剂量为1e14～1e16cm-2的P型杂质离子形成的；在所述P型埋层101的P型杂质离子注入过程中，有源区通过在其顶部形成硬掩膜层和其侧壁形成氧化硅侧墙或者用光刻胶来做阻挡层，防止所述P型埋层101的P型杂质离子注入到有源区；通过所述P型埋层101的P型杂质离子的横向扩散，进入到有源区，其在所述有源区的深度和所述浅槽底部的深度一样。所述P型埋层101还和第二个有源区202相连，所述第二个有源区202为和所述第一个有源区通过所述P型埋层101所对应的沟槽相隔离的有源区，通过在所述第二个有源区202形成P型杂质离子注入层并做金属接触引出所述集电区201。
所述基区301，由形成于所述集电区201上部并和所述集电区201连接的一N型杂质离子注入层构成；所述基区301的N型杂质离子注入层是采用NMOS管的NLDD注入形成，注入的杂质为磷或者砷、剂量为5e12～1e15cm-2、能量为10～60keV。
所述发射区602，由所述基区301上部的P型外延层进行重掺杂后形成，所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，所述发射区602直接通过一金属接触引出。所述基区上部的P型外延层生长采用NPN三极管的P型的基区外延层工艺，掺杂为本征掺杂、掺入的杂质为硼；形成所述发射区602时要在本征掺杂的基础上再通过NPN三极管的非本征基区注入进行P型重掺杂，注入杂质为硼、氟化硼或者铟、剂量为5e12～1e15cm-2、能量为5～60keV。
所述基区301上部的P型外延层部分反型为N型，用作所述基区的连接；反型为N型的方法为：在其上面淀积一层多晶硅，然后进行N型源漏的重型掺杂注入，并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，而使原来是P型外延层反型为N型，最后形成如图1所示的多晶硅601，实现与N型基区的连接，所述多晶硅601再连接一金属接触引出所述基区。所述N型源漏的重型掺杂注入分为两步，第一步注入杂质为磷、剂量为1e12～1e14cm-2、能量为20～60keV，第二步注入杂质为磷或者砷、剂量为1e14～1e16cm-2、能量为5～50keV。
如图2A-图2F所示，为本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管在制造过程中的结构示意图。
工艺步骤一、如图2A所示，在硅衬底上形成有源区和浅槽即图2A中浅沟槽隔离中的浅沟槽；形成集电区的P型埋层101，是通过在所述浅槽底部注入剂量为1e14～1e16cm-2的P型杂质离子形成的，在所述P型埋层101的P型杂质离子注入过程中，有源区通过在其顶部形成硬掩膜层和其侧壁形成氧化硅侧墙或者用光刻胶来做阻挡层，防止所述P型埋层的P型杂质离子注入到有源区；形成浅槽场氧，即在图2A中浅沟槽隔离中填入场氧。
工艺步骤二、如图2B所示，形成集电区201，在所述有源区中进行P型杂质离子注入形成，所述P型杂质离子注入采用MOSFET中P阱注入工艺，此注入分三步，注入杂质为硼，第一步注入的剂量为1e12～5e13cm-2、能量为200～300keV；第二步注入的剂量为5e11～5e13cm-2、能量为25～200keV；第三步注入的剂量为1e11～1e13cm-2、能量为5～25keV；或者仅取上述的第二步与第三步注入。形成所述集电区201的同时在其浅槽隔离的另一侧的有源区202也进行了P型杂质离子注入形成所述集电区201的引出区。利用退火工艺使所述集电区201的P型埋层101通过纵向和横向扩散进入到所述有源区并和所述集电区201和有源区202相连接。
工艺步骤三、如图2C所示，形成基区301，通过在所述集电区201上部进行N型杂质离子注入形成，所述N型杂质离子注入采用形成N型MOSFET中的LDD注入工艺，注入的杂质为磷或者砷、剂量为5e12～1e15cm-2、能量为10～60keV，其注入区用光阻定义。
工艺步骤四、如图2D所示，先淀积一层氧化膜404和多晶硅，该多晶硅层也可不做，利用刻蚀工艺将集电区打开即去除所述基区301上部生长的氧化膜404和多晶硅，再在所述基区301上部形成P型外延层，采用NPN三极管的P型的基区外延层工艺，掺杂为本征掺杂、掺入的杂质为硼，形成于基区301上部和基区连接P型外延层401为单晶结构、和场氧连接的P型外延层402为多晶结构，所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层之一。
工艺步骤五、如图2E所示，P型外延层401和402上形成10～50纳米厚的氧化硅层501和10～50纳米厚的氮化硅层502，然后刻蚀，仅 留下所述P型外延层401上的氧化硅层501和氮化硅层502，从而实现所述发射区401与随后淀积的150～350纳米多晶硅503的隔离，用以作为所述发射区602的屏蔽层，氧化硅层501和氮化硅层502所覆盖的区域可以与有源区即集电区201一样大小或者比有源区小，也可以比有源区大，但不能大太多。采用N型在位掺杂或不掺杂在所述P型外延层402以及所述P型外延层401的屏蔽层上淀积一层150～350纳米厚多晶硅503，所掺杂质可选用磷或者砷。然后再通过高剂量N型注入来改变所述多晶硅503的形态和减小其电阻，所述N型注入可以是单独的对此多晶硅503的注入，也可以在NMOS的源漏注入时一起注入，或者两个注入都注入到这个多晶硅区域。掺杂区域可用光阻来定义；仅仅对本发明所述的BiCMOS工艺中的寄生垂直型PNP三极管而言，也可以不用光阻，对这个区域进行普注。所述N型源漏的重型掺杂注入即NMOS的源漏注入分为两步，第一步注入杂质为磷、剂量为1e12～1e14cm-2、能量为20～60keV，第二步注入杂质为磷或者砷、剂量为1e14～1e16cm-2、能量为5～50keV。
工艺步骤六、如图2F所示，形成发射区602，由所述P型外延层401未反型部分再注入高剂量的P型杂质进行重掺杂后形成。刻蚀氧化硅层603即图2E所示的氧化硅层501、氮化硅层604即图2E所示的氮化硅层502以及其上面的多晶硅层，形成一发射区602的窗口，通过该窗口对所述发射区602注入高剂量的P型杂质进行重掺杂，所注入高剂量的P型杂质是硼、氟化硼或者铟，这步注入可以使用NPN三极管的非本征基区注入，注入剂量为5e12～1e15cm-2、能量为5～60keV。利用退火最终形成所述发射区602。所述发射区602的掺杂浓度大于通过NLDD掺杂的所述基区301 的掺杂浓度，使形成的发射区和基区间的PN结在纵向推进到LDD区域。同时退火推进使所述多晶硅503的N型杂质发生纵向和横向的扩散，使所述P型外延层402及与其相连的所述P型外延层401的边缘部分反型为N型外延层，反型后形成N型多晶硅601，通过所述N型多晶硅601和所述基区301相连。最后，如图1所示，通过有源区202、反射区602、在所述N型多晶硅601上做金属接触分别引出所述集电区201、发射区602和基区301。
如图3A和3B所示，分别为TCAD模拟的本发明实施例的BiCMOS工艺中的寄生垂直型PNP三极管的Gummel曲线和增益曲线，可以看出：通过浅槽高剂量注入的杂质有效地减少了集电极连接电阻；用于连接基区的呈多晶态的P型硅外延层、锗硅外延层或者锗硅碳外延层被有效地反型成N型并成功实现对N型基区的连接；硅外延层、锗硅或者锗硅碳外延层作为发射区，有效地与NLDD注入形成的基区形成发射区-基区结。器件的最大增益也实现了16以上。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。
Claims (9)
1.一种BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于，有源区由浅槽场氧隔离，包括：
一集电区，由形成于第一个有源区中的一P型杂质离子注入层构成，所述集电区底部连接一P型埋层，所述P型埋层形成于所述集电区两侧的浅槽底部，所述P型埋层还和第二个有源区相连，所述第二个有源区为和所述第一个有源区通过所述P型埋层所对应的浅槽相隔离的有源区，通过在所述第二个有源区形成P型杂质离子注入层并做金属接触引出所述集电区；
一基区，由形成于所述集电区上部并和所述集电区连接的一N型杂质离子注入层构成；
一发射区，由所述基区上部的P型外延层构成，所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层，所述发射区直接通过一金属接触引出；
所述基区上部的P型外延层部分反型为N型，用作所述基区的连接；
所述集电区的P型杂质离子注入层是利用MOSFET中P阱注入工艺实现，此注入分三步，注入杂质为硼，第一步注入的剂量为1e12～5e13cm-2、能量为200～300keV；第二步注入的剂量为5e11～5e13cm-2、能量为25～200keV；第三步注入的剂量为1e11～1e13cm-2、能量为5～25keV；或者所述P型杂质离子注入层仅取上述的第二步与第三步注入形成。
2.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述集电区的P型埋层离子注入剂量为1e14～1e16cm-2。
3.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述基区的N型杂质离子注入层是采用NMOS管的NLDD注入形成，注入的杂质为磷或者砷、剂量为5e12～1e15cm-2、能量为10～60keV。
4.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述基区上部的P型外延层为本征掺杂、掺入的杂质为硼、掺杂方法采用NPN三极管的P型的基区外延层工艺；形成所述发射区的P型外延层要在本征掺杂的基础上再通过NPN三极管的非本征基区注入进行P型重掺杂，该注入杂质为硼、氟化硼或者铟、剂量为5e12～1e15cm-2、能量为5～60keV。
5.如权利要求1所述的BiCMOS工艺中的寄生垂直型PNP三极管，其特征在于：所述基区上部的P型外延层部分反型为N型的方法为：在其上面淀积一层多晶硅，然后进行N型源漏的重型掺杂注入，并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，而使原来是P型外延层反型为N型，实现与N型基区的连接；所述N型源漏的重型掺杂注入分为两步，第一步注入杂质为磷、剂量为1e12～1e14cm-2、能量为20～60keV，第二步注入杂质为磷或者砷、剂量为1e14～1e16cm-2、能量为5～50keV。
6.一种BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，其特征在于：
在硅衬底上形成有源区和浅槽；
形成集电区的P型埋层，是通过在所述浅槽底部注入剂量为1e14～1e16cm-2的P型杂质离子形成的；
形成浅槽场氧；
形成集电区，通过在所述有源区中进行P型杂质离子注入形成，所述P型杂质离子注入采用MOSFET中P阱注入工艺，利用退火工艺使所述集电区的P型埋层横向扩散到所述有源区并和所述集电区相连接；所述集电区的P型杂质离子注入采用MOSFET中P阱注入工艺，此注入分三步，注入杂质为硼，第一步注入的剂量为1e12～5e13cm-2、能量为200～300keV；第二步注入的剂量为5e11～5e13cm-2、能量为25～200keV；第三步注入的剂量为1e11～1e13cm-2、能量为5～25keV；或者仅取上述的第二步与第三步注入；
形成基区，通过在所述集电区上部进行N型杂质离子注入形成；
在所述基区上部形成P型外延层，并进行本征掺杂、所掺入的杂质为硼；所述P型外延层为硅外延层、锗硅外延层或者锗硅碳外延层；使所述基区上部的P型外延层部分反型为N型；
形成发射区，所述基区上部的P型外延层注入高剂量的P型杂质进行重掺杂形成，所注入高剂量的P型杂质是硼、氟化硼或者铟；
形成所述集电区、基区和发射区的金属接触。
7.如权利要求6所述的BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，其特征在于：所述基区的N型杂质离子注入采用NMOS管的NLDD注入，注入的杂质为磷或者砷、剂量为5e12～1e15cm-2、能量为10～60keV。
8.如权利要求6所述的BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，其特征在于：在所述基区上部形成P型外延层采用NPN三极管的P型的基区外延层工艺，其本征掺杂、厚度以及杂质的分布情况由NPN三 极管的性能决定；所述发射区的重掺杂采用NPN三极管的非本征基区注入工艺，该注入杂质为硼、氟化硼或者铟、剂量为5e12～1e15cm-2、能量为5～60keV。
9.如权利要求6所述的BiCMOS工艺中的寄生垂直型PNP三极管的制造方法，其特征在于：所述基区上部的P型外延层部分反型为N型的方法为：在其上面淀积一层多晶硅，然后进行N型源漏的重型掺杂注入，并利用杂质在多晶硅中的高温快速扩散特性，借助热退火推进杂质均匀分布整个多晶硅，而使原来是P型外延层反型为N型，实现与N型基区的连接；所述N型源漏的重型掺杂注入分为两步，第一步注入杂质为磷、剂量为1e12～1e14cm-2、能量为20～60keV，第二步注入杂质为磷或者砷、剂量为1e14～1e16cm-2、能量为5～50keV。
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| CN103165667B (zh) * | 2011-12-09 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | 锗硅hbt工艺中垂直寄生型pnp三极管及制作方法 |
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| CN1398432A (zh) * | 2000-05-23 | 2003-02-19 | 松下电器产业株式会社 | 双极晶体管及其制造方法 |
| US7297992B1 (en) * | 2004-11-23 | 2007-11-20 | Newport Fab, Llc | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process |
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