CN107742645A - 具有自对准体区的ldmos器件的制造方法 - Google Patents

具有自对准体区的ldmos器件的制造方法 Download PDF

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CN107742645A
CN107742645A CN201710842708.5A CN201710842708A CN107742645A CN 107742645 A CN107742645 A CN 107742645A CN 201710842708 A CN201710842708 A CN 201710842708A CN 107742645 A CN107742645 A CN 107742645A
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semiconductor substrate
layer
area
body area
gate
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乔伊·迈克格雷格
肖德明
姚泽强
吉杨永
郑志星
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

公开了一种LDMOS器件的制造方法，包括：形成半导体衬底；在半导体衬底上形成介质层；在介质层上形成导电层；在导电层上形成第一光刻胶层；通过第一掩膜对第一光刻胶层进行刻印，以形成第一开口；通过第一开口对导电层进行刻蚀；通过第一开口向半导体衬底中注入具有第一掺杂类型的杂质，以形成靠近半导体衬底上表面的第一体区和位于第一体区之下的第二体区；去除第一光刻胶层；以及使用第二光刻胶层和第二掩膜对导电层进行刻蚀。

Description

具有自对准体区的LDMOS器件的制造方法
技术领域
本发明涉及半导体器件，特别涉及LDMOS器件(Laterally Diffused Metal OxideSemiconductor Device)的制造方法。
背景技术
作为集成电路制造工艺的一部分，在LDMOS功率晶体管的制作过程中，考虑到性能和成本因素，需要功率晶体管尽可能小。此外，出于成本的原因，还需要尽量减少制作过程中所使用到的光刻步骤。
图1示出现有的LDMOS晶体管的截面图。功率LDMOS晶体管通常被布局为非常宽的条状，由条状源极区和条状漏极区交替而成。LDMOS有源极区的面积即为总宽度与半间距(Halfpitch)之积，其中半间距如图1所示，为条状源极区的中心与条状漏极区的中心之间的距离。
在条状源极区中分别制作有重掺杂的N+和P+区域以分别接触源极区和体区。在N+和P+区域下方有一个P型浅体区，该P型浅体区在多晶硅栅下方的侧向扩散决定了LDMOS的沟道。用于形成该区域的离子注入非常浅，使得多晶硅栅足以构成有效的离子注入阻挡层，这意味着该浅体区能与多晶硅栅的边沿构成自对准。
此外，在条状源极区内还需要一P型深体区，以增大体区与漏极区之间PN结(体/漏结)的曲率半径，并降低位于N+源极区下的体区的电阻值，从而防止在高漏极电压的情况下因寄生NPN晶体管导通而造成的器件损坏。
形成深体区的离子注入必须具有高达约0.5um的投影射程，而LDMOS的多晶硅栅的厚度通常为0.1-0.3um，因而不足以阻挡深体区离子注入。因此，深体区必须通过专门的光刻步骤、使用至少0.8um厚的光刻胶层来实现。该光刻步骤可以在多晶硅栅制作之前进行(参见图2a所示的简化工艺流程)，也可以在多晶硅栅制作之后进行(如图2b所示)。无论采用哪种方式，由于深体区和多晶硅栅是由两个不同的掩膜来定义，两者之间无法对准，它们之间的偏差在不同的晶片上不一样，在同一晶片上不同的位置也不相同。如果深体区的离子注入与多晶硅栅存在局部重叠，LDMOS的阈值电压将根据重叠情况不同有不同程度的增大。为了避免阈值电压的大幅度变化，深体区掩膜的开口必须位于多晶硅层的源区开口之内，且两者之间的距离必须大于深体区注入离子的侧向扩散距离与深体区掩膜和多晶硅栅掩膜之间最大偏差之和。这无疑会增大源/体区的最小尺寸。
减小阈值电压变化的另一种方式是使深体区与多晶硅栅之间的重叠尺寸远大于前述最大偏差，但这会导致器件的沟道长度和半间距均增大。
根据以上分析可以得出，功率集成电路制造领域们迫切需要一种半导体工艺，它既能有效缩小源/体区的面积从而缩少LDMOS的尺寸，同时又不会增加光刻步骤的总数量。
发明内容
本发明的实施例提供一种LDMOS器件的制造方法，包括：形成半导体衬底；在半导体衬底上形成介质层；在介质层上形成导电层；在导电层上形成第一光刻胶层；通过第一掩膜对第一光刻胶层进行刻印，以形成第一开口；通过第一开口对导电层进行刻蚀；通过第一开口向半导体衬底中注入具有第一掺杂类型的杂质，以形成靠近半导体衬底上表面的第一体区和位于第一体区之下的第二体区；去除第一光刻胶层；以及使用第二光刻胶层和第二掩膜对导电层进行刻蚀。
根据本发明实施例的一种制作于半导体衬底中的LDMOS器件，包括：形成于半导体衬底上的栅极氧化物区；形成于栅极氧化物区上的栅极多晶硅区；形成于半导体衬底中的具有第一掺杂类型的第一体区，其中该第一体区位于栅极多晶硅区的第一侧，并靠近半导体衬底的上表面；形成于第一体区下方的第二体区；形成于第一体区之内的具有第二掺杂类型的源极区；以及形成于半导体衬底中的具有第二掺杂类型的漏极区，其中该漏极区位于栅极多晶硅区的第二侧；其中栅极多晶硅区和第一体区以及第二体区是由同一掩膜定义，并自对准。
根据本发明实施例的一种LDMOS器件的制造方法，包括：形成半导体衬底；在半导体衬底上形成栅极氧化物层；在栅极氧化物层上形成栅极多晶硅层；使用第一掩膜对栅极多晶硅层进行刻蚀；使用第一掩膜向半导体衬底中注入具有第一掺杂类型的杂质，以形成靠近半导体衬底上表面的第一体区和位于第一体区之下的第二体区；使用第二掩膜对栅极多晶硅层进行刻蚀，以形成LDMOS的栅极区；在位于栅极区一侧的第一体区内形成具有第二掺杂类型的源极区；以及在栅极区的另一侧形成具有第二掺杂类型的漏极区。
本发明的实施例采用同一掩膜来进行多晶硅栅刻蚀和深体区离子注入，因而避免了现有技术中深体区掩膜和多晶硅栅掩膜之间的偏差造成的不利影响。此外，在深体区离子注入中栅极多晶硅层与光刻胶一起构成注入阻挡层，这可以减少光刻胶的厚度从而减小源区开口的最小尺寸，节约了硅片面积。
附图说明
以下将结合附图对本发明做进一步描述，其中相似的元件采用相似的标号。本领域技术人员可以理解，所有附图均是为了说明的目的。它们可能仅示出了器件的一部分，并且不一定是按比例绘制。
图1示出了现有的LDMOS的截面图；
图2a和2b为可用于制作图1所示器件的制造工艺的简化工艺流程图；
图3示出根据本发明实施例的具有自对准体区的LDMOS 300的截面图；
图4根据本发明实施例的LDMOS制造方法的简化工艺流程图；
图5a-5i示出处于图4所示制造方法中不同阶段的LDMOS的截面图。
图6示出根据本发明另一实施例的LDMOS 600的截面图；
图7示出与本发明又一实施例的具有沟槽源极接触的LDMOS 700的剖面图。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和、或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。在说明书或权利要求书中出现的“左”、“右”、“内”、“外”、“前”、“后”、“上”、“下”、“顶部”、“底部”、“之上”、“之下”或类似的描述，均仅是为了说明的目的，而非用于描述固定的相对位置。应当理解，以上术语在适当的情况下是可以互换的，从而使得相应的实施例可以在其它方向上正常工作。
在图1所示的现有LDMOS晶体管中，多晶硅栅和位于源/体区中心的P型深体区是经由两个不同的掩膜制作而成。为了确保阈值电压和导通电阻的变化处于可接受范围之内，多晶硅栅和P型深体区必须彼此分离，亦或相互重叠一段大于掩膜之间的最大偏差的距离。这两种解决方案具有很多缺点，例如源区开口大、多晶硅宽度长或导通电阻大。根据本发明实施例的LDMOS器件采用同一掩膜来进行多晶硅栅刻蚀和深体区离子注入，从而减小源区开口的最小尺寸，并降低阈值电压和导通电阻的变化。
图3示出根据本发明实施例的LDMOS 300的截面图。LDMOS 300形成于由P型初始衬底320、N+掩埋层(NBL)319和N阱318组成的半导体衬底内。该半导体衬底上可能还集成有其它的电路或器件，例如BJT和CMOS。在一些实施例中，半导体衬底可以具有其它的结构。例如，N+掩埋层是可选的，可以被省略。N阱318可以制作于淀积在初始衬底320上的N型外延层中，而非直接形成于初始衬底320之内。此外，在N阱318之下还可以进一步形成P型Resurf层。
LDMOS 300包括漏极区311、多晶硅栅区312以及栅极氧化物区313、源极区314、体接触区315、浅体区316以及深体区317。LDMOS 300通常被布局为非常宽的条状，由条状源极区和条状漏极区交替而成。通常情况下，在多晶硅栅区312的顶部和侧壁上形成有栅极密封氧化物，但这在其它实施例中可以被省略或被其它结构所替代。
重掺杂的源极区314和体接触区315均制作于浅体区316之内，以提供良好的欧姆接触。它们通常如图3所示，被布置为P+条状区域居中、N+条状区域位于两侧。然而，它们也可能采用其它排列形式，例如N+和P+在宽度方向上交替出现。
与图1所示的现有技术相比，LDMOS 300中的多晶硅栅刻蚀、浅体区离子注入和深体区离子注入均通过相同的掩膜实现，因此多晶硅栅区域312、浅体区316和深体区317是“自对准”的。通过这样做，LDMOS 300在多晶硅栅区域312的边缘下方形成了一个基本垂直的体/漏结。
图4为用以制造上述结构的半导体工艺的简化工艺流程图，而图5a-5i示出处于制作过程中不同阶段的LDMOS 300的截面图。
到制作多晶硅栅之前，该工艺流程均类似于图2b中所示的现有技术。前端制作可以包括制备初始衬底320、形成N+掩埋层319、定义有源区和形成N阱318，如图5a中所示。然后，如图5b所示，半导体衬底的上表面被氧化以形成栅极氧化物层313。接着，在图5c，淀积多晶硅以形成栅极多晶硅层312，该多晶硅层随后通过刻蚀被刻印为栅区。本领域技术人员均了解，栅极氧化物层313用作介质层，栅极多晶硅层313用作导电层，并且都可以由其他适合的材料来代替。
与现有技术不同，图4中体区的制作是在多晶硅栅刻蚀之前，通过光刻胶层321来完成。如图5d所示，在栅极多晶硅层312上形成光刻胶层321，然后使用一体区掩膜(bodymask)对其进行刻印以形成源区开口。此时硅片的其它区域均被光刻胶所覆盖。此步骤必须使用较厚的光刻胶，以确保栅极多晶硅层312和光刻胶层321的组合厚度足以阻挡具有最高能量的深体区离子注入。
随后，如图5e中所示，光刻胶层321被用于对栅极多晶硅层312进行刻蚀。然后，在光刻胶层321尚存的情况下，如图5f所示，通过源区开口进行深体区和浅体区的离子注入(受主离子，例如硼和铟)。
在去除光刻胶层321后，如图5g所示，淀积第二光刻胶层322，然后通过多晶硅栅掩膜对其进行刻印。该光刻胶层322被用于刻蚀多晶硅栅的另一侧。在如图5h中所示将光刻胶层322去除之后，该工艺流程如现有技术一样继续进行，包括多晶硅密封氧化、N+和P+注入及激活、硅化物形成、接触和后端工艺。图5i示出了在钨塞接触形成后的LDMOS器件的截面图。
可以对本发明能节省的硅片面积作粗略估计。在保证成本效益的情况下，可制作的最小光刻胶开口的尺寸约为光刻胶厚度T_block的三分之一。T_block的值由深体区离子注入的最高能量决定。如果深体区注入离子的侧向扩散距离加上深体区掩膜和多晶硅栅掩膜之间最大偏差为d，则现有技术中的最小源区开口尺寸约为：
(T_block/3)+2*d
而对于本发明的自对准方法而言，其中光刻胶的厚度可以大概减小多晶硅栅的厚度T_poly。因此，其最小源区开口尺寸约为：
(T_block-T_poly)/3
假设T_block为0.95um，T_poly为0.2um，d为0.15um，那么最小源区开口尺寸将从0.62um缩小到0.25um，这毫无疑问是一个非常显著的改变。
采用本发明提出的方法，深体区和浅体区的离子注入均通过同一掩膜来完成。如果在现有技术中的深体区掩膜是专用于LDMOS区域，那么本发明的方法将整个集成电路制造工艺中的光刻步骤减少了一步，这足以将硅片成本降低好几个百分点。
除了前述由于掩膜错位造成的局限之外，还存在另一个可能限制最小源区开口尺寸的因素，那就是在开口内形成三个不同的重掺杂表面区域(源极区和体接触区，N+/P+/N+)、并维持到源极区和体区的强欧姆接触所需的最小开口尺寸。
图6示出了根据本发明另一实施例的LDMOS，它消除了在源/体区内形成N+和P+区域的需要，从而减小了源/体区域的面积。
图6所示实施例中，与多晶硅栅自对准的浅体区和深体区横跨整个源区开口，在侧墙形成后(在多晶硅栅的侧壁形成的氧化物或氮化物侧墙，用于定义源极区)通过离子注入形成的N+源极区也横跨整个源区开口。位于浅体区316之内的N+源极区614的结深相当浅，通常在0.1um的量级。这是由于为了增大LDMOS的牢固度，位于N+源极区正下方的P型掺杂浓度相当高。
在LDMOS栅区和漏极区的硅化完成后，通过淀积形成金属前介质层623(也被称为接触介质)。该介质层由各种掺杂和未掺杂的氧化物、氮化物、氮氧化物和/或碳化物组成，将第一金属层与下面的器件隔离开来。
然后，形成光刻胶层，并通过沟槽接触掩膜在光刻胶层中沿着LDMOS所有源极区的中心形成长条状的沟槽接触开口。随后通过该开口对金属前介质层623进行刻蚀，例如，使用标准的接触刻蚀工艺。其后，位于沟槽接触开口内的硅被刻蚀掉，以形成一深度大于N+源极区614最大结深的沟槽，该沟槽的深度通常为0.15-0.2um。接着，去除光刻胶层，然后进行常规接触的定义和刻蚀。在用于形成常规接触的光刻胶被去除后，在硅片的顶部淀积接触衬垫624，以覆盖常规接触和沟槽接触的边缘以及底部。接触衬垫624通常包括钛粘合层和氮华钛阻挡层。随后，对硅片进行快速热退火，以减少残留在接触底部的含氧物，并使接触衬垫624在其后的钨淀积步骤作为扩散阻挡层。最后，通过化学气相淀积(CVD)填充钨，然后进行反向抛光以去除所有位于金属前介质层623上方的钨和接触衬垫。由于N+源极区614以及位于N+源极区614下方的浅体区316均具有足够高的掺杂浓度，以使得接触衬垫中的钛形成低阻硅化钛接触，因此对沟槽接触无需进行专门的硅化。
图6所示的沟槽源接触方案仅需要完全贯穿源区开口的N+区域，因此减小了源区开口尺寸。虽然在前述工艺流程中沟槽源接触形成于常规接触之前，但它也可以在常规接触形成之后完成。此外，用于形成钨塞接触的钨也可以用其它合适的金属代替。
在实际应用中，从小小的接触开口中去除光刻胶可能比较困难。因此，在在一些实施例中，刻蚀——去除光刻胶——淀积衬垫——快速热退火——钨CVD——平坦化的工艺步骤会重复两次，一次用于沟槽接触，另一次用于普通接触。
图7示出了根据本发明又一实施例的具有沟槽源接触的LDMOS 700，其中的栅极氧化物区713呈阶梯状，在靠近源极区的地方较薄而在靠近漏极区的地方较厚。对于低压器件而言，这样的设置并非必需，多晶硅栅可以完全位于薄的栅极氧化物层之上，如图3所示。
在图7中还进一步示出了位于整个有源器件下方的的P型“Resurf”层726。设置该P型区域的目的是为了从底部以及从源极侧耗尽N型漂移区(N阱)，以减小横向电场，从而增大击穿电压。在Resurf器件中，深体区必须深得足以与P型Resurf层726形成电接触。当击穿电压在20V以上时，该深度通常大于0.5um。
图7的器件700在多晶硅栅的下方还形成有浅N型区域725，作为LDMOS的实际源极区。这些浅浅的N型源极区可以和深体区以及浅体区一样，通过同一个光刻胶层注入形成。
应当注意的是，在前述实施例中各区域的掺杂类型均可以改变，例如，N型区域可以由P型区域代替，反之亦然。此外，N型掺杂物可以从以下物质中选取：氮、磷、砷、锑、铋以及它们的组合，而P型掺杂物可以以下物质中选取：硼、铝、镓、铟、铊及其组合。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

1.一种LDMOS器件的制造方法，包括：
形成半导体衬底；
在半导体衬底上形成介质层；
在介质层上形成导电层；
在导电层上形成第一光刻胶层；
通过第一掩膜对第一光刻胶层进行刻印，以形成第一开口；
通过第一开口对导电层进行刻蚀；
通过第一开口向半导体衬底中注入具有第一掺杂类型的杂质，以形成靠近半导体衬底上表面的第一体区和位于第一体区之下的第二体区；
去除第一光刻胶层；以及
使用第二光刻胶层和第二掩膜对导电层进行刻蚀。
2.如权利要求1所述的制造方法，其中形成半导体衬底的步骤包括：
在具有第一掺杂类型的初始衬底中形成具有第二掺杂类型的掩埋层。
3.如权利要求2所述的制造方法，其中形成半导体衬底的步骤还包括：
在初始衬底中形成具有第二掺杂类型的阱。
4.如权利要求2所述的制造方法，其中形成半导体衬底的步骤还包括：
在掩埋层上形成具有第一掺杂类型且与第二体区相接触的RESURF层。
5.如权利要求1所述的制造方法，其中介质层包括栅极氧化物层，导电层包括栅极多晶硅层。
6.如权利要求1所述的制造方法，还包括：
通过第一开口向半导体衬底内、浅于第一体区的位置注入具有第二掺杂类型的杂质。
7.如权利要求1所述的制造方法，还包括：
在导电层的侧壁形成侧墙；
向半导体衬底中注入具有第二掺杂类型的杂质，以在第一体区内形成源极区；
在半导体衬底上形成金属前介质层；
使用第三掩膜和第三光刻胶层对金属前介质层进行刻蚀，以形成第二开口；
将位于第二开口内的半导体衬底刻蚀至大于源极区最大结深的深度；
淀积接触衬垫并进行退火；以及
淀积金属并进行抛光。
8.一种制作于半导体衬底中的LDMOS器件，包括：
形成于半导体衬底上的栅极氧化物区；
形成于栅极氧化物区上的栅极多晶硅区；
形成于半导体衬底中的具有第一掺杂类型的第一体区，其中该第一体区位于栅极多晶硅区的第一侧，并靠近半导体衬底的上表面；
形成于第一体区下方的第二体区；
形成于第一体区之内的具有第二掺杂类型的源极区；以及
形成于半导体衬底中的具有第二掺杂类型的漏极区，其中该漏极区位于栅极多晶硅区的第二侧；
其中栅极多晶硅区和第一体区以及第二体区是由同一掩膜定义，并自对准。
9.如权利要求8所述的LDMOS器件，还包括：
形成于半导体衬底上的金属前介质层；
形成于金属前介质层和第一体区中的沟槽，其中该沟槽横向位于源极区的中心，而纵向由金属前介质层的上表面延伸至大于源极区最大结深的深度；
淀积于沟槽底部和侧壁的接触衬垫；以及
填充在沟槽中的金属。
10.一种LDMOS器件的制造方法，包括：
形成半导体衬底；
在半导体衬底上形成栅极氧化物层；
在栅极氧化物层上形成栅极多晶硅层；
使用第一掩膜对栅极多晶硅层进行刻蚀；
使用第一掩膜向半导体衬底中注入具有第一掺杂类型的杂质，以形成靠近半导体衬底上表面的第一体区和位于第一体区之下的第二体区；
使用第二掩膜对栅极多晶硅层进行刻蚀，以形成LDMOS的栅极区；
在位于栅极区一侧的第一体区内形成具有第二掺杂类型的源极区；以及
在栅极区的另一侧形成具有第二掺杂类型的漏极区。
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