CN104637811B - 晶体管制造方法和晶体管 - Google Patents
晶体管制造方法和晶体管 Download PDFInfo
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Abstract
本发明提供了一种晶体管制造方法和一种晶体管,其中晶体管制造方法包括:在形成有第一氧化层和第一基区的衬底的表面生长第二氧化层,第二氧化层位于第一基区的上方;在第二氧化层上的第一预设区域形成发射区;在第二氧化层上的第二预设区域形成接触孔,其中,第二预设区域与第一预设区域不相交;对接触孔区域的第一基区的表层注入掺杂元素;对衬底进行热处理,以激活掺杂元素形成第二基区。本发明能够将浓基区光刻层和接触孔光刻层巧妙的进行工艺整合,实现了浓基区光刻层和接触孔光刻层两者的自对准关系,解决了浓基区与接触孔的对准偏差问题。
Description
技术领域
本发明涉及半导体器件制造技术领域,具体而言,涉及一种晶体管制造方法和一种采用该晶体管制造方法制造的晶体管。
背景技术
随着射频和无线通信技术的发展,高频晶体管被越来越多的使用。广义的高频晶体管包括高频双极型晶体管和高频场效应晶体管等类型,狭义的高频晶体管特指高频双极型晶体管(RF Bipolar,下文所述“高频晶体管”都特指高频双极型晶体管)。
衡量高频晶体管性能的最重要参数即其工作频率,为了提升高频晶体管的工作频率,在实践工艺中都采用小线条的梳状条形结构,并且采用多晶硅发射极结构。
图1是晶体管的剖面结构示意图,晶体管包括集电区、基区1004和发射区;集电区包括N型外延和N型衬底;发射区包括多晶硅和N型扩散区,其中N型扩散区是由多晶硅中的掺杂元素(磷或者砷)在高温环境下热扩散至基区1004表层形成的。为了提升工作频率,在发射区之外的基区1004中制作浓基区以减小基区电阻,实践工艺中,为了防止浓基区和发射区发生短路,两者之间设置某间隔距离(图中所示S)。基区1004和浓基区所在的区域为有源区,有源区的表面覆盖薄氧化层1006,有源区之外的区域(称之为场区)覆盖厚氧化层1002(厚氧化层也称之为场氧化层)。集电区、基区和发射区分别对应集电极、基极和发射极共三个金属电极,其中,集电极从N型衬底即芯片的背面引出(图中没有标示),发射极由多晶硅表面的金属引出,基极由浓基区表面的金属通过接触孔引出,接触孔是浓基区上方的氧化层窗口,为了保证接触孔电阻足够小,浓基区的宽度必须大于或等于接触孔的宽度(如图1中d1所示),否则接触孔偏离至基区的上方。基区的掺杂浓度比较低,接触孔电阻较大。
下面简单解释相关名词。所有半导体器件的制造工艺都是在晶圆上实施的,晶圆是圆形的半导体衬底(衬底材料为单晶硅、锗、锗硅等,衬底的直径为3英寸、4英寸、5英寸、6英寸、8英寸或12英寸)。在集成电路的晶圆制造工艺中,需要经历几次、十几次或几十次的光刻工艺,通过这些光刻工艺(及光刻工艺之后的离子注入、刻蚀等工艺)把掩模版上的图形一一复制到晶圆上,在半导体技术中,习惯把每“一次”光刻称之为“一层”光刻,把每一次光刻工艺及这一次光刻工艺之后的离子注入、刻蚀等工艺步骤合称为一个“光刻层”。光刻工艺的核心设备是光刻机。
在光刻工艺中,层与层之间的对准精度非常重要。层与层之间的对准偏差的理想值为0,但实践中必然会出现一定量值的对准偏差,当其中任何一层光刻出现超过额定规范的对准偏差时,会导致整个芯片失效。光刻工艺的对准操作是由光刻机采集一种叫做“对准标记”的光学标记的坐标来实现的,对准标记是在本层光刻之前的光刻工艺(称之为前层光刻)及光刻工艺之后的刻蚀、氧化等工艺过程中预留和制作在晶圆上设定坐标位置的剖面呈台阶状的光学标记。
传统工艺中,晶体管的制作工艺包括:
1、制作厚氧化层1002和基区:在生长有N型外延的N型衬底的表面,通过光刻、刻蚀、氧化、离子注入等工艺步骤,在预设区域分别形成厚氧化层1002(场氧化层)和基区,形成如图2所示的半成品,厚氧化层1002覆盖的区域为场区,场区之外的区域为有源区,基区位于有源区所在区域。形成厚氧化层1002的光刻层称之为有源区光刻层,形成基区的光刻层称之为基区光刻层。
2、制作浓基区:通过光刻、离子注入、退火等工艺步骤,在预设区域形成浓基区,如图3所示。形成浓基区的光刻层称之为浓基区光刻层。
3、制作薄氧化层1006:在如图3所示的结构表面生长薄氧化层1006,见图4。
4、制作多晶硅发射极:通过光刻、刻蚀等工艺步骤,在预设区域形成氧化层窗口(称之为发射区窗口),然后生长多晶硅,并对多晶硅进行掺杂,然后通过光刻、刻蚀等工艺步骤,在所述氧化层窗口区域形成多晶硅发射极。前文所述,发射区与浓基区之间必须间隔设定距离,如图5所示,两者间隔距离为S。形成发射区窗口的光刻层称之为发射区光刻层,形成多晶硅发射极的光刻层称之为多晶硅光刻层。
5、高温热处理,以激活多晶硅中的掺杂元素,并使之热扩散至基区表层形成N型扩散区,如图6所示。
6、制作接触孔:通过光刻、刻蚀等工艺步骤,在预设区域形成氧化层窗口(即接触孔)。前文所述,浓基区的宽度必须大于或等于接触孔的宽度,如图7所示,浓基区的宽度比接触孔的宽度大(单边大d1的距离)。形成接触孔的光刻层称之为接触孔光刻层。
7、制作金属电极:通过金属淀积、光刻、刻蚀等工艺步骤,在预设区域形成发射极电极和基区电极,如图8所示。形成金属电极的光刻层称之为金属光刻层。
至此,高频晶体管的器件主体结构已经完成,后续工艺步骤,包括制作钝化保护层和背面的集电极金属电极等,都属于本领域常见的工艺,在此不做赘述。
以上传统晶体管制作方法,存在以下缺点:
1、光刻层次比较多:浓基区的制作需要单独的光刻层工艺实现(上述第2步),工艺成本较高;
2、晶体管的浓基区的宽度必须大于或等于接触孔的宽度,在以上传统方法中,浓基区和接触孔的制作是通过不同的光刻层实现的,而不同光刻层之间必然存在一定量值的对准偏差,为了保证在出现光刻对准偏差的情况下,接触孔仍然不偏离出浓基区所在的区域,必须在芯片设计时使得浓基区的宽度比接触孔的宽度大得足够多(如上述第6步中图7中所示的d1),这种做法导致芯片面积变大,成本较高。
3、晶体管的发射区与浓基区之间必须间隔设定距离,在以上传统方法中,浓基区光刻层和发射区光刻层是不同的光刻层,而且都是通过对准有源区光刻层预留的对准标记实现对准的,即浓基区光刻层和发射区光刻层是间接对准关系,而不是直接对准关系(直接对准关系是指两者分别是对准层和被对准层)。因为浓基区光刻层是在发射区光刻层之前完成的,但由于浓基区光刻层仅仅是在预设区域进行离子注入掺杂,没有包含可制作台阶状对准标记的工艺步骤,所以无法在浓基区光刻层预留和制作对准标记,也就是说发射区光刻必须对准有源区光刻层预留的对准标记以实现对准(与浓基区光刻层不是对准和被对准关系)。
由于这种间接对准的层与层之间的对准偏差比直接对准的更难控制,为了保证在出现较大对准偏差的情况下,发射区与浓基区之间仍然保持安全距离(以保证两者不短路),必须在芯片设计时使得发射区与浓基区之间的设定距离足够大,这种做法导致芯片面积较大,成本较高。
发明内容
本发明正是基于上述技术问题至少之一,提出了一种新的晶体管制造方法,能够巧妙地将浓基区光刻层和接触孔光刻层进行工艺整合,减少了光刻层工艺,并且避免了浓基区光刻层和发射区光刻层之间间接对准关系,减少了对准误差并节省了芯片面积。
根据本发明的一个方面,提供了一种晶体管制造方法,包括:在形成有第一氧化层和第一基区的衬底的表面生长第二氧化层,所述第二氧化层位于所述第一基区的上方;在所述第二氧化层上的第一预设区域形成发射区;在所述第二氧化层上的第二预设区域形成接触孔,其中,所述第二预设区域与所述第一预设区域不相交;对所述接触孔区域的第一基区的表层注入掺杂元素;对所述衬底进行热处理,以激活所述掺杂元素形成第二基区(浓基区)。
在根据本发明的实施例的晶体管制造方法中,先形成接触孔,然后在在接触孔区域中注入掺杂元素,形成浓基区。在这过程中仅有形成接触孔的光刻层,在形成浓基区时没有采用光刻层,因此节省了浓基区光刻层的工艺,降低了工艺成本。
由于浓基区和接触孔是通过同一光刻层实现的,因此两者之间不存在对准偏差的问题,也就不需要像传统方法那样在芯片设计时,使得浓基区的宽度必须比接触孔的宽度大得足够多,从而节省了芯片面积,降低成本。
另外,接触孔光刻层是在发射区光刻层之后制作的,在制作浓基区(即接触孔光刻)时可采取对准发射区光刻层预留和制作的对准标记以实现对准,即实现了浓基区光刻层与发射区光刻层两者的直接对准关系,其对准精度比传统方法中那种间接对准的精度更高,从而可以在芯片设计时设置更小的发射区与浓基区间隔距离,以节省芯片面积,降低成本。
根据本发明的另一方面,还提供了一种晶体管,所述晶体管由上述技术方案中所述的晶体管制造方法制作而成。
附图说明
图1示出了相关技术中的晶体管剖面结构示意图;
图2示出了相关技术中形成厚氧化层和基区之后的半成品剖面结构示意图;
图3示出了相关技术中形成浓基区之后的晶体管剖面结构示意图;
图4示出了相关技术中形成薄氧化层之后的晶体管剖面结构示意图;
图5示出了相关技术中形成多晶硅发射极之后的晶体管剖面结构示意图;
图6示出了相关技术中高温热处理之后的晶体管剖面结构示意图;
图7示出了相关技术中形成接触孔之后的晶体管剖面结构示意图;
图8示出了相关技术中形成金属电极之后的晶体管剖面结构示意图;
图9示出了根据本发明的实施例的晶体管制造方法的流程图;
图10示出了根据本发明的实施例的形成薄氧化层之后的晶体管剖面结构示意图;
图11示出了根据本发明的实施例的形成多晶硅发射极之后的晶体管剖面结构示意图;
图12示出了根据本发明的实施例的完成接触孔光刻之后的晶体管剖面结构示意图;
图13示出了根据本发明的实施例的形成接触孔以及完成硼离子注入之后的晶体管剖面结构示意图;
图14示出了根据本发明的实施例的经过高温热处理之后的晶体管剖面结构示意图;
图15示出了根据本发明的实施例的形成金属电极之后的晶体管剖面结构示意图。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点,下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是,在不冲突的情况下,本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是,本发明还可以采用其他不同于在此描述的其他方式来实施,因此,本发明并不限于下面公开的具体实施例的限制。
图9示出了根据本发明的实施例的晶体管制造方法的流程图。
如图9所示,根据本发明的实施例的晶体管制造方法可以包括以下步骤:
步骤902,在形成有第一氧化层和第一基区的衬底的表面生长第二氧化层,第二氧化层位于第一基区的上方;
步骤904,在第二氧化层上的第一预设区域形成发射区;
步骤906,在第二氧化层上的第二预设区域形成接触孔,其中,第二预设区域与第一预设区域不相交;
步骤908,对接触孔区域的第一基区的表层注入掺杂元素;
步骤910,对衬底进行热处理,以激活掺杂元素形成第二基区。
在根据本发明的实施例的晶体管制造方法中,先形成接触孔,然后在在接触孔区域中注入掺杂元素,形成浓基区。在这过程中仅有形成接触孔的光刻层,在形成浓基区时没有采用光刻层,因此节省了浓基区光刻层的工艺,降低了工艺成本。
由于浓基区和接触孔是通过同一光刻层实现的,因此两者之间不存在对准偏差的问题,也就不需要像传统方法那样在芯片设计时,使得浓基区的宽度必须比接触孔的宽度大得足够多,从而节省了芯片面积,降低成本。
另外,接触孔光刻层是在发射区光刻层之后制作的,在制作浓基区(即接触孔光刻)时可采取对准发射区光刻层预留和制作的对准标记以实现对准,即实现了浓基区光刻层与发射区光刻层两者的直接对准关系,其对准精度比传统方法中那种间接对准的精度更高,从而可以在芯片设计时设置更小的发射区与浓基区间隔距离,以节省芯片面积,降低成本。
在上述技术方案中,优选的,所述在所述第二氧化层上的第二预设区域形成接触孔的步骤具体可以包括:在形成有所述第一氧化层、所述第一基区、所述第二氧化层和所述发射区的衬底表面涂覆光刻胶;去除所述第二氧化层上的第二预设区域的光刻胶,在所述第二预设区域形成光刻胶窗口;刻蚀所述光刻胶窗口区域的第二氧化层,以形成所述接触孔。
在上述技术方案中,优选的,在所述对所述接触孔区域的第一基区的表层注入掺杂元素之后,在所述对所述衬底进行热处理之前,还可以包括:去除覆盖在所述晶体管半成品表面的剩余光刻胶。
在上述技术方案中,优选的,所述接触孔的底部与所述第一基区之间保留有预设厚度的第二氧化层。
为了减少刻蚀和离子注入工艺对基区的损伤,可以在接触孔底部保留少许氧化层。
在上述技术方案中,优选的,所述预设厚度为200埃~500埃。
在上述技术方案中,优选的,在所述对所述衬底进行热处理之后,还可以包括:采用氢氟酸溶液漂洗掉所述接触孔底部的所述预设厚度的第二氧化层。采用化学液去除接触孔底部残余的氧化硅层,可减少干法刻蚀对基区表面带来的损伤。
在上述技术方案中,优选的,在所述采用氢氟酸溶液漂洗掉所述接触孔底部的所述预设厚度的第二氧化层之后,还可以包括:在所述第二基区上和所述发射区上分别制作金属电极。
在上述技术方案中,优选的,所述第二氧化层的厚度小于所述第一氧化层的厚度。
本发明的实施例的晶体管,该晶体管由上述任一技术方案中所述的晶体管制造方法制作而成。
接下来结合图10至图15进一步说明根据本发明的又一实施例。
根据本发明的实施例的晶体管制造方法,可以包括以下处理过程:
首先,在形成有N型衬底、N型外延、厚氧化层(场氧化层,即第一氧化层)1002和基区(即第一基区)1004的半导体衬底表面,生长薄氧化层(即第二氧化层)1006,如图10所示。
所述包括有N型衬底、N型外延、厚氧化层(场氧化层)和基区的晶体管的半成品,其厚氧化层覆盖的区域为场区,场区之外的区域为有源区,基区位于有源区所在区域,所述厚氧化层的厚度为5000~30000埃。所述薄氧化层的厚度为1000~4000埃。
如图11所示,在薄氧化层1006上的预设区域形成发射区窗口,然后在所述发射区窗口区域形成多晶硅发射极1008,所述多晶硅发射极1008中掺有杂质元素磷或者砷。本步的具体工艺步骤与背景技术中描述的传统方法中的第4步相同,在此不再赘述。
接着进行接触孔光刻,以在薄氧化层表面的预设区域形成光刻胶窗口,具体包括:
如图12所示,在图11所示的结构表面涂覆光刻胶,然后通过光刻去除位于薄氧化层表面预设区域的光刻胶,形成光刻胶窗口,以露出预设区域的薄氧化层,保留预设区域之外的区域的光刻胶。
通过刻蚀去除所述光刻胶窗口区域的薄氧化层,形成氧化层窗口(即接触孔),并向所述光刻胶窗口区域的基区中注入硼离子,参见图13。
在刻蚀光刻胶窗口所在区域的薄氧化层的过程中,先采用垂直向下的等离子体干法刻蚀,刻蚀所述光刻胶窗口区域的薄氧化层至所述薄氧化层的剩余厚度小于某设定值(优选为200埃左右,即形成底部残留少许薄氧化层的氧化层窗口),然后采用离子注入工艺透过剩余的薄氧化层,向所述光刻胶窗口区域的基区中注入硼离子,然后采用化学腐蚀剂漂洗掉光刻胶窗口区域剩余的薄氧化层。这种处理方式可以减少刻蚀和离子注入工艺对基区表层的损伤。本领域内技术人员应理解,也可以在接触孔底部不保留少许的薄氧化层。
所述硼离子的注入剂量优选为1E15~1E16原子/平方厘米,注入能量为15~300千电子伏。
接着如图14所示,去除光刻胶,然后对半导体衬底进行高温热处理,以使得上一步骤中注入在基区中的硼离子激活并发生热扩散形成浓基区(即第二基区)1010,同时,以激活多晶硅中的掺杂元素(磷或者砷)并使之热扩散至基区表层形成N型扩散区。
如图15所示,制作金属电极。本步与传统方法相同,即通过金属淀积、光刻、刻蚀等工艺步骤,在预设区域形成发射极电极1012和基区电极1014。
至此,晶体管的的器件主体结构已经完成,后续工艺步骤,包括制作钝化保护层和背面的集电极金属电极等,都属于本领域常见工艺,在此不做赘述。
通过上述处理过程可知,在根据本发明的晶体管制造方法中,将浓基区光刻层和接触孔光刻层巧妙得进行工艺整合,在本发明中,两者整合为同一光刻层,即接触孔光刻层同时也是浓基区光刻层,从而减少了一个光刻层,降低了工艺成本。
其次,在本发明中,浓基区和接触孔是通过同一光刻层实现的,因此两者之间不存在对准偏差的问题,也就不需要像传统方法那样在芯片设计时,使得浓基区的宽度必须比接触孔的宽度大得足够多,从而节省了芯片面积,降低成本。
另外,在本发明中,浓基区光刻层(也即接触孔光刻层)是在发射区光刻层之后制作的,在浓基区光刻(即接触孔光刻)时,可使用发射区光刻层预留和制作的对准标记进行对准,即实现了浓基区光刻层与发射区光刻层两者的直接对准关系,其对准精度比传统方法中那种间接对准的精度更高,从而可以在芯片设计时,设置更小的发射区与浓基区间隔距离,以节省芯片面积,进而降低芯片成本。
尽管已描述了本发明的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例做出另外的变更和修改。所以,所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
以上仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (9)
1.一种晶体管制造方法,其特征在于,包括:
在形成有第一氧化层和第一基区的衬底的表面生长第二氧化层,其中,所述第二氧化层位于所述第一基区的上方;
在所述第二氧化层上的第一预设区域形成发射区;
在所述第二氧化层上的第二预设区域形成接触孔,其中,所述第二预设区域与所述第一预设区域不相交;
对所述接触孔区域的第一基区的表层注入掺杂元素;
对所述衬底进行热处理,以激活所述掺杂元素形成第二基区;
所述在所述第二氧化层上的第二预设区域形成接触孔的步骤具体包括:
在形成有所述第一氧化层、所述第一基区、所述第二氧化层和所述发射区的衬底表面涂覆光刻胶;
去除所述第二氧化层上的第二预设区域的光刻胶,在所述第二预设区域形成光刻胶窗口;
刻蚀所述光刻胶窗口区域的第二氧化层,以形成所述接触孔。
2.根据权利要求1所述的晶体管制造方法,其特征在于,在所述对所述接触孔区域的第一基区的表层注入掺杂元素之后,在所述对所述衬底进行热处理之前,还包括:
去除覆盖在所述衬底表面的剩余光刻胶。
3.根据权利要求1所述的晶体管制造方法,其特征在于,所述接触孔的底部与所述第一基区之间保留有预设厚度的第二氧化层。
4.根据权利要求3所述的晶体管制造方法,其特征在于,所述预设厚度为200埃~500埃。
5.根据权利要求3所述的晶体管制造方法,其特征在于,在所述对所述衬底进行热处理之后,还包括:
采用氢氟酸溶液漂洗掉所述接触孔底部的所述预设厚度的第二氧化层。
6.根据权利要求5所述的晶体管制造方法,其特征在于,在所述采用氢氟酸溶液漂洗掉所述接触孔底部的所述预设厚度的第二氧化层之后,还包括:
在所述第二基区上和所述发射区上分别制作金属电极。
7.根据权利要求1至6中任一项所述的晶体管制造方法,其特征在于,所述第二氧化层的厚度小于所述第一氧化层的厚度。
8.根据权利要求1至6中任一项所述的晶体管制造方法,其特征在于,所述掺杂元素为硼元素。
9.一种晶体管,其特征在于,所述晶体管由如权利要求1至8中任一项所述的晶体管制造方法制作而成。
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US4055444A (en) * | 1976-01-12 | 1977-10-25 | Texas Instruments Incorporated | Method of making N-channel MOS integrated circuits |
CN85103578A (zh) * | 1985-05-08 | 1986-11-05 | 菲利浦光灯制造公司 | 半导体器件的制造方法 |
US5807780A (en) * | 1991-09-27 | 1998-09-15 | Harris Corporation | High frequency analog transistors method of fabrication and circuit implementation |
US6137147A (en) * | 1998-02-20 | 2000-10-24 | Seiko Instruments Inc. | Bipolar transistor and semiconductor integrated circuit device |
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US4055444A (en) * | 1976-01-12 | 1977-10-25 | Texas Instruments Incorporated | Method of making N-channel MOS integrated circuits |
CN85103578A (zh) * | 1985-05-08 | 1986-11-05 | 菲利浦光灯制造公司 | 半导体器件的制造方法 |
US5807780A (en) * | 1991-09-27 | 1998-09-15 | Harris Corporation | High frequency analog transistors method of fabrication and circuit implementation |
US6137147A (en) * | 1998-02-20 | 2000-10-24 | Seiko Instruments Inc. | Bipolar transistor and semiconductor integrated circuit device |
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