WO2023005669A1 - 像素电路及其驱动方法、显示基板、显示装置 - Google Patents

像素电路及其驱动方法、显示基板、显示装置 Download PDF

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Publication number
WO2023005669A1
WO2023005669A1 PCT/CN2022/105457 CN2022105457W WO2023005669A1 WO 2023005669 A1 WO2023005669 A1 WO 2023005669A1 CN 2022105457 W CN2022105457 W CN 2022105457W WO 2023005669 A1 WO2023005669 A1 WO 2023005669A1
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WIPO (PCT)
Prior art keywords
transistor
circuit
line
control
coupled
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Ceased
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PCT/CN2022/105457
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English (en)
French (fr)
Inventor
王刚
张锴
魏昕宇
蔡兴瑞
付强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/548,974 priority Critical patent/US12444338B2/en
Publication of WO2023005669A1 publication Critical patent/WO2023005669A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • the driving transistor works at a certain bias voltage for a period of time, its characteristics will shift, that is, hysteresis, which will cause short-term afterimages and slow response time.
  • the purpose of the present disclosure is to provide a pixel circuit and its driving method, a display substrate, and a display device.
  • the first aspect of the present disclosure provides a pixel circuit, including: a driving circuit, a data writing circuit and a reset circuit;
  • the data writing circuit is respectively coupled to the first scanning line, the data line and the second end of the driving circuit, and is used to control the data writing under the control of the first scanning signal provided by the first scanning line.
  • the line communicates with the second end of the drive circuit;
  • the reset circuit is respectively coupled to the third scan line, the reset voltage line and the second terminal of the driving circuit, and is used to control the reset voltage under the control of the third scan signal provided by the third scan line. line and the second terminal of the driving circuit; or, the reset circuit is respectively coupled with the third scanning line, the reset voltage line and the first terminal of the driving circuit, for the third scanning Under the control of the signal, control the communication between the reset voltage line and the first end of the driving circuit;
  • the driving circuit is used to control the communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of the control terminal.
  • the pixel circuit further includes: a compensation control circuit, a first initialization circuit, a light emission control circuit, an energy storage circuit and a light emitting element;
  • the compensation control circuit is respectively electrically connected to the second scanning line, the control terminal of the driving circuit and the first terminal of the driving circuit, and is used to control the second scanning signal provided by the second scanning line, controlling the communication between the control terminal of the driving circuit and the first terminal of the driving circuit;
  • the first initialization circuit is respectively coupled to the initialization control line, the first initialization voltage line and the control terminal of the driving circuit, and is used to control the first initialization control signal under the control of the initialization control signal provided by the initialization control line.
  • the initialization voltage line is connected to the control terminal of the drive circuit;
  • the light emission control circuit is respectively coupled to the light emission control line, the first end of the drive circuit and the light emitting element, and is used to control the light emission of the drive circuit under the control of the light emission control signal provided by the light emission control line.
  • the first end communicates with the light-emitting element;
  • the energy storage circuit is coupled to the control terminal of the driving circuit and the second terminal of the driving circuit respectively.
  • the pixel circuit further includes: a second initialization circuit
  • the second initialization circuit is respectively coupled to the third scan line, the second initialization voltage line and the light-emitting element, and is used to control the second initialization voltage line and the second initialization voltage line under the control of the third scan signal.
  • the light emitting elements are communicated with each other.
  • the first initialization voltage line is multiplexed as the reset voltage line.
  • the light emission control circuit is further coupled to the first voltage line and the second end of the drive circuit, for controlling the first voltage line and the drive circuit under the control of the light emission control signal. There is communication between the second ends of the circuit.
  • the compensation control circuit includes a first transistor, the first initialization circuit includes a second transistor, the drive circuit includes a third transistor, and the light emission control circuit includes a fifth transistor and a sixth transistor;
  • the gate of the first transistor is coupled to the second scan line, the first pole of the first transistor is coupled to the second pole of the third transistor, and the second pole of the first transistor is coupled to the second scan line.
  • the gate of the third transistor is coupled;
  • the gate of the second transistor is coupled to the initialization control line, the first pole of the second transistor is coupled to the first initialization voltage line, and the second pole of the second transistor is coupled to the first initialization voltage line.
  • the gates of the three transistors are coupled;
  • the gate of the fifth transistor is coupled to the light emission control line, the first pole of the fifth transistor is coupled to the first voltage line, the second pole of the fifth transistor is coupled to the third The first pole of the transistor is coupled;
  • the gate of the sixth transistor is coupled to the light-emitting control line
  • the first pole of the sixth transistor is coupled to the second pole of the third transistor
  • the second pole of the sixth transistor is coupled to the light emitting control line.
  • the light-emitting element is coupled.
  • the first transistor and the second transistor are oxide thin film transistors.
  • the second initialization circuit includes a seventh transistor
  • the gate of the seventh transistor is coupled to the third scan line, the first pole of the seventh transistor is coupled to the second initialization voltage line, the second pole of the seventh transistor is coupled to the The light emitting element is coupled.
  • the data writing circuit includes a fourth transistor, and the reset circuit includes an eighth transistor;
  • the gate of the fourth transistor is coupled to the first scan line, the first pole of the fourth transistor is coupled to the data line, the second pole of the fourth transistor is coupled to the third transistor The first pole coupling;
  • the gate of the eighth transistor is coupled to the third scanning line, the first pole of the eighth transistor is coupled to the reset voltage line, the second pole of the eighth transistor is coupled to the third The first pole or the second pole of the transistor is coupled.
  • the second aspect of the present disclosure provides a driving method applied to the above-mentioned pixel circuit.
  • the display cycle includes a writing compensation phase and a bias voltage compensation phase.
  • the driving method includes:
  • the data writing circuit controls the communication between the data line and the second end of the driving circuit under the control of the first scanning signal
  • the reset circuit controls the communication between the reset voltage line and the second terminal of the driving circuit; or, under the control of the third scanning signal, the reset circuit controls The reset voltage line communicates with the first terminal of the driving circuit.
  • the display period further includes an initialization phase and a light-emitting phase
  • the first initialization circuit in the pixel circuit controls the first initialization voltage line to communicate with the control terminal of the driving circuit under the control of an initialization control signal;
  • the compensation control circuit in the pixel circuit controls the communication between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the second scanning signal;
  • the light-emitting control circuit in the pixel circuit controls the communication between the first voltage line and the second terminal of the driving circuit under the control of the light-emitting control signal, and controls the first
  • the terminal is connected with the light-emitting element, and the driving circuit drives the light-emitting element to emit light.
  • the display cycle further includes a plurality of light emitting stages and a plurality of bias compensation stages, and the light emitting stages and the bias compensation stages are arranged alternately.
  • a third aspect of the present disclosure provides a display substrate, including a substrate and a plurality of sub-pixels disposed on the substrate, the sub-pixels include the above-mentioned pixel circuit; the sub-pixels further include:
  • Data line, reset voltage line, first scan line and third scan line includes at least a portion extending along a first direction, the first scan line includes at least a portion extending along a second direction, and the first scan line includes at least a portion extending along a second direction.
  • three scan lines including at least a portion extending along the second direction intersecting the first direction;
  • the data writing circuit is respectively coupled to the first scanning line, the data line and the second end of the driving circuit, and is used to control the data under the control of the first scanning signal provided by the first scanning line.
  • the line communicates with the second end of the drive circuit;
  • the reset circuit is respectively coupled to the third scanning line and the reset voltage line, and is also coupled to the first terminal or the second terminal of the driving circuit, and is used for the third scanning provided on the third scanning line. Under the control of the signal, control the communication between the reset voltage line and the second terminal of the driving circuit; or control the communication between the reset voltage line and the first terminal of the driving circuit.
  • the drive circuit includes a third transistor, and the reset circuit includes an eighth transistor;
  • the gate of the eighth transistor is coupled to the third scanning line, the first pole of the eighth transistor is coupled to the reset voltage line, the second pole of the eighth transistor is coupled to the third The first pole of the transistor is coupled;
  • the reset voltage line includes at least a portion extending along the first direction, the reset voltage line and the data line are arranged along the second direction; the orthographic projection of the reset voltage line on the substrate is consistent with the Orthographic projections of the gates of the driving transistors on the substrate at least partially overlap.
  • the eighth transistor includes an eighth active layer, and the eighth active layer includes at least a portion extending along the first direction;
  • At least a portion of an orthographic projection of the eighth active layer on the substrate is located between an orthographic projection of the data line on the substrate and an orthographic projection of the reset voltage line on the substrate;
  • the orthographic projection of the eighth active layer on the substrate and the orthographic projection of the gate of the driving transistor on the substrate are arranged along the first direction.
  • the sub-pixel further includes a first conductive connection part, and the first conductive connection part is respectively coupled to the second pole of the eighth transistor and the first pole of the third transistor;
  • At least part of the orthographic projection of the first conductive connection portion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the reset voltage line on the substrate.
  • the drive circuit includes a third transistor, and the reset circuit includes an eighth transistor;
  • the gate of the eighth transistor is coupled to the third scanning line, the first pole of the eighth transistor is coupled to the reset voltage line, the second pole of the eighth transistor is coupled to the third The second pole of the transistor is coupled;
  • the reset voltage line includes at least a portion extending along the first direction, the reset voltage line and the data line are arranged along the second direction; the orthographic projection of the gate of the driving transistor on the substrate , located between the orthographic projection of the data line on the substrate and the orthographic projection of the reset voltage line on the substrate.
  • the eighth transistor includes an eighth active layer, and the eighth active layer includes at least a portion extending along the first direction;
  • the orthographic projection of the eighth active layer on the substrate at least partially overlaps the orthographic projection of the reset voltage line on the substrate.
  • the sub-pixel further includes a second conductive connection part, and the second conductive connection part is respectively coupled to the second pole of the eighth transistor and the second pole of the third transistor;
  • An orthographic projection of the second conductive connection portion on the substrate at least partially overlaps an orthographic projection of the reset voltage line on the substrate.
  • the sub-pixel further includes: a first initialization voltage line, the first initialization voltage line includes at least a portion extending along the second direction; among two adjacent sub-pixels along the first direction, one of the sub-pixels The first initialization voltage line is multiplexed as the reset voltage line in another sub-pixel.
  • a second aspect of the present disclosure provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of a first structure of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 2 is a second structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first circuit of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a characteristic shift provided by an embodiment of the present disclosure.
  • FIG. 5 is a first driving timing diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a second driving timing diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a second schematic circuit diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a third schematic circuit diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a fourth schematic circuit diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic layout diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic layout diagram corresponding to FIG. 3;
  • FIG. 12 is a schematic layout diagram of the poly active layer in FIG. 11;
  • FIG. 13 is a schematic layout diagram of the first gate metal layer in FIG. 11;
  • FIG. 14 is a schematic layout diagram of the second gate metal layer in FIG. 11;
  • FIG. 15 is a schematic layout diagram of the oxide active layer in FIG. 11;
  • FIG. 16 is a schematic layout diagram of the third gate metal layer in FIG. 11;
  • Fig. 17 is a schematic diagram of the first connecting hole in Fig. 11;
  • Fig. 18 is a schematic diagram of the second connecting hole in Fig. 11;
  • FIG. 19 is a schematic layout diagram of the first source-drain metal layer in FIG. 11;
  • FIG. 20 is a schematic diagram of a via hole formed by the passivation layer in FIG. 11;
  • FIG. 21 is a schematic diagram of a via hole formed by the first flat layer in FIG. 11;
  • FIG. 22 is a schematic layout diagram of the second source-drain metal layer in FIG. 11;
  • FIG. 23 is a schematic layout diagram corresponding to FIG. 8.
  • FIG. 24 is a schematic layout diagram of the poly active layer in FIG. 23;
  • FIG. 25 is a schematic layout diagram of the first gate metal layer in FIG. 23;
  • FIG. 26 is a schematic layout diagram of the first source-drain metal layer in FIG. 23;
  • FIG. 27 is a schematic diagram of a via hole formed by the passivation layer in FIG. 23;
  • FIG. 28 is a schematic diagram of via holes formed by the first flat layer in FIG. 23;
  • FIG. 29 is a schematic layout diagram of the second source-drain metal layer in FIG. 23;
  • FIG. 30 is a schematic layout diagram corresponding to FIG. 9;
  • FIG. 31 is a schematic layout diagram of the first source-drain metal layer in FIG. 30;
  • FIG. 32 is a schematic layout diagram of the second source-drain metal layer in FIG. 30;
  • FIG. 33 is a schematic stacking diagram of the second gate metal layer to the third gate metal layer provided by an embodiment of the present disclosure.
  • FIG. 34 is a schematic cross-sectional view of an eighth transistor provided by an embodiment of the present disclosure.
  • FIG. 35 is a schematic layout diagram of the poly active layer in FIG. 30;
  • FIG. 36 is a schematic layout diagram of the first gate metal layer in FIG. 30;
  • FIG. 37 is a schematic layout diagram of the oxide active layer in FIG. 30;
  • Fig. 38 is a schematic diagram of the first connecting hole in Fig. 30;
  • FIG. 39 is a schematic diagram of the second connecting hole in FIG. 30 .
  • an embodiment of the present disclosure provides a pixel circuit, including: a driving circuit 11 , a data writing circuit 41 and a reset circuit 20 ;
  • the data writing circuit 41 is respectively coupled to the first scanning line S1, the data line D1 and the second end of the driving circuit 11, for controlling the first scanning signal provided by the first scanning line S1 , controlling the communication between the data line D1 and the second end of the driving circuit 11;
  • the reset circuit 20 is respectively coupled to the third scanning line S3, the reset voltage line DR and the second end of the driving circuit 11, for controlling the third scanning signal provided by the third scanning line S3, Controlling the connection between the reset voltage line DR and the second terminal (i.e. the second node N2) of the driving circuit 11; or, the reset circuit 20 is respectively connected to the third scanning line S3, the reset voltage line DR and the The first terminal of the driving circuit 11 (namely the third node N3) is coupled to control the communication between the reset voltage line DR and the first terminal of the driving circuit 11 under the control of the third scanning signal. ;
  • the driving circuit 11 is used to control the communication between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the potential of the control terminal.
  • the first scan line S1 is used for writing the first scan signal
  • the data line D1 is used for writing data signals
  • the third scan line S3 is used for writing the third scan signal.
  • the reset voltage line DR is used to provide a reset voltage.
  • the data signal is used for conventional picture display.
  • the reset voltage can follow the change of the data signal, and in the bias compensation phase P2, apply a bias voltage opposite in sign to that of the light emitting phase P4 to the driving transistor included in the driving circuit 11, for example: the bias voltage Vgs of the driving transistor in the light emitting phase P4 (or Vgd) is 5V, and the bias voltage of the driving transistor is -5V through the reset voltage line DR in the compensation phase.
  • the data writing circuit 41 when the first scanning signal is at an active level, the data writing circuit 41 is configured to turn on the data line D1 and The electrical connection between the second terminals of the driving circuit 11 .
  • the data writing circuit 41 is used to disconnect the data line D1 from the drive under the control of the first scanning signal provided by the first scanning line S1. The electrical connection between the second terminals of the circuit 11.
  • the reset circuit 20 when the third scanning signal is at an active level, the reset circuit 20 is configured to conduct the reset voltage line DR and the first voltage of the driving circuit 11 under the control of the third scanning signal. The electrical connection between the two terminals or the first terminal of the drive circuit 11 .
  • the reset circuit 20 When the third scanning signal is at an inactive level, the reset circuit 20 is configured to disconnect the reset voltage line DR from the second terminal or the second end of the driving circuit 11 under the control of the third scanning signal. Electrical connection between the first terminals of the driving circuit 11 .
  • one display period in which the pixel circuit works includes: a writing compensation phase P3 and a bias voltage compensation phase P2.
  • the data writing circuit 41 controls the connection between the data line D1 and the second end of the driving circuit 11 under the control of the first scanning signal, and writes data to the second end of the driving circuit 11. Signal.
  • the reset circuit 20 controls the communication between the reset voltage line DR and the second end of the drive circuit 11 under the control of the third scan signal; Under the control of , control the communication between the reset voltage line DR and the first terminal of the driving circuit 11 ; so as to write the reset voltage into the first terminal or the second terminal of the driving circuit 11 .
  • the compensation drive circuit 11 works at a certain bias voltage for a period of time, the characteristics will shift, which can improve bad problems such as short-term afterimage and slow response time.
  • it can compensate the difference in brightness caused by the characteristic deviation of the driving circuit 11 in the long-time light-emitting period, and improve the flicker phenomenon.
  • the reset voltage provided by the reset voltage line DR can be adjusted independently, it can provide an appropriate bias voltage to each pixel circuit in the display substrate as required.
  • the pixel circuit further includes: a compensation control circuit 13, a first initialization circuit 14, a light emitting control circuit 31, an energy storage circuit 42 and a light emitting element O1;
  • the compensation control circuit 13 is electrically connected to the second scanning line S2, the control terminal (i.e. the first node N1) of the driving circuit 11 and the first end (i.e. the third node N3) of the driving circuit 11 respectively, for Under the control of the second scanning signal provided by the second scanning line S2, controlling the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11;
  • the first initialization circuit 14 is respectively coupled to the initialization control line R1, the first initialization voltage line Vinit1 and the control terminal of the driving circuit 11, for controlling the initialization control signal provided by the initialization control line R1, controlling the first initialization voltage line Vinit1 to communicate with the control terminal of the driving circuit 11;
  • the light emission control circuit 31 is respectively coupled to the light emission control line E1, the first end of the driving circuit 11 and the light emission element O1, and is used to control the light emission control signal provided by the light emission control line E1.
  • the first end of the driving circuit 11 is connected to the light emitting element O1;
  • the energy storage circuit 42 is coupled to the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively.
  • each display cycle in which the pixel circuit works includes: an initialization phase P1, a bias compensation phase P2, a writing compensation phase P3 and a light emitting phase P4.
  • the gate potential of the driving transistor becomes Vdata+Vth, where Vdata is the data voltage corresponding to the data signal, and Vth is the threshold voltage of the driving transistor .
  • the stress Vgs1 Vdata+Vth-VDD on the driving transistor, where VDD is the power supply voltage received by the driving transistor.
  • VDD the power supply voltage received by the driving transistor.
  • the reset circuit 20 writes a reset voltage V1 to the first terminal or the second terminal of the driving circuit 11 .
  • V1 2*(Vdata+Vth)-VDD
  • VDD is a fixed value
  • Vth can be obtained through testing, so the value relationship between V1 and Vdata can be obtained.
  • Setting V1 according to the above relationship can achieve the best compensation effect.
  • the driving transistor is biased with the same magnitude and opposite direction as the light-emitting phase P4, as shown in Figure 4, the characteristic curve will return from the dotted line to the solid line, thereby completing the bias compensation.
  • the pixel circuit further includes: a second initialization circuit 32;
  • the second initialization circuit 32 is respectively coupled to the third scanning line S3, the second initialization voltage line Vinit2 and the light-emitting element O1, and is used to control the second initialization circuit under the control of the third scanning signal.
  • the initialization voltage line Vinit2 communicates with the light emitting element O1.
  • the second initialization voltage line Vinit2 is used to provide a second initialization voltage.
  • the second initialization circuit 32 can reset the first pole of the light emitting element O1 under the control of the third scan signal.
  • the first pole of the light emitting element O1 includes an anode, and the second pole (ie, cathode) of the light emitting element O1 receives a negative power supply signal VSS.
  • the first initialization voltage line Vinit1 is multiplexed as the reset voltage line DR.
  • the reset circuit 20 is coupled to the first initialization voltage line Vinit1.
  • the first initialization voltage provided by the first initialization voltage line Vinit1 is adjustable.
  • the first initialization voltage provided by the first initialization voltage line Vinit1 is variable.
  • the first initialization voltage when used to reset the gate of the driving transistor, it can be set to -5V, and when the first initialization voltage is used for bias compensation, it can be set to 5V.
  • Setting the first initialization voltage line Vinit1 multiplexed as the reset voltage line DR can simplify the sub-pixel structure, reduce the layout difficulty of the sub-pixels, and improve the resolution of the display substrate.
  • the light emission control circuit 31 is also connected to the first voltage line (writing VDD signal), the second terminal of the driving circuit 11 is coupled connected, used to control the communication between the first voltage line and the second terminal of the driving circuit 11 under the control of the light emission control signal.
  • the first voltage line includes a positive power line. Whether the first voltage provided by the first voltage line is written into the second terminal of the driving circuit 11 is controlled by the light emission control signal.
  • the compensation control circuit 13 includes a first transistor T1
  • the first initialization circuit 14 includes a second transistor T2
  • the driving circuit 11 includes a third transistor T3 (that is, the driving transistor)
  • the light emission control circuit 31 includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the first transistor T1 is coupled to the second scan line S2, the first pole of the first transistor T1 is coupled to the second pole of the third transistor T3, and the first transistor T1 The second pole is coupled to the gate T3-g of the third transistor T3;
  • the gate of the second transistor T2 is coupled to the initialization control line R1, the first electrode of the second transistor T2 is coupled to the first initialization voltage line Vinit1, and the second electrode of the second transistor T2
  • the pole is coupled to the gate T3-g of the third transistor T3;
  • the gate of the fifth transistor T5 is coupled to the light emission control line E1, the first pole of the fifth transistor T5 is coupled to the first voltage line, and the second pole of the fifth transistor T5 is coupled to the first voltage line.
  • the first pole of the third transistor T3 is coupled to;
  • the gate of the sixth transistor T6 is coupled to the light emission control line E1
  • the first pole of the sixth transistor T6 is coupled to the second pole of the third transistor T3
  • the sixth transistor T6 The second pole is coupled to the light emitting element O1.
  • the first transistor T1 and the second transistor T2 are oxide thin film transistors.
  • the first transistor T1 and the second transistor T2 include low temperature polycrystalline oxide transistors (English: Low Temperature Polycrystalline Oxide, LTPO for short).
  • the first transistor T1 and the second transistor T2 are oxide thin film transistors, it is beneficial to reduce the gate leakage of the driving transistor and ensure the stability of the gate potential of the driving transistor.
  • the second initialization circuit 32 includes a seventh transistor T7,
  • the gate of the seventh transistor T7 is coupled to the third scanning line S3, the first electrode of the seventh transistor T7 is coupled to the second initialization voltage line Vinit2, and the first electrode of the seventh transistor T7
  • the diode is coupled to the light emitting element O1.
  • the data writing circuit 41 includes a fourth transistor T4, and the reset circuit 20 includes an eighth transistor T8;
  • the gate of the fourth transistor T4 is coupled to the first scan line S1, the first pole of the fourth transistor T4 is coupled to the data line D1, and the second pole of the fourth transistor T4 is coupled to the data line D1.
  • the first pole of the third transistor T3 is coupled to;
  • the gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, the first pole of the eighth transistor T8 is coupled to the reset voltage line DR, and the eighth transistor T8 The second pole is coupled to the first pole or the second pole of the third transistor T3.
  • the one labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T3;
  • the one labeled N2 is the second node, labeled N2 N3 is the third node;
  • N2 is electrically connected to the source of T3, and N3 is electrically connected to the drain of T3.
  • T1 and T2 may be oxide thin film transistors, T3, T4, T5, T6, T7 and T8 may all be low temperature polysilicon thin film transistors, T1 and T2 are n type transistors, T3, T4, T5, T6, T7 and T8 are p-type transistors, but not limited thereto.
  • T1 and T2 may be single-gate transistors or double-gate transistors.
  • the value range of W is between 2 microns and 4 microns, which may include the endpoint value
  • the value range of L is between 3 microns and 6 microns, which may be Include endpoint values.
  • the channel width-to-length ratios of T2 and T1 are the same.
  • the value range of W is between 2 microns and 3 microns, which may include the endpoint value
  • the value range of L is between 3.2 microns and 6 microns, which may be Include endpoint values.
  • the specific driving process of the pixel circuit with the above structure includes:
  • R1 provides a high voltage signal and T2 is turned on.
  • S1 provides a high voltage signal and T4 is closed.
  • S2 provides a low voltage signal and T1 is turned off.
  • S3 provides high voltage signal, T7 and T8 are closed.
  • the gate initialization of T3 is implemented in the initialization phase P1, so that T3 can be turned on when the writing compensation phase P3 starts.
  • R1 provides a low voltage signal and T2 is turned off.
  • S1 provides a high voltage signal and T4 is closed.
  • S2 provides a low voltage signal and T1 is turned off.
  • S3 provides a low voltage signal, and T7 and T8 are turned on.
  • the reset voltage provided by DR can be written into the first pole or the second pole of the third transistor T3, and the second initialization voltage can be written into the anode of O1 to initialize the anode of O1.
  • T3 is turned on.
  • R1 provides a low voltage signal and T2 is turned off.
  • S1 provides a low voltage signal and T4 is turned on.
  • S2 provides a high voltage signal and T1 is turned on.
  • S3 provides high voltage signal, T7 and T8 are closed.
  • the data voltage Vdata on the data line D1 is written into the first electrode of the third transistor T3.
  • Vdata is used to charge C through the opened T4, T3 and T1 to increase the potential of the gate of T3 until T3 is turned off. At this time, the potential of the gate of T3 is Vdata+ Vth.
  • E1 provides a low voltage signal
  • R1 provides a low voltage signal
  • S1 provides a high voltage signal
  • S2 provides a low voltage signal
  • S3 provides a high voltage signal
  • T1, T2, T4, T7 and T8 are turned off
  • T5 and T6 Turn on
  • T3 turns on to drive O1 to emit light.
  • T8 By adding T8 to provide bias voltage for the first or second pole of T3, it is beneficial to improve the stability of T3; by setting T7, the potential of the anode of O1 is initialized, which is beneficial to the freedom of switching frequency switching under low-frequency flickering .
  • the pixel circuit needs to turn on T3 in the threshold compensation phase, therefore, the voltage difference Vi1-V1 between the first initialization voltage Vi1 provided by the first initialization voltage line Vinit1 and the reset voltage V1 provided by the reset voltage line DR It needs to be less than the threshold voltage Vth of the driving transistor T3.
  • Vi1 may be -2 to -6V, for example, -2V, -3V, -4V, -5V, -6V and so on.
  • Vi1-V1 can be less than a*Vth, a can be 2-7, for example, a can be 2, 4, 6, 7;
  • Vth can be -2-5V, such as -2V, -3V, -5V and so on.
  • V1 may be greater than 1.5 times Vth, for example, V1 may be 1.6 times, 1.8 times, 2 times, etc. of Vth.
  • V1 is greater than 0.
  • the value of V1 is between 4 and 10V, which may include the endpoint value.
  • the width-to-length ratio W/L of T8 may be approximately equal to the width-to-length ratio W/L of T7; for another example, the width-to-length ratio W/L of T8 may be greater than the width-to-length ratio W/L of T7, that is The width-to-length ratio W/L of T8 can be slightly larger, so that the N2 node can be quickly reset.
  • the channel width W of T8 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it may be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of T7 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; For example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the width-to-length ratio W/L of T8 may be approximately equal to the width-to-length ratio W/L of T2; for another example, the width-to-length ratio W/L of T8 may be smaller than the width-to-length ratio W/L of T2, so that Balance the reset capabilities of N1 nodes and N2 nodes.
  • the channel width W of T8 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it may be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of T2 is 1.5-3.5, such as 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; For example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.
  • the embodiment of the present disclosure also provides a driving method, which is applied to the pixel circuit provided in the above embodiment, and the display cycle includes a writing compensation phase P3 and a bias compensation phase P2, so
  • the driving methods described above include:
  • the data writing circuit 41 controls the communication between the data line D1 and the second end of the driving circuit 11 under the control of the first scanning signal;
  • the reset circuit 20 controls the communication between the reset voltage line DR and the second end of the drive circuit 11 under the control of the third scan signal; Under the control of , the communication between the reset voltage line DR and the first terminal of the driving circuit 11 is controlled.
  • a bias voltage opposite in sign to that in the light-emitting phase P4 can be applied to the driving circuit 11 in the bias compensation phase P2, so as to compensate the driving circuit 11 to work at a certain bias voltage for a period of time. After the characteristics are shifted, the bad problems such as short-term afterimage and slow response time are improved. Moreover, when driving at low frequency, it can compensate the difference in brightness caused by the characteristic deviation of the driving circuit 11 in the long-time light-emitting period, and improve the flicker phenomenon. In addition, specific bias compensation can be implemented for the driving circuit 11 in each pixel circuit in the display substrate, and has a good compensation effect. In addition, since the reset voltage provided by the reset voltage line DR can be adjusted independently, it can provide an appropriate bias voltage to each pixel circuit in the display substrate as required.
  • the display cycle further includes an initialization phase P1 and a light emitting phase P4;
  • the first initialization circuit 14 in the pixel circuit controls the first initialization voltage line Vinit1 to communicate with the control terminal of the driving circuit 11 under the control of an initialization control signal;
  • the compensation control circuit 13 in the pixel circuit controls the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the second scanning signal. ;
  • the light emitting control circuit 31 in the pixel circuit controls the communication between the first voltage line and the second terminal of the driving circuit 11 under the control of the light emitting control signal, and controls the driving circuit
  • the first end of 11 communicates with the light emitting element O1, and the driving circuit 11 drives the light emitting element O1 to emit light.
  • the first initialization circuit 14 controls the first initialization voltage line Vinit1 to communicate with the control terminal of the driving circuit 11 to initialize the control terminal of the driving circuit 11 .
  • the reset circuit 20 controls the communication between the reset voltage line DR and the second terminal of the driving circuit 11, or controls the communication between the reset voltage line DR and the first terminal of the driving circuit 11. connection between.
  • the compensation control circuit 13 controls the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 .
  • the data writing circuit 41 controls the communication between the data line D1 and the second terminal of the driving circuit 11 .
  • the light-emitting control circuit 31 controls the communication between the first voltage line and the second terminal of the driving circuit 11, and controls the communication between the first terminal of the driving circuit 11 and the light-emitting element O1.
  • the driving circuit 11 drives the light emitting element O1 to emit light.
  • the display cycle further includes a plurality of light-emitting periods P4 and a plurality of bias compensation periods P2, and the light-emitting periods P4 and the bias compensation periods P2 are arranged alternately .
  • the display cycle sequentially includes: initialization phase P1, bias voltage compensation phase P2, write compensation phase P3, light emitting phase P4, bias voltage compensation phase P2, light emitting phase P4, bias voltage compensation phase P2, light emitting phase P4 , the bias compensation phase P2, and the light emitting phase P4.
  • the number of the light-emitting phases P4 and the number of the bias compensation phases P2 can be set according to actual needs.
  • bias compensation in several fixed stages within one frame is more conducive to implementing bias compensation for the driving circuit 11 when the display substrate is in low-frequency display.
  • 1h 1 second/(refresh frequency*total number of rows).
  • the width of the light emission control signal provided by the light emission control line E1 at an active level is between 30h ⁇ 40h, which may include endpoint values.
  • the width of the initialization control signal provided by the initialization control line R1 at an active level is between 10h ⁇ 15h, which may include endpoint values.
  • the width of the second scanning signal provided by the second scanning line S2 at an active level is between 10h ⁇ 15h, which may include endpoint values.
  • the width of the third scanning signal provided by the third scanning line S3 at an active level is between 1h ⁇ 3h, which may include endpoint values.
  • the width of the first scanning signal provided by the first scanning line S1 at an active level is between 1h and 3h, which may include endpoint values.
  • the active level width of the data signal provided by the data line D1 includes 1h.
  • the effective level width of the lighting control signal is 2 to 4 times the effective level width of the initialization control signal.
  • the effective level width of the light emission control signal is 2 to 4 times the effective level width of the second scanning signal.
  • an embodiment of the present disclosure also provides a display substrate, including a base and a plurality of sub-pixels arranged on the base, and the sub-pixels include the above-mentioned
  • the pixel circuit provided in the embodiment; the sub-pixel further includes:
  • the data line D1 includes at least a portion extending along the first direction
  • the first scan line S1 includes at least a portion extending along the second direction.
  • the third scan line S3 includes at least a part extending along the second direction, and the second direction intersects the first direction;
  • the data writing circuit 41 is respectively coupled to the first scanning line S1, the data line D1 and the second end of the driving circuit 11, for controlling the first scanning signal provided by the first scanning line S1 , controlling the communication between the data line D1 and the second end of the driving circuit 11;
  • the reset circuit 20 is respectively coupled to the third scanning line S3 and the reset voltage line DR, and is also coupled to the first terminal or the second terminal of the driving circuit 11, and is used for switching on the third scanning line S3 Under the control of the provided third scanning signal, control the communication between the reset voltage line DR and the second end of the driving circuit 11; or control the connection between the reset voltage line DR and the first end of the driving circuit 11 connection between.
  • the above display substrate includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes a pixel circuit.
  • the data lines D1 are sequentially coupled to form an integrated structure.
  • the reset voltage lines DR are sequentially coupled to form an integrated structure.
  • the reset voltage lines DR are sequentially coupled to form an integrated structure.
  • the first scanning lines S1 are sequentially coupled to form an integrated structure.
  • the third scan lines S3 are sequentially coupled to form an integrated structure.
  • the display substrate includes: a light shielding layer, an isolation layer, a first buffer layer, a poly active layer, a first gate insulating layer, a first Gate metal layer, second gate insulating layer, second gate metal layer, first interlayer insulating layer, second buffer layer, oxide active layer (such as IGZO), third gate insulating layer, third gate metal layer, second interlayer insulating layer, first source-drain metal layer, passivation layer, first planarization layer, second source-drain metal layer, second planarization layer, anode layer, pixel definition layer, spacer layer, light emitting Functional layer, cathode layer and encapsulation layer.
  • oxide active layer such as IGZO
  • the substrate includes a PI substrate.
  • a CNT drilling process (such as: CNT-L/EBA and CNT-O/EBB) can be performed, and then continue to perform the mask process of the interlayer insulating layer to form a The via hole of the second interlayer insulating layer, the via hole from the second interlayer insulating layer to the third gate insulating layer, the via hole from the second interlayer insulating layer to the first interlayer insulating layer , penetrating the via hole from the second interlayer insulating layer to the second gate insulating layer, penetrating the via hole from the second interlayer insulating layer to the first gate insulating layer, penetrating the second interlayer insulating layer vias to the isolation layer.
  • the data line D1 is made of the second source-drain metal layer.
  • the reset voltage line DR is made of the second source-drain metal layer or the first source-drain metal layer.
  • Both the first scan line S1 and the third scan line S3 are made of a first gate metal layer.
  • the first direction includes the longitudinal direction
  • the second direction includes the transverse direction
  • the display substrate provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display substrate provided by the embodiments of the present disclosure includes the above-mentioned pixel circuits
  • specific bias compensation can be implemented for the driving circuit 11 in each pixel circuit in the display substrate, which has a good compensation effect.
  • the reset voltage provided by the reset voltage line DR can be adjusted independently, it can provide an appropriate bias voltage to each pixel circuit in the display substrate as required.
  • the display substrate includes a plurality of pixel circuits P distributed in an array, a plurality of reset voltage lines DR11, DR12, DR21, DR22, and the reset voltage lines DR11, DR12, DR21, DR22 can all be used to provide reset voltages .
  • the reset voltage lines DR11 and DR12 extend along the column direction, and the reset voltage lines DR21 and DR22 extend along the row direction.
  • Pixel circuits in two adjacent rows can be connected to the reset voltage line DR extending in the same row direction.
  • the line DR can be located between the two adjacent rows of pixel driving circuits 11, and the reset voltage line DR extending along the column direction can be connected to a plurality of reset voltage lines DR extending along the row direction intersecting with it, so that the multiple reset voltage lines DR can be form a grid structure.
  • the reset voltage line DR extending along the column direction may be located in the area where the red pixel circuit is located.
  • two pixel circuits in adjacent columns can be mirrored to facilitate wiring.
  • the driving circuit 11 includes a third transistor T3, and the reset circuit 20 includes an eighth transistor T8;
  • the gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, the first pole of the eighth transistor T8 is coupled to the reset voltage line DR, and the eighth transistor T8 the second pole is coupled to the first pole of the third transistor T3;
  • the reset voltage line DR includes at least a portion extending along the first direction, the reset voltage line DR and the data line D1 are arranged along the second direction; the reset voltage line DR on the substrate
  • the orthographic projection at least partially overlaps the orthographic projection of the gate of the drive transistor on the substrate.
  • the gate T3-g of the third transistor T3 is made of the first gate metal layer.
  • the gate T8-g of the eighth transistor T8 is integrated with the third scan line S3.
  • the reset voltage line DR and the data line D1 are provided in the same layer and material.
  • the orthographic projection of the data line D1 on the substrate does not overlap with the orthographic projection of the gate of the driving transistor on the substrate.
  • the orthographic projection of the reset voltage line DR on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate.
  • the eighth transistor T8 is coupled to the reset voltage line DR through the third conductive connection portion 63 .
  • FIG. 12 shows that T3 includes the third active layer 53, T4 includes the fourth active layer 54, T5 includes the fifth active layer 55, T6 includes the sixth active layer 56, and T7 includes The seventh active layer 57 .
  • FIG. 15 illustrates the first active layer 51 included in T1 and the second active layer 52 included in T2.
  • FIG. 19 illustrates the third conductive connection portion 63 .
  • FIG. 33 shows the second gate metal layer Gate2, the first interlayer insulating layer ILD1, the second buffer layer Buffer2, the oxide layer (IGZO), the third gate insulating layer GI3, and the third gate metal layer Gate3.
  • first connection holes in FIG. 17 are used to connect the first source-drain metal layer and the corresponding structures below it, and the depths of the first connection holes in FIG. 17 may be the same or different.
  • the second connection holes in FIG. 18 are used to connect the first source-drain metal layer and the corresponding structures below it, and the depths of the second connection holes in FIG. 18 may be the same or different.
  • the above setting manner is beneficial to reduce the layout difficulty of the sub-pixels.
  • the eighth transistor T8 includes an eighth active layer 58, and the eighth active layer 58 includes at least a portion extending along the first direction;
  • At least part of the orthographic projection of the eighth active layer 58 on the substrate is located between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the reset voltage line DR on the substrate between;
  • the orthographic projection of the eighth active layer 58 on the substrate and the orthographic projection of the gate of the driving transistor on the substrate are arranged along the first direction.
  • the eighth active layer 58 is made of a poly active layer.
  • the orthographic projection of the eighth active layer 58 on the substrate at least partially overlaps the orthographic projection of the reset voltage line DR on the substrate.
  • the orthographic projection of the eighth active layer 58 on the substrate does not overlap with the orthographic projection of the data line D1 on the substrate.
  • At least part of the orthographic projection of the eighth active layer 58 on the substrate is located where the orthographic projection of the light emission control line E1 on the substrate is in the same position as the second initialization voltage line Vinit2. Between the orthographic projections on the above substrates.
  • the above arrangement is beneficial to reduce the layout difficulty of the sub-pixels and reduce the parasitic capacitance generated by the eighth transistor T8.
  • the sub-pixel further includes a first conductive connection portion 61, and the first conductive connection portion 61 is respectively connected to the second pole of the eighth transistor T8 and the second pole of the eighth transistor T8.
  • the first pole of the third transistor T3 is coupled;
  • At least part of the orthographic projection of the first conductive connecting portion 61 on the substrate is located between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the reset voltage line DR on the substrate. between.
  • the first conductive connection part 61 is made of the first source-drain metal layer.
  • the orthographic projection of the first conductive connecting portion 61 on the substrate partially overlaps the orthographic projection of the data line D1 on the substrate, and overlaps with the reset voltage line DR on the substrate.
  • the orthographic projections on are partially overlapped.
  • the orthographic projection of the first conductive connecting portion 61 on the substrate does not overlap with the orthographic projection of the data line D1 on the substrate, and does not overlap with the orthographic projection of the reset voltage line DR on the substrate.
  • the orthographic projections on do not overlap.
  • the orthographic projection of the first conductive connection portion 61 on the substrate partly overlaps the orthographic projection of the light emission control line E1 on the substrate.
  • the orthographic projection of the first conductive connection portion 61 on the substrate does not overlap with the orthographic projection of the second plate C2 of the storage capacitor C on the substrate.
  • the first conductive connection portion 61 is respectively coupled to the second pole of the eighth transistor T8 and the first pole of the third transistor T3 through corresponding via holes.
  • the first conductive connecting portion 61 includes a portion extending along the first direction, and further includes a portion extending along a third direction, and the third direction is compatible with the first direction and the second direction. Both intersect.
  • the above setting manner is beneficial to reduce the layout difficulty of the sub-pixels.
  • the second initialization voltage line Vinit2 includes a main body, a first protrusion and a second protrusion, and the main body includes a At least partially, the first protruding portion and the second protruding portion are arranged along the second direction;
  • the second initialization circuit 32 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third scanning The first pole of the seventh transistor T7 is coupled to the first protrusion; the first pole of the eighth transistor T8 is coupled to the second protrusion.
  • the seventh transistor T7 includes a seventh active layer, and the eighth active layer 58 and the seventh active layer are arranged along the second direction.
  • the orthographic projection of the eighth active layer 58 on the substrate is located between the orthographic projection of the seventh active layer on the substrate and the orthographic projection of the data line D1 on the substrate.
  • the driving circuit 11 includes a third transistor T3, and the reset circuit 20 includes an eighth transistor T8;
  • the gate T8-g of the eighth transistor T8 is coupled to the third scan line S3, the first pole of the eighth transistor T8 is coupled to the reset voltage line DR, and the eighth transistor T8 the second pole is coupled to the second pole of the third transistor T3;
  • the reset voltage line DR includes at least a portion extending along the first direction, the reset voltage line DR and the data line D1 are arranged along the second direction; the gate of the driving transistor is on the substrate
  • the orthographic projection of is located between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the reset voltage line DR on the substrate.
  • the orthographic projection of the gate of the driving transistor on the substrate does not overlap with the orthographic projection of the data line D1 on the substrate.
  • the orthographic projection of the gate of the driving transistor on the substrate does not overlap with the orthographic projection of the reset voltage line DR on the substrate.
  • the above setting method not only helps to reduce the layout difficulty of the sub-pixel, but also arranges the data line D1 and the reset voltage line DR on both sides of the sub-pixel, which can well avoid the The data line D1 interferes with the reset voltage line DR.
  • the eighth transistor T8 includes an eighth active layer 58, and the eighth active layer 58 includes at least a portion extending along the first direction;
  • the orthographic projection of the eighth active layer 58 on the substrate at least partially overlaps the orthographic projection of the reset voltage line DR on the substrate.
  • the orthographic projection of the eighth active layer 58 on the substrate is covered by the orthographic projection of the reset voltage line DR on the substrate.
  • the sub-pixel further includes a second conductive connection portion 62, and the second conductive connection portion 62 is respectively connected to the second pole of the eighth transistor T8 and the second electrode of the eighth transistor T8.
  • the second pole of the third transistor T3 is coupled;
  • the orthographic projection of the second conductive connection portion 62 on the substrate at least partially overlaps with the orthographic projection of the reset voltage line DR on the substrate.
  • the second conductive connection part 62 is made of the first source-drain metal layer.
  • the second conductive connection portion 62 includes a portion extending along the first direction and a portion extending along the third direction.
  • the orthographic projection of the second conductive connection portion 62 on the substrate partly overlaps with the orthographic projection of the light emission control line E1 on the substrate.
  • the second conductive connection portion 62 is respectively coupled to the second pole of the eighth transistor T8 and the second pole of the third transistor T3 through via holes.
  • the orthographic projection of the second conductive connection portion 62 on the substrate partially overlaps the orthographic projection of the second plate C2 of the storage capacitor C on the substrate.
  • the above setting manner is beneficial to reduce the layout difficulty of the sub-pixels.
  • the sub-pixel further includes: a first initialization voltage line Vinit1, and the first initialization voltage line Vinit1 includes At least partially; among two adjacent sub-pixels along the first direction, the first initialization voltage line Vinit1' in one of the sub-pixels is multiplexed as the reset voltage line DR in the other sub-pixel.
  • the second initialization voltage line Vinit2 is made of the first source-drain metal layer.
  • the first initialization voltage line Vinit1 is made of the first gate metal layer.
  • the small independent figure in the upper right corner in FIG. 35 is part of the eighth active layer in the previous sub-pixel adjacent along the first direction.
  • the bottom independent small figure in FIG. 37 is the second active layer in the next adjacent sub-pixel along the first direction.
  • the above-mentioned first initialization voltage line Vinit1' is multiplexed as the reset voltage line DR, which avoids laying out an additional reset voltage line DR dedicated to providing reset voltage, which is beneficial to simplify the complexity of sub-pixels and reduce the number of sub-pixels. difficulty of layout.
  • the second initialization voltage line Vinit2 includes: a first initial sub-pattern, a second initial sub-pattern, a third initial sub-pattern and a third protrusion; the first initial sub-pattern and the first initial sub-pattern The three initial sub-figures all extend along the second direction, the first initial sub-figure and the third initial sub-figure are staggered along the first direction, the first initial sub-figure and the third initial sub-figure Graphics are coupled through the second initial sub-graphic; the third protrusion is coupled with the third initial sub-graphic; the second initialization circuit 32 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to The third scanning line S3 is coupled, the first pole of the seventh transistor T7 is coupled to the first initial sub-pattern; the first pole of the eighth transistor T8 is coupled to the third protrusion .
  • the seventh transistor T7 includes a seventh active layer, and the orthographic projection of the seventh active layer on the substrate is located between the orthographic projection of the data line D1 on the substrate and the reset Line between orthographic projections on the base.
  • the orthographic projection of the seventh active layer on the substrate is located between the orthographic projection of the data line D1 on the substrate and the orthographic projection of the eighth active layer 58 on the substrate between.
  • the sub-pixel further includes a second scan line S2, and the second scan line S2 includes a first scan sub-pattern S21 and a third scan sub-pattern S22, at least part of the first scanning sub-pattern S21 and at least part of the third scanning sub-pattern S22 both extend along the second direction;
  • the compensation control circuit 13 includes a first transistor T1, and the first transistor T1 includes a first oxide active layer; in a direction perpendicular to the substrate, at least part of the first oxide active layer is located on the Between the first scan sub-pattern and the third scan sub-pattern.
  • the first scanning sub-pattern is made using a second gate metal layer
  • the third scanning sub-pattern is made using a third gate metal layer. At least a portion of the first scan sub-pattern is located between the base and the third scan sub-pattern.
  • the sub-pixels further include an initialization control line R1, and the initialization control line R1 includes a first initialization sub-pattern R11 and a second initialization sub-pattern R12, At least part of the first initialization sub-pattern R11 and at least part of the second initialization sub-pattern R12 both extend along the second direction;
  • the first initialization circuit 14 includes a second transistor T2, and the second transistor T2 includes a second oxide active layer; in a direction perpendicular to the substrate, at least part of the second oxide active layer is located on the Between the first initialization sub-graph and the second initialization sub-graph.
  • the first initialization sub-pattern is made using a second gate metal layer
  • the second initialization sub-pattern is made using a third gate metal layer. At least part of the first initialization sprite is located between the base and the second initialization sprite.
  • the first oxide active layer (such as marked 51) and the second oxide active layer (such as marked 52) are arranged along the first direction;
  • the data writing circuit 41 includes a fourth transistor T4, the fourth transistor T4 includes a fourth active layer, and the orthographic projection of the fourth active layer on the substrate is in the same position as the data line D1. Orthographic projections on the substrate at least partially overlap, and the fourth active layer and the first oxide active layer are arranged along the second direction.
  • the sub-pixel further includes an emission control line E1, and the emission control line E1 includes at least a portion extending along the second direction;
  • the light emission control circuit 31 includes a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is coupled to the light emission control line E1, the gate of the sixth transistor T6 is connected to the light emission control line E1 coupling;
  • the fifth transistor T5 includes a fifth active pattern
  • the sixth transistor T6 includes a sixth active pattern
  • the fifth active pattern and the sixth active pattern are arranged along the second direction.
  • Embodiments of the present disclosure also provide a display device, including the display substrate provided in the above embodiments.
  • the display substrate provided by the above embodiment, by setting the reset circuit 20, a bias voltage opposite in sign to that in the light-emitting phase P4 can be applied to the driving circuit 11 in the bias compensation phase P2, thereby compensating the driving circuit 11 to work at a certain bias. After pressing for a period of time, the characteristics will shift, and the bad problems such as short-term afterimage and slow response time will be improved. Moreover, when driving at low frequency, it can compensate the difference in brightness caused by the characteristic deviation of the driving circuit 11 in the long-time light-emitting period, and improve the flicker phenomenon. Therefore, when the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device provided by the embodiments of the present disclosure includes the above-mentioned display substrate, it can realize specific bias compensation for the driving circuit 11 in each pixel circuit in the display substrate, and has a good compensation effect.
  • the reset voltage provided by the reset voltage line DR can be adjusted independently, it can provide an appropriate bias voltage to each pixel circuit in the display substrate as required.
  • the display device can be any product or component with a display function such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a back panel. board etc.
  • “same layer” in the embodiments of the present disclosure may refer to film layers on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and for relevant parts, please refer to part of the description of the product embodiments.

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Abstract

本公开提供一种像素电路及其驱动方法、显示基板、显示装置。所述像素电路中，数据写入电路用于在第一扫描线提供的第一扫描信号的控制下，控制数据线与驱动电路的第二端之间连通；复位电路用于在第三扫描线提供的第三扫描信号的控制下，控制复位电压线与驱动电路的第二端之间连通；或者，复位电路分别与第三扫描线，复位电压线和驱动电路的第一端耦接，用于在第三扫描信号的控制下，控制复位电压线与驱动电路的第一端之间连通。

Description

像素电路及其驱动方法、显示基板、显示装置
相关申请的交叉引用
本申请主张在2021年08月05日在中国提交的中国专利申请号No.202110898582.X的优先权，其全部内容通过引用包含于此。
本申请主张在2021年07月30日提交的申请号为PCT/CN2021/109894的PCT申请的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示基板、显示装置。
背景技术
随着有源矩阵有机发光二极管(英语：Active-matrix organic light-emitting diode，简称：AMOLED)显示屏在中高端市场的普及，AMOLED显示屏的品质要求越来越高，对设计也提出了更精细化的要求。
AMOLED显示屏包括的像素电路中，驱动晶体管工作在某一偏压一段时间后，其特性会发生偏移，即迟滞现象，这会导致短期残像和响应时间慢等不良问题。
发明内容
本公开的目的在于提供一种像素电路及其驱动方法、显示基板、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种像素电路，包括：驱动电路、数据写入电路和复位电路；
所述数据写入电路分别与第一扫描线，数据线和所述驱动电路的第二端耦接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述数据线与所述驱动电路的第二端之间连通；
所述复位电路分别与第三扫描线，复位电压线和所述驱动电路的第二端耦接，用于在所述第三扫描线提供的第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第二端之间连通；或者，所述复位电路分别与第三扫描线，复位电压线和所述驱动电路的第一端耦接，用于在所述第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第一端之间连通；
所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通。
可选的，所述像素电路还包括：补偿控制电路、第一初始化电路、发光控制电路，储能电路和发光元件；
所述补偿控制电路分别与第二扫描线，所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
所述第一初始化电路分别与初始化控制线，第一初始化电压线和所述驱动电路的控制端耦接，用于在所述初始化控制线提供的初始化控制信号的控制下，控制所述第一初始化电压线和所述驱动电路的控制端连通；
所述发光控制电路分别与发光控制线，所述驱动电路的第一端和所述发光元件耦接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第一端与所述发光元件之间连通；
所述储能电路分别与所述驱动电路的控制端与所述驱动电路的第二端耦接。
可选的，所述像素电路还包括：第二初始化电路；
所述第二初始化电路分别与所述第三扫描线，第二初始化电压线和所述发光元件耦接，用于在所述第三扫描信号的控制下，控制所述第二初始化电压线与所述发光元件之间连通。
可选的，所述第一初始化电压线复用为所述复位电压线。
可选的，所述发光控制电路还与第一电压线，所述驱动电路的第二端耦接，用于在所述发光控制信号的控制下，控制所述第一电压线与所述驱动电路的第二端之间连通。
可选的，所述补偿控制电路包括第一晶体管，所述第一初始化电路包括 第二晶体管，所述驱动电路包括第三晶体管，所述发光控制电路包括第五晶体管和第六晶体管；
所述第一晶体管的栅极与所述第二扫描线耦接，所述第一晶体管的第一极与所述第三晶体管的第二极耦接，所述第一晶体管的第二极与所述第三晶体管的栅极耦接；
所述第二晶体管的栅极与所述初始化控制线耦接，所述第二晶体管的第一极与所述第一初始化电压线耦接，所述第二晶体管的第二极与所述第三晶体管的栅极耦接；
所述第五晶体管的栅极与所述发光控制线耦接，所述第五晶体管的第一极与所述第一电压线耦接，所述第五晶体管的第二极与所述第三晶体管的第一极耦接；
所述第六晶体管的栅极与所述发光控制线耦接，所述第六晶体管的第一极与所述第三晶体管的第二极耦接，所述第六晶体管的第二极与所述发光元件耦接。
可选的，所述第一晶体管和所述第二晶体管为氧化物薄膜晶体管。
可选的，所述第二初始化电路包括第七晶体管，
所述第七晶体管的栅极与所述第三扫描线耦接，所述第七晶体管的第一极与所述第二初始化电压线耦接，所述第七晶体管的第二极与所述发光元件耦接。
可选的，所述数据写入电路包括第四晶体管，所述复位电路包括第八晶体管；
所述第四晶体管的栅极与所述第一扫描线耦接，所述第四晶体管的第一极与所述数据线耦接，所述第四晶体管的第二极与所述第三晶体管的第一极耦接；
所述第八晶体管的栅极与所述第三扫描线耦接，所述第八晶体管的第一极与所述复位电压线耦接，所述第八晶体管的第二极与所述第三晶体管的第一极或第二极耦接。
基于上述像素电路的技术方案，本公开的第二方面提供一种驱动方法，应用于上述像素电路，显示周期包括写入补偿阶段和偏压补偿阶段，所述驱 动方法包括：
在所述写入补偿阶段，数据写入电路在第一扫描信号的控制下，控制数据线与驱动电路的第二端之间连通；
在所述偏压补偿阶段，复位电路在第三扫描信号的控制下，控制复位电压线与所述驱动电路的第二端之间连通；或者，复位电路在第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第一端之间连通。
可选的，所述显示周期还包括初始化阶段和发光阶段；
在所述初始化阶段，所述像素电路中的所述第一初始化电路在初始化控制信号的控制下，控制第一初始化电压线和所述驱动电路的控制端连通；
在所述写入补偿阶段，所述像素电路中的补偿控制电路在第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
在发光阶段，所述像素电路中的发光控制电路在发光控制信号的控制下，控制所述第一电压线与所述驱动电路的第二端之间连通，并控制所述驱动电路的第一端与发光元件之间连通，驱动电路驱动发光元件发光。
可选的，所述显示周期还包括多个发光阶段和多个偏压补偿阶段，所述发光阶段和所述偏压补偿阶段交替设置。
基于上述像素电路的技术方案，本公开的第三方面提供一种显示基板，包括基底和设置于所述基底上的多个子像素，所述子像素包括上述像素电路；所述子像素还包括：
数据线，复位电压线，第一扫描线和第三扫描线；所述数据线包括沿第一方向延伸的至少部分，所述第一扫描线包括沿第二方向延伸的至少部分，所述第三扫描线包括沿所述第二方向延伸的至少部分，所述第二方向与所述第一方向相交；
数据写入电路分别与所述第一扫描线，所述数据线和驱动电路的第二端耦接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述数据线与所述驱动电路的第二端之间连通；
复位电路分别与所述第三扫描线和所述复位电压线耦接，还与所述驱动电路的第一端或第二端耦接，用于在所述第三扫描线提供的第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第二端之间连通；或者控制 所述复位电压线与所述驱动电路的第一端之间连通。
可选的，所述驱动电路包括第三晶体管，所述复位电路包括第八晶体管；
所述第八晶体管的栅极与所述第三扫描线耦接，所述第八晶体管的第一极与所述复位电压线耦接，所述第八晶体管的第二极与所述第三晶体管的第一极耦接；
所述复位电压线包括沿所述第一方向延伸的至少部分，所述复位电压线和所述数据线沿所述第二方向排列；所述复位电压线在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影至少部分交叠。
可选的，所述第八晶体管包括第八有源层，所述第八有源层包括沿所述第一方向延伸的至少部分；
所述第八有源层在所述基底上的正投影的至少部分，位于所述数据线在所述基底上的正投影和所述复位电压线在所述基底上的正投影之间；
所述第八有源层在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影沿所述第一方向排列。
可选的，所述子像素还包括第一导电连接部，所述第一导电连接部分别与所述第八晶体管的第二极和所述第三晶体管的第一极耦接；
所述第一导电连接部在所述基底上的正投影的至少部分，位于所述数据线在所述基底上的正投影与所述复位电压线在所述基底上的正投影之间。
可选的，所述驱动电路包括第三晶体管，所述复位电路包括第八晶体管；
所述第八晶体管的栅极与所述第三扫描线耦接，所述第八晶体管的第一极与所述复位电压线耦接，所述第八晶体管的第二极与所述第三晶体管的第二极耦接；
所述复位电压线包括沿所述第一方向延伸的至少部分，所述复位电压线和所述数据线沿所述第二方向排列；所述驱动晶体管的栅极在所述基底上的正投影，位于所述数据线在所述基底上的正投影和所述复位电压线在所述基底上的正投影之间。
可选的，所述第八晶体管包括第八有源层，所述第八有源层包括沿所述第一方向延伸的至少部分；
所述第八有源层在所述基底上的正投影，与所述复位电压线在所述基底 上的正投影至少部分交叠。
可选的，所述子像素还包括第二导电连接部，所述第二导电连接部分别与所述第八晶体管的第二极和所述第三晶体管的第二极耦接；
所述第二导电连接部在所述基底上的正投影，与所述复位电压线在所述基底上的正投影至少部分交叠。
可选的，所述子像素还包括：第一初始化电压线，所述第一初始化电压线包括沿第二方向延伸的至少部分；沿第一方向相邻的两个子像素中，其中一个子像素中所述第一初始化电压线，复用为另一个所述子像素中的所述复位电压线。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的像素电路的第一结构示意图；
图2为本公开实施例提供的像素电路的第二结构示意图；
图3为本公开实施例提供的像素电路的第一电路示意图；
图4为本公开实施例提供的特性偏移示意图；
图5为本公开实施例提供的像素电路的第一驱动时序图；
图6为本公开实施例提供的像素电路的第二驱动时序图；
图7为本公开实施例提供的像素电路的第二电路示意图；
图8为本公开实施例提供的像素电路的第三电路示意图；
图9为本公开实施例提供的像素电路的第四电路示意图；
图10为本公开实施例提供的显示基板的布局示意图；
图11为图3对应的布局示意图；
图12为图11中的poly有源层的布局示意图；
图13为图11中的第一栅金属层的布局示意图；
图14为图11中的第二栅金属层的布局示意图；
图15为图11中的氧化物有源层的布局示意图；
图16为图11中的第三栅金属层的布局示意图；
图17为图11中的第一连接孔的示意图；
图18为图11中的第二连接孔的示意图；
图19为图11中的第一源漏金属层的布局示意图；
图20为图11中的钝化层形成的过孔的示意图；
图21为图11中的第一平坦层形成的过孔的示意图；
图22为图11中的第二源漏金属层的布局示意图；
图23为图8对应的布局示意图；
图24为图23中的poly有源层的布局示意图；
图25为图23中的第一栅金属层的布局示意图；
图26为图23中的第一源漏金属层的布局示意图；
图27为图23中的钝化层形成的过孔的示意图；
图28为图23中的第一平坦层形成的过孔的示意图；
图29为图23中的第二源漏金属层的布局示意图；
图30为图9对应的布局示意图；
图31为图30中的第一源漏金属层的布局示意图；
图32为图30中的第二源漏金属层的布局示意图；
图33为本公开实施例提供的第二栅金属层至第三栅金属层的层叠示意图；
图34为本公开实施例提供的第八晶体管的截面示意图；
图35为图30中的poly有源层的布局示意图；
图36为图30中的第一栅金属层的布局示意图；
图37为图30中的氧化物有源层的布局示意图；
图38为图30中的第一连接孔的示意图；
图39为图30中的第二连接孔的示意图。
具体实施方式
为了进一步说明本公开实施例提供的像素电路及其驱动方法、显示基板、显示装置，下面结合说明书附图进行详细描述。
请参阅图1，图2，图3，图7至图9，本公开实施例提供了一种像素电路，包括：驱动电路11、数据写入电路41和复位电路20；
所述数据写入电路41分别与第一扫描线S1，数据线D1和所述驱动电路11的第二端耦接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述数据线D1与所述驱动电路11的第二端之间连通；
所述复位电路20分别与第三扫描线S3，复位电压线DR和所述驱动电路11的第二端耦接，用于在所述第三扫描线S3提供的第三扫描信号的控制下，控制所述复位电压线DR与所述驱动电路11的第二端(即第二节点N2)之间连通；或者，所述复位电路20分别与第三扫描线S3，复位电压线DR和所述驱动电路11的第一端(即第三节点N3)耦接，用于在所述第三扫描信号的控制下，控制所述复位电压线DR与所述驱动电路11的第一端之间连通；
所述驱动电路11用于在其控制端的电位的控制下，控制所述驱动电路11的第一端与所述驱动电路11的第二端之间连通。
示例性的，所述第一扫描线S1用于写入所述第一扫描信号，所述数据线D1用于写入数据信号。所述第三扫描线S3用于写入所述第三扫描信号。所述复位电压线DR用于提供复位电压。
如图5和图6所示，示例性的，所述数据信号用于常规图片显示。所述复位电压能够跟随所述数据信号变化，在偏压补偿阶段P2给驱动电路11包括的驱动晶体管施加和发光阶段P4符号相反的偏压，例如：发光阶段P4驱动晶体管的偏压Vgs(或Vgd)为5V，在补偿阶段通过复位电压线DR使得驱动晶体管的偏压为-5V。
示例性的，所述第一扫描信号处于有效电平时，所述数据写入电路41用于在所述第一扫描线S1提供的第一扫描信号的控制下，导通所述数据线D1与所述驱动电路11的第二端之间的电连接。所述第一扫描信号处于非有效电平时，所述数据写入电路41用于在所述第一扫描线S1提供的第一扫描信号的控制下，断开所述数据线D1与所述驱动电路11的第二端之间的电连接。
示例性的，当所述第三扫描信号处于有效电平时，所述复位电路20用于 在所述第三扫描信号的控制下，导通所述复位电压线DR与所述驱动电路11的第二端或所述驱动电路11的第一端之间的电连接。当所述第三扫描信号处于非有效电平时，所述复位电路20用于在所述第三扫描信号的控制下，断开所述复位电压线DR与所述驱动电路11的第二端或所述驱动电路11的第一端之间的电连接。
示例性的，所述像素电路工作的一个显示周期包括：写入补偿阶段P3和偏压补偿阶段P2。
在所述写入补偿阶段P3，数据写入电路41在第一扫描信号的控制下，控制数据线D1与驱动电路11的第二端之间连通，向驱动电路11的第二端写入数据信号。
在所述偏压补偿阶段P2，复位电路20在第三扫描信号的控制下，控制复位电压线DR与所述驱动电路11的第二端之间连通；或者，复位电路20在第三扫描信号的控制下，控制所述复位电压线DR与所述驱动电路11的第一端之间连通；以实现向所述驱动电路11的第一端或第二端写入复位电压。
根据上述像素电路的具体结构可知，本公开实施例提供的像素电路中，通过设置所述复位电路20，能够在偏压补偿阶段P2给驱动电路11施加和发光阶段P4符号相反的偏压，从而补偿驱动电路11工作在某一偏压一段时间后特性发生偏移，改善短期残像和慢响应时间等不良问题。而且在低频驱动时，可以补偿因长时间发光阶段驱动电路11特性偏移引起的亮度不同，改善Flicker现象。
另外，在将本公开实施例提供的像素电路应用于显示基板时，能够实现对显示基板中的每一个像素电路中的驱动电路11进行特定的偏压补偿，具有良好的补偿效果。
此外，由于所述复位电压线DR提供的复位电压可以独立调节，因此，可以根据需要向显示基板中各像素电路提供合适的偏压。
如图2，图3，图7至图9所示，在一些实施例中，所述像素电路还包括：补偿控制电路13、第一初始化电路14、发光控制电路31，储能电路42和发光元件O1；
所述补偿控制电路13分别与第二扫描线S2，所述驱动电路11的控制端 (即第一节点N1)和所述驱动电路11的第一端(即第三节点N3)电连接，用于在所述第二扫描线S2提供的第二扫描信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第一端之间连通；
所述第一初始化电路14分别与初始化控制线R1，第一初始化电压线Vinit1和所述驱动电路11的控制端耦接，用于在所述初始化控制线R1提供的初始化控制信号的控制下，控制所述第一初始化电压线Vinit1和所述驱动电路11的控制端连通；
所述发光控制电路31分别与发光控制线E1，所述驱动电路11的第一端和所述发光元件O1耦接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述驱动电路11的第一端与所述发光元件O1之间连通；
所述储能电路42分别与所述驱动电路11的控制端与所述驱动电路11的第二端耦接。
示例性的，所述像素电路工作的每个显示周期均包括：初始化阶段P1，偏压补偿阶段P2，写入补偿阶段P3和发光阶段P4。
更详细地说，在经历所述写入补偿阶段P3之后，所述驱动晶体管的栅极电位变为Vdata+Vth，Vdata为所述数据信号对应的数据电压，Vth为所述驱动晶体管的阈值电压。在进入发光阶段P4后，驱动晶体管的受到的应力Vgs1＝Vdata+Vth-VDD，VDD为驱动晶体管接收的电源电压。如图4所示，驱动电路11包括的驱动晶体管的特性会发生偏移，即从实线偏移到虚线。
在所述偏压补偿阶段P2，复位电路20向所述驱动电路11的第一端或第二端写入复位电压V1。该复位电压使得所述驱动晶体管受到的偏位为Vgs2，Vgs2满足：Vgs2＝-Vgs1。
即：Vgs2＝Vdata+Vth-V1＝-Vgs1＝-(Vdata+Vth-VDD)
需要说明，进入偏压补偿阶段P2时，驱动晶体管的栅极电压Vg保持不变。
V1＝2*(Vdata+Vth)-VDD
由于VDD是固定值，Vth能够通过测试得到，因此能够到V1和Vdata之间的取值关系。按照上述关系设置V1，能够实现最好的补偿效果。
在所述偏压补偿阶段P2中，驱动晶体管由于受到和发光阶段P4大小相 同，方向相反的偏压，则如图4所示，特性曲线会从虚线回到实线，从而完成偏压补偿。
如图2，图3，图7至图9所示，在一些实施例中，所述像素电路还包括：第二初始化电路32；
所述第二初始化电路32分别与所述第三扫描线S3，第二初始化电压线Vinit2和所述发光元件O1耦接，用于在所述第三扫描信号的控制下，控制所述第二初始化电压线Vinit2与所述发光元件O1之间连通。
示例性的，所述第二初始化电压线Vinit2用于提供第二初始化电压。
所述第二初始化电路32能够在所述第三扫描信号的控制下，实现对所述发光元件O1的第一极的复位。
需要说明，所述发光元件O1的第一极包括阳极，所述发光元件O1的第二极(即阴极)接收负电源信号VSS。
如图7和图9所示，在一些实施例中，所述第一初始化电压线Vinit1复用为所述复位电压线DR。
示例性的，所述复位电路20与所述第一初始化电压线Vinit1耦接。所述第一初始化电压线Vinit1提供的第一初始化电压可调。
示例性的，所述第一初始化电压线Vinit1提供的第一初始化电压可变。示例性的，所述第一初始化电压用于对驱动晶体管的栅极复位时，可设置为-5V，所述第一初始化电压用于偏压补偿时，可设置为5V。
设置第一初始化电压线Vinit1复用为所述复位电压线DR能够简化子像素结构，降低子像素的布局难度，提升显示基板的分辨率。
如图2，图3，图7至图9所示，在一些实施例中，所述发光控制电路31还与第一电压线(写入VDD信号)，所述驱动电路11的第二端耦接，用于在所述发光控制信号的控制下，控制所述第一电压线与所述驱动电路11的第二端之间连通。
示例性的，所述第一电压线包括正电源线。通过所述发光控制信号控制上述第一电压线提供的第一电压是否写入至所述驱动电路11的第二端。
如图2，图3，图7至图9所示，在一些实施例中，所述补偿控制电路13包括第一晶体管T1，所述第一初始化电路14包括第二晶体管T2，所述驱 动电路11包括第三晶体管T3(即所述驱动晶体管)，所述发光控制电路31包括第五晶体管T5和第六晶体管T6；
所述第一晶体管T1的栅极与所述第二扫描线S2耦接，所述第一晶体管T1的第一极与所述第三晶体管T3的第二极耦接，所述第一晶体管T1的第二极与所述第三晶体管T3的栅极T3-g耦接；
所述第二晶体管T2的栅极与所述初始化控制线R1耦接，所述第二晶体管T2的第一极与所述第一初始化电压线Vinit1耦接，所述第二晶体管T2的第二极与所述第三晶体管T3的栅极T3-g耦接；
所述第五晶体管T5的栅极与所述发光控制线E1耦接，所述第五晶体管T5的第一极与所述第一电压线耦接，所述第五晶体管T5的第二极与所述第三晶体管T3的第一极耦接；
所述第六晶体管T6的栅极与所述发光控制线E1耦接，所述第六晶体管T6的第一极与所述第三晶体管T3的第二极耦接，所述第六晶体管T6的第二极与所述发光元件O1耦接。
在一些实施例中，所述第一晶体管T1和所述第二晶体管T2为氧化物薄膜晶体管。
示例性的，所述第一晶体管T1和所述第二晶体管T2包括低温多晶氧化物晶体管(英文：Low Temperature Polycrystalline Oxide，简称：LTPO)。
通过设置所述第一晶体管T1和所述第二晶体管T2为氧化物薄膜晶体管，有利于降低所述驱动晶体管的栅极漏电，保证驱动晶体管的栅极电位稳定。
如图2，图3，图7至图9所示，在一些实施例中，所述第二初始化电路32包括第七晶体管T7，
所述第七晶体管T7的栅极与所述第三扫描线S3耦接，所述第七晶体管T7的第一极与所述第二初始化电压线Vinit2耦接，所述第七晶体管T7的第二极与所述发光元件O1耦接。
在一些实施例中，所述数据写入电路41包括第四晶体管T4，所述复位电路20包括第八晶体管T8；
所述第四晶体管T4的栅极与所述第一扫描线S1耦接，所述第四晶体管T4的第一极与所述数据线D1耦接，所述第四晶体管T4的第二极与所述第三 晶体管T3的第一极耦接；
所述第八晶体管T8的栅极T8-g与所述第三扫描线S3耦接，所述第八晶体管T8的第一极与所述复位电压线DR耦接，所述第八晶体管T8的第二极与所述第三晶体管T3的第一极或第二极耦接。
示例性的，如图2，图3，图7至图9中，标号为N1的为第一节点，第一节点N1与T3的栅极电连接；标号为N2的为第二节点，标号为N3的为第三节点；N2与T3的源极电连接，N3与T3的漏极电连接。
示例性的，在所述像素电路的至少一实施例中，T1和T2可以为氧化物薄膜晶体管，T3、T4、T5、T6、T7和T8可以都为低温多晶硅薄膜晶体管，T1和T2为n型晶体管，T3、T4、T5、T6、T7和T8为p型晶体管，但不以此为限。
示例性的，T1和T2可以为单栅晶体管或双栅晶体管。
示例性的，T1的沟道宽长比W/L中，W的取值范围在2微米至4微米之间，可以包括端点值，L的取值范围在3微米至6微米之间，可以包括端点值。
示例性的，T2与T1的沟道宽长比相同。
示例性的，T8的沟道宽长比W/L中，W的取值范围在2微米至3微米之间，可以包括端点值，L的取值范围在3.2微米至6微米之间，可以包括端点值。
如图5和图6所示，上述结构的像素电路的具体驱动过程包括：
在初始化阶段P1，R1提供高电压信号，T2打开。S1提供高电压信号，T4关闭。S2提供低电压信号，T1关闭。S3提供高电压信号，T7和T8关闭。在所述初始化阶段P1实现对T3的栅极初始化，以使得在写入补偿阶段P3开始时，T3能够打开。
在偏压补偿时段，R1提供低电压信号，T2关闭。S1提供高电压信号，T4关闭。S2提供低电压信号，T1关闭。S3提供低电压信号，T7和T8打开。在所述偏压补偿时段，能够将DR提供的复位电压写入第三晶体管T3的第一极或第二极，将第二初始化电压写入O1的阳极，对O1的阳极初始化。
在写入补偿阶段P3，T3打开。R1提供低电压信号，T2关闭。S1提供低 电压信号，T4打开。S2提供高电压信号，T1打开。S3提供高电压信号，T7和T8关闭。数据线D1上的数据电压Vdata写入第三晶体管T3的第一极。在所述写入补偿阶段P3，通过Vdata，经过打开的T4、T3和T1为C充电，以提升T3的栅极的电位，直至T3关断，此时，T3的栅极的电位为Vdata+Vth。
在发光阶段P4，E1提供低电压信号，R1提供低电压信号，S1提供高电压信号，S2提供低电压信号，S3提供高电压信号，T1、T2、T4、T7和T8关断，T5和T6打开，T3打开，以驱动O1发光。
通过增设T8，为T3的第一极或第二极提供偏压，有利于提高T3稳定性；通过设置T7，以对O1的阳极的电位进行初始化，利于低频闪烁下的开关频率切换的自由度。
在一些实施例中，所述像素电路需要在阈值补偿阶段导通T3，因此，第一初始化电压线Vinit1提供的第一初始化电压Vi1与复位电压线DR提供的复位电压V1的电压差Vi1-V1需要小于驱动晶体管T3的阈值电压Vth。其中，Vi1可以为-2～-6V，例如，-2V、-3V、-4V、-5V、-6V等。Vi1-V1可以小于a*Vth，a可以为2～7，例如，a可以为2、4、6、7；Vth可以为-2～-5V，例如-2V、-3V、-5V等。V1可以大于1.5倍的Vth，例如，V1可以为Vth的1.6倍、1.8倍、2倍等。
示例性的，V1大于0。V1的取值在4～10V之间，可以包括端点值。
在一些实施例中，T8的宽长比W/L可以大致等于T7的宽长比W/L；又例如，T8的宽长比W/L可以大于T7的宽长比W/L，也即是T8的宽长比W/L可以稍大，如此可以使得N2节点得到快速复位。
在一些实施例中，T8的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等；T7的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
在一些实施例中，T8的宽长比W/L可以大致等于T2的宽长比W/L；又例如，T8的宽长比W/L可以小于T2的宽长比W/L，如此可以平衡N1节点和N2节点复位能力。
在一些实施例中，T8的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等；T2的沟道宽W为1.5-3.5，例如可以是1.6、1.8，、1.9、2.0、2.2、2.5、3.0等；沟道长L为2.0-4.5；例如可以是2.5、2.7、3.0、3.2、3.5、4.0等。
如图1，图5和图6所示，本公开实施例还提供了一种驱动方法，应用于上述实施例提供的像素电路，显示周期包括写入补偿阶段P3和偏压补偿阶段P2，所述驱动方法包括：
在所述写入补偿阶段P3，数据写入电路41在第一扫描信号的控制下，控制数据线D1与驱动电路11的第二端之间连通；
在所述偏压补偿阶段P2，复位电路20在第三扫描信号的控制下，控制复位电压线DR与所述驱动电路11的第二端之间连通；或者，复位电路20在第三扫描信号的控制下，控制所述复位电压线DR与所述驱动电路11的第一端之间连通。
采用本公开实施例提供的驱动方法驱动上述像素电路时，能够在偏压补偿阶段P2给驱动电路11施加和发光阶段P4符号相反的偏压，从而补偿驱动电路11工作在某一偏压一段时间后特性发生偏移，改善短期残像和慢响应时间等不良问题。而且在低频驱动时，可以补偿因长时间发光阶段驱动电路11特性偏移引起的亮度不同，改善Flicker现象。另外，能够实现对显示基板中的每一个像素电路中的驱动电路11进行特定的偏压补偿，具有良好的补偿效果。此外，由于所述复位电压线DR提供的复位电压可以独立调节，因此，可以根据需要向显示基板中各像素电路提供合适的偏压。
如图5和图6所示，在一些实施例中，所述显示周期还包括初始化阶段P1和发光阶段P4；
在所述初始化阶段P1，所述像素电路中的所述第一初始化电路14在初始化控制信号的控制下，控制第一初始化电压线Vinit1和所述驱动电路11的控制端连通；
在所述写入补偿阶段P3，所述像素电路中的补偿控制电路13在第二扫描信号的控制下，控制所述驱动电路11的控制端与所述驱动电路11的第一 端之间连通；
在发光阶段P4，所述像素电路中的发光控制电路31在发光控制信号的控制下，控制所述第一电压线与所述驱动电路11的第二端之间连通，并控制所述驱动电路11的第一端与发光元件O1之间连通，驱动电路11驱动发光元件O1发光。
更详细地说，在所述初始化阶段P1，所述第一初始化电路14控制第一初始化电压线Vinit1和所述驱动电路11的控制端连通，对所述驱动电路11的控制端初始化。在所述偏压补偿阶段P2，复位电路20控制复位电压线DR与所述驱动电路11的第二端之间连通，或者控制所述复位电压线DR与所述驱动电路11的第一端之间连通。在所述写入补偿阶段P3，补偿控制电路13控制所述驱动电路11的控制端与所述驱动电路11的第一端之间连通。在所述写入补偿阶段P3中的至少部分时段，数据写入电路41控制数据线D1与驱动电路11的第二端之间连通。在所述发光阶段P4，发光控制电路31控制所述第一电压线与所述驱动电路11的第二端之间连通，并控制所述驱动电路11的第一端与发光元件O1之间连通，驱动电路11驱动发光元件O1发光。
如图5和图6所示，在一些实施例中，所述显示周期还包括多个发光阶段P4和多个偏压补偿阶段P2，所述发光阶段P4和所述偏压补偿阶段P2交替设置。
示例性的，所述显示周期依次包括：初始化阶段P1，偏压补偿阶段P2，写入补偿阶段P3，发光阶段P4，偏压补偿阶段P2，发光阶段P4，偏压补偿阶段P2，发光阶段P4，偏压补偿阶段P2，发光阶段P4。
需要说明，所述发光阶段P4的数量和所述偏压补偿阶段P2的数量可以根据实际需要设置。
上述在一帧内几个固定阶段实施偏压补偿，更有利于显示基板处于低频显示时，对驱动电路11实现偏压补偿。
在一些实施例中，以行扫描时间h为单位，1h＝1秒/(刷新频率*总行数)。
所述发光控制线E1提供的发光控制信号处于有效电平(如高电平)的宽度在30h～40h之间，可以包括端点值。
所述初始化控制线R1提供的初始化控制信号处于有效电平(如高电平) 的宽度在10h～15h之间，可以包括端点值。
所述第二扫描线S2提供的第二扫描信号处于有效电平(如高电平)的宽度在10h～15h之间，可以包括端点值。
所述第三扫描线S3提供的第三扫描信号处于有效电平(如低电平)的宽度在1h～3h之间，可以包括端点值。
所述第一扫描线S1提供的第一扫描信号处于有效电平(如低电平)的宽度在1h～3h之间，可以包括端点值。
所述数据线D1提供的数据信号的有效电平宽度包括1h。
示例性的，发光控制信号的有效电平宽度是初始化控制信号的有效电平宽度的2至4倍。
示例性的，发光控制信号的有效电平宽度是第二扫描信号的有效电平宽度的2至4倍。
如图1至图9，图11，图23和图30所示，本公开实施例还提供了一种显示基板，包括基底和设置于所述基底上的多个子像素，所述子像素包括上述实施例提供的像素电路；所述子像素还包括：
数据线D1，复位电压线DR，第一扫描线S1和第三扫描线S3；所述数据线D1包括沿第一方向延伸的至少部分，所述第一扫描线S1包括沿第二方向延伸的至少部分，所述第三扫描线S3包括沿所述第二方向延伸的至少部分，所述第二方向与所述第一方向相交；
数据写入电路41分别与所述第一扫描线S1，所述数据线D1和驱动电路11的第二端耦接，用于在所述第一扫描线S1提供的第一扫描信号的控制下，控制所述数据线D1与所述驱动电路11的第二端之间连通；
复位电路20分别与所述第三扫描线S3和所述复位电压线DR耦接，还与所述驱动电路11的第一端或第二端耦接，用于在所述第三扫描线S3提供的第三扫描信号的控制下，控制所述复位电压线DR与所述驱动电路11的第二端之间连通；或者控制所述复位电压线DR与所述驱动电路11的第一端之间连通。
示例性的，上述显示基板包括呈阵列分布的多个子像素，每个子像素均包括像素电路。
示例性的，沿所述第一方向位于同一列的子像素中，各数据线D1依次耦接形成为一体结构。
示例性的，沿所述第一方向位于同一列的子像素中，各复位电压线DR依次耦接形成为一体结构。示例性的，沿所述第二方向位于同一行的子像素中，各复位电压线DR依次耦接形成为一体结构。
示例性的，沿所述第二方向位于同一行的子像素中，各第一扫描线S1依次耦接形成为一体结构。示例性的，沿所述第二方向位于同一行的子像素中，各第三扫描线S3依次耦接形成为一体结构。
示例性的，所述显示基板包括沿远离所述基底的方向层叠设置于所述基底上的：遮光层，隔离层，第一缓冲层，poly有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层，第二栅金属层，第一层间绝缘层，第二缓冲层，氧化物有源层(如IGZO)，第三栅极绝缘层，第三栅金属层，第二层间绝缘层，第一源漏金属层，钝化层，第一平坦层，第二源漏金属层，第二平坦层，阳极层，像素界定层，隔垫物层，发光功能层，阴极层和封装层。
示例性的，所述基底包括PI基底。在沉积形成所述第二层间绝缘层后，可以进行CNT打孔工艺(如：CNT-L/EBA和CNT-O/EBB)，然后继续进行层间绝缘层的mask工艺，形成仅贯穿所述第二层间绝缘层的过孔，贯穿所述第二层间绝缘层至第三栅极绝缘层的过孔，贯穿所述第二层间绝缘层至第一层间绝缘层的过孔，贯穿所述第二层间绝缘层至第二栅极绝缘层的过孔，贯穿所述第二层间绝缘层至第一栅极绝缘层的过孔，贯穿所述第二层间绝缘层至隔离层的过孔。
示例性的，所述数据线D1采用第二源漏金属层制作。所述复位电压线DR采用第二源漏金属层或第一源漏金属层制作。所述第一扫描线S1和所述第三扫描线S3均采用第一栅金属层制作。
示例性的，所述第一方向包括纵向，所述第二方向包括横向。
由于上述实施例提供的像素电路中，通过设置所述复位电路20，能够在偏压补偿阶段P2给驱动电路11施加和发光阶段P4符号相反的偏压，从而补偿驱动电路11工作在某一偏压一段时间后特性发生偏移，改善短期残像和慢响应时间等不良问题。而且在低频驱动时，可以补偿因长时间发光阶段驱动 电路11特性偏移引起的亮度不同，改善Flicker现象。因此，本公开实施例提供的显示基板在包括上述像素电路时，同样具有上述有益效果，此处不再赘述。
另外，在本公开实施例提供的显示基板在包括上述像素电路时，能够实现对显示基板中的每一个像素电路中的驱动电路11进行特定的偏压补偿，具有良好的补偿效果。此外，由于所述复位电压线DR提供的复位电压可以独立调节，因此，可以根据需要向显示基板中各像素电路提供合适的偏压。
在一些实施例中，所述显示基板包括多个阵列分布的像素电路P，多条复位电压线DR11、DR12、DR21、DR22，复位电压线DR11、DR12、DR21、DR22均可以用于提供复位电压。
如图10所示，复位电压线DR11、DR12沿列方向延伸，复位电压线DR21、DR22沿行方向延伸，相邻两行像素电路可以与同一行向延伸的复位电压线DR连接，该复位电压线DR可以位于上述相邻两行像素驱动电路11之间，沿列方向延伸的复位电压线DR可以连接与其相交的多条沿行方向延伸的复位电压线DR，从而多条复位电压线DR可以形成网格结构。其中，沿列方向延伸的复位电压线DR可以位于红色像素电路所在的区域内。此外，在同一像素行中，相邻列的两个像素电路可以镜像设置，以方便布线。
如图11至图22所示，在一些实施例中，所述驱动电路11包括第三晶体管T3，所述复位电路20包括第八晶体管T8；
所述第八晶体管T8的栅极T8-g与所述第三扫描线S3耦接，所述第八晶体管T8的第一极与所述复位电压线DR耦接，所述第八晶体管T8的第二极与所述第三晶体管T3的第一极耦接；
所述复位电压线DR包括沿所述第一方向延伸的至少部分，所述复位电压线DR和所述数据线D1沿所述第二方向排列；所述复位电压线DR在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影至少部分交叠。
示例性的，所述第三晶体管T3的栅极T3-g采用第一栅金属层制作。所述第八晶体管T8的栅极T8-g与所述第三扫描线S3形成为一体结构。
示例性的，所述复位电压线DR与所述数据线D1同层同材料设置。
示例性的，所述数据线D1在所述基底上的正投影与所述驱动晶体管的栅 极在所述基底上的正投影不交叠。所述复位电压线DR在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影至少部分交叠。
如图34所示，示例性的，第八晶体管T8通过第三导电连接部63与复位电压线DR耦接。
需要说明，图12中示意了T3包括的第三有源层53，T4包括的第四有源层54，T5包括的第五有源层55，T6包括的第六有源层56，T7包括第七有源层57。图15示意了T1包括的第一有源层51，T2包括的第二有源层52。图19示意了第三导电连接部63。图33中示意了第二栅金属层Gate2，第一层间绝缘层ILD1，第二缓冲层Buffer2，氧化物层(IGZO)，第三栅极绝缘层GI3，第三栅金属层Gate3。
需要说明，图17中的第一连接孔用于连接第一源漏金属层和其下方相应的结构，图17中的各个第一连接孔的深度可以相同或不同。图18中的第二连接孔用于连接第一源漏金属层和其下方相应的结构，图18中的各个第二连接孔的深度可以相同或不同。
需要说明，图23和图30对应的实施例中，有部分单层膜层没有示意，参见图11对应的单层膜层即可。
上述设置方式有利于降低所述子像素的布局难度。
如图11至图22所示，在一些实施例中，所述第八晶体管T8包括第八有源层58，所述第八有源层58包括沿所述第一方向延伸的至少部分；
所述第八有源层58在所述基底上的正投影的至少部分，位于所述数据线D1在所述基底上的正投影和所述复位电压线DR在所述基底上的正投影之间；
所述第八有源层58在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影沿所述第一方向排列。
示例性的，所述第八有源层58采用poly有源层制作。
示例性的，所述第八有源层58在所述基底上的正投影，与所述复位电压线DR在所述基底上的正投影至少部分交叠。
示例性的，所述第八有源层58在所述基底上的正投影，与所述数据线D1在所述基底上的正投影不交叠。
示例性的，所述第八有源层58在所述基底上的正投影的至少部分，位于 所述发光控制线E1在所述基底上的正投影与所述第二初始化电压线Vinit2在所述基底上的正投影之间。
上述设置方式有利于降低所述子像素的布局难度，减小所述第八晶体管T8产生的寄生电容。
如图11至图22所示，在一些实施例中，所述子像素还包括第一导电连接部61，所述第一导电连接部61分别与所述第八晶体管T8的第二极和所述第三晶体管T3的第一极耦接；
所述第一导电连接部61在所述基底上的正投影的至少部分，位于所述数据线D1在所述基底上的正投影与所述复位电压线DR在所述基底上的正投影之间。
示例性的，所述第一导电连接部61采用所述第一源漏金属层制作。
示例性的，所述第一导电连接部61在所述基底上的正投影，与所述数据线D1在所述基底上的正投影部分交叠，与所述复位电压线DR在所述基底上的正投影部分交叠。
示例性的，所述第一导电连接部61在所述基底上的正投影，与所述数据线D1在所述基底上的正投影不交叠，与所述复位电压线DR在所述基底上的正投影不交叠。
示例性的，所述第一导电连接部61在所述基底上的正投影与所述发光控制线E1在所述基底上的正投影部分交叠。
示例性的，所述第一导电连接部61在所述基底上的正投影与所述存储电容C的第二极板C2在所述基底上的正投影不交叠。
示例性的，所述第一导电连接部61分别与所述第八晶体管T8的第二极和所述第三晶体管T3的第一极通过相应的过孔耦接。
示例性的，所述第一导电连接部61包括沿所述第一方向延伸的部分，还包括沿第三方向延伸的部分，所述第三方向与所述第一方向和所述第二方向均相交。
上述设置方式有利于降低所述子像素的布局难度。
如图11至图22所示，在一些实施例中，所述第二初始化电压线Vinit2包括主体部，第一突出部和第二突出部，所述主体部包括沿所述第二方向延 伸的至少部分，所述第一突出部和所述第二突出部沿所述第二方向排列；第二初始化电路32包括第七晶体管T7，所述第七晶体管T7的栅极与所述第三扫描线S3耦接，所述第七晶体管T7的第一极与所述第一突出部耦接；所述第八晶体管T8的第一极与所述第二突出部耦接。
示例性的，所述第七晶体管T7包括第七有源层，所述第八有源层58与所述第七有源层沿所述第二方向排列。所述第八有源层58在所述基底上的正投影位于所述第七有源层在所述基底上的正投影与所述数据线D1在所述基底上的正投影之间。
如图23至图29所示，在一些实施例中，所述驱动电路11包括第三晶体管T3，所述复位电路20包括第八晶体管T8；
所述第八晶体管T8的栅极T8-g与所述第三扫描线S3耦接，所述第八晶体管T8的第一极与所述复位电压线DR耦接，所述第八晶体管T8的第二极与所述第三晶体管T3的第二极耦接；
所述复位电压线DR包括沿所述第一方向延伸的至少部分，所述复位电压线DR和所述数据线D1沿所述第二方向排列；所述驱动晶体管的栅极在所述基底上的正投影，位于所述数据线D1在所述基底上的正投影和所述复位电压线DR在所述基底上的正投影之间。
示例性的，所述驱动晶体管的栅极在所述基底上的正投影，与所述数据线D1在所述基底上的正投影不交叠。所述驱动晶体管的栅极在所述基底上的正投影，与所述复位电压线DR在所述基底上的正投影不交叠。
上述设置方式不仅有利于降低所述子像素的布局难度，而且将所述数据线D1和所述复位电压线DR布局在所述子像素的两侧，能够很好的避免同一个子像素中所述数据线D1与所述复位电压线DR之间相互干扰。
如图23至图29所示，在一些实施例中，所述第八晶体管T8包括第八有源层58，所述第八有源层58包括沿所述第一方向延伸的至少部分；
所述第八有源层58在所述基底上的正投影，与所述复位电压线DR在所述基底上的正投影至少部分交叠。
示例性的，所述第八有源层58在所述基底上的正投影，被所述复位电压线DR在所述基底上的正投影覆盖。
如图23至图29所示，在一些实施例中，所述子像素还包括第二导电连接部62，所述第二导电连接部62分别与所述第八晶体管T8的第二极和所述第三晶体管T3的第二极耦接；
所述第二导电连接部62在所述基底上的正投影，与所述复位电压线DR在所述基底上的正投影至少部分交叠。
示例性的，所述第二导电连接部62采用所述第一源漏金属层制作。
示例性的，所述第二导电连接部62包括沿所述第一方向延伸的部分和沿所述第三方向延伸的部分。
示例性的，所述第二导电连接部62在所述基底上的正投影与所述发光控制线E1在所述基底上的正投影部分交叠。
示例性的，所述第二导电连接部62分别与所述第八晶体管T8的第二极和所述第三晶体管T3的第二极通过过孔耦接。
示例性的，所述第二导电连接部62在所述基底上的正投影与所述存储电容C的第二极板C2在所述基底上的正投影部分交叠。
上述设置方式有利于降低所述子像素的布局难度。
如图30至图32，图35至图39所示，在一些实施例中，所述子像素还包括：第一初始化电压线Vinit1，所述第一初始化电压线Vinit1包括沿第二方向延伸的至少部分；沿第一方向相邻的两个子像素中，其中一个子像素中所述第一初始化电压线Vinit1’，复用为另一个所述子像素中的所述复位电压线DR。
示例性的，所述第二初始化电压线Vinit2采用所述第一源漏金属层制作。
示例性的，所述第一初始化电压线Vinit1采用所述第一栅金属层制作。
需要说明，图35中右上角的独立小图形为沿第一方向相邻的上一个子像素中的部分第八有源层。图37中最下方的独立小图形为沿第一方向相邻的下一个子像素中的第二有源层。
上述设置所述第一初始化电压线Vinit1’复用为所述复位电压线DR，避免了布局额外的专门用于提供复位电压的复位电压线DR，有利于简化子像素的复杂程度，降低子像素的布局难度。
在一些实施例中，所述第二初始化电压线Vinit2包括：第一初始子图形，第二初始子图形，第三初始子图形和第三突出部；所述第一初始子图形和所述第三初始子图形均沿所述第二方向延伸，所述第一初始子图形和所述第三初始子图形沿所述第一方向错开，所述第一初始子图形和所述第三初始子图形通过所述第二初始子图形耦接；所述第三突出部与所述第三初始子图形耦接；第二初始化电路32包括第七晶体管T7，所述第七晶体管T7的栅极与所述第三扫描线S3耦接，所述第七晶体管T7的第一极与所述第一初始子图形耦接；所述第八晶体管T8的第一极与所述第三突出部耦接。
示例性的，所述第七晶体管T7包括第七有源层，所述第七有源层在所述基底上的正投影位于所述数据线D1在所述基底上的正投影与所述复位线在所述基底上的正投影之间。
示例性的，所述第七有源层在所述基底上的正投影位于所述数据线D1在所述基底上的正投影与所述第八有源层58在所述基底上的正投影之间。
如图11，图14和图16所示，在一些实施例中，所述子像素还包括第二扫描线S2，所述第二扫描线S2包括第一扫描子图形S21和第三扫描子图形S22，所述第一扫描子图形S21的至少部分和所述第三扫描子图形S22的至少部分均沿所述第二方向延伸；
补偿控制电路13包括第一晶体管T1，所述第一晶体管T1包括第一氧化物有源层；在垂直于所述基底的方向上，所述第一氧化物有源层的至少部分位于所述第一扫描子图形和所述第三扫描子图形之间。
示例性的，所述第一扫描子图形采用第二栅金属层制作，所述第三扫描子图形采用第三栅金属层制作。所述第一扫描子图形的至少部分位于所述基底与所述第三扫描子图形之间。
如图11，图14和图16所示，在一些实施例中，所述子像素还包括初始化控制线R1，所述初始化控制线R1包括第一初始化子图形R11和第二初始化子图形R12，所述第一初始化子图形R11的至少部分和所述第二初始化子图形R12的至少部分均沿所述第二方向延伸；
第一初始化电路14包括第二晶体管T2，所述第二晶体管T2包括第二氧化物有源层；在垂直于所述基底的方向上，所述第二氧化物有源层的至少部 分位于所述第一初始化子图形和所述第二初始化子图形之间。
示例性的，所述第一初始化子图形采用第二栅金属层制作，所述第二初始化子图形采用第三栅金属层制作。所述第一初始化子图形的至少部分位于所述基底与所述第二初始化子图形之间。
如图15所示，在一些实施例中，所述第一氧化物有源层(如标记51)和所述第二氧化物有源层(如标记52)沿所述第一方向排列；
所述数据写入电路41包括第四晶体管T4，所述第四晶体管T4包括第四有源层，所述第四有源层在所述基底上的正投影，与所述数据线D1在所述基底上的正投影至少部分交叠，所述第四有源层与所述第一氧化物有源层沿所述第二方向排列。
在一些实施例中，所述子像素还包括发光控制线E1，所述发光控制线E1包括沿所述第二方向延伸的至少部分；
发光控制电路31包括第五晶体管T5和第六晶体管T6，所述第五晶体管T5的栅极与所述发光控制线E1耦接，所述第六晶体管T6的栅极与所述发光控制线E1耦接；
所述第五晶体管T5包括第五有源图形，所述第六晶体管T6包括第六有源图形，所述第五有源图形和所述第六有源图形沿所述第二方向排列。
本公开实施例还提供一种显示装置，包括上述实施例提供的显示基板。
由于上述实施例提供的显示基板中，通过设置所述复位电路20，能够在偏压补偿阶段P2给驱动电路11施加和发光阶段P4符号相反的偏压，从而补偿驱动电路11工作在某一偏压一段时间后特性发生偏移，改善短期残像和慢响应时间等不良问题。而且在低频驱动时，可以补偿因长时间发光阶段驱动电路11特性偏移引起的亮度不同，改善Flicker现象。因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
另外，在本公开实施例提供的显示装置在包括上述显示基板时，能够实现对显示基板中的每一个像素电路中的驱动电路11进行特定的偏压补偿，具有良好的补偿效果。此外，由于所述复位电压线DR提供的复位电压可以独立调节，因此，可以根据需要向显示基板中各像素电路提供合适的偏压。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板等。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何 的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种像素电路，包括：驱动电路、数据写入电路和复位电路；
    所述数据写入电路分别与第一扫描线，数据线和所述驱动电路的第二端耦接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述数据线与所述驱动电路的第二端之间连通；
    所述复位电路分别与第三扫描线，复位电压线和所述驱动电路的第二端耦接，用于在所述第三扫描线提供的第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第二端之间连通；或者，所述复位电路分别与第三扫描线，复位电压线和所述驱动电路的第一端耦接，用于在所述第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第一端之间连通；
    所述驱动电路用于在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：补偿控制电路、第一初始化电路、发光控制电路，储能电路和发光元件；
    所述补偿控制电路分别与第二扫描线，所述驱动电路的控制端和所述驱动电路的第一端电连接，用于在所述第二扫描线提供的第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
    所述第一初始化电路分别与初始化控制线，第一初始化电压线和所述驱动电路的控制端耦接，用于在所述初始化控制线提供的初始化控制信号的控制下，控制所述第一初始化电压线和所述驱动电路的控制端连通；
    所述发光控制电路分别与发光控制线，所述驱动电路的第一端和所述发光元件耦接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第一端与所述发光元件之间连通；
    所述储能电路分别与所述驱动电路的控制端与所述驱动电路的第二端耦接。
  3. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：第二初始化电路；
    所述第二初始化电路分别与所述第三扫描线，第二初始化电压线和所述 发光元件耦接，用于在所述第三扫描信号的控制下，控制所述第二初始化电压线与所述发光元件之间连通。
  4. 根据权利要求2所述的像素电路，其中，所述第一初始化电压线复用为所述复位电压线。
  5. 根据权利要求2所述的像素电路，其中，所述发光控制电路还与第一电压线，所述驱动电路的第二端耦接，用于在所述发光控制信号的控制下，控制所述第一电压线与所述驱动电路的第二端之间连通。
  6. 根据权利要求5所述的像素电路，其中，所述补偿控制电路包括第一晶体管，所述第一初始化电路包括第二晶体管，所述驱动电路包括第三晶体管，所述发光控制电路包括第五晶体管和第六晶体管；
    所述第一晶体管的栅极与所述第二扫描线耦接，所述第一晶体管的第一极与所述第三晶体管的第二极耦接，所述第一晶体管的第二极与所述第三晶体管的栅极耦接；
    所述第二晶体管的栅极与所述初始化控制线耦接，所述第二晶体管的第一极与所述第一初始化电压线耦接，所述第二晶体管的第二极与所述第三晶体管的栅极耦接；
    所述第五晶体管的栅极与所述发光控制线耦接，所述第五晶体管的第一极与所述第一电压线耦接，所述第五晶体管的第二极与所述第三晶体管的第一极耦接；
    所述第六晶体管的栅极与所述发光控制线耦接，所述第六晶体管的第一极与所述第三晶体管的第二极耦接，所述第六晶体管的第二极与所述发光元件耦接。
  7. 根据权利要求6所述的像素电路，其中，所述第一晶体管和所述第二晶体管为氧化物薄膜晶体管。
  8. 根据权利要求3所述的像素电路，其中，所述第二初始化电路包括第七晶体管，
    所述第七晶体管的栅极与所述第三扫描线耦接，所述第七晶体管的第一极与所述第二初始化电压线耦接，所述第七晶体管的第二极与所述发光元件耦接。
  9. 根据权利要求1所述的像素电路，其中，所述数据写入电路包括第四晶体管，所述复位电路包括第八晶体管；
    所述第四晶体管的栅极与所述第一扫描线耦接，所述第四晶体管的第一极与所述数据线耦接，所述第四晶体管的第二极与所述第三晶体管的第一极耦接；
    所述第八晶体管的栅极与所述第三扫描线耦接，所述第八晶体管的第一极与所述复位电压线耦接，所述第八晶体管的第二极与所述第三晶体管的第一极或第二极耦接。
  10. 一种驱动方法，应用于如权利要求1至9中任一项所述的像素电路，显示周期包括写入补偿阶段和偏压补偿阶段，所述驱动方法包括：
    在所述写入补偿阶段，数据写入电路在第一扫描信号的控制下，控制数据线与驱动电路的第二端之间连通；
    在所述偏压补偿阶段，复位电路在第三扫描信号的控制下，控制复位电压线与所述驱动电路的第二端之间连通；或者，复位电路在第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第一端之间连通。
  11. 根据权利要求10所述的驱动方法，其中，所述显示周期还包括初始化阶段和发光阶段；
    在所述初始化阶段，所述像素电路中的所述第一初始化电路在初始化控制信号的控制下，控制第一初始化电压线和所述驱动电路的控制端连通；
    在所述写入补偿阶段，所述像素电路中的补偿控制电路在第二扫描信号的控制下，控制所述驱动电路的控制端与所述驱动电路的第一端之间连通；
    在发光阶段，所述像素电路中的发光控制电路在发光控制信号的控制下，控制所述第一电压线与所述驱动电路的第二端之间连通，并控制所述驱动电路的第一端与发光元件之间连通，驱动电路驱动发光元件发光。
  12. 根据权利要求10所述的驱动方法，其中，所述显示周期还包括多个发光阶段和多个偏压补偿阶段，所述发光阶段和所述偏压补偿阶段交替设置。
  13. 一种显示基板，包括基底和设置于所述基底上的多个子像素，所述子像素包括如权利要求1～9中任一项所述的像素电路；所述子像素还包括：
    数据线，复位电压线，第一扫描线和第三扫描线；所述数据线包括沿第 一方向延伸的至少部分，所述第一扫描线包括沿第二方向延伸的至少部分，所述第三扫描线包括沿所述第二方向延伸的至少部分，所述第二方向与所述第一方向相交；
    数据写入电路分别与所述第一扫描线，所述数据线和驱动电路的第二端耦接，用于在所述第一扫描线提供的第一扫描信号的控制下，控制所述数据线与所述驱动电路的第二端之间连通；
    复位电路分别与所述第三扫描线和所述复位电压线耦接，还与所述驱动电路的第一端或第二端耦接，用于在所述第三扫描线提供的第三扫描信号的控制下，控制所述复位电压线与所述驱动电路的第二端之间连通；或者控制所述复位电压线与所述驱动电路的第一端之间连通。
  14. 根据权利要求13所述的显示基板，其中，
    所述驱动电路包括第三晶体管，所述复位电路包括第八晶体管；
    所述第八晶体管的栅极与所述第三扫描线耦接，所述第八晶体管的第一极与所述复位电压线耦接，所述第八晶体管的第二极与所述第三晶体管的第一极耦接；
    所述复位电压线包括沿所述第一方向延伸的至少部分，所述复位电压线和所述数据线沿所述第二方向排列；所述复位电压线在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影至少部分交叠。
  15. 根据权利要求14所述的显示基板，其中，所述第八晶体管包括第八有源层，所述第八有源层包括沿所述第一方向延伸的至少部分；
    所述第八有源层在所述基底上的正投影的至少部分，位于所述数据线在所述基底上的正投影和所述复位电压线在所述基底上的正投影之间；
    所述第八有源层在所述基底上的正投影与所述驱动晶体管的栅极在所述基底上的正投影沿所述第一方向排列。
  16. 根据权利要求14所述的显示基板，其中，所述子像素还包括第一导电连接部，所述第一导电连接部分别与所述第八晶体管的第二极和所述第三晶体管的第一极耦接；
    所述第一导电连接部在所述基底上的正投影的至少部分，位于所述数据线在所述基底上的正投影与所述复位电压线在所述基底上的正投影之间。
  17. 根据权利要求13所述的显示基板，其中，
    所述驱动电路包括第三晶体管，所述复位电路包括第八晶体管；
    所述第八晶体管的栅极与所述第三扫描线耦接，所述第八晶体管的第一极与所述复位电压线耦接，所述第八晶体管的第二极与所述第三晶体管的第二极耦接；
    所述复位电压线包括沿所述第一方向延伸的至少部分，所述复位电压线和所述数据线沿所述第二方向排列；所述驱动晶体管的栅极在所述基底上的正投影，位于所述数据线在所述基底上的正投影和所述复位电压线在所述基底上的正投影之间。
  18. 根据权利要求17所述的显示基板，其中，
    所述第八晶体管包括第八有源层，所述第八有源层包括沿所述第一方向延伸的至少部分；
    所述第八有源层在所述基底上的正投影，与所述复位电压线在所述基底上的正投影至少部分交叠。
  19. 根据权利要求17所述的显示基板，其中，
    所述子像素还包括第二导电连接部，所述第二导电连接部分别与所述第八晶体管的第二极和所述第三晶体管的第二极耦接；
    所述第二导电连接部在所述基底上的正投影，与所述复位电压线在所述基底上的正投影至少部分交叠。
  20. 根据权利要求13所述的显示基板，其中，所述子像素还包括：第一初始化电压线，所述第一初始化电压线包括沿第二方向延伸的至少部分；沿第一方向相邻的两个子像素中，其中一个子像素中所述第一初始化电压线，复用为另一个所述子像素中的所述复位电压线。
  21. 一种显示装置，包括如权利要求13至20中任一项所述的显示基板。
PCT/CN2022/105457 2021-07-30 2022-07-13 像素电路及其驱动方法、显示基板、显示装置 Ceased WO2023005669A1 (zh)

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