WO2023108734A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023108734A1
WO2023108734A1 PCT/CN2021/140207 CN2021140207W WO2023108734A1 WO 2023108734 A1 WO2023108734 A1 WO 2023108734A1 CN 2021140207 W CN2021140207 W CN 2021140207W WO 2023108734 A1 WO2023108734 A1 WO 2023108734A1
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WO
WIPO (PCT)
Prior art keywords
transistor
sub
pixels
gate
driving
Prior art date
Application number
PCT/CN2021/140207
Other languages
English (en)
French (fr)
Inventor
王选芸
戴超
秦芳
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Publication of WO2023108734A1 publication Critical patent/WO2023108734A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • the present application relates to the field of display technology, in particular to a display panel.
  • PMOS metal oxide semiconductor field effect transistors
  • LTPS low temperature polysilicon
  • the present application provides a display panel to realize pixel circuit design for ultra-low frequency and ultra-low power consumption display.
  • this application provides
  • a display panel which includes a plurality of sub-pixels, each sub-pixel includes a driving circuit, the driving circuit includes:
  • a light emitting device and a driving transistor are connected in series between the first power supply voltage and the second power supply voltage;
  • a first transistor the gate of the first transistor is connected to the first control signal, and the drain of the first transistor is electrically connected to the gate of the driving transistor, wherein the first transistor is an oxide film transistor;
  • one end of the first capacitor is electrically connected to the gate of the driving transistor, and the other end of the first capacitor is connected to the first power supply voltage;
  • the second transistor the gate of the second transistor is connected to the second control signal, the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is connected to the second transistor.
  • the drain of the driving transistor is electrically connected;
  • the third transistor the gate of the third transistor is connected to the third control signal, the source of the third transistor is connected to the first reset signal, and the drain of the third transistor is connected to the source of the first transistor. sexual connection.
  • the first transistor is a P-type transistor or an N-type transistor.
  • the driving transistor, the second transistor and the third transistor are low temperature polysilicon thin film transistors.
  • the driving circuit further includes a fourth transistor; the gate of the fourth transistor is connected to the second control signal, and the source of the fourth transistor is connected to the The data signal, the drain of the fourth transistor is electrically connected to the source of the driving transistor.
  • the fourth transistor is a low temperature polysilicon thin film transistor.
  • the driving circuit further includes a fifth transistor and a sixth transistor; both the gate of the fifth transistor and the gate of the sixth transistor are connected to a light-emitting control signal,
  • the source of the fifth transistor is connected to the first power supply voltage
  • the drain of the fifth transistor is electrically connected to the source of the driving transistor
  • the drain of the sixth transistor is connected to the light emitting device
  • the anode of the sixth transistor is electrically connected to the source of the sixth transistor and the drain of the driving transistor is electrically connected.
  • the second transistor and the sixth transistor have a single gate structure.
  • the fifth transistor and the sixth transistor are low temperature polysilicon thin film transistors.
  • the driving circuit further includes a seventh transistor, the gate of the seventh transistor is connected to the second control signal, and the source of the seventh transistor is connected to the first Two reset signals, the drain of the seventh transistor is electrically connected to the anode of the light emitting device.
  • the seventh transistor is a low temperature polysilicon thin film transistor.
  • the first control signal is the light emission control signal.
  • the driving circuit further includes a second capacitor, one end of the second capacitor is electrically connected to the gate of the driving transistor, and the other end of the second capacitor is connected to input the second control signal.
  • the potential of the first power supply voltage is greater than the potential of the second power supply voltage.
  • the light emitting device is an organic light emitting diode.
  • the driving circuits of the plurality of sub-pixels are arranged in an array, wherein the driving circuits of two adjacent columns of sub-pixels are arranged in a mirror-symmetrical structure.
  • the display panel further includes:
  • the first conductive channel layer includes a polysilicon active layer and a first plate of a first capacitor
  • the first metal layer including the gate electrode of the polysilicon thin film transistor and the second plate of the first capacitor;
  • the second metal layer comprising a gate electrode of an oxide thin film transistor
  • the third metal layer including the source and drain of the polysilicon thin film transistor, and the source and drain of the oxide thin film transistor;
  • a second conductive channel layer, the second conductive channel layer includes an oxide semiconductor active layer.
  • the sub-pixels located in the same row are sequentially divided into multiple pairs of sub-pixels, and each pair of sub-pixels has a common boundary
  • the active layers of the first transistors in each pair of sub-pixels are oppositely arranged and close to the common boundary of each pair of sub-pixels, and each pair of sub-pixels
  • the active layer of the first transistor is parallel to the common side of each pair of sub-pixels.
  • the first metal layer further includes a first plate of the second capacitor
  • the second conductive channel layer further includes a second plate of the second capacitor
  • the sub-pixels located in the same row are sequentially divided into multiple pairs of sub-pixels, and each pair of sub-pixels has a common boundary;
  • the second plate of the second capacitor and the active layer of the first transistor are located in the same axis direction, and the second capacitors in each pair of sub-pixels are opposite to each other. direction and close to the common boundary of each pair of sub-pixels.
  • the present application also provides a display panel, which includes a plurality of sub-pixels, each sub-pixel includes a driving circuit, and the driving circuit includes:
  • a light emitting device and a driving transistor are connected in series between the first power supply voltage and the second power supply voltage;
  • a first transistor the gate of the first transistor is connected to the first control signal, and the drain of the first transistor is electrically connected to the gate of the driving transistor, wherein the first transistor is an oxide film transistor;
  • one end of the first capacitor is electrically connected to the gate of the driving transistor, and the other end of the first capacitor is connected to the first power supply voltage;
  • the second transistor the gate of the second transistor is connected to the second control signal, the source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is connected to the second transistor.
  • the drain of the driving transistor is electrically connected;
  • the third transistor the gate of the third transistor is connected to the third control signal, the source of the third transistor is connected to the first reset signal, and the drain of the third transistor is connected to the source of the first transistor. sexual connection;
  • the driving transistor, the second transistor and the third transistor are low temperature polysilicon thin film transistors.
  • the first transistor is a P-type transistor or an N-type transistor.
  • the driving circuit further includes a fourth transistor; the gate of the fourth transistor is connected to the second control signal, and the source of the fourth transistor is connected to the The data signal, the drain of the fourth transistor is electrically connected to the source of the driving transistor.
  • the fourth transistor is a low temperature polysilicon thin film transistor.
  • the driving circuit further includes a fifth transistor and a sixth transistor; both the gate of the fifth transistor and the gate of the sixth transistor are connected to a light-emitting control signal,
  • the source of the fifth transistor is connected to the first power supply voltage
  • the drain of the fifth transistor is electrically connected to the source of the driving transistor
  • the drain of the sixth transistor is connected to the light emitting device
  • the anode of the sixth transistor is electrically connected to the source of the sixth transistor and the drain of the driving transistor is electrically connected.
  • the second transistor and the sixth transistor have a single gate structure.
  • the fifth transistor and the sixth transistor are low temperature polysilicon thin film transistors.
  • the driving circuit further includes a seventh transistor, the gate of the seventh transistor is connected to the second control signal, and the source of the seventh transistor is connected to the first Two reset signals, the drain of the seventh transistor is electrically connected to the anode of the light emitting device.
  • the seventh transistor is a low temperature polysilicon thin film transistor.
  • the first control signal is the light emission control signal.
  • the driving circuit further includes a second capacitor, one end of the second capacitor is electrically connected to the gate of the driving transistor, and the other end of the second capacitor is connected to input the second control signal.
  • the potential of the first power supply voltage is greater than the potential of the second power supply voltage.
  • the light emitting device is an organic light emitting diode.
  • the driving circuits of the plurality of sub-pixels are arranged in an array, wherein the driving circuits of two adjacent columns of sub-pixels are arranged in a mirror-symmetrical structure.
  • the display panel further includes:
  • the first conductive channel layer includes a polysilicon active layer and a first plate of a first capacitor
  • the first metal layer including the gate electrode of the polysilicon thin film transistor and the second plate of the first capacitor;
  • the second metal layer comprising a gate electrode of an oxide thin film transistor
  • the third metal layer including the source and drain of the polysilicon thin film transistor, and the source and drain of the oxide thin film transistor;
  • a second conductive channel layer, the second conductive channel layer includes an oxide semiconductor active layer.
  • the sub-pixels located in the same row are sequentially divided into multiple pairs of sub-pixels, and each pair of sub-pixels has a common boundary
  • the active layers of the first transistors in each pair of sub-pixels are oppositely arranged and close to the common boundary of each pair of sub-pixels, and each pair of sub-pixels
  • the active layer of the first transistor is parallel to the common side of each pair of sub-pixels.
  • the first metal layer further includes a first plate of the second capacitor
  • the second conductive channel layer further includes a second plate of the second capacitor
  • the sub-pixels located in the same row are sequentially divided into multiple pairs of sub-pixels, and each pair of sub-pixels has a common boundary;
  • the present application provides a display panel.
  • the display panel includes a plurality of sub-pixels, and each sub-pixel includes a driving circuit, and the driving circuit includes a light-emitting device, a driving transistor, a first transistor, a first capacitor, a second transistor and a third transistor.
  • FIG. 1 is a schematic structural diagram of a first driving circuit of a display panel provided by the present application
  • FIG. 2 is a timing diagram of the display panel described in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a second drive circuit of the display panel provided by the present application.
  • FIG. 4 is a timing diagram of the display panel described in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a third drive circuit of the display panel provided by the present application.
  • FIG. 6 is a timing diagram of the display panel described in FIG. 5;
  • FIG. 8 is a schematic diagram of the symmetrical structure of the third metal layer of the sub-pixel of the display panel provided by the present application.
  • the transistors used in all embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain can be interchanged. of. In the embodiment of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the source, and the other pole is called the drain. According to the form in the accompanying drawings, it is stipulated that the middle terminal of the switching transistor is the gate, the signal input terminal is the source terminal, and the output terminal is the drain terminal.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors, wherein, the P-type transistors are turned on when the gate is at a low level, and are turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level. It turns on when the gate is high and turns off when the gate is low.
  • the middle terminal of the transistor is the gate
  • the signal input terminal is the source terminal
  • the output terminal is the drain terminal.
  • the present application provides a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a schematic structural diagram of a first driving circuit of a display panel provided by the present application.
  • the present application provides a display panel, which includes a plurality of sub-pixels, and each sub-pixel includes a driving circuit 100, and the driving circuit 100 includes a light emitting device D, a driving transistor Td, a writing module 101, a compensation module 102, a light emission control module 103 and a first A reset module 104 .
  • the light emitting device D may be a mini light emitting diode, a micro light emitting diode or an organic light emitting diode.
  • the light emitting device D and the driving transistor Td are connected in series between the first power supply voltage VDD and the second power supply voltage VSS.
  • the source and the drain of the driving transistor Td are connected in series between the first power supply voltage and the second power supply voltage.
  • the writing module 101 receives the second control signal S2(n) and the data signal Da, and is electrically connected to the source of the driving transistor Td.
  • the writing module 101 is used for writing the data signal Da into the source of the driving transistor Td under the control of the second control signal S2(n).
  • the compensation module 102 receives the first control signal S1(n) and the first power supply voltage VDD, and is electrically connected to the drain of the driving transistor Td and the gate of the driving transistor Td. The compensation module 102 is used for compensating the threshold voltage of the driving transistor Td under the control of the first control signal S1(n).
  • the compensation module 102 includes a first transistor T1, a second transistor T2, and a first capacitor C1; the gate of the first transistor T1 is connected to the first control signal S1(n), the drain of the first transistor T1 and the first One end of the capacitor C1 is electrically connected to the gate of the driving transistor Td, the gate of the second transistor T2 is connected to the second control signal S2(n), the source of the second transistor T2 is connected to the gate of the first transistor T1 The source of the second transistor T2 is electrically connected to the drain of the driving transistor Td, the other end of the first capacitor C1 is connected to the first power supply voltage VDD, and the first transistor T1 is an oxide thin film transistors.
  • the compensation module 102 may also be formed by connecting multiple transistors and a capacitor in series.
  • the light emission control module 103 is connected with the light emission control signal EM and connected in series with the light emission circuit.
  • the light emitting control module 103 is used for controlling the light emitting circuit to be turned on or off under the control of the light emitting control signal EM. It should be noted that in this application, it is only necessary to ensure that the lighting control module 103 and the lighting device D are connected in series to the lighting circuit.
  • the display panel shown in FIG. 1 only shows a specific position of the lighting control module 103 and the lighting device D. As shown in FIG. That is, the lighting control module 103 and the lighting device D can be connected in series at any position on the lighting circuit.
  • the first reset module 104 accesses the third control signal S1(n-1) and the first reset signal V1, and is electrically connected to the source of the first transistor T1.
  • the first reset module 104 is used for receiving the third control signal S1 Under the control of (n-1), the potential of the gate of the drive transistor Td is reset.
  • the first reset module 104 includes a third transistor T3, the gate of the third transistor T3 is connected to the third control signal S1(n-1), the source of the third transistor T3 is connected to the first reset signal V1, and the second transistor T2
  • the drain of the T1 is electrically connected to the source of the first transistor T1.
  • the first reset module 104 may also be formed by using multiple transistors connected in series.
  • the drain of the first transistor is electrically connected to the gate of the driving transistor
  • the source of the third transistor is electrically connected to the source of the first transistor
  • the first transistor is an oxide thin film transistor. After the first transistor is turned off, the light-emitting device is turned on to start emitting light. After the first transistor is turned off, the low leakage characteristic of the oxide thin film transistor is used to suppress the change of the gate potential of the driving transistor within one frame time. The potential stability of the gate of the drive transistor is improved, thereby ensuring the uniformity of light emission of the light emitting device, so the leakage current is controlled by the oxide thin film transistor, and the effect of high-quality display, low frequency and low power consumption is realized.
  • the driving circuit further includes a second reset module 105, the second reset module 105 receives the second control signal S2(n) and the second reset signal V2, and is electrically connected to the light emitting device D anode.
  • the second reset module 105 is used for resetting the potential of the anode of the light emitting device D under the control of the second control signal S2(n).
  • the potential of the anode of the light emitting device D can be reset, so as to prevent the residual charge of the anode of the light emitting device D from affecting the luminous brightness of the light emitting device D.
  • FIG. 1 is a schematic structural diagram of a first driving circuit of a display panel provided by the present application.
  • the writing module 101 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the second control signal S2(n).
  • the source of the fourth transistor T4 is connected to the data signal Da.
  • the drain of the fourth transistor T4 is electrically connected to the source of the driving transistor Td.
  • the writing module 101 may also be formed by using multiple transistors connected in series.
  • the light emission control module 103 includes a fifth transistor T5 and a sixth transistor T6; the gate of the fifth transistor T5 and the gate of the sixth transistor T6 are both connected to the light emission control signal EM, the The source of the fifth transistor T5 is connected to the first power supply voltage VDD, the drain of the fifth transistor T5 is electrically connected to the source of the driving transistor Td; the drain of the sixth transistor T6 is connected to the The anode of the light-emitting device D is electrically connected, and the source of the sixth transistor T6 is electrically connected to the drain of the driving transistor Td.
  • the light emission control module 103 can also be formed by using a plurality of transistors connected in series.
  • the second reset module 105 has a seventh transistor T7, the gate of the seventh transistor T7 is connected to the second control signal S2(n), and the source of the seventh transistor T7 is connected to the first Two reset signals V2, the drain of the seventh transistor T7 is electrically connected to the anode of the light emitting device D.
  • the second reset module 105 may also be formed by using a plurality of transistors connected in series.
  • the first control signal S1(n) is set as the light emission control signal EM.
  • the arrangement of driving signals can be reduced, so as to facilitate the narrow border of the screen.
  • the display panel provided in this application uses a display panel with an 8T1C (eight transistors and one capacitor) structure to control the light-emitting device D, uses fewer components, has a simple and stable structure, and saves costs.
  • 8T1C eight transistors and one capacitor
  • both the first power supply voltage VDD and the second power supply voltage VSS are used to output a preset voltage value.
  • the potential of the first power supply voltage VDD is greater than the potential of the second power supply voltage VSS.
  • the potential of the second power supply voltage VSS may be the potential of the ground terminal.
  • the potential of the second power supply voltage VSS can also be other.
  • FIG. 7 is a schematic diagram of the symmetrical structure of the sub-pixel of the display panel provided by the present application
  • FIG. 8 is a schematic diagram of the symmetrical structure of the third metal layer of the sub-pixel of the display panel provided by the present application.
  • the driving circuits of the plurality of sub-pixels are arranged in an array, wherein the driving circuits of two adjacent columns of sub-pixels are arranged in a mirror-symmetrical structure, as shown in the driving circuits of sub-pixel n and sub-pixel n+1 in Fig. 7 and Fig. 8 It is mirror symmetrical.
  • the drive circuits of two adjacent columns of sub-pixels are arranged in a mirror-symmetrical structure, so as to provide space for improving the pixel density, which is beneficial to the realization of high pixel density panel design.
  • the display panel further includes: a first conductive channel layer, a first metal layer, a second metal layer, a third metal layer, and a second conductive channel layer;
  • the first conductive channel layer includes a polysilicon active layer and a first plate of the first capacitor C1; the first metal layer includes a gate electrode of a polysilicon thin film transistor and a second plate of the first capacitor C1;
  • the second metal layer includes the gate electrode of the oxide thin film transistor;
  • the third metal layer includes the source and drain of the polysilicon thin film transistor, and the source and drain of the oxide thin film transistor;
  • the The second conductive channel layer includes an oxide semiconductor active layer.
  • the sub-pixels located in the same row are divided into multiple pairs of sub-pixels in sequence, each pair of sub-pixels has a common boundary, and in the second conductive channel layer, each pair of sub-pixels
  • the active layer of the first transistor T1 in each pair of sub-pixels is arranged opposite to each other and close to the common boundary of each pair of sub-pixels, and the active layer of the first transistor T1 in each pair of sub-pixels is connected to that of each pair of sub-pixels common borders are parallel.
  • FIG. 2 is a timing diagram of the display panel shown in FIG. 1 .
  • the combination of the light emission control signal EM, the first control signal S1(n), the second control signal S2(n) and the third control signal S1(n-1) corresponds to the reset phase t1, the compensation phase t2 and the light emission phase t3. That is, within one frame time, the driving control sequence of the display panel provided by the present application includes a reset phase t1 , a compensation phase t2 and a light emitting phase t3 .
  • the third control signal S1(n ⁇ 1) is at a low potential.
  • the first control signal S1(n), the second control signal S2(n) and the light emission control signal EM are all high potentials.
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned off.
  • the first transistor T1 and the third transistor T3 are turned on.
  • the first reset signal V1 is output to the gate of the driving transistor Td through the third transistor and the first transistor.
  • the potential of the gate of the driving transistor Td is reset to the potential of the first reset signal V1.
  • the second control signal S2(n) is low.
  • the first control signal S1(n), the third control signal S1(n-1) and the light emission control signal EM are all high potentials.
  • the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are all turned off.
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on.
  • the data signal Da is written into the gate of the driving transistor Td through the second transistor, the driving transistor Td, the first transistor and the fourth transistor.
  • the driving transistor Td is turned off, and the potential of the gate of the driving transistor Td no longer rises.
  • the first capacitor C1 stores the potential of the gate of the driving transistor Td.
  • the seventh transistor T7 is turned on.
  • the potential of the anode of the light emitting device D is reset to the potential of the second reset signal V2. Therefore, it is ensured that the light emitting device D does not emit light during the compensation phase t2.
  • the first control signal S1(n) and the light-emitting control signal EM are both at low potential, and the second control signal S2(n) and the third control signal S1(n-1) are both at high potential.
  • the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 and the seventh transistor T7 are all turned off.
  • the driving transistor Td, the sixth transistor T6 and the fifth transistor T5 are all turned on.
  • the driving transistor Td generates a driving current corresponding to the data signal Da by the potential of the gate.
  • the driving current flows to the light emitting device D through the turned-on driving transistor Td, the fifth transistor T5 and the sixth transistor T6 to drive the light emitting device D to emit light.
  • FIG. 3 is a schematic structural diagram of the second driving circuit of the display panel provided in this application.
  • the driving circuit in this application The transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all N-type transistors for illustration, but it should not be understood as a limitation of the present application.
  • the first control signal S1(n) and the light emission control signal are independent control signals.
  • the first control signal S1(n) and the second control signal S2(n) are at low potential. Both the third control signal S1(n ⁇ 1) and the light emission control signal EM are high potentials.
  • the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are all turned off.
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on.
  • the data signal Da is written into the gate of the driving transistor Td through the second transistor, the driving transistor Td, the first transistor and the fourth transistor.
  • the driving transistor Td is turned off, and the potential of the gate of the driving transistor Td no longer rises.
  • the first capacitor C1 stores the potential of the gate of the driving transistor Td.
  • the seventh transistor T7 is turned on.
  • the potential of the anode of the light emitting device D is reset to the potential of the second reset signal V2. Therefore, it is ensured that the light emitting device D does not emit light during the compensation phase t2.
  • the light-emitting control signal EM is all at low potential, and the first control signal S1(n), the second control signal S2(n) and the third control signal S1(n-1) are all at high potential.
  • the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 and the seventh transistor T7 are all turned off.
  • the driving transistor Td, the sixth transistor T6 and the fifth transistor T5 are all turned on.
  • the driving transistor Td generates a driving current corresponding to the data signal Da by the potential of the gate.
  • the driving current flows to the light emitting device D through the turned-on driving transistor Td, the fifth transistor T5 and the sixth transistor T6 to drive the light emitting device D to emit light.
  • FIG. 5 is a schematic structural diagram of a third driving circuit of the display panel provided by the present application.
  • the driving circuit further includes a second capacitor C2.
  • One end of the second capacitor C2 is electrically connected to the gate of the driving transistor Td, and the other end of the second capacitor C2 is connected to the first control signal S1(n).
  • the potential of the drain of the first transistor will be coupled to a lower potential due to the coupling effect of the parasitic capacitance, thereby affecting the gate potential of the driving transistor Td.
  • the potential of the drain of the first transistor can be reverse-coupled, so that the potential of the drain of the first transistor can be as consistent as possible with the potential of the gate of the driving transistor Td. Thereby, the potential stability of the gate of the drive transistor Td can be further ensured.
  • the specific coupling process will be described in detail in the following embodiments.
  • the sub-pixels located in the same row are divided into multiple pairs of sub-pixels in sequence, and each pair of sub-pixels has a common boundary; in the second conductive channel layer, the second capacitance
  • the second plate and the active layer of the first transistor are located in the same axial direction, and the second capacitors in each pair of sub-pixels are oppositely disposed and close to a common boundary of each pair of sub-pixels.
  • the second capacitors in each pair of sub-pixels are arranged close to each other to facilitate insulation arrangement, which can reduce the cost and space of insulation arrangement, and is beneficial to realize high pixel density panel design.
  • arranging the second electrode plate of the second capacitor and the active layer of the first transistor in the same axial direction can reduce the design space and is beneficial to realize the panel design with high pixel density.
  • the first metal layer further includes a first plate of the second capacitor
  • the second conductive channel layer further includes a second plate of the second capacitor.
  • the driving control sequence of the display panel shown in FIG. 5 is the same as that of the display panel shown in FIG. 1 . That is, the driving control sequence of the display panel shown in FIG. 5 includes a reset phase t1 , a compensation phase t2 and a light emitting phase t3 .
  • the first control signal S1(n) changes from a high potential to a low potential.
  • the potential of the drain of the first transistor is coupled to a potential lower than that of the gate of the driving transistor Td. Subsequent in the light-emitting stage, due to the leakage of the first transistor, the potential of the gate of the driving transistor Td will continue to drop.
  • the light emission control signal EM changes from a high potential to a low potential. Due to the coupling effect of the second capacitor C2, the potential of the drain of the first transistor is pulled up. Further, by designing the capacitance of the second capacitor C2, the potential of the drain of the first transistor can be pulled up to be substantially consistent with the potential of the gate of the driving transistor Td. Therefore, the potential stability of the gate of the driving transistor Td is improved, and the luminance of the light emitting device D is prevented from changing within a frame time.
  • FIG. 6 is a timing diagram of the light emitting device driving circuit shown in FIG. 5 .
  • the drive control sequence of the display panel further includes a capacitive coupling phase t4. That is, within one frame time, the driving control sequence of the display panel provided by the present application includes a reset phase t1 , a compensation phase t2 , a capacitive coupling phase t4 and a light emitting phase t3 .
  • the working process of the display panel in the reset phase t1 and the compensation phase t2 can refer to the above-mentioned embodiments, and will not be repeated here.
  • both the second control signal S2(n) and the third control signal S1(n ⁇ 1) are at high potentials.
  • the first control signal S1(n) and the light emission control signal EM change from a high potential to a low potential.
  • the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 and the seventh transistor T7 are all turned off.
  • the fifth transistor T5 and the sixth transistor T6 are switched from off to on.
  • the first control signal S1(n) changes from a high potential to a low potential.
  • the potential of the drain of the first transistor is coupled to a lower potential than the gate of the driving transistor Td. Subsequent in the light-emitting stage, due to the leakage of the first transistor, the potential of the gate of the driving transistor Td will continue to drop.
  • the light emission control signal EM changes from a high potential to a low potential. Due to the coupling effect of the second capacitor C2, the potential of the drain of the first transistor is pulled up. Further, by designing the capacitance of the second capacitor C2, the potential of the drain of the first transistor can be pulled up to be substantially consistent with the potential of the gate of the driving transistor Td. Therefore, the potential stability of the gate of the driving transistor Td is improved, and the luminance of the light emitting device D is prevented from changing within a frame time.
  • the capacitive coupling stage t4 when the light emitting control signal EM changes from a high potential to a low potential, the light emitting device D will also emit light. However, since the time of the capacitive coupling stage t4 is very short, the overall luminance of the light emitting device D will not be affected.
  • the first control signal S1(n) and the light-emitting control signal EM are both at low potential, and the second control signal S2(n) and the third control signal S1(n-1) are both at high potential.
  • the first transistor, the second transistor, the third transistor, the fourth transistor and the seventh transistor are all turned off.
  • the driving transistor Td, the fifth transistor T5 and the sixth transistor T6 are all turned on.
  • the driving transistor Td generates a driving current corresponding to the data signal Da by the potential of the gate.
  • the driving current flows to the light emitting device D through the turned-on fifth transistor T5 , the driving transistor Td and the sixth transistor T6 , to drive the light emitting device D to emit light.

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Abstract

一种显示面板，包括多个子像素，每个子像素包含一个驱动电路，驱动电路包括发光器件（D）、驱动晶体管（Td）、第一晶体管（T1）、第一电容（C1）、第二晶体管（T2）和第三晶体管（T3）。通过第一晶体管（T1）的漏极与驱动晶体管（Td）的栅极电性连接，第一晶体管（T1）关闭后利用氧化物薄膜晶体管的低漏电特性在一帧时间内抑制驱动晶体管的栅极电位变化。

Description

显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板。
 背景技术
随着多媒体的发展，显示装置变得越来越重要。相应地，对各种类型的显示装置的要求越来越高，尤其是智能手机领域，超高频驱动显示，低功耗驱动显示，以及低频驱动显示都是现阶段和未来的发展需求方向。
P-沟道金属氧化物半导体场效应晶体管（PMOS）广泛用作显示装置的晶体管，手机领域广泛应用低温多晶硅（LTPS）。然而，LTPS存在一个致命弱点就是漏电流较大，尤其是在低频显示时闪烁（flicker）严重。
有鉴于此，现有技术需要改进。
 技术问题
本申请提供一种显示面板，以实现超低频和超低功耗显示的像素电路设计。
 技术解决方案
第一方面，本申请提供
一种显示面板，其包括多个子像素，每个子像素包含一个驱动电路，所述驱动电路包括：
发光器件和驱动晶体管，所述发光器件和所述驱动晶体管串接于第一电源电压与第二电源电压之间；
第一晶体管，所述第一晶体管的栅极接入第一控制信号，所述第一晶体管的漏极与所述驱动晶体管的栅极电性连接，其中，所述第一晶体管为氧化物薄膜晶体管；
第一电容，所述第一电容的一端与所述驱动晶体管的栅极电性连接，所述第一电容的另一端接入所述第一电源电压；
第二晶体管，所述第二晶体管的栅极接入第二控制信号，所述第二晶体管的源极与所述第一晶体管的源极电性连接，所述第二晶体管的漏极与所述驱动晶体管的漏极电性连接；
第三晶体管，所述第三晶体管的栅极接入第三控制信号，所述第三晶体管的源极接入第一复位信号，所述第三晶体管的漏极与第一晶体管的源极电性连接。
可选的，在本申请一些实施例中，所述第一晶体管为P型晶体管或N型晶体管。
可选的，在本申请一些实施例中，所述驱动晶体管、第二晶体管和第三晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述驱动电路还包括第四晶体管；所述第四晶体管的栅极接入所述第二控制信号，所述第四晶体管的源极接入所述数据信号，所述第四晶体管的漏极与所述驱动晶体管的源极电性连接。
可选的，在本申请一些实施例中，所述第四晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述驱动电路还包括第五晶体管和第六晶体管；所述第五晶体管的栅极和所述第六晶体管的栅极均接入发光控制信号，所述第五晶体管的源极接入所述第一电源电压，所述第五晶体管的漏极与所述驱动晶体管的源极电性连接；所述第六晶体管的漏极与所述发光器件的阳极电性连接，所述第六晶体管的源极与所述驱动晶体管的漏极电性连接。
可选的，在本申请一些实施例中，所述第二晶体管和所述第六晶体管为单栅极结构。
可选的，在本申请一些实施例中，所述第五晶体管和第六晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述驱动电路还包括第七晶体管，所述第七晶体管的栅极接入所述第二控制信号，所述第七晶体管的源极接入第二复位信号，所述第七晶体管的漏极与所述发光器件的阳极电性连接。
可选的，在本申请一些实施例中，所述第七晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述第一控制信号为所述发光控制信号。
可选的，在本申请一些实施例中，所述驱动电路还包括第二电容，所述第二电容的一端与所述驱动晶体管的栅极电性连接，所述第二电容的另一端接入所述第二控制信号。
可选的，在本申请一些实施例中，所述第一电源电压的电位大于第二电源电压的电位。
可选的，在本申请一些实施例中，所述发光器件为有机发光二极管。
可选的，在本申请一些实施例中，所述的多个子像素的驱动电路排布成阵列，其中相邻的两列子像素的驱动电路采用镜像对称结构设置。
可选的，在本申请一些实施例中，显示面板还包括：
第一导电沟道层，所述第一导电沟道层包括多晶硅有源层以及第一电容的第一极板；
第一金属层，所述第一金属层包括多晶硅薄膜晶体管的栅电极以及第一电容的第二极板；
第二金属层，所述第二金属层包括氧化物薄膜晶体管的栅电极；
第三金属层，所述第三金属层包括所述多晶硅薄膜晶体管的源极及漏极，以及所述氧化物薄膜晶体管的源极及漏极；
第二导电沟道层，所述第二导电沟道层包括氧化物半导体有源层。
可选的，在本申请一些实施例中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界，
在所述第二导电沟道层中，所述每对子像素中的第一晶体管的有源层相对向设置并靠近所述每对子像素的共同边界，且所述每对子像素中的第一晶体管的有源层与所述每对子像素的共同边相平行。
可选的，在本申请一些实施例中，所述第一金属层还包括第二电容的第一极板，所述第二导电沟道层还包括第二电容的第二极板。
可选的，在本申请一些实施例中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界；
在所述第二导电沟道层中，所述第二电容的第二极板和所述第一晶体管的有源层位于同一轴线方向上，且所述每对子像素中的第二电容相对向设置并靠近所述每对子像素的共同边界。
本申请还提供一种显示面板，其包括多个子像素，每个子像素包含一个驱动电路，所述驱动电路包括：
发光器件和驱动晶体管，所述发光器件和所述驱动晶体管串接于第一电源电压与第二电源电压之间；
第一晶体管，所述第一晶体管的栅极接入第一控制信号，所述第一晶体管的漏极与所述驱动晶体管的栅极电性连接，其中，所述第一晶体管为氧化物薄膜晶体管；
第一电容，所述第一电容的一端与所述驱动晶体管的栅极电性连接，所述第一电容的另一端接入所述第一电源电压；
第二晶体管，所述第二晶体管的栅极接入第二控制信号，所述第二晶体管的源极与所述第一晶体管的源极电性连接，所述第二晶体管的漏极与所述驱动晶体管的漏极电性连接；
第三晶体管，所述第三晶体管的栅极接入第三控制信号，所述第三晶体管的源极接入第一复位信号，所述第三晶体管的漏极与第一晶体管的源极电性连接；
所述驱动晶体管、第二晶体管和第三晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述第一晶体管为P型晶体管或N型晶体管。
可选的，在本申请一些实施例中，所述驱动电路还包括第四晶体管；所述第四晶体管的栅极接入所述第二控制信号，所述第四晶体管的源极接入所述数据信号，所述第四晶体管的漏极与所述驱动晶体管的源极电性连接。
可选的，在本申请一些实施例中，所述第四晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述驱动电路还包括第五晶体管和第六晶体管；所述第五晶体管的栅极和所述第六晶体管的栅极均接入发光控制信号，所述第五晶体管的源极接入所述第一电源电压，所述第五晶体管的漏极与所述驱动晶体管的源极电性连接；所述第六晶体管的漏极与所述发光器件的阳极电性连接，所述第六晶体管的源极与所述驱动晶体管的漏极电性连接。
可选的，在本申请一些实施例中，所述第二晶体管和所述第六晶体管为单栅极结构。
可选的，在本申请一些实施例中，所述第五晶体管和第六晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述驱动电路还包括第七晶体管，所述第七晶体管的栅极接入所述第二控制信号，所述第七晶体管的源极接入第二复位信号，所述第七晶体管的漏极与所述发光器件的阳极电性连接。
可选的，在本申请一些实施例中，所述第七晶体管为低温多晶硅薄膜晶体管。
可选的，在本申请一些实施例中，所述第一控制信号为所述发光控制信号。
可选的，在本申请一些实施例中，所述驱动电路还包括第二电容，所述第二电容的一端与所述驱动晶体管的栅极电性连接，所述第二电容的另一端接入所述第二控制信号。
可选的，在本申请一些实施例中，所述第一电源电压的电位大于第二电源电压的电位。
可选的，在本申请一些实施例中，所述发光器件为有机发光二极管。
可选的，在本申请一些实施例中，所述的多个子像素的驱动电路排布成阵列，其中相邻的两列子像素的驱动电路采用镜像对称结构设置。
可选的，在本申请一些实施例中，显示面板还包括：
第一导电沟道层，所述第一导电沟道层包括多晶硅有源层以及第一电容的第一极板；
第一金属层，所述第一金属层包括多晶硅薄膜晶体管的栅电极以及第一电容的第二极板；
第二金属层，所述第二金属层包括氧化物薄膜晶体管的栅电极；
第三金属层，所述第三金属层包括所述多晶硅薄膜晶体管的源极及漏极，以及所述氧化物薄膜晶体管的源极及漏极；
第二导电沟道层，所述第二导电沟道层包括氧化物半导体有源层。
可选的，在本申请一些实施例中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界，
在所述第二导电沟道层中，所述每对子像素中的第一晶体管的有源层相对向设置并靠近所述每对子像素的共同边界，且所述每对子像素中的第一晶体管的有源层与所述每对子像素的共同边相平行。
可选的，在本申请一些实施例中，所述第一金属层还包括第二电容的第一极板，所述第二导电沟道层还包括第二电容的第二极板。
可选的，在本申请一些实施例中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界；
在所述第二导电沟道层中，所述第二电容的第二极板和所述第一晶体管的有源层位于同一轴线方向上，且所述每对子像素中的第二电容相对向设置并靠近所述每对子像素的共同边界。
 有益效果
本申请提供一种显示面板。显示面板包括多个子像素，每个子像素包含一个驱动电路，所述驱动电路发光器件、驱动晶体管、第一晶体管、第一电容、第二晶体管和第三晶体管。通过第一晶体管的漏极与所述驱动晶体管的栅极电性连接，所述第三晶体管的源极与所述第一晶体管的源极电性连接，而且第一晶体管为氧化物薄膜晶体管，在第一晶体管关闭后打开发光器件开始发光，而第一晶体管关闭后利用氧化物薄膜晶体管的低漏电特性在一帧时间内抑制驱动晶体管的栅极电位变化，提高驱动晶体管的栅极的电位稳定性，进而保证发光器件的发光均匀性，因此通过氧化物薄膜晶体管控制漏电，实现高画质显示，低频低功耗的效果。由此，当显示面板在低显示频率下工作时，一帧画面显示周期内的显示更均匀，从而避免出现闪烁。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的显示面板的第一驱动电路结构示意图；
图2为图1所述的显示面板的时序图；
图3为本申请提供的显示面板的第二驱动电路结构示意图；
图4为图3所述的显示面板的时序图；
图5为本申请提供的显示面板的第三驱动电路结构示意图；
图6为图5所述的显示面板的时序图；
图7为本申请提供的显示面板的子像素的对称结构示意图；
图8为本申请提供的显示面板的子像素的第三金属层的对称结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个特征，因此不能理解为对本申请的限制。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。
本申请提供一种显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
需要说明的是，由于本申请采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。请参阅图1，图1是本申请提供的显示面板的第一驱动电路结构示意图。本申请提供一种显示面板，其包括多个子像素，每个子像素包含一个驱动电路100，驱动电路100包括发光器件D、驱动晶体管Td、写入模块101、补偿模块102、发光控制模块103以及第一复位模块104。需要说明的是，发光器件D可以为迷你发光二极管、微型发光二极管或有机发光二极管。
其中，发光器件D和驱动晶体管Td串接于第一电源电压VDD与第二电源电压VSS之间。驱动晶体管Td的源极以及漏极串接于第一电源电压与第二电源电压之间。
写入模块101接入第二控制信号S2(n)和数据信号Da，并电性连接于驱动晶体管Td的源极。写入模块101用于在第二控制信号S2(n)的控制下，将数据信号Da写入驱动晶体管Td的源极。
补偿模块102接入第一控制信号S1(n)和第一电源电压VDD，并电性连接于驱动晶体管Td的漏极以及驱动晶体管Td的栅极。补偿模块102用于在第一控制信号S1(n)的控制下，对驱动晶体管Td的阈值电压进行补偿。具体地，补偿模块102包括第一晶体管T1、第二晶体管T2和第一电容C1；第一晶体管T1的栅极接入第一控制信号S1(n)，第一晶体管T1的漏极以及第一电容C1的一端均与驱动晶体管Td的栅极电性连接，第二晶体管T2的栅极接入第二控制信号S2(n)，所述第二晶体管T2的源极与所述第一晶体管T1的源极电性连接，所述第二晶体管T2的漏极与所述驱动晶体管Td的漏极电性连接，第一电容C1的另一端接入第一电源电压VDD，第一晶体管T1为氧化物薄膜晶体管。当然，可以理解地，补偿模块102还可以采用多个晶体管和一个电容串联形成。
发光控制模块103接入发光控制信号EM，并串接于发光回路。发光控制模块103用于在发光控制信号EM的控制下，控制发光回路导通或者截止。需要说明的是，本申请只需保证发光控制模块103以及发光器件D串接于发光回路即可。图1所示的显示面板仅仅示意出发光控制模块103以及发光器件D的一种具体位置。也即，发光控制模块103以及发光器件D可以串接在发光回路上的任意位置。
第一复位模块104接入第三控制信号S1(n-1)和第一复位信号V1，并电性连接于第一晶体管T1的源极，第一复位模块104用于在第三控制信号S1(n-1)的控制下，复位驱动晶体管Td的栅极的电位。第一复位模块104包括第三晶体管T3，第三晶体管T3的栅极接入第三控制信号S1(n-1)，第三晶体管T3的源极接入第一复位信号V1，第二晶体管T2的漏极与第一晶体管T1的源极电性连接。当然，可以理解地，第一复位模块104还可以采用多个晶体管串联形成。
在本申请提供的显示面板中，通过第一晶体管的漏极与所述驱动晶体管的栅极电性连接，所述第三晶体管的源极与所述第一晶体管的源极电性连接，而且第一晶体管为氧化物薄膜晶体管，在第一晶体管关闭后打开发光器件开始发光，而第一晶体管关闭后利用氧化物薄膜晶体管的低漏电特性在一帧时间内抑制驱动晶体管的栅极电位变化，提高驱动晶体管的栅极的电位稳定性，进而保证发光器件的发光均匀性，因此通过氧化物薄膜晶体管控制漏电，实现高画质显示，低频低功耗的效果。
进一步的，请继续参阅图1，驱动电路还包括第二复位模块105，第二复位模块105接入第二控制信号S2(n)和第二复位信号V2，并电性连接于发光器件D的阳极。第二复位模块105用于在第二控制信号S2(n)的控制下，复位发光器件D的阳极的电位。
本申请通过设置第二复位模块105，可以复位发光器件D的阳极的电位，避免发光器件D的阳极残留的电荷影响发光器件D的发光亮度。
在一些实施例中，请参阅图1，图1为本申请提供的显示面板的第一驱动电路结构示意图。写入模块101包括第四晶体管T4。
第四晶体管T4的栅极接入第二控制信号S2(n)。第四晶体管T4的源极接入数据信号Da。第四晶体管T4的漏极与驱动晶体管Td的源极电性连接。当然，可以理解地，写入模块101还可以采用多个晶体管串联形成。
在一些实施例中，发光控制模块103包括第五晶体管T5和第六晶体管T6；所述第五晶体管T5的栅极和所述第六晶体管T6的栅极均接入发光控制信号EM，所述第五晶体管T5的源极接入所述第一电源电压VDD，所述第五晶体管T5的漏极与所述驱动晶体管Td的源极电性连接；所述第六晶体管T6的漏极与所述发光器件D的阳极电性连接，所述第六晶体管T6的源极与所述驱动晶体管Td的漏极电性连接。当然，可以理解地，发光控制模块103还可以采用多个晶体管串联形成。
在一些实施例中，所述第二晶体管和所述第六晶体管为单栅极结构。第二晶体管和第六晶体管采用单栅极结构，可以对驱动电路进行单栅极结构控制，而且单栅极结构相对于双栅极结构漏电较小，有利于降低驱动电路的功耗。
当然，可以理解地，在本申请提供的显示面板中，发光控制模块103可以包括3个、4个或更多个发光控制单元。每一发光控制单元均串接于发光回路。多个发光控制单元可以接入同一发光控制信号EM，也可以接入不同的发光控制信号EM。此外，可以理解的是，每一发光控制单元还可以采用多个晶体管串联形成。
在一些实施例中，第二复位模块105第七晶体管T7，所述第七晶体管T7的栅极接入所述第二控制信号S2(n)，所述第七晶体管T7的源极接入第二复位信号V2，所述第七晶体管T7的漏极与所述发光器件D的阳极电性连接。当然，可以理解地，第二复位模块105还可以采用多个晶体管串联形成。
在本实施例中，第一控制信号S1(n) 设为发光控制信号EM，通过将第一控制信号设置为发光控制信号，可以减少驱动信号的布置，以方便实现屏幕的窄边框。
本申请提供的显示面板采用8T1C（8个晶体管以及1个电容）结构的显示面板对发光器件D进行控制，用了较少的元器件，结构简单稳定，节约了成本。
在本申请中，第一电源电压VDD和第二电源电压VSS均用于输出一预设电压值。此外，在本申请中，第一电源电压VDD的电位大于第二电源电压VSS的电位。具体的，第二电源电压VSS的电位可以为接地端的电位。当然，可以理解地，第二电源电压VSS的电位还可以为其它。
在本申请中，驱动晶体管TD、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管可以为低温多晶硅薄膜晶体管、氧化物薄膜晶体管或非晶硅薄膜晶体管中的一种或者多种。此外，本申请提供的显示面板中的晶体管还可以是P型晶体管或N型晶体管。进一步的，可以设置本申请提供的显示面板中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对显示面板造成的影响。
需要说明的是，本申请以下实施例以第一晶体管为P型晶体管，驱动晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管为N型晶体管为例进行说明，但不能理解为对本申请的限定。
请参考图7和图8，图7为本申请提供的显示面板的子像素的对称结构示意图，图8为本申请提供的显示面板的子像素的第三金属层对称结构示意图，在一些实施例中，所述的多个子像素的驱动电路排布成阵列，其中相邻的两列子像素的驱动电路采用镜像对称结构设置，如图7和图8中子像素n和子像素n+1的驱动电路呈镜像对称。本申请通过将相邻的两列子像素的驱动电路镜像对称结构设置，从而为像素密度的提高提供空间，有利于实现高像素密度面板设计。
在一些实施例中，显示面板还包括：第一导电沟道层、第一金属层、第二金属层、第三金属层和第二导电沟道层；
其中，所述第一导电沟道层包括多晶硅有源层以及第一电容C1的第一极板；所述第一金属层包括多晶硅薄膜晶体管的栅电极以及第一电容C1的第二极板；所述第二金属层包括氧化物薄膜晶体管的栅电极；所述第三金属层包括所述多晶硅薄膜晶体管的源极及漏极，以及所述氧化物薄膜晶体管的源极及漏极；所述第二导电沟道层包括氧化物半导体有源层。本申请通过将第一导电沟道和第一金属层制作第一电容，可以进一步为像素密度的提高提供空间，便于设计更大高像素密度面板。
在一些实施例中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界，在所述第二导电沟道层中，所述每对子像素中的第一晶体管T1的有源层相对向设置并靠近所述每对子像素的共同边界，且所述每对子像素中的第一晶体管T1的有源层与所述每对子像素的共同边界相平行。也即是，由于第一晶体管为氧化物薄膜晶体管，因此每对子像素中的第一晶体管的有源层相靠近设置方便绝缘布置，可以减少绝缘布置的成本和空间，有利于实现高像素密度面板设计。另外，所述每对子像素中的第一晶体管的有源层与所述每对子像素的共同边界相平行，便于位于同一行上的第一晶体管T1的栅极的控制信号线进行统一布置。
也即是，在一些实施例中，驱动晶体管TD、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管可以为低温多晶硅薄膜晶体管，驱动晶体管TD、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管的有源层设在第一导电沟道层，驱动晶体管TD、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管的栅电极设在第一金属层；第一晶体管为氧化物薄膜晶体管，第一晶体管的有源层设在第二导电沟道层，第一晶体管的栅电极设在第二金属层。
请参阅图1和图2，图2为图1所示的显示面板的时序图。发光控制信号EM、第一控制信号S1(n)、第二控制信号S2(n)以及第三控制信号S1(n-1)相组合先后对应于复位阶段t1、补偿阶段t2以及发光阶段t3。也即，在一帧时间内，本申请提供的显示面板的驱动控制时序包括复位阶段t1、补偿阶段t2以及发光阶段t3。
在复位阶段t1，第三控制信号S1(n-1)为低电位。第一控制信号S1(n)、第二控制信号S2(n)和发光控制信号EM均为高电位。此时，第二晶体管T2第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均关闭。第一晶体管T1和第三晶体管T3打开。第一复位信号V1通过第三晶体管和第一晶体管输出至驱动晶体管Td的栅极。驱动晶体管Td的栅极的电位复位至第一复位信号V1的电位。
在补偿阶段t2，第二控制信号S2(n)为低电位。第一控制信号S1(n)、第三控制信号S1(n-1)和发光控制信号EM均为高电位。此时，第三晶体管T3、第五晶体管T5和第六晶体管T6均关闭。第一晶体管T1、第二晶体管T2和第四晶体管T4打开。数据信号Da通过第二晶体管、驱动晶体管Td、第一晶体管以及第四晶体管写入至驱动晶体管Td的栅极。当驱动晶体管Td的栅极的电位充电至Vdata–Vth时，驱动晶体管Td截止，驱动晶体管Td的栅极的电位不再上升。第一电容C1存储驱动晶体管Td的栅极的电位。
同时，由于第二控制信号S2(n)为低电位，第七晶体管T7打开。发光器件D的阳极的电位复位至第二复位信号V2的电位。从而保证发光器件D在补偿阶段t2不发光。
在发光阶段t3，第一控制信号S1(n) 以及发光控制信号EM 均为低电位，第二控制信号S2(n)以及第三控制信号S1(n-1)均为高电位。此时，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4以及第七晶体管T7均关闭。驱动晶体管Td、第六晶体管T6以及第五晶体管T5均打开。驱动晶体管Td通过栅极的电位产生与数据信号Da相对应的驱动电流。驱动电流经由导通的驱动晶体管Td、第五晶体管T5以及第六晶体管T6流向发光器件D，驱动发光器件D发光。
进一步地，请参考图3，图3为本申请提供的显示面板的第二驱动电路结构示意图，与图1所示的显示面板的不同之处在于，在本实施例中，本申请中的驱动晶体管、第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管以及第七晶体管均为N型晶体管为例进行说明，但不能理解为对本申请的限定。而且，在本实施例中，第一控制信号S1(n) 与发光控制信号为互为独立的控制信号。
请参阅图3和图4，图4为图3所示的显示面板的时序图。发光控制信号EM、第一控制信号S1(n)、第二控制信号S2(n)以及第三控制信号S1(n-1)相组合先后对应于复位阶段t1、补偿阶段t2以及发光阶段t3。也即，在一帧时间内，本申请提供的显示面板的驱动控制时序包括复位阶段t1、补偿阶段t2以及发光阶段t3。
在复位阶段t1，第一控制信号S1(n)和第三控制信号S1(n-1)为低电位。第二控制信号S2(n)和发光控制信号EM均为高电位。此时，第二晶体管T2第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7均关闭。第一晶体管T1和第三晶体管T3打开。第一复位信号V1通过第三晶体管和第一晶体管输出至驱动晶体管Td的栅极。驱动晶体管Td的栅极的电位复位至第一复位信号V1的电位。
在补偿阶段t2，第一控制信号S1(n)和第二控制信号S2(n)为低电位。第三控制信号S1(n-1)和发光控制信号EM均为高电位。此时，第三晶体管T3、第五晶体管T5和第六晶体管T6均关闭。第一晶体管T1、第二晶体管T2和第四晶体管T4打开。数据信号Da通过第二晶体管、驱动晶体管Td、第一晶体管以及第四晶体管写入至驱动晶体管Td的栅极。当驱动晶体管Td的栅极的电位充电至Vdata–Vth时，驱动晶体管Td截止，驱动晶体管Td的栅极的电位不再上升。第一电容C1存储驱动晶体管Td的栅极的电位。
同时，由于第二控制信号S2(n)为低电位，第七晶体管T7打开。发光器件D的阳极的电位复位至第二复位信号V2的电位。从而保证发光器件D在补偿阶段t2不发光。
在发光阶段t3，发光控制信号EM 均为低电位，第一控制信号S1(n)、第二控制信号S2(n)以及第三控制信号S1(n-1)均为高电位。此时，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4以及第七晶体管T7均关闭。驱动晶体管Td、第六晶体管T6以及第五晶体管T5均打开。驱动晶体管Td通过栅极的电位产生与数据信号Da相对应的驱动电流。驱动电流经由导通的驱动晶体管Td、第五晶体管T5以及第六晶体管T6流向发光器件D，驱动发光器件D发光。
进一步的，请参阅图5和图7，图5为本申请提供的显示面板的第三驱动电路结构示意图。与图1所示的显示面板的不同之处在于，在本实施例中，驱动电路还包括第二电容C2。第二电容C2的一端与驱动晶体管Td的栅极电性连接，第二电容C2的另一端接入第一控制信号S1(n)。
可以理解的是，在实际面板制作过程中，难以避免会产生一些寄生电容。第一晶体管的漏极的电位会因寄生电容的耦合作用，而被耦合到更低的电位，进而影响驱动晶体管Td的栅极电位。本实施例通过设置第二电容C2，可以对第一晶体管的漏极电位进行反向耦合，使得第一晶体管的漏极的电位尽量与驱动晶体管Td的栅极的电位保持一致。由此，可以进一步保证驱动晶体管Td的栅极的电位稳定性。具体耦合过程将在以下实施例中详细说明。
在一些实施例中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界；在所述第二导电沟道层中，所述第二电容的第二极板和所述第一晶体管的有源层位于同一轴线方向上，且所述每对子像素中的第二电容相对向设置并靠近所述每对子像素的共同边界。每对子像素中的第二电容相靠近设置方便绝缘布置，可以减少绝缘布置的成本和空间，有利于实现高像素密度面板设计。另外，将第二电容的第二极板和所述第一晶体管的有源层设置在同一轴线方向上，可以减少设计空间，有利于实现高像素密度面板设计。
在一些实施例中，所述第一金属层还包括第二电容的第一极板，第二导电沟道层还包括第二电容的第二极板。本申请通过将第二金属层和第二导电沟道层制作第二电容，可以进一步为像素密度的提高提供空间，便于设计更大高像素密度面板。
此外，本实施例将第二电容C2的另一端接入发光第一控制信号，可以简化显示面板内的走线。当然，在本申请其它实施例中，也可以将第二电容C2的另一端接入其它的控制信号，实现反向耦合第一晶体管漏极的电位即可。
需要说明的是，在本申请一些实施例中，图5所示的显示面板的驱动控制时序与图1所示的显示面板的驱动控制时序相同。也即，图5所示的显示面板的驱动控制时序包括复位阶段t1、补偿阶段t2以及发光阶段t3。
不同之处仅在于，在显示面板的驱动控制时序由补偿阶段t2进入发光阶段t3时，由于第二电容C2的设置，显示面板中将会发生电容耦合。
可以理解的是，当数据信号Da写入完毕后，第一控制信号S1(n)由高电位转变为低电位。第一晶体管的漏极的电位会被耦合至比驱动晶体管Td的栅极更低的一个电位。后续在发光阶段，由于第一晶体管的漏电，驱动晶体管Td的栅极的电位会不断下降。
由此，在实施例中，发光控制信号EM由高电位转变为低电位。由于第二电容C2的耦合作用，将第一晶体管的漏极的电位上拉。进一步的，通过设计第二电容C2的电容值，可以将第一晶体管的漏极的电位上拉至与驱动晶体管Td的栅极的电位基本保持一致。从而提高驱动晶体管Td的栅极的电位稳定性，避免发光器件D的发光亮度在一帧时间内发生改变。
在本申请一些实施例中，请参阅图6，图6为图5所示的发光器件驱动电路的时序图。与图2所示的驱动控制时序的不同之处在于，在本实施例中，显示面板的驱动控制时序还包括电容耦合阶段t4。也即，在一帧时间内，本申请提供的显示面板的驱动控制时序包括复位阶段t1、补偿阶段t2、电容耦合阶段t4以及发光阶段t3。
其中，显示面板在复位阶段t1以及补偿阶段t2的工作过程可参阅上述实施例，在此不再赘述。
在电容耦合阶段t4，第二控制信号S2(n)以及第三控制信号S1(n-1)均为高电位。第一控制信号S1(n)和发光控制信号EM由高电位转变为低电位。此时，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4以及第七晶体管T7均关闭。第五晶体管T5和第六晶体管T6由关闭转变为打开。
可以理解的是，当数据信号Da写入完毕后，第一控制信号S1(n)由高电位转变为低电位。第一晶体管的漏极的电位会被耦合至至比驱动晶体管Td的栅极更低的一个电位。后续在发光阶段，由于第一晶体管的漏电，驱动晶体管Td的栅极的电位会不断下降。
由此，在本申请的电容耦合阶段t4，发光控制信号EM由高电位转变为低电位。由于第二电容C2的耦合作用，将第一晶体管的漏极的电位上拉。进一步的，通过设计第二电容C2的电容值，可以将第一晶体管的漏极的电位上拉至与驱动晶体管Td的栅极的电位基本保持一致。从而提高驱动晶体管Td的栅极的电位稳定性，避免发光器件D的发光亮度在一帧时间内发生改变。
需要说明的是，在电容耦合阶段t4，当发光控制信号EM由高电位转变为低电位后，发光器件D也会发光。但由于电容耦合阶段t4的时间很短，因此不影响发光器件D的整体发光亮度。
在发光阶段t3，第一控制信号S1(n) 以及发光控制信号EM 均为低电位，第二控制信号S2(n)以及第三控制信号S1(n-1)均为高电位。此时，第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第七晶体管均关闭。驱动晶体管Td、第五晶体管T5以及第六晶体管T6均打开。驱动晶体管Td通过栅极的电位产生与数据信号Da相对应的驱动电流。驱动电流经由导通的第五晶体管T5、驱动晶体管Td以及第六晶体管T6流向发光器件D，驱动发光器件D发光。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，包括多个子像素，每个子像素包含一个驱动电路，其中，所述驱动电路包括：
    发光器件和驱动晶体管，所述发光器件和所述驱动晶体管串接于第一电源电压与第二电源电压之间；
    第一晶体管，所述第一晶体管的栅极接入第一控制信号，所述第一晶体管的漏极与所述驱动晶体管的栅极电性连接，其中，所述第一晶体管为氧化物薄膜晶体管；
    第一电容，所述第一电容的一端与所述驱动晶体管的栅极电性连接，所述第一电容的另一端接入所述第一电源电压；
    第二晶体管，所述第二晶体管的栅极接入第二控制信号，所述第二晶体管的源极与所述第一晶体管的源极电性连接，所述第二晶体管的漏极与所述驱动晶体管的漏极电性连接；
    第三晶体管，所述第三晶体管的栅极接入第三控制信号，所述第三晶体管的源极接入第一复位信号，所述第三晶体管的漏极与第一晶体管的源极电性连接。
  2. 根据权利要求1所述的显示面板，其中，所述驱动电路还包括第四晶体管；所述第四晶体管的栅极接入所述第二控制信号，所述第四晶体管的源极接入所述数据信号，所述第四晶体管的漏极与所述驱动晶体管的源极电性连接。
  3. 根据权利要求2所述的显示面板，其中，所述驱动电路还包括第五晶体管和第六晶体管；所述第五晶体管的栅极和所述第六晶体管的栅极均接入发光控制信号，所述第五晶体管的源极接入所述第一电源电压，所述第五晶体管的漏极与所述驱动晶体管的源极电性连接；所述第六晶体管的漏极与所述发光器件的阳极电性连接，所述第六晶体管的源极与所述驱动晶体管的漏极电性连接。
  4. 根据权利要求3所述的显示面板，其中，所述驱动电路还包括第七晶体管，所述第七晶体管的栅极接入所述第二控制信号，所述第七晶体管的源极接入第二复位信号，所述第七晶体管的漏极与所述发光器件的阳极电性连接。
  5. 根据权利要求4所述的显示面板，其中，所述驱动电路还包括第二电容，所述第二电容的一端与所述驱动晶体管的栅极电性连接，所述第二电容的另一端接入所述第二控制信号。
  6. 根据权利要求5所述的显示面板，其中，所述多个子像素的驱动电路排布成阵列，其中相邻的两列子像素的驱动电路采用镜像对称结构设置。
  7. 根据权利要求6所述的显示面板，其中，显示面板还包括：
    第一导电沟道层，所述第一导电沟道层包括多晶硅有源层以及第一电容的第一极板；
    第一金属层，所述第一金属层包括多晶硅薄膜晶体管的栅电极以及第一电容的第二极板；
    第二金属层，所述第二金属层包括氧化物薄膜晶体管的栅电极；
    第二导电沟道层，所述第二导电沟道层包括氧化物半导体有源层；
    第三金属层，所述第三金属层包括所述多晶硅薄膜晶体管的源极及漏极，以及所述氧化物薄膜晶体管的源极及漏极。
  8. 根据权利要求7所述的显示面板，其中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界，
    在所述第二导电沟道层中，所述每对子像素中的第一晶体管的有源层相对向设置并靠近所述每对子像素的共同边界，且所述每对子像素中的第一晶体管的有源层与所述每对子像素的共同边界相平行。
  9. 根据权利要求7所述的显示面板，其中，
    所述第一金属层还包括第二电容的第一极板，所述第二导电沟道层还包括第二电容的第二极板。
  10. 根据权利要求9所述的显示面板，其中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界；
    在所述第二导电沟道层中，所述第二电容的第二极板和所述第一晶体管的有源层位于同一轴线方向上，且所述每对子像素中的第二电容相对向设置并靠近所述每对子像素的共同边界。
  11. 一种显示面板，包括多个子像素，每个子像素包含一个驱动电路，其中，所述驱动电路包括：
    发光器件和驱动晶体管，所述发光器件和所述驱动晶体管串接于第一电源电压与第二电源电压之间；
    第一晶体管，所述第一晶体管的栅极接入第一控制信号，所述第一晶体管的漏极与所述驱动晶体管的栅极电性连接，其中，所述第一晶体管为氧化物薄膜晶体管；
    第一电容，所述第一电容的一端与所述驱动晶体管的栅极电性连接，所述第一电容的另一端接入所述第一电源电压；
    第二晶体管，所述第二晶体管的栅极接入第二控制信号，所述第二晶体管的源极与所述第一晶体管的源极电性连接，所述第二晶体管的漏极与所述驱动晶体管的漏极电性连接；
    第三晶体管，所述第三晶体管的栅极接入第三控制信号，所述第三晶体管的源极接入第一复位信号，所述第三晶体管的漏极与第一晶体管的源极电性连接；
    所述驱动晶体管、第二晶体管和第三晶体管为低温多晶硅薄膜晶体管。
  12. 根据权利要求11所述的显示面板，其中，所述驱动电路还包括第四晶体管；所述第四晶体管的栅极接入所述第二控制信号，所述第四晶体管的源极接入所述数据信号，所述第四晶体管的漏极与所述驱动晶体管的源极电性连接。
  13. 根据权利要求12所述的显示面板，其中，所述驱动电路还包括第五晶体管和第六晶体管；所述第五晶体管的栅极和所述第六晶体管的栅极均接入发光控制信号，所述第五晶体管的源极接入所述第一电源电压，所述第五晶体管的漏极与所述驱动晶体管的源极电性连接；所述第六晶体管的漏极与所述发光器件的阳极电性连接，所述第六晶体管的源极与所述驱动晶体管的漏极电性连接。
  14. 根据权利要求13所述的显示面板，其中，所述驱动电路还包括第七晶体管，所述第七晶体管的栅极接入所述第二控制信号，所述第七晶体管的源极接入第二复位信号，所述第七晶体管的漏极与所述发光器件的阳极电性连接。
  15. 根据权利要求14所述的显示面板，其中，所述驱动电路还包括第二电容，所述第二电容的一端与所述驱动晶体管的栅极电性连接，所述第二电容的另一端接入所述第二控制信号。
  16. 根据权利要求15所述的显示面板，其中，所述多个子像素的驱动电路排布成阵列，其中相邻的两列子像素的驱动电路采用镜像对称结构设置。
  17. 根据权利要求16所述的显示面板，其中，显示面板还包括：
    第一导电沟道层，所述第一导电沟道层包括多晶硅有源层以及第一电容的第一极板；
    第一金属层，所述第一金属层包括多晶硅薄膜晶体管的栅电极以及第一电容的第二极板；
    第二金属层，所述第二金属层包括氧化物薄膜晶体管的栅电极；
    第二导电沟道层，所述第二导电沟道层包括氧化物半导体有源层；
    第三金属层，所述第三金属层包括所述多晶硅薄膜晶体管的源极及漏极，以及所述氧化物薄膜晶体管的源极及漏极。
  18. 根据权利要求17所述的显示面板，其中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界，
    在所述第二导电沟道层中，所述每对子像素中的第一晶体管的有源层相对向设置并靠近所述每对子像素的共同边界，且所述每对子像素中的第一晶体管的有源层与所述每对子像素的共同边界相平行。
  19. 根据权利要求17所述的显示面板，其中，
    所述第一金属层还包括第二电容的第一极板，所述第二导电沟道层还包括第二电容的第二极板。
  20. 根据权利要求19所述的显示面板，其中，位于同一行的子像素按照先后顺序依次划分为多对子像素，所述每对子像素具有共同边界；
    在所述第二导电沟道层中，所述第二电容的第二极板和所述第一晶体管的有源层位于同一轴线方向上，且所述每对子像素中的第二电容相对向设置并靠近所述每对子像素的共同边界。
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