WO2024109060A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2024109060A1
WO2024109060A1 PCT/CN2023/104262 CN2023104262W WO2024109060A1 WO 2024109060 A1 WO2024109060 A1 WO 2024109060A1 CN 2023104262 W CN2023104262 W CN 2023104262W WO 2024109060 A1 WO2024109060 A1 WO 2024109060A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
electrode
compensation
gate
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PCT/CN2023/104262
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English (en)
French (fr)
Inventor
陈涛
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to KR1020237041186A priority Critical patent/KR20240078604A/ko
Priority to US18/522,517 priority patent/US20240169922A1/en
Publication of WO2024109060A1 publication Critical patent/WO2024109060A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources

Definitions

  • the present application relates to the field of display technology, and in particular to a pixel circuit and a display panel.
  • the present application provides a pixel circuit and a display panel to alleviate the technical problem of large brightness variation within a frame.
  • the present application provides a pixel circuit, which includes a driving transistor, a first compensation transistor, a second compensation transistor and a third compensation transistor, wherein the driving transistor is connected in series between a first power line and a second power line; a first electrode of the first compensation transistor is electrically connected to a gate of the driving transistor, and the gate of the first compensation transistor is electrically connected to a scanning line; a first electrode of the second compensation transistor is electrically connected to a second electrode of the first compensation transistor, a second electrode of the second compensation transistor is electrically connected to a first electrode of the driving transistor or a second electrode of the driving transistor, and a gate of the second compensation transistor is electrically connected to a first control line; a first electrode of the third compensation transistor is electrically connected to a second electrode of the first compensation transistor and a first electrode of the second compensation transistor, a gate of the third compensation transistor is electrically connected to a second control line, and a second electrode of the third compensation transistor is electrically connected to a first potential line.
  • the channel type of the driving transistor, the channel type of the first compensation transistor, the channel type of the second compensation transistor, and the channel type of the third compensation transistor are the same.
  • the pixel circuit also includes a first light-emitting control transistor, a light-emitting device and a reset transistor, the first electrode of the first light-emitting control transistor is electrically connected to the second electrode of the driving transistor, and the gate of the first light-emitting control transistor is electrically connected to the third control line; the anode of the light-emitting device is electrically connected to the second electrode of the first light-emitting control transistor, and the cathode of the light-emitting device is electrically connected to the second power line; the first electrode of the reset transistor is electrically connected to the anode of the light-emitting device, the second electrode of the reset transistor is electrically connected to the second potential line or the first potential line, and the gate of the reset transistor is electrically connected to the gate of the second compensation transistor.
  • a channel type of the reset transistor is the same as a channel type of the second compensation transistor.
  • the pixel circuit also includes a second light-emitting control transistor, a write transistor and a first initialization transistor, the first electrode of the second light-emitting control transistor is electrically connected to the first power line, the second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the gate of the second light-emitting control transistor is electrically connected to the gate of the first light-emitting control transistor; the first electrode of the write transistor is electrically connected to the data line, the gate of the write transistor is electrically connected to the scan line, and the second electrode of the write transistor is electrically connected to the first electrode of the driving transistor or the second electrode of the driving transistor; the first electrode of the first initialization transistor is electrically connected to the gate of the driving transistor, the gate of the first initialization transistor is electrically connected to the fourth control line, and the second electrode of the first initialization transistor is electrically connected to one of the third potential line, the first potential line or the second potential line.
  • the pixel circuit also includes a second initialization transistor, a first electrode of the second initialization transistor is electrically connected to the gate of the driving transistor, a gate of the second initialization transistor is electrically connected to the gate of the first initialization transistor, and a second electrode of the second initialization transistor is electrically connected to the first electrode of the first initialization transistor and the first electrode of the third compensation transistor.
  • the driving transistor, the first compensation transistor, the second compensation transistor, the third compensation transistor, the first light emission control transistor, the reset transistor, the second light emission control transistor, the write transistor, the first initialization transistor and the second initialization transistor are all low-temperature polysilicon thin film transistors.
  • the first compensation transistor and the second compensation transistor are both in an on state, and the third compensation transistor is in an off state to transmit the data signal to the gate of the driving transistor.
  • the first compensation transistor in the first compensation stage of the pixel circuit, is in a cut-off state, and the second compensation transistor and the third compensation transistor are both in an on state to stabilize the potential of the second electrode of the first compensation transistor, reduce the voltage difference between the gate potential of the driving transistor and the potential of the second electrode of the first compensation transistor, and reset the potential of the first electrode of the driving transistor and the potential of the second electrode of the driving transistor.
  • a frame of the pixel circuit includes a writing frame and a holding frame, and the writing stage and the first compensation stage are both located in the writing frame; the holding frame includes several second compensation stages, in the second compensation stages, the first compensation transistor is in an off state, and the second compensation transistor and the third compensation transistor are both in an on state, so as to stabilize the potential of the second pole of the first compensation transistor, reduce the voltage difference between the gate potential of the driving transistor and the potential of the second pole of the first compensation transistor, and reset the potential of the first pole of the driving transistor and the potential of the second pole of the driving transistor.
  • the reset transistor is in a conducting state in the writing phase, the first compensation phase, and the second compensation phase, so as to reset the anode potential of the light-emitting device multiple times.
  • the first potential line transmits a first potential signal;
  • a frame of the pixel circuit includes a writing frame and a holding frame, and a potential of the first potential signal in the writing frame is lower than that in the holding frame.
  • the second potential line transmits a second potential signal;
  • a frame of the pixel circuit includes a writing frame and a holding frame, and a potential of the second potential signal in the writing frame is lower than that in the holding frame.
  • the present application provides a display panel, which includes the pixel circuit of at least one of the above-mentioned embodiments, and the multiple pixel circuits are distributed in an array; each scan line is electrically connected to two adjacent rows of pixel circuits; each first control line is electrically connected to two adjacent rows of pixel circuits; each second control line is electrically connected to two adjacent rows of pixel circuits; each third control line is electrically connected to two adjacent rows of pixel circuits; and each fourth control line is electrically connected to two adjacent rows of pixel circuits.
  • the display panel also includes two gate driving circuits, a first driving circuit, a second driving circuit, a third driving circuit and a fourth driving circuit, one gate driving circuit is electrically connected to one end of the scanning line, and the other gate driving circuit is electrically connected to the other end of the scanning line;
  • the first driving circuit is electrically connected to the third control line;
  • the second driving circuit is electrically connected to the first control line;
  • the third driving circuit is electrically connected to the fourth control line;
  • the fourth driving circuit is electrically connected to the second control line; wherein the two gate driving circuits are respectively located on both sides of the plurality of pixel circuits, two of the first driving circuit, the second driving circuit, the third driving circuit and the fourth driving circuit are located on the outside of one of the gate driving circuits, and the other two of the first driving circuit, the second driving circuit, the third driving circuit and the fourth driving circuit are located on the outside of another of the gate driving circuits.
  • the first potential line can timely change the potential of the second electrode of the first compensation transistor and the potential of the first electrode of the second compensation transistor through the third compensation transistor, so as to reduce the voltage difference between the gate of the driving transistor and the second electrode of the first compensation transistor and the first electrode of the second compensation transistor, thereby reducing the gate leakage current of the driving transistor, making the light-emitting current flowing through the driving transistor more constant, and thereby improving the uniformity of the brightness within the frame.
  • the first compensation transistor is in the cut-off state, and the second compensation transistor and the third compensation transistor are in the on state.
  • the first potential line can change the potential of the first electrode and the second electrode of the driving transistor through the second compensation transistor and the third compensation transistor to reduce the unidirectional drift range of the threshold voltage of the driving transistor in a single working state, which is beneficial to further maintain the stability of the light-emitting current flowing through the driving transistor.
  • FIG. 1 is a schematic diagram of a structure of a pixel circuit in the related art.
  • FIG. 2 is a timing diagram of the pixel circuit shown in FIG. 1 .
  • FIG. 3 is another schematic diagram of the structure of a pixel circuit in the related art.
  • FIG. 4 is a schematic diagram of brightness difference of a pixel circuit in a frame in the related art.
  • FIG. 5 is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.
  • FIG. 6 is a timing diagram of the pixel circuit shown in FIG. 5 .
  • FIG. 7 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • Figure 1 is a structural schematic diagram of a pixel circuit in the related art, which pixel circuit includes a driving transistor T2, a compensation transistor T3, a first light-emitting control transistor T6, a second light-emitting control transistor T5, a first initialization transistor T7, a second initialization transistor T4, a write transistor T2, a storage capacitor Cst and at least one of the light-emitting devices D1.
  • One end of the storage capacitor Cst is electrically connected to the first power line, and the other end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T2.
  • One of the sources or drains of the second light-emitting control transistor T5 is electrically connected to the first power line, the other of the sources or drains of the second light-emitting control transistor T5 is electrically connected to one of the sources or drains of the driving transistor T2, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control line.
  • One of the sources or drains of the write transistor T2 is electrically connected to the other of the sources or drains of the second light emission control transistor T5, the other of the sources or drains of the write transistor T2 is connected to the data line, and the gate of the write transistor T2 is electrically connected to the first scan line.
  • One of the source or drain of the compensation transistor T3 is electrically connected to the other of the source or drain of the driving transistor T2, the other of the source or drain of the compensation transistor T3 is electrically connected to the gate of the driving transistor T2, and the gate of the compensation transistor T3 is electrically connected to the first scan line.
  • One of the source or drain of the first light emitting control transistor T6 is electrically connected to the other of the source or drain of the driving transistor T2, the gate of the first light emitting control transistor T6 is electrically connected to the light emitting control line, and the other of the source or drain of the first light emitting control transistor T6 is electrically connected to the anode of the light emitting device D1.
  • the cathode of the light emitting device D1 is electrically connected to the second power line.
  • One of the source or drain of the first initialization transistor T7 is electrically connected to the anode of the light emitting device D1, the other of the source or drain of the first initialization transistor T7 is connected to the initialization line, and the gate of the first initialization transistor T7 is electrically connected to the first scan line.
  • One of the source or drain of the second initialization transistor T4 is electrically connected to the gate of the driving transistor T2 , the other of the source or drain of the second initialization transistor T4 is connected to the initialization line, and the gate of the second initialization transistor T4 is electrically connected to the second scan line.
  • the data line is used to transmit a data signal Data.
  • the first power line is used to transmit a first power signal VDD
  • the second power line is used to transmit a second power signal VSS.
  • the potential of the first power signal VDD is greater than the potential of the second power signal VSS.
  • the light control line is used to transmit a light control signal EM(n).
  • the initialization line is used to transmit an initialization signal Vi.
  • the first scan line is used to transmit a scan signal Scan(n).
  • the second scan line is used to transmit a scan signal Scan(n-1).
  • the driving transistor T2, the compensation transistor T3, the first light emission control transistor T6, the second light emission control transistor T5, the first initialization transistor T7, the second initialization transistor T4, and the writing transistor T2 are all P-channel thin film transistors and low-temperature polysilicon thin film transistors.
  • the operation of the 7T1C pixel circuit in FIG1 in one frame can be divided into the following three main operation stages as shown in FIG2:
  • Reset phase M1 the scan signal Scan(n-1) is set to a low level, the second initialization transistor T4 is turned on, and the gate of the driving transistor T1 is reset to the potential of the initialization signal Vi.
  • Charging stage M2 the scanning signal Scan(n) is set to a low level, the writing transistor T2, the driving transistor T1 and the compensation transistor T3 are all turned on, and the gate potential of the driving transistor T1 is charged to Vdata-Vth; at the same time, the first initialization transistor T7 is turned on, and the anode of the light-emitting device is reset to the potential of the initialization signal Vi.
  • Vdata is the potential of the data signal Data
  • Vth is the threshold voltage (Threshold Voltage) of the driving transistor T1.
  • Light-emitting stage M3 the light-emitting control signal EM(n) is set to a low level, and the light-emitting device emits light.
  • the second initialization transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all turned off.
  • the data signal Data charges the gate of the driving transistor T1 through the path of the write transistor T2, the driving transistor T1, and the compensation transistor T3.
  • the driving transistor is turned off, and its gate potential no longer rises.
  • the brightness of the light-emitting device is directly determined by the gate potential of the driving transistor T1, and the most important factor affecting the gate potential of the driving transistor T1 is the leakage current. Since the gate of the driving transistor T1 is connected to the compensation transistor T3 and the second initialization transistor T4, the leakage current characteristics of these two transistors will directly affect the brightness stability of the light-emitting stage.
  • the gate potential (i.e., Q point) of the driving transistor T1 is unstable within one frame (the two dotted lines in FIG1 show the corresponding leakage current path), resulting in changes in Ids, i.e., the light-emitting current, flowing through the driving transistor T1, thereby causing changes in the brightness of the screen within one frame.
  • the related technology improves the compensation transistor T3 and the second initialization transistor T4 in the pixel circuit into a double-gate thin film transistor structure as shown in Figure 3. This is mainly because the leakage current of the double-gate thin film transistor is theoretically smaller than the leakage current of the single-gate thin film transistor.
  • it is difficult to avoid the generation of some parasitic capacitances.
  • the potential of point D between the dual-gate thin-film transistors T3-1 & T3-2 and point E between the dual-gate thin-film transistors T4-1 & T4-2 will be coupled to a potential higher than the potential of point Q due to the coupling effect of the parasitic capacitance when the potential of the scanning signal Scan (n-1) or the scanning signal Scan (n) changes from low to high (i.e., during the shutdown process of the corresponding transistors).
  • the potential of point Q will continue to rise, and the gate-source voltage difference (Vgs) corresponding to the driving transistor T1 will become smaller, thereby causing the light-emitting brightness of the light-emitting device D1 to gradually decrease within one frame time.
  • Vgs gate-source voltage difference
  • the related technology adopts a new LTPO (LTPS TFT + IGZO TFT) technology, that is, the compensation transistor T3 and the second initialization transistor T4 in Figure 1 are replaced with an indium gallium zinc oxide thin film transistor (IGZO TFT) with a lower leakage current to solve the problem of severe flicker under low-frequency driving, so that a lower-frequency driving scheme can be used when displaying static images, ultimately achieving the purpose of reducing power consumption.
  • IGZO TFT indium gallium zinc oxide thin film transistor
  • the backplane that combines LTPS TFT and IGZO TFT together has a more complex structure and process, and the cost will be higher.
  • the present embodiment provides a pixel circuit 100, please refer to Figures 5 and 6.
  • the pixel circuit 100 includes a driving transistor T1, a first compensation transistor T3, a second compensation transistor T8 and a third compensation transistor T9.
  • the driving transistor T1 is connected in series between the first power line and the second power line; the first electrode of the first compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the first compensation transistor T3 is electrically connected to the scanning line; the first electrode of the second compensation transistor T8 is electrically connected to the second electrode of the first compensation transistor T3, the second electrode of the second compensation transistor T8 is electrically connected to the first electrode of the driving transistor T1 or the second electrode of the driving transistor T1, and the gate of the second compensation transistor T8 is electrically connected to the first control line; the first electrode of the third compensation transistor T9 is electrically connected to the second electrode of the first compensation transistor T3 and the first electrode of the second compensation transistor T8, the gate of the third compensation transistor T9 is electrically connected to the second control line, and the second electrode of the third compensation transistor T9 is electrically connected to the first potential line.
  • the first potential line can change the potential of the second electrode of the first compensation transistor T3 and the potential of the first electrode of the second compensation transistor T8 in a timely manner through the third compensation transistor T9, so as to reduce the voltage difference between the gate of the driving transistor T1 and the second electrode of the first compensation transistor T3 and the first electrode of the second compensation transistor T8, thereby reducing the gate leakage current of the driving transistor T1, making the light-emitting current flowing through the driving transistor T1 more constant, thereby improving the uniformity of the brightness within the frame.
  • the first compensation transistor T3 is in the cut-off state, and the second compensation transistor T8 and the third compensation transistor T9 are in the on state.
  • the first potential line can change the potential of the first electrode and the second electrode of the driving transistor T1 through the second compensation transistor T8 and the third compensation transistor T9, so as to reduce the unidirectional drift range of the threshold voltage of the driving transistor T1 in a single working state, which is beneficial to further maintain the stability of the light-emitting current flowing through the driving transistor T1.
  • the first electrode may be one of the source electrode and the drain electrode
  • the second electrode may be the other of the source electrode and the drain electrode.
  • the first electrode is the source electrode
  • the second electrode is the drain electrode
  • the first electrode is the drain electrode
  • the second electrode is the source electrode
  • the first potential line is used to transmit the first potential signal VI3; a frame of the pixel circuit 100 includes a writing frame and a holding frame, and the potential of the first potential signal VI3 in the writing frame is lower than that in the holding frame.
  • the potential of the first potential signal VI3 in the write frame is lower than that in the hold frame, which is not only conducive to reducing the gate leakage current of the driving transistor T1, but also conducive to changing the potential of point B and the potential of point A to reduce the unidirectional drift range of the threshold voltage of the driving transistor T1 in a single working state.
  • the potential of point B can be linked with the potential of point A through the driving transistor T1, that is, when the potential of one of point A or point B changes, the potential of the other of point A or point B also changes accordingly.
  • the pixel circuit 100 further includes a first light-emitting control transistor T6, a light-emitting device D1 and a reset transistor T7, wherein a first electrode of the first light-emitting control transistor T6 is electrically connected to a second electrode of the driving transistor T1, and a gate of the first light-emitting control transistor T6 is electrically connected to a third control line; an anode of the light-emitting device D1 is electrically connected to a second electrode of the first light-emitting control transistor T6, and a cathode of the light-emitting device D1 is electrically connected to a second power supply line; a first electrode of the reset transistor T7 is electrically connected to an anode of the light-emitting device D1, a second electrode of the reset transistor T7 is electrically connected to a second potential line or a first potential line, and a gate of the reset transistor T7 is electrically connected to a gate of a second compensation transistor T8.
  • the gate of the reset transistor T7 is electrically connected to the gate of the second compensation transistor T8, so that the gate of the reset transistor T7 and the gate of the second compensation transistor T8 share the same first control line, thereby reducing the number of signal lines required for the pixel circuit 100, which is beneficial to improving the density and aperture ratio of the pixel circuit 100.
  • the reset transistor T7 can be turned on multiple times in different stages of a frame to adjust or reset the anode potential of the light emitting device D1 multiple times, which can improve the luminance of the light emitting device D1 and further improve the brightness difference within the frame.
  • the light emitting device D1 may be an organic light emitting diode, a quantum dot light emitting diode, a micro light emitting diode or a mini light emitting diode.
  • the second potential line transmits a second potential signal VI2; the potential of the second potential signal VI2 in a write frame is lower than that in a hold frame.
  • the potential of the second potential signal VI2 in the write frame is lower than that in the hold frame, which is beneficial to adjust or reset the anode potential of the light emitting device D1 to further improve the brightness difference within the frame.
  • the channel type of the reset transistor T7 is the same as the channel type of the second compensation transistor T8.
  • the channel type of the reset transistor T7 is the same as the channel type of the second compensation transistor T8, so that the reset transistor T7 and the second compensation transistor T8 can be in a synchronous state, so as to achieve the reset transistor T7 and the second compensation transistor T8 being synchronously opened multiple times in different stages within the frame.
  • the pixel circuit 100 further includes a second light-emitting control transistor T5, a write transistor T2, and a first initialization transistor T41, wherein a first electrode of the second light-emitting control transistor T5 is electrically connected to a first power supply line, a second electrode of the second light-emitting control transistor T5 is electrically connected to a first electrode of the driving transistor T1, and a gate of the second light-emitting control transistor T5 is electrically connected to a gate of the first light-emitting control transistor T6; a first electrode of the write transistor T2 is electrically connected to a data line, a gate of the write transistor T2 is electrically connected to a scan line, a second electrode of the write transistor T2 is electrically connected to a first electrode of the driving transistor T1 or a second electrode of the driving transistor T1; a first electrode of the first initialization transistor T41 is electrically connected to a gate of the driving transistor T1, a gate of the first initialization transistor T41 is electrically connected to
  • the gate of the second light-emitting control transistor T5 is electrically connected to the gate of the first light-emitting control transistor T6, so that the gate of the second light-emitting control transistor T5 and the gate of the first light-emitting control transistor T6 can share the same third control line, thereby reducing the number of signal lines required for the pixel circuit 100, which is beneficial to improving the density and aperture ratio of the pixel circuit 100.
  • the gate of the write transistor T2 is electrically connected to the scan line, so that the gate of the write transistor T2 and the gate of the first compensation transistor T3 share the same scan line, thereby reducing the number of signal lines required for the pixel circuit 100, which is beneficial to improving the density and aperture ratio of the pixel circuit 100.
  • the first initialization transistor T41 can share the same potential line with the third compensation transistor T9 or the reset transistor T7, thereby reducing the number of signal lines required for the pixel circuit 100, which is beneficial to improving the density and aperture ratio of the pixel circuit 100.
  • the pixel circuit 100 further includes a second initialization transistor T42, a first electrode of the second initialization transistor T42 is electrically connected to the gate of the driving transistor T1, a gate of the second initialization transistor T42 is electrically connected to the gate of the first initialization transistor T41, and a second electrode of the second initialization transistor T42 is electrically connected to the first electrode of the first initialization transistor T41 and the first electrode of the third compensation transistor T9.
  • the second electrode of the second initialization transistor T42 is electrically connected to the first electrode of the first initialization transistor T41 and the first electrode of the third compensation transistor T9, which can also improve the potential stability of the connection node between the second electrode of the second initialization transistor T42 and the first electrode of the first initialization transistor T41, and reduce the potential difference between the connection node and the gate of the driving transistor T1, so as to reduce the gate leakage current of the driving transistor T1, thereby improving the brightness difference within the frame.
  • the channel type of these transistors is conducive to simplifying the manufacturing process, structure and cost.
  • the channel type can be P channel or N channel.
  • At least two of the driving transistor T1, the first compensation transistor T3, the second compensation transistor T8, the third compensation transistor T9, the first light emission control transistor T6, the reset transistor T7, the second light emission control transistor T5, the write transistor T2, the first initialization transistor T41 and the second initialization transistor T42 are low-temperature polysilicon thin film transistors.
  • the channel materials of these transistors are all low-temperature polysilicon, which is not only conducive to improving the dynamic performance of the pixel circuit 100, but also conducive to further simplifying the manufacturing process, structure and cost.
  • the above-mentioned transistors are all low-temperature polysilicon thin-film transistors, which can be used as a preferred solution, but is not limited to this. At least one of the above-mentioned transistors can also be an indium gallium zinc oxide thin-film transistor.
  • the pixel circuit 100 further includes a storage capacitor C1 , one end of the storage capacitor C1 is electrically connected to the first power line, and the other end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T1 .
  • the first power line is used to transmit a first power signal VDD
  • the second power line is used to transmit a second power signal VSS
  • the potential of the first power signal VDD is higher than the potential of the second power signal VSS.
  • the data line is used to transmit a data signal Data.
  • the first potential line is used to transmit a first potential signal VI3.
  • the second potential line is used to transmit a second potential signal VI2.
  • the third potential line is used to transmit a third potential signal VI1.
  • the scan line is used to transmit a scan signal Scan.
  • the first control line is used to transmit a first control signal EM2-2.
  • the second control line is used to transmit a second control signal EM1-2.
  • the third control line is used to transmit a third control signal EM1-1.
  • the fourth control line is used to transmit a fourth control signal EM2-1.
  • one frame of the pixel circuit 100 when the pixel circuit 100 operates at the highest refresh frequency, one frame of the pixel circuit 100 includes only a write frame but not a hold frame; when the pixel circuit 100 operates at a lower refresh frequency (lower than the highest refresh frequency), one frame of the pixel circuit 100 includes a write frame and a hold frame.
  • the following takes the state of operating at a lower refresh frequency as an example to illustrate the working process of one frame of the pixel circuit 100:
  • Writing a frame consists of the following stages:
  • Phase P1 the third control signal EM1-1 is at a high level, turning off the first light-emitting control transistor T6 and the second light-emitting control transistor T5; the scan signal Scan is at a high potential, turning off the write transistor T2 and the first compensation transistor T3; the first control signal EM2-2 is at a high potential, turning off the second compensation transistor T8 and the reset transistor T7; the second control signal EM1-2 is at a high potential, turning off the third compensation transistor T9; the fourth control signal EM2-1 is at a low level, turning on the first initialization transistor T41 and the second initialization transistor T42, and the third potential signal VI1 resets the gate of the driving transistor T1 or the other end of the storage capacitor C1.
  • the third control signal EM1-1 is at a high level, turning off the first light-emitting control transistor T6 and the second light-emitting control transistor T5; the second control signal EM1-2 is at a high potential, turning off the third compensation transistor T9; the fourth control signal EM2-1 is at a high level, turning off the first initialization transistor T41 and the second initialization transistor T42; the scan signal Scan is at a high potential, turning on the write transistor T2 and the first compensation transistor T3, the first control signal EM2-2 is at a low potential, turning on the second compensation transistor T8 and the reset transistor T7, and the data signal Data is written to the gate of the driving transistor T1 via the write transistor T2, the driving transistor T1, the second compensation transistor T8 and the first compensation transistor T3 in sequence; at the same time, the second potential signal VI2 resets the anode of the light-emitting device D1 via the reset transistor T7.
  • the third control signal EM1-1 is at a high level, turning off the first light-emitting control transistor T6 and the second light-emitting control transistor T5;
  • the scan signal Scan is at a high level, turning on the write transistor T2 and the first compensation transistor T3;
  • the fourth control signal EM2-1 is at a high level, turning off the first initialization transistor T41 and the second initialization transistor T42;
  • the second control signal EM1-2 is at a low level, turning on the third compensation transistor T9, and the first control signal EM2-2 is at a low level, turning on the second compensation transistor T8 and the reset transistor T7, so as to stabilize the potential of the second electrode of the first compensation transistor T3, reduce the voltage difference between the gate potential of the driving transistor T1 and the potential of the second electrode of the first compensation transistor T3 to reduce the leakage current of the first compensation transistor T3, and reset the potential of the first electrode of the driving transistor T1 and the potential of the second electrode of the driving transistor T1 to improve the working state of the driving transistor T
  • First light-emitting stage P4 the third control signal EM1-1 is at a low level, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 are turned on, the driving transistor T1 is in the on state, the other transistors are in the off state, and the light-emitting device D1 emits light.
  • the hold frame consists of the following stages:
  • Second compensation stage P5 The second compensation stage P5 repeats the working conditions of the first compensation stage P3 to stabilize the potential of the second electrode of the first compensation transistor T3, reduce the voltage difference between the gate potential of the driving transistor T1 and the potential of the second electrode of the first compensation transistor T3, and reset the potential of the first electrode of the driving transistor T1 and the potential of the second electrode of the driving transistor T1. At the same time, the anode potential of the light emitting device D1 is reset multiple times.
  • the second light emitting stage is located between two adjacent second compensation stages P5 to achieve light emission of the light emitting device D1.
  • the potential of the first potential signal VI3 may also remain consistent in the write frame and the hold frame, and the range may be 0 to 7.6 V.
  • the potential of the second potential signal VI2 may also remain consistent in the write frame and the hold frame, and the range may be 0 to -6 V.
  • the potential of the third potential signal VI1 may remain consistent in the write frame and the hold frame, or the potential of the third potential signal VI1 in the write frame is higher than that in the hold frame, and the range may be 0 to -6 V.
  • the present embodiment provides a display panel, which includes the pixel circuit 100 of at least one of the above-mentioned embodiments, and the multiple pixel circuits 100 are distributed in an array; each scanning line is electrically connected to two adjacent rows of pixel circuits 100; each first control line is electrically connected to two adjacent rows of pixel circuits 100; each second control line is electrically connected to two adjacent rows of pixel circuits 100; each third control line is electrically connected to two adjacent rows of pixel circuits 100; and each fourth control line is electrically connected to two adjacent rows of pixel circuits 100.
  • the first potential line can change the potential of the second electrode of the first compensation transistor T3 and the potential of the first electrode of the second compensation transistor T8 in a timely manner through the third compensation transistor T9, so as to reduce the voltage difference between the gate of the driving transistor T1 and the second electrode of the first compensation transistor T3 and the first electrode of the second compensation transistor T8, thereby reducing the gate leakage current of the driving transistor T1, making the light-emitting current flowing through the driving transistor T1 more constant, thereby improving the uniformity of the brightness within the frame.
  • the first compensation transistor T3 is in the cut-off state
  • the second compensation transistor T8 and the third compensation transistor T9 are in the on state
  • the first potential line can change the potential of the first electrode and the second electrode of the driving transistor T1 through the second compensation transistor T8 and the third compensation transistor T9, so as to reduce the unidirectional drift range of the threshold voltage of the driving transistor T1 in a single working state, which is beneficial to further maintain the stability of the light-emitting current flowing through the driving transistor T1.
  • the display panel can further reduce the number of required signal lines, which is beneficial to improving the pixel density and aperture ratio of the display panel.
  • the display panel further includes two gate driving circuits, a first driving circuit 200, a second driving circuit 300, a third driving circuit 400 and a fourth driving circuit 500, one gate driving circuit is electrically connected to one end of the scanning line, and the other gate driving circuit is electrically connected to the other end of the scanning line;
  • the first driving circuit 200 is electrically connected to the third control line;
  • the second driving circuit 300 is electrically connected to the first control line;
  • the third driving circuit 400 is electrically connected to the fourth control line;
  • the fourth driving circuit 500 is electrically connected to the second control line;
  • the two gate driving circuits are respectively located on both sides of the plurality of pixel circuits 100, two of the first driving circuit 200, the second driving circuit 300, the third driving circuit 400 and the fourth driving circuit 500 are located on the outside of one of the gate driving circuits, and the other two of the first driving circuit 200, the second driving circuit 300, the third driving circuit 400 and the fourth driving circuit 500 are located on the outside of another of the gate driving circuits.
  • such a layout in this embodiment can not only realize the normal driving of the pixel circuit 100, but also facilitate the layout design of each circuit and the narrow frame.
  • Each gate driving circuit includes a plurality of cascaded gate driving units, for example, a first gate driving unit, a second gate driving unit, etc.
  • Each scan line is electrically connected to two corresponding gate driving units to improve the driving capability of the scan signal Scan.

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Abstract

本申请公开了一种像素电路及显示面板，该像素电路包括驱动晶体管、第一补偿晶体管、第二补偿晶体管以及第三补偿晶体管，第一电位线通过第三补偿晶体管可以适时改变第一补偿晶体管的第二极的电位、第二补偿晶体管的第一极的电位，减小了驱动晶体管的栅极漏电流，使得流经驱动晶体管的发光电流更为恒定。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
 背景技术
在低频驱动的情况下，一帧的时间较长，因此在一帧内像素电路的亮度会产生较大的变化，这会导致人眼可感受到较大的闪烁（Flicker）发生，影响了显示品质。
 发明概述
本申请提供一种像素电路及显示面板，以缓解帧内亮度变化较大的技术问题。
第一方面，本申请提供一种像素电路，该像素电路包括驱动晶体管、第一补偿晶体管、第二补偿晶体管以及第三补偿晶体管，驱动晶体管串联于第一电源线与第二电源线之间；第一补偿晶体管的第一极与驱动晶体管的栅极电连接，第一补偿晶体管的栅极与扫描线电连接；第二补偿晶体管的第一极与第一补偿晶体管的第二极电连接，第二补偿晶体管的第二极与驱动晶体管的第一极或者驱动晶体管的第二极电连接，第二补偿晶体管的栅极与第一控制线电连接；第三补偿晶体管的第一极与第一补偿晶体管的第二极、第二补偿晶体管的第一极电连接，第三补偿晶体管的栅极与第二控制线电连接，第三补偿晶体管的第二极与第一电位线电连接。
在其中一些实施方式中，驱动晶体管的沟道类型、第一补偿晶体管的沟道类型、第二补偿晶体管的沟道类型以及第三补偿晶体管的沟道类型均相同。
在其中一些实施方式中，像素电路还包括第一发光控制晶体管、发光器件以及复位晶体管，第一发光控制晶体管的第一极与驱动晶体管的第二极电连接，第一发光控制晶体管的栅极与第三控制线电连接；发光器件的阳极与第一发光控制晶体管的第二极电连接，发光器件的阴极与第二电源线电连接；复位晶体管的第一极与发光器件的阳极电连接，复位晶体管的第二极与第二电位线或者第一电位线电连接，复位晶体管的栅极与第二补偿晶体管的栅极电连接。
在其中一些实施方式中，复位晶体管的沟道类型与第二补偿晶体管的沟道类型相同。
在其中一些实施方式中，像素电路还包括第二发光控制晶体管、写入晶体管以及第一初始化晶体管，第二发光控制晶体管的第一极与第一电源线电连接，第二发光控制晶体管的第二极与驱动晶体管的第一极电连接，第二发光控制晶体管的栅极与第一发光控制晶体管的栅极电连接；写入晶体管的第一极与数据线电连接，写入晶体管的栅极与扫描线电连接，写入晶体管的第二极与驱动晶体管的第一极或者驱动晶体管的第二极电连接；第一初始化晶体管的第一极与驱动晶体管的栅极电连接，第一初始化晶体管的栅极与第四控制线电连接，第一初始化晶体管的第二极与第三电位线、第一电位线或者第二电位线中的一个电连接。
在其中一些实施方式中，像素电路还包括第二初始化晶体管，第二初始化晶体管的第一极与驱动晶体管的栅极电连接，第二初始化晶体管的栅极与第一初始化晶体管的栅极电连接，第二初始化晶体管的第二极与第一初始化晶体管的第一极、第三补偿晶体管的第一极电连接。
在其中一些实施方式中，驱动晶体管、第一补偿晶体管、第二补偿晶体管、第三补偿晶体管、第一发光控制晶体管、复位晶体管、第二发光控制晶体管、写入晶体管、第一初始化晶体管以及第二初始化晶体管均为低温多晶硅薄膜晶体管。
在其中一些实施方式中，在像素电路的写入阶段中，第一补偿晶体管、第二补偿晶体管均处于导通状态，第三补偿晶体管处于截止状态，以传输数据信号至驱动晶体管的栅极。
在其中一些实施方式中，在像素电路的第一补偿阶段中，第一补偿晶体管处于截止状态，第二补偿晶体管、第三补偿晶体管均处于导通状态，以稳定第一补偿晶体管的第二极的电位、缩小驱动晶体管的栅极电位与第一补偿晶体管的第二极的电位之间的压差、以及复位驱动晶体管的第一极的电位和驱动晶体管的第二极的电位。
在其中一些实施方式中，像素电路的一帧包括写入帧和保持帧，写入阶段、第一补偿阶段均位于写入帧中；保持帧包括若干个第二补偿阶段，在第二补偿阶段中，第一补偿晶体管处于截止状态，第二补偿晶体管、第三补偿晶体管均处于导通状态，以稳定第一补偿晶体管的第二极的电位、缩小驱动晶体管的栅极电位与第一补偿晶体管的第二极的电位之间的压差、以及复位驱动晶体管的第一极的电位和驱动晶体管的第二极的电位。
在其中一些实施方式中，复位晶体管在写入阶段、第一补偿阶段以及第二补偿阶段中均处于导通状态，以多次复位发光器件的阳极电位。
在其中一些实施方式中，第一电位线传输第一电位信号；像素电路的一帧包括写入帧和保持帧，第一电位信号在写入帧中的电位低于在保持帧中的电位。
在其中一些实施方式中，第二电位线传输第二电位信号；像素电路的一帧包括写入帧和保持帧，第二电位信号在写入帧中的电位低于在保持帧中的电位。
第二方面，本申请提供一种显示面板，该显示面板包括上述至少一实施方式中的像素电路，多个像素电路呈阵列分布；每一扫描线与相邻的两行像素电路电连接；每一第一控制线与相邻的两行像素电路电连接；每一第二控制线与相邻的两行像素电路电连接；每一第三控制线与相邻的两行像素电路电连接；每一第四控制线与相邻的两行像素电路电连接。
在其中一些实施方式中，显示面板还包括两个栅极驱动电路、第一驱动电路、第二驱动电路、第三驱动电路以及第四驱动电路，一个栅极驱动电路与扫描线的一端电连接，另一个栅极驱动电路与扫描线的另一端电连接；第一驱动电路与第三控制线电连接；第二驱动电路与第一控制线电连接；第三驱动电路与第四控制线电连接；第四驱动电路与第二控制线电连接；其中，两个栅极驱动电路分别位于多个像素电路的两侧，第一驱动电路、第二驱动电路、第三驱动电路以及第四驱动电路中的两个位于其中一个栅极驱动电路的外侧，第一驱动电路、第二驱动电路、第三驱动电路以及第四驱动电路中的另两个位于其中另一个栅极驱动电路的外侧。
有益效果
本申请提供的像素电路及显示面板，第一电位线通过第三补偿晶体管可以适时改变第一补偿晶体管的第二极的电位、第二补偿晶体管的第一极的电位，以缩小驱动晶体管的栅极与第一补偿晶体管的第二极、第二补偿晶体管的第一极之间的压差，减小了驱动晶体管的栅极漏电流，使得流经驱动晶体管的发光电流更为恒定，进而提高了帧内亮度的均一性。
又，第一补偿晶体管处于截止状态，第二补偿晶体管、第三补偿晶体管处于导通状态下，第一电位线可以通过第二补偿晶体管、第三补偿晶体管改变驱动晶体管的第一极、第二极的电位，以缩小驱动晶体管在单一工作状态下阈值电压的单方向漂移范围，有利于进一步保持流经驱动晶体管的发光电流的稳定性。
 附图说明
图1为相关技术中像素电路的一种结构示意图。
图2为图1所示像素电路的时序示意图。
图3为相关技术中像素电路的另一种结构示意图。
图4为相关技术中像素电路在一帧中的亮度差异示意图。
图5为本申请实施例提供的像素电路的结构示意图。
图6为图5所示像素电路的时序示意图。
图7为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
图1为相关技术中像素电路的一种结构示意图，该像素电路包括驱动晶体管T2、补偿晶体管T3、第一发光控制晶体管T6、第二发光控制晶体管T5、第一初始化晶体管T7、第二初始化晶体管T4、写入晶体管T2、存储电容Cst以及发光器件D1中的至少一个。
其中，存储电容Cst的一端与第一电源线电连接，存储电容Cst的另一端与驱动晶体管T2的栅极电连接。
第二发光控制晶体管T5的源极或者漏极中的一个与第一电源线电连接，第二发光控制晶体管T5的源极或者漏极中的另一个与驱动晶体管T2的源极或者漏极中的一个电连接，第二发光控制晶体管T5的栅极与发光控制线电连接。
写入晶体管T2的源极或者漏极中的一个与第二发光控制晶体管T5的源极或者漏极中的另一个电连接，写入晶体管T2的源极或者漏极中的另一个与数据线连接，写入晶体管T2的栅极与第一扫描线电连接。
补偿晶体管T3的源极或者漏极中的一个与驱动晶体管T2的源极或者漏极中的另一个电连接，补偿晶体管T3的源极或者漏极中的另一个与驱动晶体管T2的栅极电连接，补偿晶体管T3的栅极与第一扫描线电连接。
第一发光控制晶体管T6的源极或者漏极中的一个与驱动晶体管T2的源极或者漏极中的另一个电连接，第一发光控制晶体管T6的栅极与发光控制线电连接，第一发光控制晶体管T6的源极或者漏极中的另一个与发光器件D1的阳极电连接。
发光器件D1的阴极与第二电源线电连接。
第一初始化晶体管T7的源极或者漏极中的一个与发光器件D1的阳极电连接，第一初始化晶体管T7的源极或者漏极中的另一个与初始化线连接，第一初始化晶体管T7的栅极与第一扫描线电连接。
第二初始化晶体管T4的源极或者漏极中的一个与驱动晶体管T2的栅极电连接，第二初始化晶体管T4的源极或者漏极中的另一个与初始化线连接，第二初始化晶体管T4的栅极与第二扫描线电连接。
其中，数据线用于传输数据信号Data。第一电源线用于传输第一电源信号VDD，第二电源线用于传输第二电源信号VSS，第一电源信号VDD的电位大于第二电源信号VSS的电位。发光控制线用于传输发光控制信号EM（n）。初始化线用于传输初始化信号Vi。第一扫描线用于传输扫描信号Scan（n）。第二扫描线用于传输扫描信号Scan（n-1）。
其中，驱动晶体管T2、补偿晶体管T3、第一发光控制晶体管T6、第二发光控制晶体管T5、第一初始化晶体管T7、第二初始化晶体管T4、写入晶体管T2均为P沟道型薄膜晶体管且为低温多晶硅薄膜晶体管。
图1所述的7T1C像素电路在一帧中的工作可以分成如图2所示的以下三个主要运作阶段：
复位阶段M1：扫描信号Scan(n-1) 置为低电平，第二初始化晶体管T4打开，驱动晶体管T1的栅极复位到初始化信号Vi的电位。
充电阶段M2：扫描信号Scan(n)置为低电平，写入晶体管T2、驱动晶体管T1以及补偿晶体管T3均打开，驱动晶体管T1的栅极电位充电至Vdata–Vth；与此同时，第一初始化晶体管T7打开，发光器件的阳极复位到初始化信号Vi的电位。其中，Vdata为数据信号Data的电位，Vth为驱动晶体管T1的阈值电压（Threshold Voltage）。
发光阶段M3：发光控制信号EM（n）置为低电平，发光器件进行发光。
需要进行说明的是，在充电阶段M2中，第二初始化晶体管T4、第一发光控制晶体管T5以及第二发光控制晶体管T6均关闭。此时，数据信号Data通过写入晶体管T2、驱动晶体管T1以及补偿晶体管T3的路径对驱动晶体管T1的栅极充电。当驱动晶体管T1的栅极电位上升到Vdata-Vth，驱动晶体管截止，其栅极电位不再上升。
发光阶段M3中，发光器件的发光亮度直接由驱动晶体管T1的栅极电位决定，而影响驱动晶体管T1的栅极（gate）电位的最主要因素是漏电流，由于驱动晶体管T1的栅极连接有补偿晶体管T3和第二初始化晶体管T4这两个晶体管，因此，这两个晶体管的漏电流特性将直接影响发光阶段的亮度稳定性。由于低温多晶硅薄膜晶体管（LTPS TFT）的漏电流较大，一帧时间内驱动晶体管T1的栅极（即Q点）电位不稳定（图1中两条虚线所示为对应的漏电流路径），导致流经驱动晶体管T1的Ids即发光电流也会发生变化，从而引起一帧时间内画面亮度的变化。
有鉴于此，为了降低驱动晶体管T1的栅极漏电流，相关技术改进像素电路中补偿晶体管T3、第二初始化晶体管T4为如图3所示的双栅极薄膜晶体管结构，这主要是考虑到双栅极薄膜晶体管的漏电流理论上会比单栅极薄膜晶体管的漏电流较小。然而，在显示面板的实际制作过程中，难以避免会产生一些寄生电容，例如，双栅极薄膜晶体管T3-1&T3-2中间的D点、双栅极薄膜晶体管T4-1&T4-2中间的E点电位会因寄生电容的耦合作用，在扫描信号Scan（n-1）或者扫描信号Scan（n）的电位由低到高（即对应晶体管的关闭过程中），D点、E点的电位被耦合成比Q点的电位更高的电位，在后续的发光过程中，由于晶体管T3-1和晶体管T4-1漏电流的原因，Q点的电位会不断上升，驱动晶体管T1对应的栅源极压差（Vgs）变小，进而导致发光器件D1的发光亮度在一帧时间内会逐渐降低，如图4所示，在一帧时间内发光器件D1的亮度下降了△L。
另外，相关技术采用了一种新的LTPO（LTPS TFT+IGZO TFT）技术，即将图1中的补偿晶体管T3和第二初始化晶体管T4替换为漏电流较低的铟镓锌氧化物薄膜晶体管（IGZO TFT），用来解决低频驱动下闪烁（Flicker）较严重的问题，从而使得在显示静态画面时可以采用较低频的驱动方案，最终达到降低功耗的目的。然而，将LTPS TFT和IGZO TFT结合在一起的背板，其结构和工艺更加复杂，成本也会更高。
有鉴于上述提及的不足，本实施例提供了一种像素电路100，请参阅图5、图6，如图5所示，该像素电路100包括驱动晶体管T1、第一补偿晶体管T3、第二补偿晶体管T8以及第三补偿晶体管T9，驱动晶体管T1串联于第一电源线与第二电源线之间；第一补偿晶体管T3的第一极与驱动晶体管T1的栅极电连接，第一补偿晶体管T3的栅极与扫描线电连接；第二补偿晶体管T8的第一极与第一补偿晶体管T3的第二极电连接，第二补偿晶体管T8的第二极与驱动晶体管T1的第一极或者驱动晶体管T1的第二极电连接，第二补偿晶体管T8的栅极与第一控制线电连接；第三补偿晶体管T9的第一极与第一补偿晶体管T3的第二极、第二补偿晶体管T8的第一极电连接，第三补偿晶体管T9的栅极与第二控制线电连接，第三补偿晶体管T9的第二极与第一电位线电连接。
可以理解的是，本实施例提供的像素电路100，第一电位线通过第三补偿晶体管T9可以适时改变第一补偿晶体管T3的第二极的电位、第二补偿晶体管T8的第一极的电位，以缩小驱动晶体管T1的栅极与第一补偿晶体管T3的第二极、第二补偿晶体管T8的第一极之间的压差，减小了驱动晶体管T1的栅极漏电流，使得流经驱动晶体管T1的发光电流更为恒定，进而提高了帧内亮度的均一性。
又，第一补偿晶体管T3处于截止状态，第二补偿晶体管T8、第三补偿晶体管T9处于导通状态下，第一电位线可以通过第二补偿晶体管T8、第三补偿晶体管T9改变驱动晶体管T1的第一极、第二极的电位，以缩小驱动晶体管T1在单一工作状态下阈值电压的单方向漂移范围，有利于进一步保持流经驱动晶体管T1的发光电流的稳定性。
需要进行说明的是，在本申请中，第一极可以为源极或者漏极中的一个，第二极可以为源极或者漏极中的另一个。例如，第一极为源极时，第二极为漏极；或者，第一极为漏极时，第二极为源极。
在其中一个实施例中，第一电位线用于传输第一电位信号VI3；像素电路100的一帧包括写入帧和保持帧，第一电位信号VI3在写入帧中的电位低于在保持帧中的电位。
需要进行说明的是，第一电位信号VI3在写入帧中的电位低于在保持帧中的电位，不仅有利于降低驱动晶体管T1的栅极漏电流，还有利于改变B点的电位和A点的电位以缩小驱动晶体管T1在单一工作状态下阈值电压的单方向漂移范围。其中，B点的电位可以通过驱动晶体管T1与A点的电位进行联动，即当A点或者B点中的一个的电位发生变化时，A点或者B点中的另一个的电位也随之变化。
在其中一个实施例中，像素电路100还包括第一发光控制晶体管T6、发光器件D1以及复位晶体管T7，第一发光控制晶体管T6的第一极与驱动晶体管T1的第二极电连接，第一发光控制晶体管T6的栅极与第三控制线电连接；发光器件D1的阳极与第一发光控制晶体管T6的第二极电连接，发光器件D1的阴极与第二电源线电连接；复位晶体管T7的第一极与发光器件D1的阳极电连接，复位晶体管T7的第二极与第二电位线或者第一电位线电连接，复位晶体管T7的栅极与第二补偿晶体管T8的栅极电连接。
需要进行说明的是，复位晶体管T7的栅极与第二补偿晶体管T8的栅极电连接，可以实现复位晶体管T7的栅极、第二补偿晶体管T8的栅极共用同一第一控制线，进而减少了像素电路100所需的信号线的数量，有利于提高像素电路100的密度以及开口率。
又，在第一控制线的控制下，复位晶体管T7可以在一帧的不同阶段中多次打开，以多次调整或者复位发光器件D1的阳极电位，这能够改善发光器件D1的发光亮度，进而能够进一步改善帧内的亮度差异。
其中，发光器件D1可以为有机发光二极管、量子点发光二极管、微发光二极管或者迷你发光二极管中的一个。
在其中一个实施例中，第二电位线传输第二电位信号VI2；第二电位信号VI2在写入帧中的电位低于在保持帧中的电位。
需要进行说明的是，第二电位信号VI2在写入帧中的电位低于在保持帧中的电位，有利于调整或者复位发光器件D1的阳极电位，以进一步改善帧内的亮度差异。
在其中一个实施例中，复位晶体管T7的沟道类型与第二补偿晶体管T8的沟道类型相同。
需要进行说明的是，由于复位晶体管T7的栅极、第二补偿晶体管T8的栅极共用同一第一控制线，复位晶体管T7的沟道类型与第二补偿晶体管T8的沟道类型相同可以使得复位晶体管T7、第二补偿晶体管T8处于同步状态，以实现复位晶体管T7、第二补偿晶体管T8在帧内不同阶段中多次同步打开。
在其中一个实施例中，像素电路100还包括第二发光控制晶体管T5、写入晶体管T2以及第一初始化晶体管T41，第二发光控制晶体管T5的第一极与第一电源线电连接，第二发光控制晶体管T5的第二极与驱动晶体管T1的第一极电连接，第二发光控制晶体管T5的栅极与第一发光控制晶体管T6的栅极电连接；写入晶体管T2的第一极与数据线电连接，写入晶体管T2的栅极与扫描线电连接，写入晶体管T2的第二极与驱动晶体管T1的第一极或者驱动晶体管T1的第二极电连接；第一初始化晶体管T41的第一极与驱动晶体管T1的栅极电连接，第一初始化晶体管T41的栅极与第四控制线电连接，第一初始化晶体管T41的第二极与第三电位线、第一电位线或者第二电位线中的一个电连接。
需要进行说明的是，第二发光控制晶体管T5的栅极与第一发光控制晶体管T6的栅极电连接，可以实现第二发光控制晶体管T5的栅极与第一发光控制晶体管T6的栅极可以共用同一第三控制线，进而减少了像素电路100所需的信号线的数量，有利于提高像素电路100的密度以及开口率。
又，写入晶体管T2的栅极与扫描线电连接，可以实现写入晶体管T2的栅极与第一补偿晶体管T3的栅极共用同一扫描线，进而减少了像素电路100所需的信号线的数量，有利于提高像素电路100的密度以及开口率。
又，当第一初始化晶体管T41的第二极与第一电位线或者第二电位线电连接时，第一初始化晶体管T41可以与第三补偿晶体管T9或者复位晶体管T7共用同一电位线，进而减少了像素电路100所需的信号线的数量，有利于提高像素电路100的密度以及开口率。
在其中一个实施例中，像素电路100还包括第二初始化晶体管T42，第二初始化晶体管T42的第一极与驱动晶体管T1的栅极电连接，第二初始化晶体管T42的栅极与第一初始化晶体管T41的栅极电连接，第二初始化晶体管T42的第二极与第一初始化晶体管T41的第一极、第三补偿晶体管T9的第一极电连接。
需要进行说明的是，第二初始化晶体管T42的第二极与第一初始化晶体管T41的第一极、第三补偿晶体管T9的第一极电连接，同样能够改善第二初始化晶体管T42的第二极与第一初始化晶体管T41的第一极的连接节点的电位稳定性，并缩小该连接节点与驱动晶体管T1的栅极之间的电位差，以降低驱动晶体管T1的栅极漏电流，进而提高帧内的亮度差异。
在其中一个实施例中，驱动晶体管T1的沟道类型、第一补偿晶体管T3的沟道类型、第二补偿晶体管T8的沟道类型、第三补偿晶体管T9的沟道类型、第一发光控制晶体管T6的沟道类型、复位晶体管T7的沟道类型、第二发光控制晶体管T5的沟道类型、写入晶体管T2的沟道类型、第一初始化晶体管T41的沟道类型以及第二初始化晶体管T42的沟道类型中的至少两个均相同。
需要进行说明的是，这些晶体管的沟道类型相同有利于简化制作的工艺、结构以及成本。其中，沟道类型可以为P沟道或者N沟道。
在其中一个实施例中，驱动晶体管T1、第一补偿晶体管T3、第二补偿晶体管T8、第三补偿晶体管T9、第一发光控制晶体管T6、复位晶体管T7、第二发光控制晶体管T5、写入晶体管T2、第一初始化晶体管T41以及第二初始化晶体管T42中的至少两个均为低温多晶硅薄膜晶体管。
需要进行说明的是，这些晶体管的沟道材料均为低温多晶硅，不仅有利于提高像素电路100的动态性能，还有利于进一步简化制作的工艺、结构以及成本。其中，上述各晶体管均为低温多晶硅薄膜晶体管可以作为一个优选的方案，但并不仅限于此。上述各晶体管中的至少一个也可以为铟镓锌氧化物薄膜晶体管。
在其中一个实施例中，上述像素电路100还包括存储电容C1，存储电容C1的一端与第一电源线电连接，存储电容C1的另一端与驱动晶体管T1的栅极电连接。
需要进行说明的是，第一电源线用于传输第一电源信号VDD，第二电源线用于传输第二电源信号VSS，第一电源信号VDD的电位高于第二电源信号VSS的电位。数据线用于传输数据信号Data。第一电位线用于传输第一电位信号VI3。第二电位线用于传输第二电位信号VI2。第三电位线用于传输第三电位信号VI1。扫描线用于传输扫描信号Scan。第一控制线用于传输第一控制信号EM2-2。第二控制线用于传输第二控制信号EM1-2。第三控制线用于传输第三控制信号EM1-1。第四控制线用于传输第四控制信号EM2-1。
需要进行说明的是，如图6所示，上述像素电路100工作于最高刷新频率的状态下，该像素电路100的一帧仅包括写入帧而不包括保持帧；上述像素电路100工作于较低刷新频率（低于最高刷新频率）的状态下，该像素电路100的一帧包括写入帧和保持帧。下面以工作于较低刷新频率的状态为例，对上述像素电路100的一帧的工作过程进行说明：
写入帧包括以下阶段：
阶段P1：第三控制信号EM1-1为高电平，关闭第一发光控制晶体管T6、第二发光控制晶体管T5；扫描信号Scan为高电位，关闭写入晶体管T2、第一补偿晶体管T3；第一控制信号EM2-2为高电位，关闭第二补偿晶体管T8、复位晶体管T7；第二控制信号EM1-2为高电位，关闭第三补偿晶体管T9；第四控制信号EM2-1为低电平，打开第一初始化晶体管T41、第二初始化晶体管T42，第三电位信号VI1对驱动晶体管T1的栅极或存储电容C1的另一端进行复位。
写入阶段P2：第三控制信号EM1-1为高电平，关闭第一发光控制晶体管T6、第二发光控制晶体管T5；第二控制信号EM1-2为高电位，关闭第三补偿晶体管T9；第四控制信号EM2-1为高电平，关闭第一初始化晶体管T41、第二初始化晶体管T42；扫描信号Scan为高电位，打开写入晶体管T2、第一补偿晶体管T3，第一控制信号EM2-2为低电位，打开第二补偿晶体管T8、复位晶体管T7，数据信号Data依次经写入晶体管T2、驱动晶体管T1、第二补偿晶体管T8以及第一补偿晶体管T3被写入至驱动晶体管T1的栅极；同时，第二电位信号VI2经复位晶体管T7对发光器件D1的阳极进行复位。
第一补偿阶段P3：第三控制信号EM1-1为高电平，关闭第一发光控制晶体管T6、第二发光控制晶体管T5；扫描信号Scan为高电位，打开写入晶体管T2、第一补偿晶体管T3；第四控制信号EM2-1为高电平，关闭第一初始化晶体管T41、第二初始化晶体管T42；第二控制信号EM1-2为低电位，打开第三补偿晶体管T9，第一控制信号EM2-2为低电位，打开第二补偿晶体管T8、复位晶体管T7，以稳定第一补偿晶体管T3的第二极的电位、缩小驱动晶体管T1的栅极电位与第一补偿晶体管T3的第二极的电位之间的压差以减小第一补偿晶体管T3的漏电流、以及复位驱动晶体管T1的第一极的电位和驱动晶体管T1的第二极的电位以改善驱动晶体管T1的工作状态，避免长时间处于同一应力状态而导致其阈值电压朝正向或者负向偏移。
第一发光阶段P4：第三控制信号EM1-1为低电平，打开第一发光控制晶体管T6、第二发光控制晶体管T5，驱动晶体管T1处于导通状态，其他晶体管处于截止状态，发光器件D1发光。
保持帧包括以下阶段：
第二补偿阶段P5：该第二补偿阶段P5重复上述第一补偿阶段P3的工况，以稳定第一补偿晶体管T3的第二极的电位、缩小驱动晶体管T1的栅极电位与第一补偿晶体管T3的第二极的电位之间的压差、以及复位驱动晶体管T1的第一极的电位和驱动晶体管T1的第二极的电位。同时，多次复位发光器件D1的阳极电位。
第二发光阶段：位于相邻的两个第二补偿阶段P5之间，以实现发光器件D1的发光。
需要进行说明的是，第一电位信号VI3的电位也可以在写入帧、保持帧中保持一致，其范围可以为0~7.6V。第二电位信号VI2的电位也可以在写入帧、保持帧中保持一致，其范围可以为0~-6V。第三电位信号VI1的电位可以在写入帧、保持帧中保持一致，或者，第三电位信号VI1在写入帧的电位高于在保持帧中的电位，其范围可以为0~-6V。
在其中一个实施例中，本实施例提供一种显示面板，该显示面板包括上述至少一实施例中的像素电路100，多个像素电路100呈阵列分布；每一扫描线与相邻的两行像素电路100电连接；每一第一控制线与相邻的两行像素电路100电连接；每一第二控制线与相邻的两行像素电路100电连接；每一第三控制线与相邻的两行像素电路100电连接；每一第四控制线与相邻的两行像素电路100电连接。
可以理解的是，本实施例提供的显示面板，第一电位线通过第三补偿晶体管T9可以适时改变第一补偿晶体管T3的第二极的电位、第二补偿晶体管T8的第一极的电位，以缩小驱动晶体管T1的栅极与第一补偿晶体管T3的第二极、第二补偿晶体管T8的第一极之间的压差，减小了驱动晶体管T1的栅极漏电流，使得流经驱动晶体管T1的发光电流更为恒定，进而提高了帧内亮度的均一性。
又，第一补偿晶体管T3处于截止状态，第二补偿晶体管T8、第三补偿晶体管T9处于导通状态下，第一电位线可以通过第二补偿晶体管T8、第三补偿晶体管T9改变驱动晶体管T1的第一极、第二极的电位，以缩小驱动晶体管T1在单一工作状态下阈值电压的单方向漂移范围，有利于进一步保持流经驱动晶体管T1的发光电流的稳定性。
又，由于相邻的两行像素电路100可以共用同一扫描线，相邻的两行像素电路100电又可以共用同一第一控制线、第二控制线、第三控制线以及第四控制线，该显示面板能够进一步减少所需的信号线数量，有利于提高显示面板的像素密度及开口率。
在其中一个实施例中，如图7所示，显示面板还包括两个栅极驱动电路、第一驱动电路200、第二驱动电路300、第三驱动电路400以及第四驱动电路500，一个栅极驱动电路与扫描线的一端电连接，另一个栅极驱动电路与扫描线的另一端电连接；第一驱动电路200与第三控制线电连接；第二驱动电路300与第一控制线电连接；第三驱动电路400与第四控制线电连接；第四驱动电路500与第二控制线电连接；其中，两个栅极驱动电路分别位于多个像素电路100的两侧，第一驱动电路200、第二驱动电路300、第三驱动电路400以及第四驱动电路500中的两个位于其中一个栅极驱动电路的外侧，第一驱动电路200、第二驱动电路300、第三驱动电路400以及第四驱动电路500中的另两个位于其中另一个栅极驱动电路的外侧。
需要进行说明的是，本实施例如此布局不仅可以实现像素电路100的正常驱动，还有利于实现各电路的版图设计以及窄边框。
其中，每个栅极驱动电路均包括多个级联的栅极驱动单元，例如，第一栅极驱动单元、第二栅极驱动单元...等等，每一扫描线均与对应的两个栅极驱动单元电连接以提高扫描信号Scan的驱动能力。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，其中，所述像素电路包括：
    驱动晶体管，所述驱动晶体管串联于第一电源线与第二电源线之间；
    第一补偿晶体管，所述第一补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一补偿晶体管的栅极与扫描线电连接；
    第二补偿晶体管，所述第二补偿晶体管的第一极与所述第一补偿晶体管的第二极电连接，所述第二补偿晶体管的第二极与所述驱动晶体管的第一极或者所述驱动晶体管的第二极电连接，所述第二补偿晶体管的栅极与第一控制线电连接；
    第三补偿晶体管，所述第三补偿晶体管的第一极与所述第一补偿晶体管的第二极、所述第二补偿晶体管的第一极电连接，所述第三补偿晶体管的栅极与第二控制线电连接，所述第三补偿晶体管的第二极与第一电位线电连接。
  2. 根据权利要求1所述的像素电路，其中，所述驱动晶体管的沟道类型、所述第一补偿晶体管的沟道类型、所述第二补偿晶体管的沟道类型以及所述第三补偿晶体管的沟道类型均相同。
  3. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    第一发光控制晶体管，所述第一发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第一发光控制晶体管的栅极与第三控制线电连接；
    发光器件，所述发光器件的阳极与所述第一发光控制晶体管的第二极电连接，所述发光器件的阴极与所述第二电源线电连接；
    复位晶体管，所述复位晶体管的第一极与所述发光器件的阳极电连接，所述复位晶体管的第二极与第二电位线或者所述第一电位线电连接，所述复位晶体管的栅极与所述第二补偿晶体管的栅极电连接。
  4. 根据权利要求3所述的像素电路，其中，所述复位晶体管的沟道类型与所述第二补偿晶体管的沟道类型相同。
  5. 根据权利要求3所述的像素电路，其中，所述像素电路还包括：
    第二发光控制晶体管，所述第二发光控制晶体管的第一极与所述第一电源线电连接，所述第二发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第二发光控制晶体管的栅极与所述第一发光控制晶体管的栅极电连接；
    写入晶体管，所述写入晶体管的第一极与数据线电连接，所述写入晶体管的栅极与所述扫描线电连接，所述写入晶体管的第二极与所述驱动晶体管的第一极或者所述驱动晶体管的第二极电连接；
    第一初始化晶体管，所述第一初始化晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一初始化晶体管的栅极与第四控制线电连接，所述第一初始化晶体管的第二极与第三电位线、所述第一电位线或者所述第二电位线中的一个电连接。
  6. 根据权利要求5所述的像素电路，其中，所述像素电路还包括：
    第二初始化晶体管，所述第二初始化晶体管的第一极与所述驱动晶体管的栅极电连接，所述第二初始化晶体管的栅极与所述第一初始化晶体管的栅极电连接，所述第二初始化晶体管的第二极与所述第一初始化晶体管的第一极、所述第三补偿晶体管的第一极电连接。
  7. 根据权利要求6所述的像素电路，其中，所述驱动晶体管、所述第一补偿晶体管、所述第二补偿晶体管、所述第三补偿晶体管、所述第一发光控制晶体管、所述复位晶体管、所述第二发光控制晶体管、所述写入晶体管、所述第一初始化晶体管以及所述第二初始化晶体管均为低温多晶硅薄膜晶体管。
  8. 根据权利要求3所述的像素电路，其中，在所述像素电路的写入阶段中，所述第一补偿晶体管、所述第二补偿晶体管均处于导通状态，所述第三补偿晶体管处于截止状态，以传输数据信号至所述驱动晶体管的栅极。
  9. 根据权利要求8所述的像素电路，其中，在所述像素电路的第一补偿阶段中，所述第一补偿晶体管处于截止状态，所述第二补偿晶体管、所述第三补偿晶体管均处于导通状态，以稳定所述第一补偿晶体管的第二极的电位、缩小所述驱动晶体管的栅极电位与所述第一补偿晶体管的第二极的电位之间的压差、以及复位所述驱动晶体管的第一极的电位和所述驱动晶体管的第二极的电位。
  10. 根据权利要求9所述的像素电路，其中，所述像素电路的一帧包括写入帧和保持帧，所述写入阶段、所述第一补偿阶段均位于所述写入帧中；
    所述保持帧包括若干个第二补偿阶段，在所述第二补偿阶段中，所述第一补偿晶体管处于截止状态，所述第二补偿晶体管、所述第三补偿晶体管均处于导通状态，以稳定所述第一补偿晶体管的第二极的电位、缩小所述驱动晶体管的栅极电位与所述第一补偿晶体管的第二极的电位之间的压差、以及复位所述驱动晶体管的第一极的电位和所述驱动晶体管的第二极的电位。
  11. 根据权利要求10所述的像素电路，其中，所述复位晶体管在所述写入阶段、所述第一补偿阶段以及所述第二补偿阶段中均处于导通状态，以多次复位所述发光器件的阳极电位。
  12. 根据权利要求1所述的像素电路，其中，所述第一电位线传输第一电位信号；所述像素电路的一帧包括写入帧和保持帧，所述第一电位信号在所述写入帧中的电位低于在所述保持帧中的电位。
  13. 根据权利要求3所述的像素电路，其中，所述第二电位线传输第二电位信号；所述像素电路的一帧包括写入帧和保持帧，所述第二电位信号在所述写入帧中的电位低于在所述保持帧中的电位。
  14. 一种显示面板，其中，所述显示面板包括如权利要求1所述的像素电路，多个所述像素电路呈阵列分布；每一所述扫描线与相邻的两行所述像素电路电连接；每一所述第一控制线与相邻的两行所述像素电路电连接；每一所述第二控制线与相邻的两行所述像素电路电连接；每一第三控制线与相邻的两行所述像素电路电连接；每一第四控制线与相邻的两行所述像素电路电连接。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括：
    两个栅极驱动电路，一个所述栅极驱动电路与所述扫描线的一端电连接，另一个所述栅极驱动电路与所述扫描线的另一端电连接；
    第一驱动电路，所述第一驱动电路与所述第三控制线电连接；
    第二驱动电路，所述第二驱动电路与所述第一控制线电连接；
    第三驱动电路，所述第三驱动电路与所述第四控制线电连接；
    第四驱动电路，所述第四驱动电路与所述第二控制线电连接；
    其中，两个所述栅极驱动电路分别位于多个所述像素电路的两侧，所述第一驱动电路、所述第二驱动电路、所述第三驱动电路以及所述第四驱动电路中的两个位于其中一个所述栅极驱动电路的外侧，所述第一驱动电路、所述第二驱动电路、所述第三驱动电路以及所述第四驱动电路中的另两个位于其中另一个所述栅极驱动电路的外侧。
  16. 根据权利要求14所述的显示面板，其中，所述驱动晶体管的沟道类型、所述第一补偿晶体管的沟道类型、所述第二补偿晶体管的沟道类型以及所述第三补偿晶体管的沟道类型均相同。
  17. 根据权利要求14所述的显示面板，其中，所述像素电路还包括：
    第一发光控制晶体管，所述第一发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第一发光控制晶体管的栅极与第三控制线电连接；
    发光器件，所述发光器件的阳极与所述第一发光控制晶体管的第二极电连接，所述发光器件的阴极与所述第二电源线电连接；
    复位晶体管，所述复位晶体管的第一极与所述发光器件的阳极电连接，所述复位晶体管的第二极与第二电位线或者所述第一电位线电连接，所述复位晶体管的栅极与所述第二补偿晶体管的栅极电连接。
  18. 根据权利要求16所述的显示面板，其中，所述复位晶体管的沟道类型与所述第二补偿晶体管的沟道类型相同。
  19. 根据权利要求16所述的显示面板，其中，所述像素电路还包括：
    第二发光控制晶体管，所述第二发光控制晶体管的第一极与所述第一电源线电连接，所述第二发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第二发光控制晶体管的栅极与所述第一发光控制晶体管的栅极电连接；
    写入晶体管，所述写入晶体管的第一极与数据线电连接，所述写入晶体管的栅极与所述扫描线电连接，所述写入晶体管的第二极与所述驱动晶体管的第一极或者所述驱动晶体管的第二极电连接；
    第一初始化晶体管，所述第一初始化晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一初始化晶体管的栅极与第四控制线电连接，所述第一初始化晶体管的第二极与第三电位线、所述第一电位线或者所述第二电位线中的一个电连接。
  20. 根据权利要求18所述的显示面板，其中，所述像素电路还包括：
    第二初始化晶体管，所述第二初始化晶体管的第一极与所述驱动晶体管的栅极电连接，所述第二初始化晶体管的栅极与所述第一初始化晶体管的栅极电连接，所述第二初始化晶体管的第二极与所述第一初始化晶体管的第一极、所述第三补偿晶体管的第一极电连接。
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Publication number Priority date Publication date Assignee Title
CN115938275A (zh) * 2022-11-23 2023-04-07 武汉华星光电半导体显示技术有限公司 像素电路及显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150129234A (ko) * 2014-05-09 2015-11-19 엘지디스플레이 주식회사 유기발광표시장치 및 그 구동방법
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN107591124A (zh) * 2017-09-29 2018-01-16 上海天马微电子有限公司 像素补偿电路、有机发光显示面板及有机发光显示装置
CN111754938A (zh) * 2020-07-24 2020-10-09 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
CN114078430A (zh) * 2021-12-09 2022-02-22 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN114582287A (zh) * 2022-04-21 2022-06-03 武汉天马微电子有限公司 显示面板及显示装置
CN115083335A (zh) * 2022-06-08 2022-09-20 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN115938275A (zh) * 2022-11-23 2023-04-07 武汉华星光电半导体显示技术有限公司 像素电路及显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150129234A (ko) * 2014-05-09 2015-11-19 엘지디스플레이 주식회사 유기발광표시장치 및 그 구동방법
CN106910468A (zh) * 2017-04-28 2017-06-30 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN107591124A (zh) * 2017-09-29 2018-01-16 上海天马微电子有限公司 像素补偿电路、有机发光显示面板及有机发光显示装置
CN111754938A (zh) * 2020-07-24 2020-10-09 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
CN114078430A (zh) * 2021-12-09 2022-02-22 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN114582287A (zh) * 2022-04-21 2022-06-03 武汉天马微电子有限公司 显示面板及显示装置
CN115083335A (zh) * 2022-06-08 2022-09-20 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN115938275A (zh) * 2022-11-23 2023-04-07 武汉华星光电半导体显示技术有限公司 像素电路及显示面板

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