WO2023115533A1 - 像素电路以及显示面板 - Google Patents

像素电路以及显示面板 Download PDF

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Publication number
WO2023115533A1
WO2023115533A1 PCT/CN2021/141183 CN2021141183W WO2023115533A1 WO 2023115533 A1 WO2023115533 A1 WO 2023115533A1 CN 2021141183 W CN2021141183 W CN 2021141183W WO 2023115533 A1 WO2023115533 A1 WO 2023115533A1
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Prior art keywords
thin film
film transistor
circuit
terminal
source
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PCT/CN2021/141183
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English (en)
French (fr)
Inventor
曾勉
孙亮
Original Assignee
武汉华星光电半导体显示技术有限公司
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Publication of WO2023115533A1 publication Critical patent/WO2023115533A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Definitions

  • the present application relates to the technical field of display driving, in particular to a pixel circuit and a display panel.
  • AMOLED Active-matrix organic light-emitting diode
  • active-matrix organic light-emitting diode active-matrix organic light-emitting diode
  • LTPS TFT Low Temperature Poly-Silicon Thin Film Transistor, Low Temperature Poly-Silicon Thin Film Transistor
  • the gate potential of the driving TFT in the LTPS TFT driving circuit is unstable within one frame time, and the output current corresponding to the driving TFT will also change accordingly, which eventually causes the gate potential of the driving TFT within one frame time.
  • the screen brightness flickers Due to the large leakage current of the LTPS TFT, the gate potential of the driving TFT in the LTPS TFT driving circuit is unstable within one frame time, and the output current corresponding to the driving TFT will also change accordingly, which eventually causes the gate potential of the driving TFT within one frame time.
  • the screen brightness flickers Due to the large leakage current of the LTPS TFT, the gate potential of the driving TFT in the LTPS TFT driving circuit is unstable within one frame time, and the output current corresponding to the driving TFT will also change accordingly, which eventually causes the gate potential of the driving TFT within one frame time.
  • the screen brightness flickers Due to the large leakage current of the LTPS TFT, the gate potential of the driving TFT in the LTPS TFT driving circuit is unstable within
  • an embodiment of the present application provides a pixel circuit, including a drive circuit, a first light emission control circuit, a second light emission control circuit, a data writing circuit, a reset circuit, a storage circuit, a first thin film transistor, and a second thin film transistor ;
  • the first end of the drive circuit is respectively connected to the first end of the first light emission control circuit and the first end of the data writing circuit, and the second end is respectively connected to the source of the first thin film transistor, the drain of the second thin film transistor and the second
  • the first terminal and the third terminal of the lighting control circuit are respectively connected to the drain of the first thin film transistor and the first terminal of the storage circuit;
  • the second terminal of the first lighting control circuit is respectively connected to the second terminal of the storage circuit and the voltage source, and the third terminal is connected to the lighting signal; the second terminal of the second lighting control circuit is connected to the lighting signal, and the third terminal is connected to the reset circuit.
  • One end is used to connect the light-emitting device;
  • the second end of the data writing circuit is connected to the first scanning line of the current row, and the third end is connected to the data line;
  • the second end of the reset circuit is connected to the first scanning line of the current row, and the third end is connected to the first initial voltage signal;
  • the gate of the first thin film transistor is connected to the second scan line of the current row; the gate of the second thin film transistor is connected to the first scan line of the previous row, and the source is connected to the second initial voltage signal.
  • an embodiment of the present application provides a display panel, including a light emitting layer and a driving layer; the driving layer is used to drive the light emitting layer to emit light; the driving layer is provided with a pixel circuit;
  • the pixel circuit includes a drive circuit, a first light emission control circuit, a second light emission control circuit, a data writing circuit, a reset circuit, a storage circuit, a first thin film transistor and a second thin film transistor;
  • the first end of the drive circuit is respectively connected to the first end of the first light emission control circuit and the first end of the data writing circuit, and the second end is respectively connected to the source of the first thin film transistor, the drain of the second thin film transistor and the second
  • the first terminal and the third terminal of the lighting control circuit are respectively connected to the drain of the first thin film transistor and the first terminal of the storage circuit;
  • the second terminal of the first lighting control circuit is respectively connected to the second terminal of the storage circuit and the voltage source, and the third terminal is connected to the lighting signal; the second terminal of the second lighting control circuit is connected to the lighting signal, and the third terminal is connected to the reset circuit.
  • One end is used to connect the light-emitting device;
  • the second end of the data writing circuit is connected to the first scanning line of the current row, and the third end is connected to the data line;
  • the second end of the reset circuit is connected to the first scanning line of the current row, and the third end is connected to the first initial voltage signal;
  • the gate of the first thin film transistor is connected to the second scan line of the current row; the gate of the second thin film transistor is connected to the first scan line of the previous row, and the source is connected to the second initial voltage signal.
  • the pixel circuit of the present application includes a drive circuit, a first light emission control circuit, a second light emission control circuit, a data writing circuit, a reset circuit, a storage circuit, a first thin film transistor and a second thin film transistor, wherein the drain of the first thin film transistor
  • the drain of the second thin film transistor is directly connected to the driving circuit, and the drain of the second thin film transistor is indirectly connected to the driving circuit, so that the number of thin film transistors directly connected to the driving circuit is reduced, and the leakage current path of the driving circuit is reduced, so that the output of the driving circuit in the light emitting stage The current is more stable, which solves the problem of screen brightness flickering.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by the implementation of the present application.
  • FIG. 2 is another schematic structural diagram of the pixel circuit provided by the implementation of the present application.
  • FIG. 3 is a first circuit diagram of a pixel circuit provided by the implementation of the present application.
  • FIG. 4 is a second circuit diagram of the pixel circuit provided by the implementation of the present application.
  • FIG. 5 is a third circuit diagram of the pixel circuit provided by the implementation of the present application.
  • FIG. 6 is a fourth circuit diagram of the pixel circuit provided by the implementation of the present application.
  • FIG. 7 is a fifth circuit diagram of the pixel circuit provided by the implementation of the present application.
  • FIG. 8 is a sixth circuit diagram of the pixel circuit provided by the implementation of the present application.
  • FIG. 9 is a timing diagram of driving signals corresponding to display scanning of the pixel circuit provided by the implementation of the present application.
  • FIG. 10 is a timing diagram of the GOA drive signal corresponding to the pixel circuit provided by the implementation of the present application.
  • Figure 11 is a schematic diagram of the pixel circuit corresponding to the panel driving sequence provided by the implementation of the present application (taking 60 Hz as an example).
  • FIG. 12 is a schematic diagram of the brightness measurement effect of the pixel circuit provided by the implementation of the present application.
  • an embodiment of the present application provides a pixel circuit 1 .
  • the pixel circuit 1 of the present application includes a drive circuit 11, a first light emission control circuit 12, a second light emission control circuit 13, a data writing circuit 14, a reset circuit 15, a storage circuit 16, a first thin film transistor T1 and The second thin film transistor T2.
  • the driving circuit 11 is used to drive the light emitting device to emit light according to the data voltage signal (the data voltage signal transmitted by the data line is written into the driving circuit 11 by the data writing circuit 14 ).
  • the first end of the driving circuit 11 is respectively connected to the first end of the first light emission control circuit 12 and the first end of the data writing circuit 14 .
  • the second terminal of the driving circuit 11 is respectively connected to the source of the first TFT T1 , the drain of the second TFT T2 and the first terminal of the second light emission control circuit 13 .
  • the third terminal of the driving circuit 11 is respectively connected to the drain of the first thin film transistor T1 and the first terminal of the storage circuit 16 .
  • the first light emission control circuit 12 and the second light emission control circuit 13 are used to control the storage circuit 16 to couple the data voltage to the driving circuit 11 during the light emitting stage of the pixel circuit 1 of the present application, so that the driving circuit 11 forms a driving current according to the data signal to drive the light emitting device glow.
  • the first terminal of the first light emission control circuit 12 is connected to the first terminal of the driving circuit 11 .
  • the second terminal of the first lighting control circuit 12 is respectively connected to the second terminal of the storage circuit 16 and a voltage source (VDD in FIG. 1 ).
  • the third terminal of the first light emission control circuit 12 is connected to an light emission (Emitting, EM) signal (EM(n) in FIG. 1 ).
  • a first terminal of the second light emission control circuit 13 is connected to a second terminal of the driving circuit 11 .
  • the second end of the second light emission control circuit 13 is connected to the light emission signal.
  • the third end of the second light emission control circuit 13 is connected to one end of the reset circuit 15 and used for connecting to the light emitting device.
  • the data writing circuit 14 is used to connect the data line to receive the data voltage signal transmitted by the data line, and write the data voltage signal into the driving circuit 11 .
  • the first terminal of the data writing circuit 14 is connected to the first terminal of the driving circuit 11 .
  • the second end of the data writing circuit 14 is connected to the first scan line of the current row (A_Scan(n) in FIG. 1 ). It should be noted that the first scan line is used to transmit high-frequency scan signals.
  • the third end of the data writing circuit 14 is connected to the data line (Data in FIG. 1 ).
  • the reset circuit 15 is used to reset the potential of the light emitting device.
  • the first end of the reset circuit 15 is connected to the third end of the second light emission control circuit 13 .
  • the second end of the reset circuit 15 is connected to the first scan line of the current row.
  • the third terminal of the reset circuit 15 is connected to the first initial voltage signal (Vi_1 in FIG. 1 ).
  • the reset circuit 15 and the second thin film transistor T2 are respectively connected to the first initial voltage signal and the second initial voltage signal (Vi_2 in FIG. 1 ).
  • the third terminal of the reset circuit 15 is connected to the source of the second thin film transistor T2; the first initial voltage signal and the second initial voltage signal are the same signal.
  • the reset circuit 15 and the second thin film transistor T2 share an initial voltage signal.
  • the first thin film transistor T1 and the second thin film transistor T2 are used to reset the driving circuit 11 (specifically, reset the potential at point Q as shown in FIGS. 1-8 ).
  • the source of the first thin film transistor T1 is connected to the second terminal of the driving circuit 11 .
  • the drain of the first thin film transistor T1 is connected to the third terminal of the driving circuit 11 .
  • the gate of the first thin film transistor T1 is connected to the second scan line (B_Scan(n) in FIG. 1 ) of the current row. It should be noted that the second scan line is used to transmit low-frequency scan signals.
  • the drain of the second thin film transistor T2 is connected to the second terminal of the driving circuit 11 .
  • the gate of the second thin film transistor T2 is connected to the first scan line of the previous row (A_Scan(n ⁇ 1) in FIG. 1 ).
  • the source of the second thin film transistor T2 is connected to the second initial voltage signal.
  • the first end of the blocking circuit 17 is respectively connected to the second end of the driving circuit 11 and the first end of the second light emission control circuit 13, and the second end of the blocking circuit 17 is respectively connected to the source of the first thin film transistor T1. and the drain of the second TFT T2, and the third terminal of the blocking circuit 17 is connected to the first scan line of the current row.
  • the blocking circuit 17 can avoid the influence of the potential of the point B on the potential of the point Q, thereby avoiding flickering of the screen brightness within one frame time of the panel.
  • the drive circuit 11 , the first light emission control circuit 12 , the second light emission control circuit 13 , the data writing circuit 14 , the reset circuit 15 and the storage circuit 16 can be set to different circuits according to actual needs.
  • the blocking circuit 17 includes a third thin film transistor T3.
  • the source of the third thin film transistor T3 is respectively connected to the second end of the driving circuit 11 and the first end of the second light emission control circuit 13, and the drain of the third thin film transistor T3 is respectively connected to the source of the first thin film transistor T1 and the second end of the second light emission control circuit.
  • the drain of the TFT T2 and the gate of the third TFT T3 are connected to the first scan line of the current row.
  • the driving circuit 11 includes a fourth thin film transistor T4.
  • the source of the fourth thin film transistor T4 is respectively connected to the first terminal of the first light emission control circuit 12 and the first terminal of the data writing circuit 14, and the drain of the fourth thin film transistor T4 is respectively connected to the source of the first thin film transistor T1,
  • the drain of the second TFT T2 is connected to the first terminal of the second light emission control circuit 13
  • the gate of the fourth TFT T4 is respectively connected to the drain of the first TFT T1 and the first terminal of the storage circuit 16 .
  • the first light emission control circuit 12 includes a fifth thin film transistor T5.
  • the source of the fifth thin film transistor T5 is respectively connected to the second terminal of the storage circuit 16 and the voltage source, the drain of the fifth thin film transistor T5 is connected to the source of the fourth thin film transistor T4, and the gate of the fifth thin film transistor T5 is connected to emit light. Signal.
  • the second light emission control circuit 13 includes a sixth thin film transistor T6.
  • the source of the sixth thin film transistor T6 is respectively connected to the source of the first thin film transistor T1, the drain of the second thin film transistor T2 and the drain of the fourth thin film transistor T4, and the gate of the sixth thin film transistor T6 is connected to the light emitting signal,
  • the drain of the sixth thin film transistor T6 is connected to one end of the reset circuit 15 and used for connecting to the light emitting device.
  • the data writing circuit 14 includes a seventh thin film transistor T7; the drain of the seventh thin film transistor T7 is respectively connected to the source of the fourth thin film transistor T4 and the drain of the fifth thin film transistor T5, and the gate of the seventh thin film transistor T7 is connected to the current
  • the source of the seventh thin film transistor T7 is connected to the data line.
  • the reset circuit 15 includes an eighth thin film transistor T8.
  • the drain of the eighth thin film transistor T8 is connected to the drain of the sixth thin film transistor T6 respectively, the gate of the eighth thin film transistor T8 is connected to the first scan line of the current row, and the source of the eighth thin film transistor T8 is connected to the first initial voltage signal.
  • the storage circuit 16 includes a capacitor Cst. A first end of the capacitor Cst is connected to the gate of the fourth TFT T4, and a second end of the capacitor Cst is connected to the source of the fifth TFT T5.
  • the type of the first thin film transistor T1 can be selected according to actual needs, and the first thin film transistor T1 is a single gate thin film transistor or a double gate thin film transistor.
  • the type of the first thin film transistor T1 can be selected according to actual needs, and the second thin film transistor T2 is a single gate thin film transistor or a double gate thin film transistor.
  • Four schemes can be combined as follows: 1.
  • the first thin film transistor T1 is a single gate thin film transistor, and the second thin film transistor T2 is a single gate thin film transistor; 2.
  • the first thin film transistor T1 is a double gate thin film transistor;
  • the thin film transistor T2 is a single gate thin film transistor; 3.
  • the first thin film transistor T1 is a single gate thin film transistor, and the second thin film transistor T2 is a double gate thin film transistor; 4.
  • the first thin film transistor T1 is a double gate thin film transistor,
  • the second thin film transistor T2 is a double gate thin film transistor. It should be noted that the leakage current avoidance effect of the double-gate thin film transistor is better than that of the single-gate thin film transistor.
  • the pixel circuit 1 of the present application includes a drive circuit 11, a first light emission control circuit 12, a second light emission control circuit 13, a data writing circuit 14, a reset circuit 15, a storage circuit 16, a first thin film transistor T1 and a second thin film transistor T2 .
  • the first thin film transistor T1 is a double gate thin film transistor
  • the second thin film transistor T2 is a double gate thin film transistor
  • the blocking circuit 17 includes a third thin film transistor T3
  • the driving circuit 11 includes a fourth thin film transistor T4
  • the control circuit 12 includes a fifth thin film transistor T5
  • the second light emission control circuit 13 includes a sixth thin film transistor T6
  • the data writing circuit 14 includes a seventh thin film transistor T7
  • the reset circuit 15 includes an eighth thin film transistor T8
  • the storage circuit 16 includes a capacitor Cst.
  • the source of the first thin film transistor T1 is respectively connected to the drain of the second thin film transistor T2 and the drain of the third thin film transistor T3, and the drain of the first thin film transistor T1 is respectively connected to the gate of the fourth thin film transistor T4 and the capacitor Cst. At one end, the gate of the first thin film transistor T1 is connected to the second scan line of the current row.
  • the drain of the second thin film transistor T2 is respectively connected to the source of the first thin film transistor T1 and the drain of the third thin film transistor T3, the gate of the second thin film transistor T2 is connected to the first scanning line of the previous row, and the gate of the second thin film transistor T2 The source is connected to the second initial voltage signal.
  • the drain of the third thin film transistor T3 is respectively connected to the source of the first thin film transistor T1 and the drain of the second thin film transistor T2, and the source of the third thin film transistor T3 is respectively connected to the drain of the fourth thin film transistor T4 and the sixth thin film transistor T4.
  • the source of the transistor T6 and the gate of the third thin film transistor T3 are connected to the first scan line of the current row.
  • the gate of the fourth thin film transistor T4 is respectively connected to the drain of the first thin film transistor T1 and one end of the capacitor Cst, and the source of the fourth thin film transistor T4 is respectively connected to the drain of the fifth thin film transistor T5 and the drain of the seventh thin film transistor T7
  • the drain of the fourth thin film transistor T4 is respectively connected to the source of the third thin film transistor T3 and the source of the sixth thin film transistor T6.
  • the drain of the fifth thin film transistor T5 is respectively connected to the source of the fourth thin film transistor T4 and the drain of the seventh thin film transistor T7, the source of the fifth thin film transistor T5 is respectively connected to the other end of the capacitor Cst, and the fifth thin film transistor T5
  • the grid is connected to the luminous signal.
  • the source of the sixth thin film transistor T6 is respectively connected to the source of the third thin film transistor T3 and the drain of the fourth thin film transistor T4, and the drain of the sixth thin film transistor T6 is respectively connected to the drain of the eighth thin film transistor T8 and the light emitting device,
  • the gate of the sixth thin film transistor T6 is connected to the light emitting signal.
  • the drain of the seventh thin film transistor T7 is respectively connected to the source of the fourth thin film transistor T4 and the drain of the fifth thin film transistor T5, the source of the seventh thin film transistor T7 is connected to the data line, and the gate of the seventh thin film transistor T7 is connected to the current the first scan line.
  • the drain of the eighth thin film transistor T8 is respectively connected to the drain of the sixth thin film transistor T6 and the light-emitting device, the source of the eighth thin film transistor T8 is connected to the first initial voltage signal, and the gate of the eighth thin film transistor T8 is connected to the first initial voltage signal of the current row. a scan line.
  • the timing diagram of the driving signal corresponding to the display scanning of the pixel circuit 1 in this example the work of the pixel circuit 1 is mainly divided into three stages:
  • the signals transmitted by the first scan line of the previous row and the second scan line of the current row are both low level, and the signals transmitted by the first scan line of the current row and the light-emitting signal are both high level
  • the first thin film transistor T1 and the second thin film transistor T2 are turned on at the same time
  • the third thin film transistor T3, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7 and the eighth thin film transistor T8 are turned off
  • the third thin film transistor T3 is turned off.
  • the gates of the four thin film transistors T4 are reset to the second initial voltage signal.
  • the light emitting signals are still at high level, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned off.
  • the signals transmitted by the first scan line of the current row and the second scan line of the current row are both low level, the first thin film transistor T1 and the seventh thin film transistor T7 are turned on at the same time, and the data signal transmitted by the data line passes through the first thin film transistor T1 and the seventh thin film transistor T7.
  • the seven thin film transistors T7 are written to point Q, and reversely capture the start voltage (Vth) of the fourth thin film transistor T4.
  • the eighth thin film transistor T8 is turned on to reset the anode of the light emitting device to the first initial voltage signal.
  • the signals transmitted by the first scan line of the current row and the second scan line of the current row are both high-level, and the light-emitting signals are all low-potential, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned on,
  • the fourth thin film transistor T4 generates a current corresponding to the data signal through the potential of point Q, and drives the light emitting device to emit light.
  • FIG. 10 is a timing diagram of the GOA (Gate on Array, gate array) drive signal corresponding to the pixel circuit 1 of the present application, wherein the first scan line of the current row and the second scan line of the current row can pass through two sets of GOAs or one set of GOAs. GOA circuit generated.
  • GOA Gate on Array, gate array
  • the second scanning line of the current row When driving at low frequency, as shown in Figure 11, the second scanning line of the current row is set to the corresponding low-frequency scanning, the first scanning line of the current row still maintains high-frequency scanning, and the data signal transmitted by the data line is designed as VGMP (VGMP is the highest voltage of Gamma (gamma voltage), corresponding to the highest grayscale voltage) high-potential signal, the drain of the fourth thin film transistor T4 can be connected to the Bias signal of VGMP at a high frequency, and the fourth thin film transistor T4 can be relieved because of the low frequency The start-up voltage shifts under long-term pressure, and the resulting display quality is degraded.
  • the second scanning line corresponds to the writing of data signals during low-frequency driving, and its frequency is consistent with the data signal refresh frequency. state of stress.
  • pixel circuit 1 of the present application reduces the leakage path of point Q, and adds a thin film transistor between point B and point D as shown in Figures 1 to 8, reducing the potential of point B in the light-emitting phase
  • the impact on the potential of the Q point can minimize the leakage of the Q point.
  • this application can reduce the amount of potential change at point Q within one frame time, and can reduce the start-up voltage offset of the fourth thin film transistor T4 due to long-term stress at low frequency; The amount of change in brightness of the light-emitting device, thereby reducing the flicker when driving at low frequency, and improving the display quality when driving at low frequency.
  • Applying the pixel circuit 1 of the present application to a display panel provides a display panel, including a light emitting layer and a driving layer.
  • the driving layer is used to drive the light emitting layer to emit light.
  • the driving layer is provided with the pixel circuit 1 as described above.
  • the luminous stability of the display panel of the present application ( ⁇ L' in Figure 12) is significantly improved compared with that of the traditional display panel ( ⁇ L in Figure 12).
  • the pixel circuit 1 of this embodiment is the same as that described in the foregoing embodiments of the pixel circuit 1 of the present application, and will not be repeated here.

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Abstract

一种像素电路（1）以及显示面板。像素电路（1）中的驱动电路（11）的第一端分别连接第一发光控制电路（12）的第一端和数据写入电路（14）的第一端，第二端连接第一薄膜晶体管（T1）的源极，第三端分别连接第一薄膜晶体管（T1）的漏极和存储电路（16）的第一端，使得驱动电路（11）直接连接的薄膜晶体管数量减少，减少驱动电路（11）的漏电流途径。

Description

像素电路以及显示面板 技术领域
本申请涉及显示驱动技术领域，特别是涉及像素电路以及显示面板。
 背景技术
随着显示面板技术的不断发展，出现了许多不同类型的显示面板，其中，AMOLED（Active-matrix organic light-emitting diode，主动矩阵有机发光二极体）面板也越来越约受到人们关注。为了驱动AMOLED面板，目前主流采用LTPS TFT（Low Temperature Poly-Silicon Thin Film Transistor，低温多晶硅薄膜晶体管）驱动技术。
 技术问题
由于LTPS TFT的漏电流较大，导致一帧时间内LTPS TFT驱动电路中的驱动TFT的栅极电位不稳定，驱动TFT对应产生的输出电流也会随着发生变化，最终引起一帧时间内的画面亮度闪烁。
 技术解决方案
一方面，本申请实施例提供了一种像素电路，包括驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、复位电路、存储电路、第一薄膜晶体管以及第二薄膜晶体管；
驱动电路的第一端分别连接第一发光控制电路的第一端和数据写入电路的第一端，第二端分别连接第一薄膜晶体管的源极、第二薄膜晶体管的漏极和第二发光控制电路的第一端，第三端分别连接第一薄膜晶体管的漏极和存储电路的第一端；
第一发光控制电路的第二端分别连接存储电路的第二端和电压源，第三端接入发光信号；第二发光控制电路的第二端接入发光信号，第三端连接复位电路的一端且用于连接发光器件；
数据写入电路的第二端连接当前行第一扫描线，第三端连接数据线；复位电路的第二端连接当前行第一扫描线，第三端接入第一初始电压信号；
第一薄膜晶体管的栅极连接当前行第二扫描线；第二薄膜晶体管的栅极连接上一行第一扫描线，源极接入第二初始电压信号。
另一方面，本申请实施例提供了一种显示面板，包括发光层和驱动层；驱动层用于驱动发光层发光；驱动层设置有像素电路；
像素电路包括驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、复位电路、存储电路、第一薄膜晶体管以及第二薄膜晶体管；
驱动电路的第一端分别连接第一发光控制电路的第一端和数据写入电路的第一端，第二端分别连接第一薄膜晶体管的源极、第二薄膜晶体管的漏极和第二发光控制电路的第一端，第三端分别连接第一薄膜晶体管的漏极和存储电路的第一端；
第一发光控制电路的第二端分别连接存储电路的第二端和电压源，第三端接入发光信号；第二发光控制电路的第二端接入发光信号，第三端连接复位电路的一端且用于连接发光器件；
数据写入电路的第二端连接当前行第一扫描线，第三端连接数据线；复位电路的第二端连接当前行第一扫描线，第三端接入第一初始电压信号；
第一薄膜晶体管的栅极连接当前行第二扫描线；第二薄膜晶体管的栅极连接上一行第一扫描线，源极接入第二初始电压信号。
 有益效果
本申请像素电路包括驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、复位电路、存储电路、第一薄膜晶体管以及第二薄膜晶体管，其中，第一薄膜晶体管的漏极直接连接驱动电路，第二薄膜晶体管的漏极间隔第一薄膜晶体管间接连接驱动电路，使得驱动电路直接连接的薄膜晶体管数量减少，减少驱动电路的漏电流途径，从而使得驱动电路在发光阶段输出的电流更加稳定，解决画面亮度闪烁的问题。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施提供的像素电路的一种结构示意图。
图2为本申请实施提供的像素电路的另一种结构示意图。
图3为本申请实施提供的像素电路的第一种电路图。
图4为本申请实施提供的像素电路的第二种电路图。
图5为本申请实施提供的像素电路的第三种电路图。
图6为本申请实施提供的像素电路的第四种电路图。
图7为本申请实施提供的像素电路的第五种电路图。
图8为本申请实施提供的像素电路的第六种电路图。
图9为本申请实施提供的像素电路对应显示扫描的驱动信号时序图。
图10为本申请实施提供的像素电路对应GOA驱动信号时序图。
图11为本申请实施提供的像素电路对应面板驱动时序示意图(以60Hz为例 )。
图12为本申请实施提供的像素电路的亮度测量效果示意图。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件并与之结合为一体，或者可能同时存在居中元件。本文所使用的术语“安装”、“一端”、“另一端”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了解决传统技术中AMOLED面板存在画面亮度闪烁的技术问题，本申请实施例提供了一种像素电路1。如图1所示，本申请像素电路1包括驱动电路11、第一发光控制电路12、第二发光控制电路13、数据写入电路14、复位电路15、存储电路16、第一薄膜晶体管T1和第二薄膜晶体管T2。
驱动电路11用于根据数据电压信号（由数据写入电路14将数据线传输的数据电压信号写入驱动电路11中）驱动发光器件发光。在本申请像素电路1中，驱动电路11的第一端分别连接第一发光控制电路12的第一端和数据写入电路14的第一端。驱动电路11的第二端分别连接第一薄膜晶体管T1的源极、第二薄膜晶体管T2的漏极和第二发光控制电路13的第一端。驱动电路11的第三端分别连接第一薄膜晶体管T1的漏极和存储电路16的第一端。
第一发光控制电路12和第二发光控制电路13用于在本申请像素电路1的发光阶段控制存储电路16耦合数据电压至驱动电路11，使驱动电路11根据数据信号形成驱动电流，驱动发光器件发光。在本申请像素电路1中，第一发光控制电路12的第一端连接驱动电路11的第一端。第一发光控制电路12的第二端分别连接存储电路16的第二端和电压源（为图1中的VDD）。第一发光控制电路12的第三端接入发光（Emitting，EM）信号（为图1中的EM（n））。第二发光控制电路13的第一端连接驱动电路11的第二端。第二发光控制电路13的第二端接入发光信号。第二发光控制电路13的第三端连接复位电路15的一端且用于连接发光器件。
数据写入电路14用于连接数据线接收数据线传输的数据电压信号，并将数据电压信号写入驱动电路11中。在本申请像素电路1中，数据写入电路14的第一端连接驱动电路11的第一端。数据写入电路14的第二端连接当前行第一扫描线（为图1中的A_Scan(n)），需要说明的是，第一扫描线用于传输高频扫描信号。数据写入电路14的第三端连接数据线（为图1中的Data）。
复位电路15用于对发光器件的电位进行复位。在本申请像素电路1中，在一个示例中，如图3至6所示，复位电路15的第一端连接第二发光控制电路13的第三端。复位电路15的第二端连接当前行第一扫描线。复位电路15的第三端接入第一初始电压信号（为图1中的Vi_1）。本示例中，复位电路15和第二薄膜晶体管T2分别接入第一初始电压信号和第二初始电压信号（为图1中的Vi_2）。在另一个示例中，如图7和8所示，复位电路15的第三端连接第二薄膜晶体管T2的源极；第一初始电压信号和第二初始电压信号为同一信号。本示例中，复位电路15和第二薄膜晶体管T2共用一个初始电压信号。
第一薄膜晶体管T1和第二薄膜晶体管T2用于对驱动电路11进行复位（具体的，对如图1-8所示的Q点电位进行复位）。在本申请像素电路1中，第一薄膜晶体管T1的源极连接驱动电路11的第二端。第一薄膜晶体管T1的漏极连接驱动电路11的第三端。第一薄膜晶体管T1的栅极连接当前行第二扫描线（为图1中的B_Scan(n)），需要说明的是，第二扫描线用于传输低频扫描信号。第二薄膜晶体管T2的漏极连接驱动电路11的第二端。第二薄膜晶体管T2的栅极连接上一行第一扫描线（为图1中的A_Scan(n-1)）。第二薄膜晶体管T2的源极接入第二初始电压信号。通过本申请提供的第一薄膜晶体管T1和第二薄膜晶体管T2与驱动电路11的连接方式，减少驱动电路11的Q点连接的薄膜晶体管的数量，从而实现减少驱动电路11的Q点的漏电流，避免面板一帧时间内的画面亮度闪烁。
为了减少在发光阶段中如图1-8所示的B点电位对Q点电位的影响，如图2所示，本申请像素电路1还包括阻断电路17。具体的，阻断电路17的第一端分别连接驱动电路11的第二端和第二发光控制电路13的第一端，阻断电路17的第二端分别连接第一薄膜晶体管T1的源极和第二薄膜晶体管T2的漏极，阻断电路17的第三端连接当前行第一扫描线。阻断电路17可避免B点电位对Q点电位的影响，从而避免面板一帧时间内的画面亮度闪烁。
驱动电路11、第一发光控制电路12、第二发光控制电路13、数据写入电路14、复位电路15和存储电路16可根据实际需求设定不同的电路。
在一个示例中，如图3-8所示，阻断电路17包括第三薄膜晶体管T3。第三薄膜晶体管T3的源极分别连接驱动电路11的第二端和第二发光控制电路13的第一端，第三薄膜晶体管T3的漏极分别连接第一薄膜晶体管T1的源极和第二薄膜晶体管T2的漏极，第三薄膜晶体管T3的栅极连接当前行第一扫描线。
驱动电路11包括第四薄膜晶体管T4。第四薄膜晶体管T4的源极分别连接第一发光控制电路12的第一端和数据写入电路14的第一端，第四薄膜晶体管T4的漏极分别连接第一薄膜晶体管T1的源极、第二薄膜晶体管T2的漏极和第二发光控制电路13的第一端，第四薄膜晶体管T4的栅极分别连接第一薄膜晶体管T1的漏极和存储电路16的第一端。
第一发光控制电路12包括第五薄膜晶体管T5。第五薄膜晶体管T5的源极分别连接存储电路16的第二端和电压源，第五薄膜晶体管T5的漏极连接第四薄膜晶体管T4的源极，第五薄膜晶体管T5的栅极接入发光信号。
第二发光控制电路13包括第六薄膜晶体管T6。第六薄膜晶体管T6的源极分别连接第一薄膜晶体管T1的源极、第二薄膜晶体管T2的漏极和第四薄膜晶体管T4的漏极，第六薄膜晶体管T6的栅极接入发光信号，第六薄膜晶体管T6的漏极连接复位电路15的一端且用于连接发光器件。
数据写入电路14包括第七薄膜晶体管T7；第七薄膜晶体管T7的漏极分别连接第四薄膜晶体管T4的源极和第五薄膜晶体管T5的漏极，第七薄膜晶体管T7的栅极连接当前行第一扫描线，第七薄膜晶体管T7的源极连接数据线。
复位电路15包括第八薄膜晶体管T8。第八薄膜晶体管T8的漏极分别连接第六薄膜晶体管T6漏极，第八薄膜晶体管T8的栅极连接当前行第一扫描线，第八薄膜晶体管T8的源极接入第一初始电压信号。
存储电路16包括电容Cst。电容Cst的第一端连接第四薄膜晶体管T4的栅极，电容Cst的第二端连接第五薄膜晶体管T5的源极。
第一薄膜晶体管T1的类型可根据实际需求而选定，第一薄膜晶体管T1为单栅极薄膜晶体管或者双栅极薄膜晶体管。第一薄膜晶体管T1的类型可根据实际需求而选定，第二薄膜晶体管T2为单栅极薄膜晶体管或者双栅极薄膜晶体管。以下可以组合出四种方案：一、第一薄膜晶体管T1为单栅极薄膜晶体管，第二薄膜晶体管T2为单栅极薄膜晶体管；二、第一薄膜晶体管T1为双栅极薄膜晶体管，第二薄膜晶体管T2为单栅极薄膜晶体管；三、第一薄膜晶体管T1为单栅极薄膜晶体管，第二薄膜晶体管T2为双栅极薄膜晶体管；四、第一薄膜晶体管T1为双栅极薄膜晶体管，第二薄膜晶体管T2为双栅极薄膜晶体管。需要说明的是，双栅极薄膜晶体管的避免漏电流的效果好于单栅极薄膜晶体管。
为了便于理解本申请像素电路1的工作原理，以下以一示例进行说明。
本申请像素电路1，包括驱动电路11、第一发光控制电路12、第二发光控制电路13、数据写入电路14、复位电路15、存储电路16、第一薄膜晶体管T1以及第二薄膜晶体管T2。
其中，第一薄膜晶体管T1为双栅极薄膜晶体管，第二薄膜晶体管T2为双栅极薄膜晶体管，阻断电路17包括第三薄膜晶体管T3，驱动电路11包括第四薄膜晶体管T4，第一发光控制电路12包括第五薄膜晶体管T5，第二发光控制电路13包括第六薄膜晶体管T6，数据写入电路14包括第七薄膜晶体管T7，复位电路15包括第八薄膜晶体管T8，存储电路16包括电容Cst。
第一薄膜晶体管T1的源极分别连接第二薄膜晶体管T2的漏极和第三薄膜晶体管T3的漏极，第一薄膜晶体管T1的漏极分别连接第四薄膜晶体管T4的栅极和电容Cst的一端，第一薄膜晶体管T1的栅极连接当前行第二扫描线。
第二薄膜晶体管T2的漏极分别连接第一薄膜晶体管T1的源极和第三薄膜晶体管T3的漏极，第二薄膜晶体管T2的栅极连接上一行第一扫描线，第二薄膜晶体管T2的源极接入第二初始电压信号。
第三薄膜晶体管T3的漏极分别连接第一薄膜晶体管T1的源极和第二薄膜晶体管T2的漏极，第三薄膜晶体管T3的源极分别连接第四薄膜晶体管T4的漏极和第六薄膜晶体管T6的源极，第三薄膜晶体管T3的栅极连接当前行第一扫描线。
第四薄膜晶体管T4的栅极分别连接第一薄膜晶体管T1的漏极和电容Cst的一端，第四薄膜晶体管T4的源极分别连接第五薄膜晶体管T5的漏极和第七薄膜晶体管T7的漏极，第四薄膜晶体管T4的漏极分别连接第三薄膜晶体管T3的源极和第六薄膜晶体管T6的源极。
第五薄膜晶体管T5的漏极分别连接第四薄膜晶体管T4的源极和第七薄膜晶体管T7的漏极，第五薄膜晶体管T5的源极分别连接电容Cst的另一端，第五薄膜晶体管T5的栅极接入发光信号。
第六薄膜晶体管T6的源极分别连接第三薄膜晶体管T3的源极和第四薄膜晶体管T4的漏极，第六薄膜晶体管T6的漏极分别连接第八薄膜晶体管T8的漏极和发光器件，第六薄膜晶体管T6的栅极接入发光信号。
第七薄膜晶体管T7的漏极分别连接第四薄膜晶体管T4的源极和第五薄膜晶体管T5的漏极，第七薄膜晶体管T7的源极连接数据线，第七薄膜晶体管T7的栅极连接当前行第一扫描线。
第八薄膜晶体管T8的漏极分别连接第六薄膜晶体管T6的漏极和发光器件，第八薄膜晶体管T8的源极接入第一初始电压信号，第八薄膜晶体管T8的栅极连接当前行第一扫描线。
需要说明的是，为图9所示为本示例像素电路1对应显示扫描的驱动信号时序图，像素电路1的工作主要分成了三个阶段：
第一阶段（复位重置Q点电位阶段），上一行第一扫描线和当前行第二扫描线传输的信号均为低电平，当前行第一扫描线传输的信号和发光信号均为高电平，第一薄膜晶体管T1、第二薄膜晶体管T2均同时打开，第三薄膜晶体管T3、第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7和第八薄膜晶体管T8关闭，第四薄膜晶体管T4的栅极复位到第二初始电压信号。
第二阶段（充电以及复位发光器件的阳极阶段），发光信号仍均为高电平，第五薄膜晶体管T5和第六薄膜晶体管T6关闭。当前行第一扫描线和当前行第二扫描线传输的信号均为低电平，第一薄膜晶体管T1、第七薄膜晶体管T7同时打开，数据线传输的数据信号通过第一薄膜晶体管T1和第七薄膜晶体管T7写入至Q点，并反向抓取第四薄膜晶体管T4的启动电压（Vth）。第八薄膜晶体管T8打开，将发光器件的阳极复位至第一初始电压信号。
第三阶段（发光阶段），当前行第一扫描线和当前行第二扫描线传输的信号均为高电平，发光信号均为低电位，第五薄膜晶体管T5和第六薄膜晶体管T6开启，第四薄膜晶体管T4通过Q点电位产生与数据信号相对应的电流，并驱动发光器件发光。
为图10所示为本申请像素电路1对应的GOA（Gate on Array，栅阵列）驱动信号时序图，其中，当前行第一扫描线和当前行第二扫描线可以通过两组GOA或者一组GOA电路产生。在低频驱动时，如图11所示，当前行第二扫描线设置为对应的低频扫描，当前行第一扫描线仍维持高频率扫描，数据线传输的数据信号在空白区间设计为VGMP（VGMP为Gamma（伽马电压）的最高电压，对应最高灰阶电压）高电位信号，可将第四薄膜晶体管T4的漏极按高频率接入VGMP的Bias信号，减轻第四薄膜晶体管T4因为在低频下长时间压力的状态下的启动电压偏移，而因此带来的显示品质下降。其中，第二扫描线对应低频驱动时的数据信号写入，其频率与数据信号刷新频率一致，第一扫描线用来复位，避免原来设计中第一薄膜晶体管T1在低频驱动时会受到长时间压力的状态。
本申请像素电路1与传统像素电路相比，减少了Q点的漏电途径，并增加B点与如图1至8所示的D点之间增加薄膜晶体管，减小了在发光阶段B点电位对Q点电位的影响，从而可以尽量减少Q点的漏电。另外，本申请可使得一帧时间内Q点电位变化量减小，并可减轻第四薄膜晶体管T4因为在低频下长时间压力的状态下的启动电压偏移；从而降低低频驱动时一帧内的发光器件亮度的变化量，从而减小低频驱动时的闪烁，提升低频驱动时的显示品质。
将本申请像素电路1应用到显示面板上，提供了一种显示面板，包括发光层和驱动层。驱动层用于驱动发光层发光。驱动层设置有如上述的像素电路1。
如图12所示，本申请显示面板的发光稳定性（如图12中的△L’）相比于传统显示面板的发光稳定性（如图12中的△L）有明显地提升。需要说明的是，本实施例的像素电路1与前述本申请像素电路1各实施例所述的相同，此处不再赘述。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种像素电路，其特征在于，包括驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、复位电路、存储电路、第一薄膜晶体管以及第二薄膜晶体管；
    所述驱动电路的第一端分别连接所述第一发光控制电路的第一端和所述数据写入电路的第一端，第二端分别连接所述第一薄膜晶体管的源极、所述第二薄膜晶体管的漏极和所述第二发光控制电路的第一端，第三端分别连接所述第一薄膜晶体管的漏极和所述存储电路的第一端；
    所述第一发光控制电路的第二端分别连接所述存储电路的第二端和电压源，第三端接入发光信号；所述第二发光控制电路的第二端接入发光信号，第三端连接所述复位电路的第一端且用于连接发光器件；
    所述数据写入电路的第二端连接当前行第一扫描线，第三端连接数据线；所述复位电路的第二端连接所述当前行第一扫描线，第三端接入第一初始电压信号；
    所述第一薄膜晶体管的栅极连接当前行第二扫描线；所述第二薄膜晶体管的栅极连接上一行第一扫描线，源极接入第二初始电压信号。
  2. 根据权利要求1所述的像素电路，其特征在于，还包括阻断电路；
    所述阻断电路的第一端分别连接所述驱动电路的第二端和所述第二发光控制电路的第一端，第二端分别连接所述第一薄膜晶体管的源极和所述第二薄膜晶体管的漏极，第三端连接所述当前行第一扫描线。
  3. 根据权利要求2所述的像素电路，其特征在于，所述阻断电路包括第三薄膜晶体管；
    所述第三薄膜晶体管的源极分别连接所述驱动电路的第二端和所述第二发光控制电路的第一端，漏极分别连接所述第一薄膜晶体管的源极和所述第二薄膜晶体管的漏极，栅极连接所述当前行第一扫描线。
  4. 根据权利要求1所述的像素电路，其特征在于，所述第一薄膜晶体管为单栅极薄膜晶体管或者双栅极薄膜晶体管；所述第二薄膜晶体管为单栅极薄膜晶体管或者双栅极薄膜晶体管。
  5. 根据权利要求1所述的像素电路，其特征在于，所述复位电路的第三端连接所述第二薄膜晶体管的源极；所述第一初始电压信号和所述第二初始电压信号为同一信号。
  6. 根据权利要求1所述的像素电路，其特征在于，所述驱动电路包括第四薄膜晶体管；
    所述第四薄膜晶体管的源极分别连接所述第一发光控制电路的第一端和所述数据写入电路的第一端，漏极分别连接所述第一薄膜晶体管的源极、所述第二薄膜晶体管的漏极和所述第二发光控制电路的第一端，栅极分别连接所述第一薄膜晶体管的漏极和所述存储电路的第一端。
  7. 根据权利要求6所述的像素电路，其特征在于，所述第一发光控制电路包括第五薄膜晶体管；
    所述第五薄膜晶体管的源极分别连接所述存储电路的第二端和所述电压源，漏极连接所述第四薄膜晶体管的源极，栅极接入所述发光信号。
  8. 根据权利要求7所述的像素电路，其特征在于，所述第二发光控制电路包括第六薄膜晶体管；
    所述第六薄膜晶体管的源极分别连接所述第一薄膜晶体管的源极、所述第二薄膜晶体管的漏极和所述第四薄膜晶体管的漏极，栅极接入所述发光信号，漏极连接所述复位电路的一端且用于连接所述发光器件。
  9. 根据权利要求8所述的像素电路，其特征在于，所述数据写入电路包括第七薄膜晶体管；
    所述第七薄膜晶体管的漏极分别连接所述第四薄膜晶体管的源极和所述第五薄膜晶体管的漏极，栅极连接所述当前行第一扫描线，源极连接所述数据线。
  10. 根据权利要求9所述的像素电路，其特征在于，所述复位电路包括第八薄膜晶体管；
    所述第八薄膜晶体管的漏极分别连接所述第六薄膜晶体管漏极，栅极连接所述当前行第一扫描线，源极接入所述第一初始电压信号。
  11. 根据权利要求10所述的像素电路，其特征在于，所述存储电路包括电容；
    所述电容的第一端连接所述第四薄膜晶体管的栅极，第二端连接所述第五薄膜晶体管的源极。
  12. 一种显示面板，其特征在于，包括发光层和驱动层；所述驱动层用于驱动所述发光层发光；
    所述驱动层设置有像素电路；
    所述像素电路包括驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、复位电路、存储电路、第一薄膜晶体管以及第二薄膜晶体管；
    所述驱动电路的第一端分别连接所述第一发光控制电路的第一端和所述数据写入电路的第一端，第二端分别连接所述第一薄膜晶体管的源极、所述第二薄膜晶体管的漏极和所述第二发光控制电路的第一端，第三端分别连接所述第一薄膜晶体管的漏极和所述存储电路的第一端；
    所述第一发光控制电路的第二端分别连接所述存储电路的第二端和电压源，第三端接入发光信号；所述第二发光控制电路的第二端接入发光信号，第三端连接所述复位电路的第一端且用于连接发光器件；
    所述数据写入电路的第二端连接当前行第一扫描线，第三端连接数据线；所述复位电路的第二端连接所述当前行第一扫描线，第三端接入第一初始电压信号；
    所述第一薄膜晶体管的栅极连接当前行第二扫描线；所述第二薄膜晶体管的栅极连接上一行第一扫描线，源极接入第二初始电压信号。
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