WO2022188191A1 - 发光器件驱动电路、背光模组以及显示面板 - Google Patents

发光器件驱动电路、背光模组以及显示面板 Download PDF

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Publication number
WO2022188191A1
WO2022188191A1 PCT/CN2021/080789 CN2021080789W WO2022188191A1 WO 2022188191 A1 WO2022188191 A1 WO 2022188191A1 CN 2021080789 W CN2021080789 W CN 2021080789W WO 2022188191 A1 WO2022188191 A1 WO 2022188191A1
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WO
WIPO (PCT)
Prior art keywords
light
signal
transistor
emitting
drain
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PCT/CN2021/080789
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English (en)
French (fr)
Inventor
刘斌
刘全胜
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/281,102 priority Critical patent/US11908403B2/en
Publication of WO2022188191A1 publication Critical patent/WO2022188191A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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    • G—PHYSICS
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    • G09G2320/04—Maintaining the quality of display appearance
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the present application relates to the field of display technology, and in particular, to a driving circuit of a light-emitting device, a backlight module and a display panel.
  • Light-emitting devices such as mini light-emitting diodes, micro-light-emitting diodes, and organic light-emitting diodes have the advantages of high brightness, high contrast, and high color gamut, and have been rapidly applied to new display fields.
  • the threshold voltage of the driving transistor is prone to shift under long-term current pressure, so that the brightness of the light-emitting device is attenuated, resulting in uneven display.
  • the driving method of time-sliced gray-scale pulse width modulation is usually combined in the pixel driving circuit, so that the light-emitting device always works at In the stable light-emitting stage of high current, the problem of uneven display will not occur, and at the same time, the threshold voltage compensation of the driving transistor can be realized.
  • the number of gray scales in the existing light-emitting device driving circuit is relatively small.
  • the present application provides a light-emitting device driving circuit, a backlight module and a display panel, which can increase the number of gray scales while solving the problem of luminance attenuation of the light-emitting device caused by the shift of the threshold voltage of the driving transistor.
  • the present application provides a light-emitting device driving circuit, including:
  • the light-emitting device is connected in series to the light-emitting circuit formed by the first power supply signal and the second power supply signal;
  • the source and drain of the driving transistor are connected in series with the light-emitting circuit, and the driving transistor is used to control the current flowing through the light-emitting circuit;
  • the data signal writing module is connected to the first scan signal and the data signal, and is electrically connected to one of the source electrode and the drain electrode of the driving transistor, the data signal writing module for writing the data signal into one of the source and the drain of the driving transistor under the control of the first scan signal;
  • the first power signal writing module is connected to the second scanning signal and the first power signal, and is electrically connected to the gate of the driving transistor, the first power signal
  • the writing module is used for writing the first power signal into the gate of the driving transistor under the control of the second scanning signal;
  • a second power signal writing module is connected to the third scanning signal and the second power signal, and is electrically connected to the gate of the driving transistor, and the second power signal
  • the writing module is used for writing the second power signal into the gate of the driving transistor under the control of the third scanning signal
  • the light-emitting control module is connected to a light-emitting control signal and is connected in series with the light-emitting circuit, and the light-emitting control module is configured to control the light-emitting circuit to be turned on or off based on the light-emitting control signal;
  • a storage module is electrically connected to the gate of the driving transistor and connected to the second power supply signal, and the storage module is used for storing the potential of the gate of the driving transistor.
  • the light-emitting device driving circuit further includes a compensation module; the compensation module is connected to the fourth scan signal and is electrically connected to the source and the drain of the driving transistor. The other and the gate of the driving transistor, the compensation module is used for compensating the threshold voltage of the driving transistor under the control of the fourth scan signal.
  • the compensation module includes a first transistor
  • the gate of the first transistor is connected to the fourth scan signal, one of the source and the drain of the first transistor is electrically connected to the gate of the driving transistor, and the first transistor is The other of the source and the drain is electrically connected to one of the source and the drain of the driving transistor.
  • the light-emitting control module includes:
  • the first lighting control unit is connected to the lighting control signal, and the first lighting control unit is connected in series with the lighting circuit, and the first lighting control unit is used for the lighting control signal Under the control of , control the light-emitting circuit to be turned on or off; and/or
  • the second light-emitting control unit, the second light-emitting control unit is connected to the light-emitting control signal, and the second light-emitting control unit is serially connected to the light-emitting circuit, and the second light-emitting control unit is used for the light-emitting control signal.
  • the light-emitting circuit is controlled to be turned on or off.
  • the light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit, the first light-emitting control unit includes a second transistor; the second light-emitting control unit includes a first light-emitting control unit three transistors;
  • the gate of the second transistor and the gate of the third transistor are both connected to the light-emitting control signal, and one of the source and the drain of the second transistor is electrically connected to one end of the light-emitting device connected, the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the driving transistor;
  • One of the source and drain of the third transistor is connected to the second power supply signal, and the other of the source and the drain of the third transistor is connected to the source and drain of the driving transistor The other of the poles is electrically connected.
  • the data signal writing module includes a fourth transistor
  • the gate of the fourth transistor is connected to the first scan signal, one of the source and the drain of the fourth transistor is connected to the data signal, and the source and the drain of the fourth transistor are connected to the data signal. the other is electrically connected to one of the source and the drain of the driving transistor;
  • the first power signal writing module includes a fifth transistor
  • the gate of the fifth transistor is connected to the second scan signal, one of the source and the drain of the fifth transistor is connected to the first power supply signal, and the source and the drain of the fifth transistor are connected to the first power supply signal.
  • the other one of the drains is electrically connected to the gate of the driving transistor;
  • the second power signal writing module includes a sixth transistor
  • the gate of the sixth transistor is connected to the third scan signal, one of the source and the drain of the sixth transistor is connected to the second power signal, and the source and the drain of the sixth transistor are connected to the second power supply signal. one of the drains is electrically connected to the gate of the drive transistor;
  • the storage module includes a storage capacitor
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is connected to the second power supply signal.
  • the light-emitting device driving circuit controls the time node at which the sixth transistor is turned on through the third scan signal, and divides the molecular fields such as the pulse width of the light-emitting device into non- Equimolecular field.
  • the driving control sequence of the light-emitting device driving circuit includes a reset phase, a compensation phase, a light-emitting phase, and a black insertion phase;
  • the first scan signal and the second scan signal are all high potentials, and the fourth scan signal, the third scan signal and the light-emitting control signal are all low potentials;
  • the first scan signal and the fourth scan signal are all high potentials, and the second scan signal, the third scan signal and the light-emitting control signal are all low potentials;
  • the light-emitting control signal is at a high level, and the first scan signal, the second scan signal, the fourth scan signal, and the third scan signal are all at a low level;
  • the light emission control signal and the third scan signal are all high potentials, and the first scan signal, the second scan signal and the fourth scan signal are all low potentials.
  • the potential of the first power supply signal is greater than the potential of the second power supply signal.
  • the present application also provides a backlight module, comprising:
  • the data line is used to provide a data signal
  • the first scan line is used to provide a first scan signal
  • the second scan line is used to provide a second scan signal
  • the third scan line is used to provide a third scan signal
  • the light-emitting control signal line is used to provide a light-emitting control signal
  • the light-emitting device driving circuit is connected to the data line, the first scan line, the second scan line, the third scan line and the light-emitting control signal line;
  • the light-emitting device driving circuit includes:
  • the light-emitting device is connected in series to the light-emitting circuit formed by the first power supply signal and the second power supply signal;
  • the source and drain of the driving transistor are connected in series with the light-emitting circuit, and the driving transistor is used to control the current flowing through the light-emitting circuit;
  • the data signal writing module is connected to the first scan signal and the data signal, and is electrically connected to one of the source electrode and the drain electrode of the driving transistor, the data signal writing module for writing the data signal into one of the source and the drain of the driving transistor under the control of the first scan signal;
  • the first power signal writing module is connected to the second scanning signal and the first power signal, and is electrically connected to the gate of the driving transistor, the first power signal
  • the writing module is used for writing the first power signal into the gate of the driving transistor under the control of the second scanning signal;
  • a second power signal writing module is connected to the third scanning signal and the second power signal, and is electrically connected to the gate of the driving transistor, and the second power signal
  • the writing module is used for writing the second power signal into the gate of the driving transistor under the control of the third scanning signal
  • the light-emitting control module is connected to a light-emitting control signal and is connected in series with the light-emitting circuit, and the light-emitting control module is configured to control the light-emitting circuit to be turned on or off based on the light-emitting control signal;
  • a storage module is electrically connected to the gate of the driving transistor and connected to the second power supply signal, and the storage module is used for storing the potential of the gate of the driving transistor.
  • the light-emitting device driving circuit further includes a compensation module; the compensation module is connected to the fourth scan signal and is electrically connected to another of the source and drain of the driving transistor. One and the gate of the driving transistor, the compensation module is used for compensating the threshold voltage of the driving transistor under the control of the fourth scan signal.
  • the compensation module includes a first transistor
  • the gate of the first transistor is connected to the fourth scan signal, one of the source and the drain of the first transistor is electrically connected to the gate of the driving transistor, and the first transistor is The other of the source and the drain is electrically connected to one of the source and the drain of the driving transistor.
  • the light-emitting control module includes:
  • the first lighting control unit is connected to the lighting control signal, and the first lighting control unit is connected in series with the lighting circuit, and the first lighting control unit is used for the lighting control signal Under the control of , control the light-emitting circuit to be turned on or off; and/or
  • the second light-emitting control unit, the second light-emitting control unit is connected to the light-emitting control signal, and the second light-emitting control unit is serially connected to the light-emitting circuit, and the second light-emitting control unit is used for the light-emitting control signal.
  • the light-emitting circuit is controlled to be turned on or off.
  • the lighting control module includes a first lighting control unit and a second lighting control unit, the first lighting control unit includes a second transistor; the second lighting control unit includes a third lighting control unit transistor;
  • the gate of the second transistor and the gate of the third transistor are both connected to the light-emitting control signal, and one of the source and the drain of the second transistor is electrically connected to one end of the light-emitting device connected, the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the driving transistor;
  • One of the source and drain of the third transistor is connected to the second power supply signal, and the other of the source and the drain of the third transistor is connected to the source and drain of the driving transistor The other of the poles is electrically connected.
  • the data signal writing module includes a fourth transistor
  • the gate of the fourth transistor is connected to the first scan signal, one of the source and the drain of the fourth transistor is connected to the data signal, and the source and the drain of the fourth transistor are connected to the data signal. the other is electrically connected to one of the source and the drain of the driving transistor;
  • the first power signal writing module includes a fifth transistor
  • the gate of the fifth transistor is connected to the second scan signal, one of the source and the drain of the fifth transistor is connected to the first power supply signal, and the source and the drain of the fifth transistor are connected to the first power supply signal.
  • the other one of the drains is electrically connected to the gate of the driving transistor;
  • the second power signal writing module includes a sixth transistor
  • the gate of the sixth transistor is connected to the third scan signal, one of the source and the drain of the sixth transistor is connected to the second power signal, and the source and the drain of the sixth transistor are connected to the second power supply signal. one of the drains is electrically connected to the gate of the drive transistor;
  • the storage module includes a storage capacitor
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is connected to the second power supply signal.
  • the present application further provides a display panel, the display panel includes a plurality of pixel units arranged in an array;
  • the light-emitting device driving circuit includes:
  • the light-emitting device is connected in series to the light-emitting circuit formed by the first power supply signal and the second power supply signal;
  • the source and drain of the driving transistor are connected in series with the light-emitting circuit, and the driving transistor is used to control the current flowing through the light-emitting circuit;
  • the data signal writing module is connected to the first scan signal and the data signal, and is electrically connected to one of the source electrode and the drain electrode of the driving transistor, the data signal writing module for writing the data signal into one of the source and the drain of the driving transistor under the control of the first scan signal;
  • the first power signal writing module is connected to the second scanning signal and the first power signal, and is electrically connected to the gate of the driving transistor, the first power signal
  • the writing module is used for writing the first power signal into the gate of the driving transistor under the control of the second scanning signal;
  • a second power signal writing module is connected to the third scanning signal and the second power signal, and is electrically connected to the gate of the driving transistor, and the second power signal
  • the writing module is used for writing the second power signal into the gate of the driving transistor under the control of the third scanning signal
  • the light-emitting control module is connected to a light-emitting control signal and is connected in series with the light-emitting circuit, and the light-emitting control module is configured to control the light-emitting circuit to be turned on or off based on the light-emitting control signal;
  • a storage module is electrically connected to the gate of the driving transistor and connected to the second power supply signal, and the storage module is used for storing the potential of the gate of the driving transistor.
  • the light-emitting device driving circuit further includes a compensation module; the compensation module is connected to the fourth scan signal and is electrically connected to the other of the source electrode and the drain electrode of the driving transistor and the gate of the driving transistor, and the compensation module is configured to compensate the threshold voltage of the driving transistor under the control of the fourth scan signal.
  • the light-emitting control module includes:
  • the first lighting control unit is connected to the lighting control signal, and the first lighting control unit is connected in series with the lighting circuit, and the first lighting control unit is used for the lighting control signal Under the control of , control the light-emitting circuit to be turned on or off; and/or
  • the second light-emitting control unit, the second light-emitting control unit is connected to the light-emitting control signal, and the second light-emitting control unit is serially connected to the light-emitting circuit, and the second light-emitting control unit is used for the light-emitting control signal.
  • the light-emitting circuit is controlled to be turned on or off.
  • the lighting control module includes a first lighting control unit and a second lighting control unit, the first lighting control unit includes a second transistor; the second lighting control unit includes a third transistor ;
  • the gate of the second transistor and the gate of the third transistor are both connected to the light-emitting control signal, and one of the source and the drain of the second transistor is electrically connected to one end of the light-emitting device connected, the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the driving transistor;
  • One of the source and drain of the third transistor is connected to the second power supply signal, and the other of the source and the drain of the third transistor is connected to the source and drain of the driving transistor The other of the poles is electrically connected.
  • the data signal writing module includes a fourth transistor
  • the gate of the fourth transistor is connected to the first scan signal, one of the source and the drain of the fourth transistor is connected to the data signal, and the source and the drain of the fourth transistor are connected to the data signal. the other is electrically connected to one of the source and the drain of the driving transistor;
  • the first power signal writing module includes a fifth transistor
  • the gate of the fifth transistor is connected to the second scan signal, one of the source and the drain of the fifth transistor is connected to the first power supply signal, and the source and the drain of the fifth transistor are connected to the first power supply signal.
  • the other one of the drains is electrically connected to the gate of the driving transistor;
  • the second power signal writing module includes a sixth transistor
  • the gate of the sixth transistor is connected to the third scan signal, one of the source and the drain of the sixth transistor is connected to the second power signal, and the source and the drain of the sixth transistor are connected to the second power supply signal. one of the drains is electrically connected to the gate of the drive transistor;
  • the storage module includes a storage capacitor
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is connected to the second power supply signal.
  • the backlight module and the display panel provided by the present application, by setting the second power signal writing module to insert black on the light-emitting device, and adjusting the molecular fields such as the pulse width of the light-emitting device to emit light, the molecular fields can be unequal molecular fields, thereby realizing Various grayscale variations.
  • FIG. 1 is a schematic structural diagram of a light-emitting device driving circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic circuit diagram of a light-emitting device driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a timing diagram of a light-emitting device driving circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the reset stage under the driving sequence shown in FIG. 3 .
  • FIG. 5 is a schematic path diagram of the compensation stage of the light-emitting device driving circuit according to the embodiment of the present application under the driving sequence shown in FIG. 3 .
  • FIG. 6 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the light-emitting stage under the driving sequence shown in FIG. 3 .
  • FIG. 7 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the light-emitting stage under the driving sequence shown in FIG. 3 .
  • FIG. 8 is a schematic diagram of sub-field distribution of a conventionally provided light-emitting device driving circuit.
  • FIG. 9 is a schematic diagram of sub-field distribution of the light-emitting device driving circuit provided by the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a backlight module provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a light-emitting device driving circuit provided by an embodiment of the present application.
  • the light-emitting device driving circuit 10 provided by the embodiment of the present application includes a light-emitting device D, a driving transistor T1 , a data signal writing module 101 , a first power signal writing module 102 , and a second power signal writing module 104 , a lighting control module 105 and a storage module 106 .
  • the light-emitting device D may be a mini light-emitting diode, a micro-light-emitting diode or an organic light-emitting diode.
  • the light-emitting device D is serially connected to the light-emitting circuit formed by the first power supply signal VDD and the second power supply signal VSS.
  • the source and drain of the driving transistor T1 are connected in series with the light-emitting circuit.
  • the data signal writing module 101 is connected to the first scan signal S1 and the data signal DA, and is electrically connected to one of the source electrode and the drain electrode of the driving transistor T1.
  • the first power signal writing module 102 is connected to the second scan signal S2 and the first power signal VDD, and is electrically connected to the gate of the driving transistor T1.
  • the second power signal writing module 104 receives the third scan signal S4 and the second power signal VSS, and is electrically connected to the gate of the driving transistor T1.
  • the light-emitting control module 105 is connected to the light-emitting control signal EM, and is connected to the light-emitting circuit in series.
  • the storage module 106 is electrically connected to the gate of the driving transistor T1 and connected to the second power supply signal VSS.
  • the light-emitting control module 105 and the light-emitting device D are connected in series to the light-emitting circuit.
  • the light-emitting device driving circuit 10 shown in FIG. a specific location. That is, the light-emitting control module 105 and the light-emitting device D can be connected in series at any position on the light-emitting circuit.
  • the light-emitting device driving circuit 10 provided in the embodiment of the present application further includes a compensation module 103 .
  • the compensation module 103 is connected to the fourth scan signal S3 and is electrically connected to the other of the source and the drain of the driving transistor T1 and the gate of the driving transistor T1.
  • the driving transistor T1 is used to control the current flowing through the light-emitting circuit.
  • the data signal writing module 101 is configured to write the data signal DA into one of the source and the drain of the driving transistor T1 under the control of the first scan signal S1.
  • the first power signal writing module 102 is configured to write the first power signal VDD to the gate of the driving transistor T1 under the control of the second scanning signal S2.
  • the compensation module 103 is configured to compensate the threshold voltage of the driving transistor T1 under the control of the fourth scan signal S3.
  • the second power signal writing module 104 is configured to write the second power signal VSS to the gate of the driving transistor T1 under the control of the third scanning signal S4.
  • the lighting control module 105 is configured to control the lighting circuit to be turned on or off based on the lighting control signal EM.
  • the storage module 106 is used to store the potential of the gate of the driving transistor T1.
  • the molecular fields are unequal molecular fields, so that multiple fields can be realized.
  • the data signal writing module 101 includes a fourth transistor T2 .
  • the gate of the fourth transistor T2 is connected to the first scan signal S1.
  • One of the source and drain of the fourth transistor T2 is connected to the data signal DA.
  • the other of the source and the drain of the fourth transistor T2 is electrically connected to one of the source and the drain of the driving transistor T1.
  • the data signal writing module 101 can also be formed by using a plurality of transistors in series.
  • the lighting control module 105 includes a first lighting control unit 1051 and a second lighting control unit 1052 .
  • the first light-emitting control unit 1051 is electrically connected to one end of the light-emitting device D and the source of the driving transistor T1, and is connected to the light-emitting control signal EM.
  • the second light emission control unit 1052 is electrically connected to the drain of the driving transistor T1, and is connected to the light emission control signal EM and the second power supply signal VSS.
  • the first light-emitting control unit 1051 and the second light-emitting control unit 1052 are both configured to control the light-emitting circuit to be turned on or off under the control of the light-emitting control signal EM.
  • the lighting control module 105 only needs to be provided with the first lighting control unit 1051 or the second lighting control unit 1052 .
  • the light control module 105 may further include three or more lighting control units.
  • the first lighting control unit 1051 includes a second transistor T3.
  • the second light emission control unit 1052 includes a third transistor T4.
  • the gate of the second transistor T3 and the gate of the third transistor T4 are both connected to the light-emitting control signal EM.
  • One of the source electrode and the drain electrode of the second transistor T3 is electrically connected to one end of the light emitting device D.
  • the other of the source and the drain of the second transistor T3 is electrically connected to one of the source and the drain of the driving transistor T1.
  • One of the source and the drain of the third transistor T4 is connected to the second power supply signal VSS.
  • the other of the source and the drain of the third transistor T4 is electrically connected to the other of the source and the drain of the driving transistor T1.
  • the first light-emitting control unit 1051 may also be formed by using multiple transistors in series; the second light-emitting control unit 1052 may also be formed by using multiple transistors in series.
  • the compensation module 103 includes a first transistor T5 .
  • the gate of the first transistor T5 is connected to the fourth scan signal S3.
  • One of the source and drain of the first transistor T5 is electrically connected to the gate of the driving transistor T1.
  • the other of the source and the drain of the first transistor T5 is electrically connected to one of the source and the drain of the driving transistor T1.
  • the compensation module 103 can also be formed by using a plurality of transistors in series.
  • the first power signal writing module 102 includes a fifth transistor T6 .
  • the gate of the fifth transistor T6 is connected to the second scan signal S2.
  • One of the source and drain of the fifth transistor T6 is connected to the first power supply signal VDD.
  • the other of the source and the drain of the fifth transistor T6 is electrically connected to the gate of the driving transistor T1.
  • the first power signal writing module 102 can also be formed by using a plurality of transistors in series.
  • the second power signal writing module 104 includes a sixth transistor T7 .
  • the gate of the sixth transistor T7 is connected to the third scan signal S4.
  • One of the source and the drain of the sixth transistor T7 is connected to the second power supply signal VSS.
  • the other of the source and drain of the sixth transistor T7 is electrically connected to the gate of the driving transistor T1.
  • the second power signal writing module 104 can also be formed by using a plurality of transistors in series.
  • the light-emitting device driving circuit 10 controls the time node when the sixth transistor T7 is turned on, and adjusts the molecular fields such as the pulse width of the light-emitting device D to be an unequal molecular field, so that various grayscales can be realized. order changes to achieve an increase in the number of bits.
  • the storage module 106 includes a storage capacitor C1 .
  • One end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T1.
  • the other end of the storage capacitor C1 is connected to the second power supply signal VSS.
  • the light-emitting device driving circuit 10 uses a light-emitting device driving circuit with a 7T1C (7 transistors and 1 capacitor) structure to control the light-emitting device D, uses fewer components, has a simple and stable structure, and saves costs .
  • both the first power supply signal VDD and the second power supply signal VSS are used to output a predetermined voltage value.
  • the potential of the first power supply signal VDD is greater than the potential of the second power supply signal VSS.
  • the potential of the second power supply signal VSS may be the potential of the ground terminal.
  • the potential of the second power supply signal VSS can also be other.
  • the driving transistor T1, the fourth transistor T2, the second transistor T3, the third transistor T4, the first transistor T5, the fifth transistor T6 and the sixth transistor T7 may be low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors One or more of transistors or amorphous silicon thin film transistors.
  • the transistors in the light-emitting device driving circuit 10 provided by the embodiments of the present application can be set to be the same type of transistors, so as to avoid the influence on the light-emitting device driving circuit 10 caused by differences between different types of transistors.
  • FIG. 3 is a timing diagram of a light-emitting device driving circuit according to an embodiment of the present application.
  • the combination of the light emission control signal EM, the first scan signal S1, the second scan signal S2, the fourth scan signal S3 and the third scan signal S4 corresponds to the reset phase t1, the compensation phase t2, the light emission phase t3 and the black insertion phase t4. That is, within one frame time, the driving control sequence of the light-emitting device driving circuit 10 provided by the embodiment of the present application includes a reset phase t1, a compensation phase t2, a light-emitting phase t3, and a black insertion phase t4.
  • the first scan signal S1 and the second scan signal S2 are both high potentials
  • the fourth scan signal S3, the third scan signal S4 and the emission control signal EM are all low potentials.
  • the potential of the data signal DA is a low potential.
  • the first scan signal S1 and the fourth scan signal S3 are all high level, and the second scan signal S2, the third scan signal S4 and the light emission control signal EM are all low level.
  • the potential of the data signal DA is a high potential.
  • the light-emitting control signal EM is at a high level, and the first scan signal S1, the second scan signal S2, the fourth scan signal S3 and the third scan signal S4 are all at a low level.
  • the potential of the data signal DA is a high potential.
  • the light emission control signal EM and the third scan signal S4 are all high potentials, and the first scan signal S1, the second scan signal S2 and the fourth scan signal S3 are all low potentials.
  • the potential of the data signal DA is a high potential.
  • the pulse width of the third scan signal S4 can be set as required, and the light-emitting device driving circuit provided by the embodiment of the present application can control the time when the sixth transistor T7 is turned on by setting the pulse width of the third scan signal S4 node, and adjust the molecular field such as the pulse width of the light-emitting device D to be an unequal molecular field, and then various gray scale changes can be realized.
  • FIG. 4 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the reset stage under the driving sequence shown in FIG. 3 .
  • the first scan signal S1 is at a high level
  • the fourth transistor T2 is turned on under the control of the high level of the first scan signal S1
  • the data signal DA is written into one of the source and drain of the driving transistor T1.
  • the potential of the data signal DA is at a low potential
  • the low potential of the data signal DA is written into one of the source and drain of the driving transistor T1 through the fourth transistor T2, so as to realize the control of the source and drain of the driving transistor T1.
  • the second scan signal S2 is at a high level
  • the fifth transistor T6 is turned on under the control of the high level of the second scan signal S2, and the first power signal VDD is written into the gate of the driving transistor T1.
  • the potential of the first power supply signal VDD is written into the gate of the driving transistor T1 through the fifth transistor T6, so as to initialize the gate of the driving transistor T1.
  • the driving transistor T1 is turned on.
  • the second transistor T3, the third transistor T4, the first transistor T5 and the sixth transistor are T7 are all closed.
  • FIG. 5 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the compensation stage under the driving sequence shown in FIG. 3 .
  • the first scan signal S1 is at a high level
  • the fourth transistor T2 is turned on under the control of the high level of the first scan signal S1
  • the data signal DA is written into one of the source and drain of the driving transistor T1.
  • the potential of the data signal DA is a high potential
  • the high potential of the data signal DA is written into one of the source and drain of the driving transistor T1 through the fourth transistor T2, and the source and drain of the driving transistor T1
  • the potential of one is changed from the low potential of the data signal DA to the high potential of the data signal DA.
  • the fourth scan signal S3 is at a high level
  • the first transistor T5 is turned on under the control of the high level of the fourth scan signal S3.
  • the first transistor T5 connects one of the source and the drain of the driving transistor T1 and the gate of the driving transistor T1, and one of the source and the drain of the driving transistor T1 and the gate of the driving transistor T1 are formed
  • the diode structure makes the potential of the gate of the driving transistor T1 drop from the potential of the first power supply signal VDD to the sum of the high potential of the data signal DA and the threshold voltage of the driving transistor T1.
  • the potential of the gate of the driving transistor T1 is maintained at the sum of the high potential of the data signal DA and the threshold voltage of the driving transistor T1. At this time, the driving transistor T1 is still turned on.
  • the second transistor T3, the third transistor T4, the fifth transistor T6 and the sixth transistor are T7 are all closed.
  • FIG. 6 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the light-emitting stage under the driving timing shown in FIG. 3 .
  • the light-emitting control signal EM is at a high potential
  • the second transistor T3 is turned on under the high-potential control of the light-emitting control signal EM
  • the third transistor T4 is turned on under the high-potential control of the light-emitting control signal EM.
  • the potential of the gate of the driving transistor T1 is the sum VDATA+Vth of the high potential of the data signal DA and the threshold voltage of the driving transistor T1
  • the potential of one of the source and drain of the driving transistor T1 is V0.
  • IOLED 1/2Cox( ⁇ 1W1/L1)(Vgs-Vth))2, where IOLED is the current flowing through the light-emitting device D, ⁇ 1 is the carrier mobility of the driving transistor T1, W1 and L1 are the first transistor T1 respectively The width and length of the channel, Vgs is the voltage difference between the gate of the driving transistor T1 and one of the source and drain, and Vth is the threshold voltage of the driving transistor T1.
  • the driving transistor T1 is still turned on, the light-emitting device D emits light, and the current flowing through the light-emitting device D has nothing to do with the threshold voltage of the driving transistor T1, thereby realizing the compensation effect of the threshold voltage.
  • the fourth transistor T2 since the first scan signal S1, the second scan signal S2, the fourth scan signal S3 and the third scan signal S4 are all low potentials, the fourth transistor T2, the first transistor T5, the third The five transistors T6 and the sixth transistor T7 are both turned off.
  • FIG. 7 is a schematic diagram of the path of the light-emitting device driving circuit provided in the embodiment of the present application in the light-emitting stage under the driving sequence shown in FIG. 3 .
  • the light emitting control signal EM is at a high potential
  • the second transistor T3 is turned on under the high potential control of the light emitting control signal EM
  • the third transistor T4 is turned on under the high potential control of the light emitting control signal EM.
  • the third scan signal S4 is at a high potential
  • the sixth transistor T7 is turned on under the control of the high potential of the third scan signal S4, and the second power signal VSS is written into the gate of the driving transistor T1 through the sixth transistor T7 . That is, the potential of the gate of the driving transistor T1 is pulled down to the potential of the second power supply signal VSS, so that the driving transistor T1 is turned off, thereby realizing black insertion of the light-emitting device.
  • the molecular fields such as the pulse width of the light emitting device D can be adjusted to an unequal molecular field, so that various gray scale changes can be realized and the number of bits can be increased.
  • FIG. 8 is a schematic diagram of sub-field distribution of a conventionally provided light-emitting device driving circuit.
  • FIG. 9 is a schematic diagram of sub-field distribution of the light-emitting device driving circuit provided by the embodiment of the present application. Among them, the abscissa in FIG. 8 and FIG. 9 represents time, and the ordinate represents current.
  • the difference between the existing pixel driving circuit and the pixel driving circuit of the present application is that the second power signal writing module is not provided in the existing pixel driving circuit.
  • the existing light-emitting device driving circuit realizes the molecular field driving method, which can only achieve 8 grayscale.
  • the light-emitting device driving circuit of the present application controls the second power signal writing module 104, that is, by controlling the turn-on time node of the sixth transistor T7, so that the light-emitting device is inserted into black, so that the original 8 equal molecular fields become 8 non-magnetic fields.
  • Equal molecular fields that is, 8 unequal molecular fields can realize 256 kinds of gray scale changes, and the number of bits can be greatly increased without losing the compensation range, that is, the number of gray scales is increased.
  • FIG. 10 is a schematic structural diagram of a backlight module provided by an embodiment of the present application.
  • Embodiments of the present application further provide a backlight module 100, which includes a first scan line 20, a second scan line 30, a third scan line 40, a light-emitting control signal line 50, a data line 60, and the above-mentioned light-emitting device driver circuit 10.
  • the data line 60 is used for providing data signals.
  • the first scan line 20 is used for providing the first scan signal.
  • the second scan line 30 is used for providing the second scan signal.
  • the third scan line 40 is used for providing a third scan signal.
  • the lighting control signal line 50 is used for providing lighting control signals.
  • the light emitting device driving circuit 10 is connected to the data line 60 , the first scan line 20 , the second scan line 30 , the third scan line 40 and the light emission control signal line 50 .
  • the light-emitting device driving circuit 10 reference may be made to the above description of the light-emitting device driving circuit, which is not repeated here.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the embodiment of the present application further provides a display panel 200, which includes a plurality of pixel units 2000 arranged in an array, and each pixel unit 2000 includes the light-emitting device driving circuit 10 described above. The description of the circuit 10 will not be repeated here.

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Abstract

本申请公开了一种发光器件驱动电路、背光模组以及显示面板。发光器件驱动电路包括发光器件、驱动晶体管、数据信号写入模块、第一电源信号写入模块、第二电源信号写入模块、发光控制模块以及存储模块。

Description

发光器件驱动电路、背光模组以及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种发光器件驱动电路、背光模组以及显示面板。
 背景技术
迷你发光二极管、微型发光二极管以及有机发光二极管等发光器件具有高亮度、高对比度及高色域等优点，目前已被迅速应用到新型显示领域中。在现有的发光器件驱动电路中，驱动晶体管容易在长期的电流压力下发生阈值电压偏移，从而使得发光器件的亮度衰减，造成显示不均匀。
近些年，为了解决驱动晶体管的阈值电压偏移引起的发光器件的亮度衰减，出现了大量补偿电路。对于迷你发光二极管和微型发光二极管来讲，电压灰阶切分方式会发生低灰阶显示亮度不均的问题，究其原因是低电流下发光器件发光不均匀引起的。为了避免发光器件工作在低电流引起亮度显示不均及电流压力引起的阈值电压偏移的问题，通常在像素驱动电路中结合时间切分灰阶脉冲宽度调制的驱动方式，让发光器件始终工作在大电流稳定发光阶段，则不会出现显示不均的问题，同时又实现驱动晶体管阈值电压补偿。然而，现有的发光器件驱动电路的灰阶数量比较少。
 技术问题
本申请提供一种发光器件驱动电路、背光模组以及显示面板，可以在解决驱动晶体管阈值电压偏移引起的发光器件的亮度衰减的问题的同时，增加灰阶数量。
 技术解决方案
第一方面，本申请提供一种发光器件驱动电路，包括：
发光器件，所述发光器件串接于第一电源信号与第二电源信号构成的发光回路；
驱动晶体管，所述驱动晶体管的源极以及漏接串接于所述发光回路，所述驱动晶体管用于控制流经所述发光回路的电流；
数据信号写入模块，所述数据信号写入模块接入第一扫描信号以及数据信号，并电性连接于所述驱动晶体管的源极和漏极中的一者，所述数据信号写入模块用于在所述第一扫描信号的控制下，将所述数据信号写入所述驱动晶体管的源极和漏极中的一者；
第一电源信号写入模块，所述第一电源信号写入模块接入第二扫描信号以及所述第一电源信号，并电性连接于所述驱动晶体管的栅极，所述第一电源信号写入模块用于在所述第二扫描信号的控制下，将所述第一电源信号写入所述驱动晶体管的栅极；
第二电源信号写入模块，所述第二电源信号写入模块接入第三扫描信号以及所述第二电源信号，并电性连接于所述驱动晶体管的栅极，所述第二电源信号写入模块用于在所述第三扫描信号的控制下，将所述第二电源信号写入所述驱动晶体管的栅极；
发光控制模块，所述发光控制模块接入发光控制信号，并串接于所述发光回路，所述发光控制模块用于基于所述发光控制信号控制所述发光回路导通或者截止；
存储模块，所述存储模块电性连接于所述驱动晶体管的栅极，并接入所述第二电源信号，所述存储模块用于存储所述驱动晶体管的栅极的电位。
在本申请提供的发光器件驱动电路中，所述发光器件驱动电路还包括补偿模块；所述补偿模块接入第四扫描信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及所述驱动晶体管的栅极，所述补偿模块用于在所述第四扫描信号的控制下，对所述驱动晶体管的阈值电压进行补偿。
在本申请提供的发光器件驱动电路中，所述补偿模块包括第一晶体管；
所述第一晶体管的栅极接入所述第四扫描信号，所述第一晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接。
在本申请提供的发光器件驱动电路中，所述发光控制模块包括：
第一发光控制单元，所述第一发光控制单元接入发光控制信号，且所述第一发光控制单元串接于所述发光回路，所述第一发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止；和/或
第二发光控制单元，所述第二发光控制单元接入发光控制信号，且所述第二发光控制单元串接于所述发光回路，所述第二发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止。
在本申请提供的发光器件驱动电路中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元包括第二晶体管；所述第二发光控制单元包括第三晶体管；
所述第二晶体管的栅极和所述第三晶体管的栅极均接入所述发光控制信号，所述第二晶体管的源极和漏极中的一者与所述发光器件的一端电性连接，所述第二晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
所述第三晶体管的源极和漏极中的一者接入所述第二电源信号，所述第三晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的另一者电性连接。
在本申请提供的发光器件驱动电路中，所述数据信号写入模块包括第四晶体管；
所述第四晶体管的栅极接入所述第一扫描信号，所述第四晶体管的源极和漏极中的一者接入数据信号，所述第四晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
所述第一电源信号写入模块包括第五晶体管；
所述第五晶体管的栅极接入所述第二扫描信号，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
所述第二电源信号写入模块包括第六晶体管；
所述第六晶体管的栅极接入所述第三扫描信号，所述第六晶体管的源极和漏极中的一者接入所述第二电源信号，所述第六晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接；
所述存储模块包括存储电容；
所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端接入所述第二电源信号。
在本申请提供的发光器件驱动电路中，所述发光器件驱动电路通过所述第三扫描信号控制所述第六晶体管打开的时间节点，将所述发光器件的脉冲宽度等分子场切分为非等分子场。
在本申请提供的发光器件驱动电路中，所述发光器件驱动电路的驱动控制时序包括复位阶段、补偿阶段、发光阶段以及插黑阶段；
在所述复位阶段，所述第一扫描信号以及所述第二扫描信号均为高电位，所述第四扫描信号、所述第三扫描信号以及所述发光控制信号均为低电位；
在所述补偿阶段，所述第一扫描信号以及所述第四扫描信号均为高电位，所述第二扫描信号、所述第三扫描信号以及所述发光控制信号均为低电位；
在所述发光阶段，所述发光控制信号为高电位，所述第一扫描信号、所述第二扫描信号、所述第四扫描信号以及所述第三扫描信号均为低电位；
在所述插黑阶段，所述发光控制信号以及所述第三扫描信号均为高电位，所述第一扫描信号、所述第二扫描信号以及所述第四扫描信号均为低电位。
在本申请提供的发光器件驱动电路中，所述第一电源信号的电位大于所述第二电源信号的电位。
第二方面，本申请还提供一种背光模组，包括：
数据线，所述数据线用于提供数据信号；
第一扫描线，所述第一扫描线用于提供第一扫描信号；
第二扫描线，所述第二扫描线用于提供第二扫描信号；
第三扫描线，所述第三扫描线用于提供第三扫描信号；
发光控制信号线，所述发光控制信号线用于提供发光控制信号；以及
发光器件驱动电路，所述发光器件驱动电路与所述数据线、所述第一扫描线、所述第二扫描线、所述第三扫描线以及所述发光控制信号线连接；
所述发光器件驱动电路包括：
发光器件，所述发光器件串接于第一电源信号与第二电源信号构成的发光回路；
驱动晶体管，所述驱动晶体管的源极以及漏接串接于所述发光回路，所述驱动晶体管用于控制流经所述发光回路的电流；
数据信号写入模块，所述数据信号写入模块接入第一扫描信号以及数据信号，并电性连接于所述驱动晶体管的源极和漏极中的一者，所述数据信号写入模块用于在所述第一扫描信号的控制下，将所述数据信号写入所述驱动晶体管的源极和漏极中的一者；
第一电源信号写入模块，所述第一电源信号写入模块接入第二扫描信号以及所述第一电源信号，并电性连接于所述驱动晶体管的栅极，所述第一电源信号写入模块用于在所述第二扫描信号的控制下，将所述第一电源信号写入所述驱动晶体管的栅极；
第二电源信号写入模块，所述第二电源信号写入模块接入第三扫描信号以及所述第二电源信号，并电性连接于所述驱动晶体管的栅极，所述第二电源信号写入模块用于在所述第三扫描信号的控制下，将所述第二电源信号写入所述驱动晶体管的栅极；
发光控制模块，所述发光控制模块接入发光控制信号，并串接于所述发光回路，所述发光控制模块用于基于所述发光控制信号控制所述发光回路导通或者截止；
存储模块，所述存储模块电性连接于所述驱动晶体管的栅极，并接入所述第二电源信号，所述存储模块用于存储所述驱动晶体管的栅极的电位。
在本申请提供的背光模组中，所述发光器件驱动电路还包括补偿模块；所述补偿模块接入第四扫描信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及所述驱动晶体管的栅极，所述补偿模块用于在所述第四扫描信号的控制下，对所述驱动晶体管的阈值电压进行补偿。
在本申请提供的背光模组中，所述补偿模块包括第一晶体管；
所述第一晶体管的栅极接入所述第四扫描信号，所述第一晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接。
在本申请提供的背光模组中，所述发光控制模块包括：
第一发光控制单元，所述第一发光控制单元接入发光控制信号，且所述第一发光控制单元串接于所述发光回路，所述第一发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止；和/或
第二发光控制单元，所述第二发光控制单元接入发光控制信号，且所述第二发光控制单元串接于所述发光回路，所述第二发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止。
在本申请提供的背光模组中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元包括第二晶体管；所述第二发光控制单元包括第三晶体管；
所述第二晶体管的栅极和所述第三晶体管的栅极均接入所述发光控制信号，所述第二晶体管的源极和漏极中的一者与所述发光器件的一端电性连接，所述第二晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
所述第三晶体管的源极和漏极中的一者接入所述第二电源信号，所述第三晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的另一者电性连接。
在本申请提供的背光模组中，所述数据信号写入模块包括第四晶体管；
所述第四晶体管的栅极接入所述第一扫描信号，所述第四晶体管的源极和漏极中的一者接入数据信号，所述第四晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
所述第一电源信号写入模块包括第五晶体管；
所述第五晶体管的栅极接入所述第二扫描信号，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
所述第二电源信号写入模块包括第六晶体管；
所述第六晶体管的栅极接入所述第三扫描信号，所述第六晶体管的源极和漏极中的一者接入所述第二电源信号，所述第六晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接；
所述存储模块包括存储电容；
所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端接入所述第二电源信号。
第三方面，本申请还提供一种显示面板，所述显示面板包括多个呈阵列排布的像素单元；
所述发光器件驱动电路包括：
发光器件，所述发光器件串接于第一电源信号与第二电源信号构成的发光回路；
驱动晶体管，所述驱动晶体管的源极以及漏接串接于所述发光回路，所述驱动晶体管用于控制流经所述发光回路的电流；
数据信号写入模块，所述数据信号写入模块接入第一扫描信号以及数据信号，并电性连接于所述驱动晶体管的源极和漏极中的一者，所述数据信号写入模块用于在所述第一扫描信号的控制下，将所述数据信号写入所述驱动晶体管的源极和漏极中的一者；
第一电源信号写入模块，所述第一电源信号写入模块接入第二扫描信号以及所述第一电源信号，并电性连接于所述驱动晶体管的栅极，所述第一电源信号写入模块用于在所述第二扫描信号的控制下，将所述第一电源信号写入所述驱动晶体管的栅极；
第二电源信号写入模块，所述第二电源信号写入模块接入第三扫描信号以及所述第二电源信号，并电性连接于所述驱动晶体管的栅极，所述第二电源信号写入模块用于在所述第三扫描信号的控制下，将所述第二电源信号写入所述驱动晶体管的栅极；
发光控制模块，所述发光控制模块接入发光控制信号，并串接于所述发光回路，所述发光控制模块用于基于所述发光控制信号控制所述发光回路导通或者截止；
存储模块，所述存储模块电性连接于所述驱动晶体管的栅极，并接入所述第二电源信号，所述存储模块用于存储所述驱动晶体管的栅极的电位。
在本申请提供的显示面板中，所述发光器件驱动电路还包括补偿模块；所述补偿模块接入第四扫描信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及所述驱动晶体管的栅极，所述补偿模块用于在所述第四扫描信号的控制下，对所述驱动晶体管的阈值电压进行补偿。
在本申请提供的显示面板中，所述发光控制模块包括：
第一发光控制单元，所述第一发光控制单元接入发光控制信号，且所述第一发光控制单元串接于所述发光回路，所述第一发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止；和/或
第二发光控制单元，所述第二发光控制单元接入发光控制信号，且所述第二发光控制单元串接于所述发光回路，所述第二发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止。
在本申请提供的显示面板中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元包括第二晶体管；所述第二发光控制单元包括第三晶体管；
所述第二晶体管的栅极和所述第三晶体管的栅极均接入所述发光控制信号，所述第二晶体管的源极和漏极中的一者与所述发光器件的一端电性连接，所述第二晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
所述第三晶体管的源极和漏极中的一者接入所述第二电源信号，所述第三晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的另一者电性连接。
在本申请提供的显示面板中，所述数据信号写入模块包括第四晶体管；
所述第四晶体管的栅极接入所述第一扫描信号，所述第四晶体管的源极和漏极中的一者接入数据信号，所述第四晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
所述第一电源信号写入模块包括第五晶体管；
所述第五晶体管的栅极接入所述第二扫描信号，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
所述第二电源信号写入模块包括第六晶体管；
所述第六晶体管的栅极接入所述第三扫描信号，所述第六晶体管的源极和漏极中的一者接入所述第二电源信号，所述第六晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接；
所述存储模块包括存储电容；
所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端接入所述第二电源信号。
 有益效果
本申请提供的发光器件驱动电路、背光模组以及显示面板，通过设置第二电源信号写入模块对发光器件插黑，调整发光器件发光的脉冲宽度等分子场为非等分子场，从而可以实现多种灰阶变化。
 附图说明
图1为本申请实施例提供的发光器件驱动电路的结构示意图。
图2为本申请实施例提供的发光器件驱动电路的电路示意图。
图3为本申请实施例提供的发光器件驱动电路的时序图。
图4为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的复位阶段的通路示意图。
图5为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的补偿阶段的通路示意图。
图6为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的发光阶段的通路示意图。
图7为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的发光阶段的通路示意图。
图8为现有提供的发光器件驱动电路的子场分布示意图。
图9为本申请实施例提供的发光器件驱动电路的子场分布示意图。
图10为本申请实施例提供的背光模组的结构示意图。
图11为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
需要说明的是，由于本申请采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。
请参阅图1，图1为本申请实施例提供的发光器件驱动电路的结构示意图。如图1所示，本申请实施例提供的发光器件驱动电路10包括发光器件D、驱动晶体管T1、数据信号写入模块101、第一电源信号写入模块102、第二电源信号写入模块104、发光控制模块105以及存储模块106。需要说明的是，发光器件D可以为迷你发光二极管、微型发光二极管或有机发光二极管。
其中，发光器件D串接于第一电源信号VDD与第二电源信号VSS构成的发光回路。驱动晶体管T1的源极以及漏接串接于发光回路。数据信号写入模块101接入第一扫描信号S1以及数据信号DA，并电性连接于驱动晶体管T1的源极和漏极中的一者。第一电源信号写入模块102接入第二扫描信号S2以及第一电源信号VDD，并电性连接于驱动晶体管T1的栅极。第二电源信号写入模块104接入第三扫描信号S4以及第二电源信号VSS，并电性连接于驱动晶体管T1的栅极。发光控制模块105接入发光控制信号EM，并串接于发光回路。存储模块106电性连接于驱动晶体管T1的栅极，并接入第二电源信号VSS。
需要说明的是，本申请实施例只需保证发光控制模块105以及发光器件D串接于发光回路即可，图1所示的发光器件驱动电路10仅仅示意出发光控制模块105以及发光器件D的一种具体位置。也即，发光控制模块105以及发光器件D可以串接在发光回路上的任意位置。
进一步的，本申请实施例提供的发光器件驱动电路10还包括补偿模块103。补偿模块103接入第四扫描信号S3，并电性连接于驱动晶体管T1的源极和漏极中的另一者以及驱动晶体管T1的栅极。
具体的，驱动晶体管T1用于控制流经发光回路的电流。数据信号写入模块101用于在第一扫描信号S1的控制下，将数据信号DA写入驱动晶体管T1的源极和漏极中的一者。第一电源信号写入模块102用于在第二扫描信号S2的控制下，将第一电源信号VDD写入驱动晶体管T1的栅极。补偿模块103用于在第四扫描信号S3的控制下，对驱动晶体管T1的阈值电压进行补偿。第二电源信号写入模块104用于在第三扫描信号S4的控制下，将第二电源信号VSS写入驱动晶体管T1的栅极。发光控制模块105用于基于发光控制信号EM控制发光回路导通或者截止。存储模块106用于存储驱动晶体管T1的栅极的电位。
本申请实施例提供的发光器件驱动电路10，通过设置第二电源信号写入模块104对发光器件D插黑，调整发光器件D发光的脉冲宽度等分子场为非等分子场，从而可以实现多种灰阶变化，实现比特数提升。
在一些实施例中，请参阅图2，图2为本申请实施例提供的发光器件驱动电路的电路示意图。结合图1、图2所示，数据信号写入模块101包括第四晶体管T2。第四晶体管T2的栅极接入第一扫描信号S1。第四晶体管T2的源极和漏极中的一者接入数据信号DA。第四晶体管T2的源极和漏极中的另一者与驱动晶体管T1的源极和漏极中的一者电性连接。当然，可以理解地，数据信号写入模块101还可以采用多个晶体管串联形成。
在一些实施例中，请继续参阅图1和图2，发光控制模块105包括第一发光控制单元1051和第二发光控制单元1052。第一发光控制单元1051与发光器件D的一端和驱动晶体管T1的源极电性连接，并接入发光控制信号EM。第二发光控制单元1052与驱动晶体管T1的漏极电性连接，并接入发光控制信号EM以及第二电源信号VSS。第一发光控制单元1051与第二发光控制单元1052均用于在发光控制信号EM的控制下，控制发光回路导通或者截止。当然，可以理解地，发光控制模块105仅仅只设置第一发光控制单元1051或第二发光控制单元1052即可。或者，光控制模块105还可以包括三个或者三个以上的发光控制单元。
在一具体实施例中，第一发光控制单元1051包括第二晶体管T3。第二发光控制单元1052包括第三晶体管T4。第二晶体管T3的栅极和第三晶体管T4的栅极均接入发光控制信号EM。第二晶体管T3的源极和漏极中的一者与发光器件D的一端电性连接。第二晶体管T3的源极和漏极中的另一者与驱动晶体管T1的源极和漏极中的一者电性连接。第三晶体管T4的源极和漏极中的一者接入第二电源信号VSS。第三晶体管T4的源极和漏极中的另一者与驱动晶体管T1的源极和漏极中的另一者电性连接。当然，可以理解地，第一发光控制单元1051还可以采用多个晶体管串联形成；第二发光控制单元1052还可以采用多个晶体管串联形成。
在一些实施例中，请继续参阅图1和图2，补偿模块103包括第一晶体管T5。第一晶体管T5的栅极接入第四扫描信号S3。第一晶体管T5的源极和漏极中的一者与驱动晶体管T1的栅极电性连接。第一晶体管T5的源极和漏极中的另一者与驱动晶体管T1的源极和漏极中的一者电性连接。当然，可以理解地，补偿模块103还可以采用多个晶体管串联形成。
在一些实施例中，请继续参阅图1和图2，第一电源信号写入模块102包括第五晶体管T6。第五晶体管T6的栅极接入第二扫描信号S2。第五晶体管T6的源极和漏极中的一者接入第一电源信号VDD。第五晶体管T6的源极和漏极中的另一者与驱动晶体管T1的栅极电性连接。当然，可以理解地，第一电源信号写入模块102还可以采用多个晶体管串联形成。
在一些实施例中，请继续参阅图1和图2，第二电源信号写入模块104包括第六晶体管T7。第六晶体管T7的栅极接入第三扫描信号S4。第六晶体管T7的源极和漏极中的一者接入第二电源信号VSS。第六晶体管T7的源极和漏极中的另一者与驱动晶体管T1的栅极电性连接。当然，可以理解地，第二电源信号写入模块104还可以采用多个晶体管串联形成。
需要说明的是，本申请实施例提供的发光器件驱动电路10通过控制第六晶体管T7打开的时间节点，调整发光器件D发光的脉冲宽度等分子场为非等分子场，从而可以实现多种灰阶变化，实现比特数提升。
在一些实施例中，请继续参阅图1和图2，存储模块106包括存储电容C1。存储电容C1的一端与驱动晶体管T1的栅极电性连接。存储电容C1的另一端接入第二电源信号VSS。
本申请实施例提供的发光器件驱动电路10采用7T1C（7个晶体管以及1个电容）结构的发光器件驱动电路对发光器件D进行控制，用了较少的元器件，结构简单稳定，节约了成本。
在一些实施例中，第一电源信号VDD和第二电源信号VSS均用于输出一预设电压值。此外，在本申请实施例中，第一电源信号VDD的电位大于第二电源信号VSS的电位。具体的，第二电源信号VSS的电位可以为接地端的电位。当然，可以理解地，第二电源信号VSS的电位还可以为其它。
在一些实施例中，驱动晶体管T1、第四晶体管T2、第二晶体管T3、第三晶体管T4、第一晶体管T5、第五晶体管T6以及第六晶体管T7可以为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管中的一种或者多种。进一步的，可以设置本申请实施例提供的发光器件驱动电路10中的晶体管为同一种类型的晶体管，从而避免不同类型的晶体管之间的差异性对发光器件驱动电路10造成的影响。
请参阅图3，图3为本申请实施例提供的发光器件驱动电路的时序图。发光控制信号EM、第一扫描信号S1、第二扫描信号S2、第四扫描信号S3以及第三扫描信号S4相组合先后对应于复位阶段t1、补偿阶段t2、发光阶段t3以及插黑阶段t4。也即，在一帧时间内，本申请实施例提供的发光器件驱动电路10的驱动控制时序包括复位阶段t1、补偿阶段t2、发光阶段t3以及插黑阶段t4。
在一些实施例中，复位阶段t1，第一扫描信号S1以及第二扫描信号S2均为高电位，第四扫描信号S3、第三扫描信号S4以及发光控制信号EM均为低电位。此时，数据信号DA的电位为低电位。
在一些实施例中，补偿阶段t2，第一扫描信号S1以及第四扫描信号S3均为高电位，第二扫描信号S2、第三扫描信号S4以及发光控制信号EM均为低电位。此时，数据信号DA的电位为高电位。
在一些实施例中，发光阶段t3，发光控制信号EM为高电位，第一扫描信号S1、第二扫描信号S2、第四扫描信号S3以及第三扫描信号S4均为低电位。此时，数据信号DA的电位为高电位。
在一些实施例中，插黑阶段t4，发光控制信号EM以及第三扫描信号S4均为高电位，第一扫描信号S1、第二扫描信号S2以及第四扫描信号S3均为低电位。此时，数据信号DA的电位为高电位。需要说明的是，第三扫描信号S4的脉冲宽度可以根据需要进行设置，本申请实施例提供的发光器件驱动电路通过设置第三扫描信号S4的脉冲宽度，从而可以控制第六晶体管T7打开的时间节点，调整发光器件D发光的脉冲宽度等分子场为非等分子场，进而可以实现多种灰阶变化。
具体的，请参阅图3和图4，图4为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的复位阶段的通路示意图。在复位阶段t1，第一扫描信号S1为高电位，第四晶体管T2在第一扫描信号S1的高电位控制下打开，数据信号DA写入驱动晶体管T1的源极和漏极中的一者。此时，数据信号DA的电位为低电位，数据信号DA的低电位经第四晶体管T2写入驱动晶体管T1的源极和漏极中的一者，以实现对驱动晶体管T1的源极和漏极中的一者的初始化。在复位阶段t1，第二扫描信号S2为高电位，第五晶体管T6在第二扫描信号S2的高电位控制下打开，第一电源信号VDD写入驱动晶体管T1的栅极。第一电源信号VDD的电位经第五晶体管T6写入驱动晶体管T1的栅极，以实现对驱动晶体管T1的栅极的初始化。此时，驱动晶体管T1打开。
与此同时，在复位阶段t1，由于发光控制信号EM、第四扫描信号S3以及第三扫描信号S4均为低电位，使得第二晶体管T3、第三晶体管T4、第一晶体管T5以及第六晶体管T7均关闭。
请参阅图3和图5，图5为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的补偿阶段的通路示意图。在补偿阶段t2，第一扫描信号S1为高电位，第四晶体管T2在第一扫描信号S1的高电位控制下打开，数据信号DA写入驱动晶体管T1的源极和漏极中的一者。此时，数据信号DA的电位为高电位，数据信号DA的高电位经第四晶体管T2写入驱动晶体管T1的源极和漏极中的一者，驱动晶体管T1的源极和漏极中的一者的电位由数据信号DA的低电位转为数据信号DA的高电位。在补偿阶段t2，第四扫描信号S3为高电位，第一晶体管T5在第四扫描信号S3的高电位控制下打开。此时，第一晶体管T5连接驱动晶体管T1的源极和漏极中的一者和驱动晶体管T1的栅极，驱动晶体管T1的源极和漏极中的一者和驱动晶体管T1的栅极形成二极管结构，使得驱动晶体管T1的栅极的电位由第一电源信号VDD的电位降为数据信号DA的高电位与驱动晶体管T1的阈值电压之和。并且，由于存储电容C1的存在，驱动晶体管T1的栅极的电位会维持在数据信号DA的高电位与驱动晶体管T1的阈值电压之和。此时，驱动晶体管T1仍然打开。
与此同时，在补偿阶段t2，由于发光控制信号EM、第二扫描信号S2以及第三扫描信号S4均为低电位，使得第二晶体管T3、第三晶体管T4、第五晶体管T6以及第六晶体管T7均关闭。
请参阅图3和图6，图6为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的发光阶段的通路示意图。在发光阶段t3，发光控制信号EM为高电位，第二晶体管T3在发光控制信号EM的高电位控制下打开，第三晶体管T4在发光控制信号EM的高电位控制下打开。此时，驱动晶体管T1的栅极的电位为数据信号DA的高电位与驱动晶体管T1的阈值电压之和VDATA+Vth，驱动晶体管T1的源极和漏极中的一者的电位为V0。
进一步地，计算流经发光器件D的电流的公式为：
IOLED＝1/2Cox(μ1W1/L1)（Vgs－Vth））2 ，其中IOLED为流经发光器件D的电流，μ1为驱动晶体管T1的载流子迁移率，W1和L1分别为第一晶体管T1的沟道的宽度和长度，Vgs为驱动晶体管T1的栅极与源极和漏极中的一者之间的压差，Vth为驱动晶体管T1的阈值电压。
也即，流经发光器件D的电流：IOLED＝1/2Cox(μ1W1/L1)（Vgs-Vth）2=1/2Cox(μ1W1/L1)（VDATA+Vth-V0-Vth）2=1/2Cox(μ1W1/L1)（VDATA-V0）2。
此时，驱动晶体管T1仍然打开，发光器件D发光，流经发光器件D的电流与驱动晶体管T1的阈值电压无关，从而实现阈值电压的补偿效果。
与此同时，在发光阶段t3，由于第一扫描信号S1、第二扫描信号S2、第四扫描信号S3以及第三扫描信号S4均为低电位，使得第四晶体管T2、第一晶体管T5、第五晶体管T6以及第六晶体管T7均关闭。
请参阅图3和图7，图7为本申请实施例提供的发光器件驱动电路在图3所示的驱动时序下的发光阶段的通路示意图。在插黑阶段t4，发光控制信号EM为高电位，第二晶体管T3在发光控制信号EM的高电位控制下打开，第三晶体管T4在发光控制信号EM的高电位控制下打开。在插黑阶段t4，第三扫描信号S4为高电位，第六晶体管T7在第三扫描信号S4的高电位控制下打开，第二电源信号VSS经第六晶体管T7写入驱动晶体管T1的栅极。也即，驱动晶体管T1的栅极的电位拉低至第二电源信号VSS的电位，从而使得驱动晶体管T1关闭，进而实现发光器件插黑。如此，可以通过控制第六晶体管T7打开的时间节点，进而将发光器件D发光的脉冲宽度等分子场调整为非等分子场，从而可以实现多种灰阶变化，实现比特数提升。
进一步的，请参阅图8以及图9，图8为现有提供的发光器件驱动电路的子场分布示意图。图9为本申请实施例提供的发光器件驱动电路的子场分布示意图。其中，图8、图9中横坐标表示时间，纵坐标表示电流。
需要说明的是，现有的像素驱动电路与本申请的像素驱动电路的区别在于：现有的像素驱动电路中未设置第二电源信号写入模块。
结合图8、图9所示，以240Hz，10行面板为例，假定阈值电压探测及补偿需占用50微秒时间，现有的发光器件驱动电路实现等分子场驱动方式，仅能实现8个灰阶。本申请的发光器件驱动电路通过控制第二电源信号写入模块104，也即，通过控制第六晶体管T7的打开时间节点，使得发光器件插黑，使原先8个等分子场变为8个非等分子场，即8个非等分子场可实现256种灰阶变化，在不损失补偿范围的情况下可实现比特数大幅提升，也即增加了灰阶数量。
请参阅图10，图10为本申请实施例提供的背光模组的结构示意图。本申请实施例还提供一种背光模组100，其包括第一扫描线20、第二扫描线30、第三扫描线40、发光控制信号线50、数据线60以及以上所述的发光器件驱动电路10。其中，数据线60用于提供数据信号。第一扫描线20用于提供第一扫描信号。第二扫描线30用于提供第二扫描信号。第三扫描线40用于提供第三扫描信号。发光控制信号线50用于提供发光控制信号。发光器件驱动电路10与数据线60、第一扫描线20、第二扫描线30、第三扫描线40以及发光控制信号线50连接。发光器件驱动电路10具体可参照以上对该发光器件驱动电路的描述，在此不做赘述。
请参阅图11，图11为本申请实施例提供的显示面板的结构示意图。本申请实施例还提供一种显示面板200，包括多个呈阵列排布的像素单元2000，每一像素单元2000均包括以上所述的发光器件驱动电路10，具体可参照以上对该发光器件驱动电路10的描述，在此不做赘述。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种发光器件驱动电路，其包括：
    发光器件，所述发光器件串接于第一电源信号与第二电源信号构成的发光回路；
    驱动晶体管，所述驱动晶体管的源极以及漏接串接于所述发光回路，所述驱动晶体管用于控制流经所述发光回路的电流；
    数据信号写入模块，所述数据信号写入模块接入第一扫描信号以及数据信号，并电性连接于所述驱动晶体管的源极和漏极中的一者，所述数据信号写入模块用于在所述第一扫描信号的控制下，将所述数据信号写入所述驱动晶体管的源极和漏极中的一者；
    第一电源信号写入模块，所述第一电源信号写入模块接入第二扫描信号以及所述第一电源信号，并电性连接于所述驱动晶体管的栅极，所述第一电源信号写入模块用于在所述第二扫描信号的控制下，将所述第一电源信号写入所述驱动晶体管的栅极；
    第二电源信号写入模块，所述第二电源信号写入模块接入第三扫描信号以及所述第二电源信号，并电性连接于所述驱动晶体管的栅极，所述第二电源信号写入模块用于在所述第三扫描信号的控制下，将所述第二电源信号写入所述驱动晶体管的栅极；
    发光控制模块，所述发光控制模块接入发光控制信号，并串接于所述发光回路，所述发光控制模块用于基于所述发光控制信号控制所述发光回路导通或者截止；
    存储模块，所述存储模块电性连接于所述驱动晶体管的栅极，并接入所述第二电源信号，所述存储模块用于存储所述驱动晶体管的栅极的电位。
  2. 根据权利要求1所述的发光器件驱动电路，其中，所述发光器件驱动电路还包括补偿模块；所述补偿模块接入第四扫描信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及所述驱动晶体管的栅极，所述补偿模块用于在所述第四扫描信号的控制下，对所述驱动晶体管的阈值电压进行补偿。
  3. 根据权利要求2所述的发光器件驱动电路，其中，所述补偿模块包括第一晶体管；
    所述第一晶体管的栅极接入所述第四扫描信号，所述第一晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接。
  4. 根据权利要求1所述的发光器件驱动电路，其中，所述发光控制模块包括：
    第一发光控制单元，所述第一发光控制单元接入发光控制信号，且所述第一发光控制单元串接于所述发光回路，所述第一发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止；和/或
    第二发光控制单元，所述第二发光控制单元接入发光控制信号，且所述第二发光控制单元串接于所述发光回路，所述第二发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止。
  5. 根据权利要求4所述的发光器件驱动电路，其中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元包括第二晶体管；所述第二发光控制单元包括第三晶体管；
    所述第二晶体管的栅极和所述第三晶体管的栅极均接入所述发光控制信号，所述第二晶体管的源极和漏极中的一者与所述发光器件的一端电性连接，所述第二晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
    所述第三晶体管的源极和漏极中的一者接入所述第二电源信号，所述第三晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的另一者电性连接。
  6. 根据权利要求1所述的发光器件驱动电路，其中，所述数据信号写入模块包括第四晶体管；
    所述第四晶体管的栅极接入所述第一扫描信号，所述第四晶体管的源极和漏极中的一者接入数据信号，所述第四晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
    所述第一电源信号写入模块包括第五晶体管；
    所述第五晶体管的栅极接入所述第二扫描信号，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
    所述第二电源信号写入模块包括第六晶体管；
    所述第六晶体管的栅极接入所述第三扫描信号，所述第六晶体管的源极和漏极中的一者接入所述第二电源信号，所述第六晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接；
    所述存储模块包括存储电容；
    所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端接入所述第二电源信号。
  7. 根据权利要求6所述的发光器件驱动电路，其中，所述发光器件驱动电路通过所述第三扫描信号控制所述第六晶体管打开的时间节点，将所述发光器件的脉冲宽度等分子场切分为非等分子场。
  8. 根据权利要求1所述的发光器件驱动电路，其中，所述发光器件驱动电路的驱动控制时序包括复位阶段、补偿阶段、发光阶段以及插黑阶段；
    在所述复位阶段，所述第一扫描信号以及所述第二扫描信号均为高电位，所述第四扫描信号、所述第三扫描信号以及所述发光控制信号均为低电位；
    在所述补偿阶段，所述第一扫描信号以及所述第四扫描信号均为高电位，所述第二扫描信号、所述第三扫描信号以及所述发光控制信号均为低电位；
    在所述发光阶段，所述发光控制信号为高电位，所述第一扫描信号、所述第二扫描信号、所述第四扫描信号以及所述第三扫描信号均为低电位；
    在所述插黑阶段，所述发光控制信号以及所述第三扫描信号均为高电位，所述第一扫描信号、所述第二扫描信号以及所述第四扫描信号均为低电位。
  9. 根据权利要求1所述的发光器件驱动电路，其中，所述第一电源信号的电位大于所述第二电源信号的电位。
  10. 一种背光模组，其包括：
    数据线，所述数据线用于提供数据信号；
    第一扫描线，所述第一扫描线用于提供第一扫描信号；
    第二扫描线，所述第二扫描线用于提供第二扫描信号；
    第三扫描线，所述第三扫描线用于提供第三扫描信号；
    发光控制信号线，所述发光控制信号线用于提供发光控制信号；以及
    发光器件驱动电路，所述发光器件驱动电路与所述数据线、所述第一扫描线、所述第二扫描线、所述第三扫描线以及所述发光控制信号线连接；
    所述发光器件驱动电路包括：
    发光器件，所述发光器件串接于第一电源信号与第二电源信号构成的发光回路；
    驱动晶体管，所述驱动晶体管的源极以及漏接串接于所述发光回路，所述驱动晶体管用于控制流经所述发光回路的电流；
    数据信号写入模块，所述数据信号写入模块接入第一扫描信号以及数据信号，并电性连接于所述驱动晶体管的源极和漏极中的一者，所述数据信号写入模块用于在所述第一扫描信号的控制下，将所述数据信号写入所述驱动晶体管的源极和漏极中的一者；
    第一电源信号写入模块，所述第一电源信号写入模块接入第二扫描信号以及所述第一电源信号，并电性连接于所述驱动晶体管的栅极，所述第一电源信号写入模块用于在所述第二扫描信号的控制下，将所述第一电源信号写入所述驱动晶体管的栅极；
    第二电源信号写入模块，所述第二电源信号写入模块接入第三扫描信号以及所述第二电源信号，并电性连接于所述驱动晶体管的栅极，所述第二电源信号写入模块用于在所述第三扫描信号的控制下，将所述第二电源信号写入所述驱动晶体管的栅极；
    发光控制模块，所述发光控制模块接入发光控制信号，并串接于所述发光回路，所述发光控制模块用于基于所述发光控制信号控制所述发光回路导通或者截止；
    存储模块，所述存储模块电性连接于所述驱动晶体管的栅极，并接入所述第二电源信号，所述存储模块用于存储所述驱动晶体管的栅极的电位。
  11. 根据权利要求10所述的背光模组，其中，所述发光器件驱动电路还包括补偿模块；所述补偿模块接入第四扫描信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及所述驱动晶体管的栅极，所述补偿模块用于在所述第四扫描信号的控制下，对所述驱动晶体管的阈值电压进行补偿。
  12. 根据权利要求11所述的背光模组，其中，所述补偿模块包括第一晶体管；
    所述第一晶体管的栅极接入所述第四扫描信号，所述第一晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接。
  13. 根据权利要求10所述的背光模组，其中，所述发光控制模块包括：
    第一发光控制单元，所述第一发光控制单元接入发光控制信号，且所述第一发光控制单元串接于所述发光回路，所述第一发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止；和/或
    第二发光控制单元，所述第二发光控制单元接入发光控制信号，且所述第二发光控制单元串接于所述发光回路，所述第二发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止。
  14. 根据权利要求13所述的背光模组，其中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元包括第二晶体管；所述第二发光控制单元包括第三晶体管；
    所述第二晶体管的栅极和所述第三晶体管的栅极均接入所述发光控制信号，所述第二晶体管的源极和漏极中的一者与所述发光器件的一端电性连接，所述第二晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
    所述第三晶体管的源极和漏极中的一者接入所述第二电源信号，所述第三晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的另一者电性连接。
  15. 根据权利要求10所述的背光模组，其中，所述数据信号写入模块包括第四晶体管；
    所述第四晶体管的栅极接入所述第一扫描信号，所述第四晶体管的源极和漏极中的一者接入数据信号，所述第四晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
    所述第一电源信号写入模块包括第五晶体管；
    所述第五晶体管的栅极接入所述第二扫描信号，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
    所述第二电源信号写入模块包括第六晶体管；
    所述第六晶体管的栅极接入所述第三扫描信号，所述第六晶体管的源极和漏极中的一者接入所述第二电源信号，所述第六晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接；
    所述存储模块包括存储电容；
    所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端接入所述第二电源信号。
  16. 一种显示面板，其包括多个呈阵列排布的像素单元，每一所述像素单元均包括发光器件驱动电路；
    所述发光器件驱动电路包括：
    发光器件，所述发光器件串接于第一电源信号与第二电源信号构成的发光回路；
    驱动晶体管，所述驱动晶体管的源极以及漏接串接于所述发光回路，所述驱动晶体管用于控制流经所述发光回路的电流；
    数据信号写入模块，所述数据信号写入模块接入第一扫描信号以及数据信号，并电性连接于所述驱动晶体管的源极和漏极中的一者，所述数据信号写入模块用于在所述第一扫描信号的控制下，将所述数据信号写入所述驱动晶体管的源极和漏极中的一者；
    第一电源信号写入模块，所述第一电源信号写入模块接入第二扫描信号以及所述第一电源信号，并电性连接于所述驱动晶体管的栅极，所述第一电源信号写入模块用于在所述第二扫描信号的控制下，将所述第一电源信号写入所述驱动晶体管的栅极；
    第二电源信号写入模块，所述第二电源信号写入模块接入第三扫描信号以及所述第二电源信号，并电性连接于所述驱动晶体管的栅极，所述第二电源信号写入模块用于在所述第三扫描信号的控制下，将所述第二电源信号写入所述驱动晶体管的栅极；
    发光控制模块，所述发光控制模块接入发光控制信号，并串接于所述发光回路，所述发光控制模块用于基于所述发光控制信号控制所述发光回路导通或者截止；
    存储模块，所述存储模块电性连接于所述驱动晶体管的栅极，并接入所述第二电源信号，所述存储模块用于存储所述驱动晶体管的栅极的电位。
  17. 根据权利要求16所述的显示面板，其中，所述发光器件驱动电路还包括补偿模块；所述补偿模块接入第四扫描信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及所述驱动晶体管的栅极，所述补偿模块用于在所述第四扫描信号的控制下，对所述驱动晶体管的阈值电压进行补偿。
  18. 根据权利要求16所述的显示面板，其中，所述发光控制模块包括：
    第一发光控制单元，所述第一发光控制单元接入发光控制信号，且所述第一发光控制单元串接于所述发光回路，所述第一发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止；和/或
    第二发光控制单元，所述第二发光控制单元接入发光控制信号，且所述第二发光控制单元串接于所述发光回路，所述第二发光控制单元用于在所述发光控制信号的控制下，控制所述发光回路导通或者截止。
  19. 根据权利要求16所述的显示面板，其中，所述发光控制模块包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元包括第二晶体管；所述第二发光控制单元包括第三晶体管；
    所述第二晶体管的栅极和所述第三晶体管的栅极均接入所述发光控制信号，所述第二晶体管的源极和漏极中的一者与所述发光器件的一端电性连接，所述第二晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
    所述第三晶体管的源极和漏极中的一者接入所述第二电源信号，所述第三晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的另一者电性连接。
  20. 根据权利要求16所述的显示面板，其中，所述数据信号写入模块包括第四晶体管；
    所述第四晶体管的栅极接入所述第一扫描信号，所述第四晶体管的源极和漏极中的一者接入数据信号，所述第四晶体管的源极和漏极中的另一者与所述驱动晶体管的源极和漏极中的一者电性连接；
    所述第一电源信号写入模块包括第五晶体管；
    所述第五晶体管的栅极接入所述第二扫描信号，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
    所述第二电源信号写入模块包括第六晶体管；
    所述第六晶体管的栅极接入所述第三扫描信号，所述第六晶体管的源极和漏极中的一者接入所述第二电源信号，所述第六晶体管的源极和漏极中的一者与所述驱动晶体管的栅极电性连接；
    所述存储模块包括存储电容；
    所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端接入所述第二电源信号。
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