WO2022041329A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

Info

Publication number
WO2022041329A1
WO2022041329A1 PCT/CN2020/114778 CN2020114778W WO2022041329A1 WO 2022041329 A1 WO2022041329 A1 WO 2022041329A1 CN 2020114778 W CN2020114778 W CN 2020114778W WO 2022041329 A1 WO2022041329 A1 WO 2022041329A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
light
emitting
pixel circuit
driving transistor
Prior art date
Application number
PCT/CN2020/114778
Other languages
English (en)
French (fr)
Inventor
周永祥
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/051,778 priority Critical patent/US11238784B1/en
Publication of WO2022041329A1 publication Critical patent/WO2022041329A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present application relates to the field of display technology, in particular to the field of in-plane driving technology, and in particular to a pixel circuit and a display panel.
  • Mini-LED the current required by Mini-LED is relatively large, and the driving thin-film transistor (TFT) is subjected to a long-term high-current working environment, and its stability is poor, which may easily cause problems such as uneven display or even display failure.
  • TFT driving thin-film transistor
  • the present application provides a pixel circuit and a display panel, which solve the problem that the driving transistor in the pixel circuit is in a working state for a long time, resulting in poor stability.
  • the present application provides a pixel circuit, which includes a first driving transistor, a second driving transistor, a first switching transistor and a second switching transistor; the first driving transistor is connected in series with the first power supply signal and the second power supply signal
  • the formed light-emitting circuit is used to control the current flowing through the light-emitting circuit;
  • the second driving transistor is connected in parallel with the first driving transistor and is connected in series with the light-emitting circuit for controlling the current flowing through the light-emitting circuit; the output end of the first switching transistor is connected to the light-emitting circuit.
  • the control terminal of the first driving transistor is connected to control the first driving transistor according to the first control signal;
  • the output terminal of the second switching transistor is connected to the control terminal of the second driving transistor and used to control the second driving transistor according to the second control signal transistor; wherein, the first driving transistor and the second driving transistor work alternately.
  • the pixel circuit further includes a writing transistor, and the output terminal of the writing transistor is connected to the output terminal of the first driving transistor and the output terminal of the second driving transistor, using The data signal is controlled to be written into the pixel circuit according to the first scan signal.
  • the pixel circuit further includes a compensation transistor, and the input end of the compensation transistor is connected to the input end of the first driving transistor and the input of the second driving transistor The output end of the compensation transistor is connected to the input end of the first switching transistor and the input end of the second switching transistor, and the control end of the compensation transistor is used for accessing the first scanning signal.
  • the pixel circuit further includes a storage capacitor, the first end of the storage capacitor is connected to the output end of the compensation transistor, and the second end of the storage capacitor is connected to the output end of the compensation transistor. Connect with the second power signal.
  • the pixel circuit further includes an initialization transistor, and an output end of the initialization transistor is connected to the first end of the storage capacitor, for scanning according to the second scan
  • the signal initializes the potential of the first end of the storage capacitor to the potential of the initial voltage signal.
  • the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor; the first light-emitting control transistor is connected in series with the light-emitting loop and The output end of the first light-emitting control transistor is connected with the input end of the first driving transistor and the input end of the second driving transistor, and is used to control the light-emitting circuit on and off according to the light-emitting control signal; the second light-emitting control transistor is connected in series with the light-emitting circuit and the third The input ends of the two light-emitting control transistors are connected to the output end of the first driving transistor and the output end of the second driving transistor, and are used for on-off control of the light-emitting circuit according to the light-emitting control signal.
  • the pixel circuit further includes a light-emitting device, the light-emitting device is connected in series with the light-emitting circuit, and the input end of the light-emitting device is connected to the first power supply signal , or, the output end of the light-emitting device is connected to the second power signal.
  • the potential of the first power supply signal is greater than the potential of the second power supply signal.
  • the first driving transistor, the second driving transistor, the first switching transistor, the second switching transistor, the writing transistor, the compensation transistor, the initialization At least one of the transistor, the first light emission control transistor and the second light emission control transistor is an N-type thin film transistor.
  • the present application provides a display panel including the pixel circuit in any one of the above embodiments.
  • the first switching transistor and the second switching transistor are used to control the first driving transistor and the second driving transistor to work alternately, so that the duty cycle of the first driving transistor and/or the second driving transistor can be shortened, The stability of the driving transistor can be improved, thereby enhancing the reliability and service life of the pixel circuit and the display panel.
  • FIG. 1 is a schematic diagram of a first structure of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a second structure of a pixel circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic timing diagram of a pixel circuit according to an embodiment of the present application.
  • this embodiment provides a pixel circuit, which includes a first driving transistor T4, a second driving transistor T5, a first switching transistor T2 and a second switching transistor T3; the first driving transistor T4
  • the light-emitting loop formed by the first power supply signal VDD and the second power supply signal VSS is connected in series to control the current flowing through the light-emitting loop;
  • the second driving transistor T5 is connected in parallel with the first driving transistor T4 and is connected in series with the light-emitting loop for controlling the current flowing through the light-emitting loop.
  • the output end of the first switching transistor T2 is connected to the control end of the first driving transistor T4 for controlling the first driving transistor T4 according to the first control signal LC1;
  • the output end of the second switching transistor T3 It is connected to the control terminal of the second driving transistor T5, and is used for controlling the second driving transistor T5 according to the second control signal LC2; wherein, the first driving transistor T4 and the second driving transistor T5 work alternately.
  • the first switching transistor T2 and the second switching transistor T3 may be, but are not limited to, thin film transistors of the same type.
  • they may both be N-channel type thin film transistors, or both may be P-channel type thin film transistors. thin film transistor.
  • the duty cycles of the first control signal LC1 and the second control signal LC2 are alternated or at least partially overlapped.
  • the duty cycle of the first control signal LC1 and the second control signal LC2 is the high level duration
  • the duty cycles of the first control signal LC1 and the second control signal LC2 operate in an alternate manner, the falling edge of the first control signal LC1 and the rising edge of the second control signal LC2 may be coincident or at the same time, Alternatively, the rising edge of the second control signal LC2 may be located between the rising edge and the falling edge of the first control signal LC1.
  • the duty cycle of the first control signal LC1 and the second control signal LC2 is the duration of the low level
  • the duty cycles of the first control signal LC1 and the second control signal LC2 operate in an alternate manner, the rising edge of the first control signal LC1 and the falling edge of the second control signal LC2 may be coincident or at the same time, Alternatively, the falling edge of the second control signal LC2 may be located between the falling edge and the rising edge of the first control signal LC1.
  • the first switching transistor T2 may be an N-channel thin film transistor
  • the second switching transistor T3 may be a P-channel thin film transistor; or, the first switching transistor T2 may be a P-channel thin film transistor, and the second switching transistor T3
  • the transistor T3 may be an N-channel thin film transistor.
  • any one of the first control signal LC1 and the second control signal LC2 can also be used, for example, the first control signal LC1 or the second control signal LC2 and the control terminal of the first switching transistor T2 and the second control signal LC2 The control terminal of the switching transistor T3 is connected.
  • the first switching transistor T2 is turned on, and the second switching transistor T3 is turned off; or the first switching transistor T2 is turned off, The second switching transistor T3 is turned on.
  • the first control signal LC1 or the second control signal LC2 is in a low potential state
  • the first switching transistor T2 is turned off and the second switching transistor T3 is turned on; or the first switching transistor T2 is turned on and the second switching transistor T3 is turned off.
  • the first switching transistor T2 can control whether the control terminal of the first driving transistor T4 is connected to the corresponding driving signal
  • the second switching transistor T3 can control whether the control terminal of the second driving transistor T5 is connected to the corresponding driving signal
  • the first driving transistor T4 and the second driving transistor T5 can work alternately, so that the driving transistor can obtain a corresponding rotation, which is beneficial to restore the electrical characteristics of the driving transistor, thereby improving the working stability of the driving transistor, thereby improving the overall driving circuit. Working life, enhance its reliability.
  • the first switching transistor T2 and the second switching transistor T3 are used to control the first driving transistor T4 and the second driving transistor T5 to work alternately, which can improve the stability of the driving transistor, and further Enhance the reliability and service life of pixel circuits and display panels.
  • the pixel circuit further includes a writing transistor T8, the output terminal of the writing transistor T8, the output terminal of the first driving transistor T4 and the output terminal of the second driving transistor T5 connected to control the writing of the data signal Vdata to the pixel circuit according to the first scan signal S1.
  • the pixel circuit further includes a compensation transistor T9, and the input end of the compensation transistor T9 is connected to the input end of the first driving transistor T4 and the input end of the second driving transistor T5, The output end of the compensation transistor T9 is connected to the input end of the first switching transistor T2 and the input end of the second switching transistor T3, and the control end of the compensation transistor T9 is used for accessing the first scan signal S1.
  • the pixel circuit further includes a storage capacitor C1, the first terminal of the storage capacitor C1 is connected to the output terminal of the compensation transistor T9, and the second terminal of the storage capacitor C1 is connected to the second terminal of the compensation transistor T9. Power supply signal VSS connection.
  • the pixel circuit further includes an initialization transistor T1 , and the output end of the initialization transistor T1 is connected to the first end of the storage capacitor C1 for initializing storage according to the second scan signal S2 The potential of the first end of the capacitor C1 reaches the potential of the initial voltage signal VI.
  • the pixel circuit further includes a first light-emitting control transistor T6 and a second light-emitting control transistor T7; the first light-emitting control transistor T6 is serially connected to the light-emitting loop and the first light-emitting control transistor T6 The output end of the transistor T6 is connected with the input end of the first driving transistor T4 and the input end of the second driving transistor T5, and is used to control the light-emitting loop on and off according to the light-emitting control signal EM; the second light-emitting control transistor T7 is connected in series with the light-emitting loop and The input terminal of the second light-emitting control transistor T7 is connected to the output terminal of the first driving transistor T4 and the output terminal of the second driving transistor T5, and is used for on-off control of the light-emitting circuit according to the light-emitting control signal EM.
  • the pixel circuit further includes a light-emitting device LED, the light-emitting device LED is connected in series with the light-emitting circuit, and the input end of the light-emitting device LED is connected to the first power supply signal VDD, or the output end of the light-emitting device LED is connected to the second power supply signal VDD. Power supply signal VSS connection.
  • the input end of the light emitting device LED can be connected to the first power signal VDD, and the output end of the light emitting device LED can be connected to the input end of the first light emitting control transistor T6 .
  • the input end of the light emitting device LED can be connected to the output end of the second light emitting control transistor T7 , and the output end of the light emitting device LED is connected to the second power supply signal VSS.
  • the light-emitting device LED in this example can be any one of mini-led, micro-led and oled.
  • the potential of the first power supply signal VDD is greater than the potential of the second power supply signal VSS.
  • at least one of the second light-emitting control transistors T7 is an N-type thin film transistor.
  • first control signal LC1 and/or the second control signal LC2 may be, but not limited to, clock signals with relatively low frequency or low frequency.
  • the input end of the corresponding transistor described in the embodiments of the present application may be its drain electrode or its source electrode.
  • the output end of the corresponding transistor described in the embodiments of the present application may be its drain electrode or its source electrode.
  • the control terminal of the corresponding transistor described in the embodiments of the present application is its gate.
  • the working sequence of the pixel circuits of the two structures provided in this example may include the following stages:
  • the initialization transistor T1 is turned on, and the initial voltage signal VI can be written to the Q point to achieve reset.
  • the first control signal LC1 and the second control signal LC2 are low-frequency clock signals, which are opposite to each other, and one is a high potential (VGH) and the other is a low potential (VGL). Therefore, one of the first switching transistor T2 and the second switching transistor T3 is in an on state, and the other is in an off state.
  • the first driving transistor T4 or the second driving transistor T5 is controlled to work by the first control signal LC1 and the second control signal LC2, so that they can work for half of the time and rest for half of the time, so that the electrical properties of the corresponding driving transistors can be restored, As a result, stability and reliability are improved.
  • the writing transistor T8 and the compensation transistor T9 are turned on, the data signal Vdata is written to the Q point, and the threshold voltage of the corresponding driving transistor ( Vth) compensation.
  • the light-emitting control signal EM changes from a low potential to a high potential, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on, and the light-emitting device LED starts to emit light.
  • first scan signal S1 may be, but is not limited to, the Nth-level scan signal SCAN(N), and may also be other types of square wave signals.
  • the second scan signal S2 may be, but is not limited to, the N-1 th scan signal SCAN(N-1), and may also be other types of square wave signals.
  • the first power supply signal VDD may be a DC high level signal
  • the second power supply signal VSS may be a DC low level signal
  • the present application provides a display panel, which includes the pixel circuit in any of the above embodiments.
  • the size of the first driving transistor T4 and the size of the second driving transistor T5 may be the same and larger than that of the first light emission control transistor T6 Or the size of the second light emission control transistor T7.
  • the size of the first light-emitting control transistor T6 may be, but not limited to, the same as the size of the second light-emitting control transistor T7.
  • the size of any one of the first switching transistor T2, the second switching transistor T3, the writing transistor T8, the compensation transistor T9 and the initialization transistor T1 is smaller than that of the first light emitting transistor or the second light emitting transistor.
  • the display panel provided by this embodiment can control the first driving transistor T4 and the second driving transistor T5 to work alternately through the first switching transistor T2 and the second switching transistor T3, which can improve the stability of the driving transistor, thereby enhancing the pixel circuit and the display panel. reliability and service life.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开了一种像素电路及显示面板，其包括第一驱动晶体管、第二驱动晶体管、第一切换晶体管以及第二切换晶体管；通过第一切换晶体管、第二切换晶体管控制第一驱动晶体管和第二驱动晶体管交替工作，可以缩短第一驱动晶体管和/或第二驱动晶体管的工作周期，能够提高驱动晶体管的稳定性。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及面内驱动技术领域，具体涉及一种像素电路和显示面板。
 背景技术
当今，社会科技迅猛发展，显示面板也被越来越多的应用在工作和生活中。因此，人们对于显示面板的要求也是越来越高。Mini-LED由于其独特的优势，如对比度高，稳定性好，制程较micro-LED简单等优势，逐渐越来越受到广泛的关注。
但是，Mini-LED所需的电流较大，驱动薄膜晶体管（TFT）长期承受大电流的工作环境，其稳定性较差，进而容易造成显示不均一甚至是显示失效等问题。
 技术问题
本申请提供一种像素电路及显示面板，解决了像素电路中驱动晶体管长期处于工作状态，导致其稳定性较差的问题。
 技术解决方案
第一方面，本申请提供一种像素电路，其包括第一驱动晶体管、第二驱动晶体管、第一切换晶体管以及第二切换晶体管；第一驱动晶体管串接于第一电源信号与第二电源信号构成的发光回路，用于控制流经发光回路的电流；第二驱动晶体管与第一驱动晶体管并联且串接于发光回路，用于控制流经发光回路的电流；第一切换晶体管的输出端与第一驱动晶体管的控制端连接，用于根据第一控制信号控制第一驱动晶体管；第二切换晶体管的输出端与第二驱动晶体管的控制端连接，用于根据第二控制信号控制第二驱动晶体管；其中，第一驱动晶体管与第二驱动晶体管交替工作。
基于第一方面，在第一方面的第一种实施方式中，像素电路还包括写入晶体管，写入晶体管的输出端与第一驱动晶体管的输出端和第二驱动晶体管的输出端连接，用于根据第一扫描信号控制数据信号写入至像素电路。
基于第一方面的第一种实施方式，在第一方面的第二种实施方式中，像素电路还包括补偿晶体管，补偿晶体管的输入端与第一驱动晶体管的输入端和第二驱动晶体管的输入端连接，补偿晶体管的输出端与第一切换晶体管的输入端和第二切换晶体管的输入端连接，补偿晶体管的控制端用于接入第一扫描信号。
基于第一方面的第二种实施方式，在第一方面的第三种实施方式中，像素电路还包括存储电容，存储电容的第一端与补偿晶体管的输出端连接，存储电容的第二端与第二电源信号连接。
基于第一方面的第三种实施方式，在第一方面的第四种实施方式中，像素电路还包括初始化晶体管，初始化晶体管的输出端与存储电容的第一端连接，用于根据第二扫描信号初始化存储电容的第一端的电位至初始电压信号的电位。
基于第一方面的第四种实施方式，在第一方面的第五种实施方式中，像素电路还包括第一发光控制晶体管和第二发光控制晶体管；第一发光控制晶体管串接于发光回路且第一发光控制晶体管的输出端与第一驱动晶体管的输入端和第二驱动晶体管的输入端连接，用于根据发光控制信号通断控制发光回路；第二发光控制晶体管串接于发光回路且第二发光控制晶体管的输入端与第一驱动晶体管的输出端和第二驱动晶体管的输出端连接，用于根据发光控制信号通断控制发光回路。
基于第一方面的第五种实施方式，在第一方面的第六种实施方式中，像素电路还包括发光器件，发光器件串接于发光回路，且发光器件的输入端与第一电源信号连接，或者，发光器件的输出端与第二电源信号连接。
基于第一方面的任一实施方式，在第一方面的第七种实施方式中，第一电源信号的电位大于第二电源信号的电位。
基于第一方面的任一实施方式，在第一方面的第八种实施方式中，第一驱动晶体管、第二驱动晶体管、第一切换晶体管、第二切换晶体管、写入晶体管、补偿晶体管、初始化晶体管、第一发光控制晶体管以及第二发光控制晶体管中至少一个为N型薄膜晶体管。
第二方面，本申请提供一种显示面板，其包括上述任一实施方式中的像素电路。
 有益效果
本申请提供的像素电路及显示面板，通过第一切换晶体管、第二切换晶体管控制第一驱动晶体管和第二驱动晶体管交替工作，可以缩短第一驱动晶体管和/或第二驱动晶体管的工作周期，能够提高驱动晶体管的稳定性，进而增强像素电路及显示面板的信赖性和使用寿命。
 附图说明
图1为本申请实施例提供的像素电路的第一种结构示意图。
图2为本申请实施例提供的像素电路的第二种结构示意图。
图3为本申请实施例提供的像素电路的时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1或者图2所示，本实施例提供了一种像素电路，其包括第一驱动晶体管T4、第二驱动晶体管T5、第一切换晶体管T2以及第二切换晶体管T3；第一驱动晶体管T4串接于第一电源信号VDD与第二电源信号VSS构成的发光回路，用于控制流经发光回路的电流；第二驱动晶体管T5与第一驱动晶体管T4并联且串接于发光回路，用于控制流经发光回路的电流；第一切换晶体管T2的输出端与第一驱动晶体管T4的控制端连接，用于根据第一控制信号LC1控制第一驱动晶体管T4；第二切换晶体管T3的输出端与第二驱动晶体管T5的控制端连接，用于根据第二控制信号LC2控制第二驱动晶体管T5；其中，第一驱动晶体管T4与第二驱动晶体管T5交替工作。
其中，在本实施例中，第一切换晶体管T2、第二切换晶体管T3可以但不限于为同类型的薄膜晶体管，例如，可以均为N沟道型薄膜晶体管，也可以均为P沟道型薄膜晶体管。对应地，第一控制信号LC1、第二控制信号LC2的工作周期是交替的或者至少部分重叠的。
当第一切换晶体管T2、第二切换晶体管T3均为N沟道型薄膜晶体管时，第一控制信号LC1、第二控制信号LC2的工作周期是其位于高电平持续期间，那么可以理解的是，当第一控制信号LC1、第二控制信号LC2的工作周期以交替方式进行工作时，可以是第一控制信号LC1的下降沿与第二控制信号LC2的上升沿相重合或者是在同一时刻，也可以是第二控制信号LC2的上升沿位于第一控制信号LC1的上升沿与下降沿之间。
当第一切换晶体管T2、第二切换晶体管T3均为P沟道型薄膜晶体管时，第一控制信号LC1、第二控制信号LC2的工作周期是其位于低电平持续期间，那么可以理解的是，当第一控制信号LC1、第二控制信号LC2的工作周期以交替方式进行工作时，可以是第一控制信号LC1的上升沿与第二控制信号LC2的下降沿相重合或者是在同一时刻，也可以是第二控制信号LC2的下降沿位于第一控制信号LC1的下降沿与上升沿之间。
同样地，第一切换晶体管T2可以为N沟道型薄膜晶体管，第二切换晶体管T3可以为P沟道型薄膜晶体管；或者，第一切换晶体管T2可以为P沟道型薄膜晶体管，第二切换晶体管T3可以为N沟道型薄膜晶体管。这样的话，还可以采用第一控制信号LC1、第二控制信号LC2中任一控制信号即可，例如，第一控制信号LC1或者第二控制信号LC2与第一切换晶体管T2的控制端和第二切换晶体管T3的控制端连接，此时，第一控制信号LC1或者第二控制信号LC2处于高电位状态时，第一切换晶体管T2打开，第二切换晶体管T3关闭；或者第一切换晶体管T2关闭，第二切换晶体管T3打开。第一控制信号LC1或者第二控制信号LC2处于低电位状态时，第一切换晶体管T2关闭，第二切换晶体管T3打开；或者第一切换晶体管T2打开，第二切换晶体管T3关闭。
通过上述可知，第一切换晶体管T2可以控制第一驱动晶体管T4的控制端是否接入对应的驱动信号，第二切换晶体管T3可以控制第二驱动晶体管T5的控制端是否接入对应的驱动信号，以便第一驱动晶体管T4与第二驱动晶体管T5可以进行交替工作，使得驱动晶体管可以得到对应的轮休，有利于恢复驱动晶体管的电特性，进而提高驱动晶体管的工作稳定性，从而提升驱动电路整体的工作寿命，增强其信赖性。
综上所述，本申请实施例提供的像素电路，通过第一切换晶体管T2、第二切换晶体管T3控制第一驱动晶体管T4和第二驱动晶体管T5交替工作，可以提高驱动晶体管的稳定性，进而增强像素电路及显示面板的信赖性和使用寿命。
如图1或者图2所示，在其中一个实施例中，像素电路还包括写入晶体管T8，写入晶体管T8的输出端与第一驱动晶体管T4的输出端和第二驱动晶体管T5的输出端连接，用于根据第一扫描信号S1控制数据信号Vdata写入至像素电路。
如图1或者图2所示，在其中一个实施例中，像素电路还包括补偿晶体管T9，补偿晶体管T9的输入端与第一驱动晶体管T4的输入端和第二驱动晶体管T5的输入端连接，补偿晶体管T9的输出端与第一切换晶体管T2的输入端和第二切换晶体管T3的输入端连接，补偿晶体管T9的控制端用于接入第一扫描信号S1。
如图1或者图2所示，在其中一个实施例中，像素电路还包括存储电容C1，存储电容C1的第一端与补偿晶体管T9的输出端连接，存储电容C1的第二端与第二电源信号VSS连接。
如图1或者图2所示，在其中一个实施例中，像素电路还包括初始化晶体管T1，初始化晶体管T1的输出端与存储电容C1的第一端连接，用于根据第二扫描信号S2初始化存储电容C1的第一端的电位至初始电压信号VI的电位。
如图1或者图2所示，在其中一个实施例中，像素电路还包括第一发光控制晶体管T6和第二发光控制晶体管T7；第一发光控制晶体管T6串接于发光回路且第一发光控制晶体管T6的输出端与第一驱动晶体管T4的输入端和第二驱动晶体管T5的输入端连接，用于根据发光控制信号EM通断控制发光回路；第二发光控制晶体管T7串接于发光回路且第二发光控制晶体管T7的输入端与第一驱动晶体管T4的输出端和第二驱动晶体管T5的输出端连接，用于根据发光控制信号EM通断控制发光回路。
在其中一个实施例中，像素电路还包括发光器件LED，发光器件LED串接于发光回路，且发光器件LED的输入端与第一电源信号VDD连接，或者，发光器件LED的输出端与第二电源信号VSS连接。
需要进行说明的是，如图1所示，发光器件LED的输入端可以与第一电源信号VDD连接，发光器件LED的输出端可以与第一发光控制晶体管T6的输入端连接。也可以是如图2所示，发光器件LED的输入端可以与第二发光控制晶体管T7的输出端连接，发光器件LED的输出端与第二电源信号VSS连接。
其中，本实例中的发光器件LED可以为mini-led、micro-led以及oled中的任一种。
在其中一个实施例中，第一电源信号VDD的电位大于第二电源信号VSS的电位。
在其中一个实施例中，第一驱动晶体管T4、第二驱动晶体管T5、第一切换晶体管T2、第二切换晶体管T3、写入晶体管T8、补偿晶体管T9、初始化晶体管T1、第一发光控制晶体管T6以及第二发光控制晶体管T7中至少一个为N型薄膜晶体管。
需要进行说明的是，第一控制信号LC1和/或第二控制信号LC2可以但不限于为频率较低或者低频率的时钟信号。
需要进行说明的是，在本申请的实施例中描述的对应晶体管的输入端可以是其漏极，也可以是其源极。在本申请的实施例中描述的对应晶体管的输出端可以是其漏极，也可以是其源极。在本申请的实施例中描述的对应晶体管的控制端是其栅极。
如图3所示，本实例提供的两种结构的像素电路的工作时序可以包括如下阶段：
复位阶段，当第N-1级扫描信号SCAN（N-1）从低电位变成高电位，初始化晶体管T1打开，即可向Q点写入初始电压信号VI，实现复位。
其中，第一控制信号LC1和第二控制信号LC2为低频时钟信号，互为反相，一个为高电位（VGH），另一个为低电位（VGL）。所以，第一切换晶体管T2和第二切换晶体管T3是其中一个处于开态，则另一个处于关态。通过第一控制信号LC1和第二控制信号LC2来控制是第一驱动晶体管T4或第二驱动晶体管T5工作，这样它们就可以一半时间工作一半时间休息，使得对应的驱动晶体管的电性得以恢复，从而稳定性和信赖性得到提升。
补偿阶段，当第N级扫描信号SCAN（N）从低电位变成高电位，写入晶体管T8和补偿晶体管T9打开，将数据信号Vdata写入到Q点，同时完成对应驱动晶体管的阈值电压（Vth）补偿。
发光阶段，发光控制信号EM从低电位变成高电位，第一发光控制晶体管T6和第二发光控制晶体管T7打开，发光器件LED开始发光。
需要进行说明的是，第一扫描信号S1可以但不限于为第N级扫描信号SCAN（N），也可以是其它类的方波信号。第二扫描信号S2可以但不限于为第N-1级扫描信号SCAN（N-1），也可以是其它类的方波信号。
需要进行说明的是，第一电源信号VDD可以为直流高电位信号，第二电源信号VSS可以为直流低电位信号。
在其中一个实施例中，本申请提供一种显示面板，其包括上述任一实施例中的像素电路。
需要进行说明的是，像素电路中的晶体管以薄膜形成于显示面板的膜层结构中时，第一驱动晶体管T4的尺寸与第二驱动晶体管T5的尺寸可以相同，且大于第一发光控制晶体管T6或者第二发光控制晶体管T7的尺寸。其中，第一发光控制晶体管T6的尺寸可以但不限于与第二发光控制晶体管T7的尺寸相同。第一切换晶体管T2、第二切换晶体管T3、写入晶体管T8、补偿晶体管T9以及初始化晶体管T1中任一晶体管的尺寸均小于第一发光晶体管或者第二发光晶体管的尺寸。
本实施例提供的显示面板可以通过第一切换晶体管T2、第二切换晶体管T3控制第一驱动晶体管T4和第二驱动晶体管T5交替工作，可以提高驱动晶体管的稳定性，进而增强像素电路及显示面板的信赖性和使用寿命。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，其中，包括：
    第一驱动晶体管，串接于第一电源信号与第二电源信号构成的发光回路，用于控制流经所述发光回路的电流；
    第二驱动晶体管，与所述第一驱动晶体管并联且串接于所述发光回路，用于控制流经所述发光回路的电流；
    第一切换晶体管，所述第一切换晶体管的输出端与所述第一驱动晶体管的控制端连接，用于根据第一控制信号控制所述第一驱动晶体管；以及
    第二切换晶体管，所述第二切换晶体管的输出端与所述第二驱动晶体管的控制端连接，用于根据第二控制信号控制所述第二驱动晶体管；
    其中，所述第一驱动晶体管与所述第二驱动晶体管交替工作。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    写入晶体管，所述写入晶体管的输出端与所述第一驱动晶体管的输出端和所述第二驱动晶体管的输出端连接，用于根据第一扫描信号控制数据信号写入至所述像素电路。
  3. 根据权利要求2所述的像素电路，其中，所述像素电路还包括：
    补偿晶体管，所述补偿晶体管的输入端与所述第一驱动晶体管的输入端和所述第二驱动晶体管的输入端连接，所述补偿晶体管的输出端与所述第一切换晶体管的输入端和所述第二切换晶体管的输入端连接，所述补偿晶体管的控制端用于接入所述第一扫描信号。
  4. 根据权利要求3所述的像素电路，其中，所述像素电路还包括：
    存储电容，所述存储电容的第一端与所述补偿晶体管的输出端连接，所述存储电容的第二端与所述第二电源信号连接。
  5. 根据权利要求4所述的像素电路，其中，所述像素电路还包括：
    初始化晶体管，所述初始化晶体管的输出端与所述存储电容的第一端连接，用于根据第二扫描信号初始化所述存储电容的第一端的电位至初始电压信号的电位。
  6. 根据权利要求5所述的像素电路，其中，所述像素电路还包括：
    第一发光控制晶体管，串接于所述发光回路且第一发光控制晶体管的输出端与所述第一驱动晶体管的输入端和所述第二驱动晶体管的输入端连接，用于根据发光控制信号通断控制所述发光回路；和
    第二发光控制晶体管，串接于所述发光回路且第二发光控制晶体管的输入端与所述第一驱动晶体管的输出端和所述第二驱动晶体管的输出端连接，用于根据所述发光控制信号通断控制所述发光回路。
  7. 根据权利要求6所述的像素电路，其中，所述像素电路还包括：
    发光器件，所述发光器件串接于所述发光回路，且所述发光器件的输入端与所述第一电源信号连接，或者，所述发光器件的输出端与所述第二电源信号连接。
  8. 根据权利要求1所述的像素电路，其中，所述第一电源信号的电位大于所述第二电源信号的电位。
  9. 根据权利要求1所述的像素电路，其中，所述第一驱动晶体管、所述第二驱动晶体管、所述第一切换晶体管、所述第二切换晶体管、所述写入晶体管、所述补偿晶体管、所述初始化晶体管、所述第一发光控制晶体管以及所述第二发光控制晶体管中至少一个为N型薄膜晶体管。
  10. 一种显示面板，其中，包括如权利要求1所述的像素电路。
  11. 根据权利要求10所述的显示面板，其中，所述第一驱动晶体管的尺寸与所述第二驱动晶体管的尺寸相同；所述第一切换晶体管的尺寸与所述第二切换晶体管的尺寸相同；且所述第一驱动晶体管的尺寸大于所述第一切换晶体管的尺寸。
  12. 根据权利要求11所述的显示面板，其中，所述像素电路还包括：
    写入晶体管，所述写入晶体管的输出端与所述第一驱动晶体管的输出端和所述第二驱动晶体管的输出端连接，用于根据第一扫描信号控制数据信号写入至所述像素电路。
  13. 根据权利要求12所述的显示面板，其中，所述像素电路还包括：
    补偿晶体管，所述补偿晶体管的输入端与所述第一驱动晶体管的输入端和所述第二驱动晶体管的输入端连接，所述补偿晶体管的输出端与所述第一切换晶体管的输入端和所述第二切换晶体管的输入端连接，所述补偿晶体管的控制端用于接入所述第一扫描信号。
  14. 根据权利要求13所述的显示面板，其中，所述像素电路还包括：
    存储电容，所述存储电容的第一端与所述补偿晶体管的输出端连接，所述存储电容的第二端与所述第二电源信号连接。
  15. 根据权利要求14所述的显示面板，其中，所述像素电路还包括：
    初始化晶体管，所述初始化晶体管的输出端与所述存储电容的第一端连接，用于根据第二扫描信号初始化所述存储电容的第一端的电位至初始电压信号的电位。
  16. 根据权利要求15所述的显示面板，其中，所述像素电路还包括：
    第一发光控制晶体管，串接于所述发光回路且第一发光控制晶体管的输出端与所述第一驱动晶体管的输入端和所述第二驱动晶体管的输入端连接，用于根据发光控制信号通断控制所述发光回路；和
    第二发光控制晶体管，串接于所述发光回路且第二发光控制晶体管的输入端与所述第一驱动晶体管的输出端和所述第二驱动晶体管的输出端连接，用于根据所述发光控制信号通断控制所述发光回路。
  17. 根据权利要求16所述的显示面板，其中，所述像素电路还包括：
    发光器件，所述发光器件串接于所述发光回路，且所述发光器件的输入端与所述第一电源信号连接，或者，所述发光器件的输出端与所述第二电源信号连接。
  18. 根据权利要求17所述的显示面板，其中，所述第一电源信号的电位大于所述第二电源信号的电位。
  19. 根据权利要求18所述的显示面板，其中，所述第一驱动晶体管、所述第二驱动晶体管、所述第一切换晶体管、所述第二切换晶体管、所述写入晶体管、所述补偿晶体管、所述初始化晶体管、所述第一发光控制晶体管以及所述第二发光控制晶体管中至少一个为N型薄膜晶体管。
  20. 根据权利要求16所述的显示面板，其中，所述第一发光控制晶体管的尺寸与所述第二发光控制晶体管的尺寸相同；所述第一驱动晶体管的尺寸大于所述第一发光控制晶体管的尺寸；且所述第一发光控制晶体管的尺寸大于所述第一切换晶体管的尺寸。
PCT/CN2020/114778 2020-08-27 2020-09-11 像素电路及显示面板 WO2022041329A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/051,778 US11238784B1 (en) 2020-08-27 2020-09-11 Pixel circuit and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010881106.2 2020-08-27
CN202010881106.2A CN111986615B (zh) 2020-08-27 2020-08-27 像素电路及显示面板

Publications (1)

Publication Number Publication Date
WO2022041329A1 true WO2022041329A1 (zh) 2022-03-03

Family

ID=73440142

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/114778 WO2022041329A1 (zh) 2020-08-27 2020-09-11 像素电路及显示面板

Country Status (2)

Country Link
CN (1) CN111986615B (zh)
WO (1) WO2022041329A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112767881A (zh) * 2021-02-10 2021-05-07 Tcl华星光电技术有限公司 像素驱动电路及显示面板
CN114927095A (zh) * 2022-05-25 2022-08-19 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003022049A (ja) * 2001-07-09 2003-01-24 Seiko Epson Corp 回路、駆動回路、有機エレクトロルミネッセンスディスプレイ装置、電気光学装置、電子機器、有機エレクトロルミネッセンス画素への電流供給を制御する方法、及び回路を駆動する方法
KR20090057709A (ko) * 2007-12-03 2009-06-08 엘지디스플레이 주식회사 유기전계발광표시장치
CN103927991A (zh) * 2014-04-29 2014-07-16 何东阳 一种amoled像素电路
CN107342043A (zh) * 2017-08-15 2017-11-10 上海天马微电子有限公司 像素驱动电路及其控制方法、显示面板和显示装置
CN109410841A (zh) * 2018-11-16 2019-03-01 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法
CN111210762A (zh) * 2019-07-17 2020-05-29 友达光电股份有限公司 像素电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4650601B2 (ja) * 2001-09-05 2011-03-16 日本電気株式会社 電流駆動素子の駆動回路及び駆動方法ならびに画像表示装置
CN100353399C (zh) * 2003-05-29 2007-12-05 友达光电股份有限公司 主动式有机电激发光显示单元
KR101066414B1 (ko) * 2004-05-19 2011-09-21 재단법인서울대학교산학협력재단 유기발광소자의 구동소자 및 구동방법과, 이를 갖는표시패널 및 표시장치
CN201177956Y (zh) * 2008-04-07 2009-01-07 上海广电光电子有限公司 一种改善有机发光器件寿命的像素电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003022049A (ja) * 2001-07-09 2003-01-24 Seiko Epson Corp 回路、駆動回路、有機エレクトロルミネッセンスディスプレイ装置、電気光学装置、電子機器、有機エレクトロルミネッセンス画素への電流供給を制御する方法、及び回路を駆動する方法
KR20090057709A (ko) * 2007-12-03 2009-06-08 엘지디스플레이 주식회사 유기전계발광표시장치
CN103927991A (zh) * 2014-04-29 2014-07-16 何东阳 一种amoled像素电路
CN107342043A (zh) * 2017-08-15 2017-11-10 上海天马微电子有限公司 像素驱动电路及其控制方法、显示面板和显示装置
CN109410841A (zh) * 2018-11-16 2019-03-01 京东方科技集团股份有限公司 像素电路、显示装置和像素驱动方法
CN111210762A (zh) * 2019-07-17 2020-05-29 友达光电股份有限公司 像素电路

Also Published As

Publication number Publication date
CN111986615B (zh) 2021-08-03
CN111986615A (zh) 2020-11-24

Similar Documents

Publication Publication Date Title
CN104700776B (zh) 像素电路及其驱动方法、显示装置
TWI534781B (zh) Scan drive circuit and organic light emitting display
WO2023000448A1 (zh) 像素驱动电路、显示面板及显示设备
WO2015143835A1 (zh) 像素补偿电路、阵列基板及显示装置
WO2021000816A1 (zh) 像素电路及其驱动方法、显示装置
US11222594B2 (en) Digital pixel driving circuit and digital pixel driving method
WO2021109237A1 (zh) 像素电路及驱动方法
WO2021046999A1 (zh) 一种oled像素补偿电路及像素补偿方法
US11501713B2 (en) Pixel circuit, driving method thereof and display device
WO2022041329A1 (zh) 像素电路及显示面板
WO2023115533A1 (zh) 像素电路以及显示面板
WO2021012559A1 (zh) 像素驱动电路和显示面板
TWM573055U (zh) Pixel circuit and display device
WO2022016722A1 (zh) 像素电路及其驱动方法
WO2022170700A1 (zh) 像素驱动电路及显示面板
WO2023103038A1 (zh) 像素电路及显示面板
CN115148144A (zh) 像素电路及显示面板
WO2022233083A1 (zh) 像素驱动电路、像素驱动方法及显示装置
WO2020199774A1 (zh) 像素驱动电路及其驱动方法以及显示面板
WO2020006854A1 (zh) 一种像素驱动电路及显示面板
TW202420284A (zh) 具有波寬補償的畫素電路及其操作方法
US11238784B1 (en) Pixel circuit and display panel
TWI721561B (zh) 畫素電路
TWI723903B (zh) 畫素驅動電路
TW202233016A (zh) 畫素電路及其驅動方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20950998

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20950998

Country of ref document: EP

Kind code of ref document: A1