WO2021012559A1 - 像素驱动电路和显示面板 - Google Patents

像素驱动电路和显示面板 Download PDF

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Publication number
WO2021012559A1
WO2021012559A1 PCT/CN2019/121182 CN2019121182W WO2021012559A1 WO 2021012559 A1 WO2021012559 A1 WO 2021012559A1 CN 2019121182 W CN2019121182 W CN 2019121182W WO 2021012559 A1 WO2021012559 A1 WO 2021012559A1
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Prior art keywords
thin film
film transistor
unit
reset
control signal
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PCT/CN2019/121182
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English (en)
French (fr)
Inventor
蔡振飞
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/625,717 priority Critical patent/US20210350744A1/en
Publication of WO2021012559A1 publication Critical patent/WO2021012559A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • This application relates to the field of electronic display, and in particular to a pixel drive circuit and a display panel.
  • the existing display panel usually uses a thin film transistor layer as a driving circuit of the display panel. Affected by the manufacturing process, transistor parameters and circuit voltage, the threshold voltage of different thin film transistors is often slightly different. At the same time, when the circuit is working, the voltage change of each node will also cause the threshold voltage of the thin film transistor to drift. Therefore, in order to eliminate the negative impact of the difference and change of the threshold voltage of the thin film transistor on the circuit, it is usually necessary to add a compensation module in the driving circuit.
  • Fig. 1 is a driving circuit commonly used in the prior art.
  • the reset circuit and compensation circuit located on both sides of the drive circuit eliminate the correlation between the threshold voltage and the drive current.
  • this circuit has a relatively large number of transistors and capacitors, and the timing is complicated, which makes it difficult to ensure the accuracy of compensation.
  • the present application provides a pixel driving circuit and a display panel, which can simplify the structure and timing of the pixel driving circuit in the prior art.
  • the present application provides a pixel drive circuit, the pixel drive circuit includes a reset unit, a compensation unit and a drive unit; wherein,
  • the first input terminal of the reset unit is connected to a reset voltage
  • the second input terminal is connected to a first control signal
  • the output terminal is connected to the drive unit.
  • the reset unit provides a reset signal to the drive unit according to the first control signal ;
  • the input end of the compensation unit is connected to a data signal, and the output end is connected to the drive unit, and the compensation unit provides a compensation signal for the drive unit according to the data signal;
  • the first input terminal of the driving unit is connected to the reset unit, the second input terminal is connected to the compensation unit, the third input terminal is connected to a second control signal, and the output terminal is connected to a second power supply voltage.
  • the driving unit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor; wherein,
  • the source of the first thin film transistor is connected to the first power supply voltage, the gate is connected to the second control signal, and the drain is connected to the source of the second thin film transistor;
  • the gate of the second thin film transistor is connected to the reset signal, and the drain is connected to the source of the third thin film transistor;
  • the gate of the third thin film transistor is connected to the second control signal, and the drain is connected to the input terminal of the organic light emitting diode to be driven.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor are N-type thin film transistors.
  • the compensation unit includes a fourth thin film transistor and a storage capacitor; wherein,
  • the source of the fourth thin film transistor is connected to the data signal, the gate is connected to the first control signal, and the drain is connected to a plate of the storage capacitor and the drain of the second thin film transistor;
  • the other plate of the storage capacitor is connected to the gate of the second thin film transistor.
  • the fourth thin film transistor is an N-type thin film transistor.
  • the aspect ratios of the first thin film transistor, the second thin film transistor, and the third thin film transistor are equal and greater than the aspect ratio of the fourth thin film transistor.
  • the reset unit includes a fifth thin film transistor and a sixth thin film transistor; wherein,
  • the source of the fifth thin film transistor is connected to the source of the second thin film transistor, the gate is connected to the first control signal, and the drain is connected to the gate of the second thin film transistor;
  • the source of the sixth thin film transistor is connected to the reset voltage, the gate is connected to the first control signal, and the drain is connected to the gate of the second thin film transistor.
  • the fifth thin film transistor and the sixth thin film transistor are N-type thin film transistors.
  • the aspect ratios of the fifth thin film transistor and the sixth thin film transistor are equal.
  • the present application also provides a display panel, the display panel includes a pixel drive circuit, and the pixel drive circuit includes a reset unit, a compensation unit, and a drive unit; wherein,
  • the first input terminal of the reset unit is connected to a reset voltage
  • the second input terminal is connected to a first control signal
  • the output terminal is connected to the drive unit.
  • the reset unit provides a reset signal to the drive unit according to the first control signal ;
  • the input end of the compensation unit is connected to a data signal, and the output end is connected to the drive unit, and the compensation unit provides a compensation signal for the drive unit according to the data signal;
  • the first input terminal of the driving unit is connected to the reset unit, the second input terminal is connected to the compensation unit, the third input terminal is connected to a second control signal, and the output terminal is connected to a second power supply voltage.
  • the thin film transistors used in the pixel drive circuit of the present application are all N-type thin film transistors. Compared with a drive circuit that uses both N-type thin film transistors and N-type thin film transistors, the manufacturing process of the drive circuit of the present application is simpler. At the same time, this application only needs one storage capacitor, and the corresponding circuit sequence is simple, which is convenient for mass production.
  • FIG. 1 is a circuit diagram of a pixel driving circuit in the prior art
  • FIG. 2 is a circuit diagram of a pixel driving circuit in a specific embodiment of the application
  • FIG. 3 is a timing diagram of the pixel driving circuit in FIG. 2.
  • Fig. 1 is a driving circuit commonly used in the prior art.
  • the reset circuit and compensation circuit located on both sides of the drive circuit eliminate the correlation between the threshold voltage and the drive current.
  • this circuit has a relatively large number of transistors and capacitors, and the timing is complicated, which makes it difficult to ensure the accuracy of compensation.
  • the present application provides a pixel driving circuit and a display panel, which can simplify the structure and timing of the pixel driving circuit in the prior art.
  • FIG. 2 is a circuit diagram of a pixel driving circuit in a specific embodiment of the application.
  • the pixel driving circuit includes a reset unit B, a compensation unit C, and a driving unit.
  • the first input terminal of the drive unit A is connected to the reset unit B
  • the second input terminal is connected to the compensation unit C
  • the third input terminal is connected to the second control signal G2
  • the output terminal is connected to the second control signal G2.
  • Two power supply voltage VSS Two power supply voltage VSS.
  • the driving unit A includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.
  • the first input terminal of the driving unit A is the gate of the second thin film transistor T2
  • the second input terminal is the drain of the second thin film transistor T2
  • the third input terminal is the first thin film transistor T1.
  • the organic light emitting diode OLED to be driven is connected to the drain of the third thin film transistor T3.
  • the source of the first thin film transistor T1 is connected to the first power supply voltage VDD
  • the gate is connected to the second control signal G2
  • the drain is connected to the source of the second thin film transistor T2.
  • the gate of the second thin film transistor T2 is connected to the reset signal, and the drain is connected to the source of the third thin film transistor T3.
  • the gate of the third thin film transistor T3 is connected to the second control signal G2, and the drain is connected to the input terminal of the organic light emitting diode.
  • the output terminal of the organic light emitting diode OLED is connected to the second power supply voltage VSS.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are N-type thin film transistors, and the light emitting diodes are organic light emitting diodes.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 have the same aspect ratio.
  • the input terminal of the compensation unit C is connected to a data signal Vdata, and the output terminal is connected to the driving unit.
  • the compensation unit C provides a compensation signal for the driving unit A according to the data signal Vdata.
  • the compensation unit C includes a fourth thin film transistor T4 and a storage capacitor C1.
  • the input terminal of the compensation unit C is the source of the fourth thin film transistor T4, and the output terminal is the drain of the fourth thin film transistor T4.
  • the source of the fourth thin film transistor T4 is connected to the data signal Vdata, the gate is connected to the first control signal G1, and the drain is connected to a plate of the storage capacitor C1 and the drain of the second thin film transistor T2. pole.
  • the other plate of the storage capacitor C1 is connected to the gate of the second thin film transistor T2.
  • the fourth thin film transistor T4 is an N-type thin film transistor.
  • the aspect ratios of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are equal and greater than the aspect ratio of the fourth thin film transistor T4.
  • the first input terminal of the reset unit B is connected to the reset voltage Vref, the second input terminal is connected to the first control signal G1, and the output terminal is connected to the driving unit.
  • the reset unit B is based on the first control signal G1.
  • the drive unit A provides a reset signal.
  • the reset unit B includes a fifth thin film transistor T5 and a sixth thin film transistor T6. Wherein, the first input terminal of the reset unit B is the source of the sixth thin film transistor T6, the second input terminal is the gate of the fifth thin film transistor T5 and the sixth thin film transistor T6, and the output terminal is the fifth thin film transistor T5 The drain.
  • the source of the fifth thin film transistor T5 is connected to the source of the second thin film transistor T2, the gate is connected to the first control signal G1, and the drain is connected to the gate of the second thin film transistor T2.
  • the source of the sixth thin film transistor T6 is connected to the reset voltage Vref, the gate is connected to the first control signal G1, and the drain is connected to the gate of the second thin film transistor T2.
  • the fifth thin film transistor T5 and the sixth thin film transistor T6 are N-type thin film transistors, and the aspect ratios of the fifth thin film transistor T5 and the sixth thin film transistor T6 are equal.
  • FIG. 3 is a timing diagram of the pixel driving circuit in FIG.
  • the first control signal G1 is at a high level.
  • the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned on, and the high level of the reset signal Vref is written into the gate and drain of the second thin film transistor T2, and the source of the second thin film transistor T2 Extremely write low level to realize the reset of the second thin film transistor T2.
  • the data signal Vdata is at a high level, and the second thin film transistor T2 is turned on due to the short-circuit of the gate and the drain, and continues to discharge, so that the voltage between the gate and the drain is gradually reduced.
  • the first control signal G1 is at a low level.
  • the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned off, the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the drain current I of the driving tube second thin film transistor T2 conforms to the following formula: The compensation of the threshold voltage is realized.
  • the thin film transistors used in the pixel drive circuit of the present application are all N-type thin film transistors. Compared with a drive circuit that uses both N-type thin film transistors and N-type thin film transistors, the manufacturing process of the drive circuit of the present application is simpler. At the same time, this application only needs one storage capacitor, and the corresponding circuit sequence is simple, which is convenient for mass production.
  • the present application also provides a display panel including the pixel driving circuit as described above.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路和显示面板,像素驱动电路包括复位单元（B）、补偿单元（C）和驱动单元（A）。复位单元（B）根据第一控制信号（G1）为驱动单元（A）提供复位信号，补偿单元（C）根据数据信号（Vdata）为驱动单元（A）提供补偿信号。驱动单元（A）的第一输入端连接复位单元（B），第二输入端连接补偿单元（C），第三输入端接入第二控制信号（G2），输出端连接第二电源电压（VSS）。

Description

像素驱动电路和显示面板 技术领域
本申请涉及电子显示领域，尤其涉及一种像素驱动电路和显示面板。
 背景技术
现有的显示面板通常使用薄膜晶体管层作为显示面板的驱动电路。受制作工艺、晶体管参数和电路电压的影响，不同薄膜晶体管的阈值电压往往略有差异。同时，在电路工作时，各个节点的电压变化也会导致薄膜晶体管的阈值电压发生漂移。因此，为了消除薄膜晶体管的阈值电压的差异和变化对电路带来的负面影响，通常去要在驱动电路中增加补偿模块。
 技术问题
图1是现有技术中常用的驱动电路。通过位于驱动电路两侧的复位电路和补偿电路消除了阈值电压和驱动电流的相关性，然而这种电路的晶体管和电容的数量都比较多，且时序复杂，难以保证补偿的准确性。
 技术解决方案
本申请提供了一种像素驱动电路和显示面板，能够简化现有技术中的像素驱动电路的结构和时序。
为解决上述问题，本申请提供了一种像素驱动电路，所述像素驱动电路包括复位单元、补偿单元和驱动单元；其中，
所述复位单元的第一输入端接入复位电压，第二输入端接入第一控制信号，输出端连接所述驱动单元，所述复位单元根据所述第一控制信号为驱动单元提供复位信号；
所述补偿单元的输入端接入数据信号，输出端连接所述驱动单元，所述补偿单元根据所述数据信号为驱动单元提供补偿信号；
所述驱动单元的第一输入端连接所述复位单元，第二输入端连接所述补偿单元，第三输入端接入第二控制信号，输出端连接第二电源电压。
根据本申请的其中一个方面，所述驱动单元包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管；其中，
所述第一薄膜晶体管的源极连接第一电源电压，栅极接入第二控制信号，漏极连接所述第二薄膜晶体管的源极；
所述第二薄膜晶体管的栅极连接所述复位信号，漏极连接所述第三薄膜晶体管的源极；
所述第三薄膜晶体管的栅极接入第二控制信号，漏极连接所述待驱动的有机发光二极管的输入端。
根据本申请的其中一个方面，所述第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管为N型薄膜晶体管。
根据本申请的其中一个方面，所述补偿单元包括第四薄膜晶体管和存储电容；其中，
所述第四薄膜晶体管的源极连接所述数据信号，栅极连接所述第一控制信号，漏极连接所述存储电容的一个极板和所述第二薄膜晶体管的漏极；
所述存储电容的另一个极板连接所述第二薄膜晶体管的栅极。
根据本申请的其中一个方面，所述第四薄膜晶体管为N型薄膜晶体管。
根据本申请的其中一个方面，所述第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管的宽长比相等且大于所述第四薄膜晶体管的宽长比。
根据本申请的其中一个方面，所述复位单元包括第五薄膜晶体管和第六薄膜晶体管；其中，
所述第五薄膜晶体管的源极连接第二薄膜晶体管的源极，栅极连接所述第一控制信号，漏极连接所述第二薄膜晶体管的栅极；
所述第六薄膜晶体管的源极连接所述复位电压，栅极连接所述第一控制信号，漏极连接所述第二薄膜晶体管的栅极。
根据本申请的其中一个方面，所述第五薄膜晶体管和第六薄膜晶体管为N型薄膜晶体管。
根据本申请的其中一个方面，所述第五薄膜晶体管和第六薄膜晶体管的宽长比相等。
相应的，本申请还提供了一种显示面板，所述显示面板包括像素驱动电路，所述像素驱动电路包括复位单元、补偿单元和驱动单元；其中，
所述复位单元的第一输入端接入复位电压，第二输入端接入第一控制信号，输出端连接所述驱动单元，所述复位单元根据所述第一控制信号为驱动单元提供复位信号；
所述补偿单元的输入端接入数据信号，输出端连接所述驱动单元，所述补偿单元根据所述数据信号为驱动单元提供补偿信号；
所述驱动单元的第一输入端连接所述复位单元，第二输入端连接所述补偿单元，第三输入端接入第二控制信号，输出端连接第二电源电压。
 有益效果
本申请的像素驱动电路使用的薄膜晶体管均为N型薄膜晶体管，相比于采用同时采用N型薄膜晶体管和N型薄膜晶体管的驱动电路，本申请的驱动电路的制备工艺更加简单。同时，本申请只需要一个存储电容，对应的电路时序简单，便于大规模量产。
 附图说明
图1为现有技术中的像素驱动电路的电路图；
图2为本申请的一个具体实施例中的像素驱动电路的电路图；
图3为图2中的像素驱动电路的时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
首先对现有技术进行简要说明，图1是现有技术中常用的驱动电路。通过位于驱动电路两侧的复位电路和补偿电路消除了阈值电压和驱动电流的相关性，然而这种电路的晶体管和电容的数量都比较多，且时序复杂，难以保证补偿的准确性。
因此，本申请提供了一种像素驱动电路和显示面板，能够简化现有技术中的像素驱动电路的结构和时序。
参见图2，图2为本申请的一个具体实施例中的像素驱动电路的电路图，所述像素驱动电路包括复位单元B、补偿单元C和驱动单元。
在本实施例中，所述驱动单元A的第一输入端连接所述复位单元B，第二输入端连接所述补偿单元C，第三输入端接入第二控制信号G2，输出端连接第二电源电压VSS。
在本实施例中，所述驱动单元A包括第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3。其中，所述驱动单元A的第一输入端为所述第二薄膜晶体管T2的栅极，第二输入端为所述第二薄膜晶体管T2的漏极，第三输入端为第一薄膜晶体管T1和第三薄膜晶体管T3栅极。本实施例中待驱动的有机发光二极管OLED连接所述第三薄膜晶体管T3的漏极。
具体的，所述第一薄膜晶体管T1的源极连接第一电源电压VDD，栅极接入第二控制信号G2，漏极连接所述第二薄膜晶体管T2的源极。所述第二薄膜晶体管T2的栅极连接所述复位信号，漏极连接所述第三薄膜晶体管T3的源极。所述第三薄膜晶体管T3的栅极接入第二控制信号G2，漏极连接所述有机发光二极管的输入端。所述有机发光二极管OLED的输出端连接所述第二电源电压VSS。
在本实施例中，所述第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3为N型薄膜晶体管，所述发光二极管为有机发光二极管。所述第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3具有相同的宽长比。
所述补偿单元C的输入端接入数据信号Vdata，输出端连接所述驱动单元，所述补偿单元C根据所述数据信号Vdata为驱动单元A提供补偿信号。参见图2，所述补偿单元C包括第四薄膜晶体管T4和存储电容C1。其中，所述补偿单元C的输入端为第四薄膜晶体管T4的源极，输出端为第四薄膜晶体管T4的漏极。所述第四薄膜晶体管T4的源极连接所述数据信号Vdata，栅极连接所述第一控制信号G1，漏极连接所述存储电容C1的一个极板和所述第二薄膜晶体管T2的漏极。所述存储电容C1的另一个极板连接所述第二薄膜晶体管T2的栅极。
在本实施例中，所述第四薄膜晶体管T4为N型薄膜晶体管。同时，所述第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3的宽长比相等且大于所述第四薄膜晶体管T4的宽长比。
所述复位单元B的第一输入端接入复位电压Vref，第二输入端接入第一控制信号G1，输出端连接所述驱动单元，所述复位单元B根据所述第一控制信号G1为驱动单元A提供复位信号。所述复位单元B包括第五薄膜晶体管T5和第六薄膜晶体管T6。其中，所述复位单元B的第一输入端为第六薄膜晶体管T6的源极，第二输入端为第五薄膜晶体管T5和第六薄膜晶体管T6的栅极，输出端为第五薄膜晶体管T5的漏极。
所述第五薄膜晶体管T5的源极连接第二薄膜晶体管T2源极，栅极连接所述第一控制信号G1，漏极连接所述第二薄膜晶体管T2的栅极。所述第六薄膜晶体管T6的源极连接所述复位电压Vref，栅极连接所述第一控制信号G1，漏极连接所述第二薄膜晶体管T2的栅极。
在本实施例中，所述第五薄膜晶体管T5和第六薄膜晶体管T6为N型薄膜晶体管，且所述第五薄膜晶体管T5和第六薄膜晶体管T6的宽长比相等。
下面对本申请的像素驱动电路的工作过程进行简要说明。参见图3，图3为图2中的像素驱动电路的时序图。
首先，在复位阶段时，第一控制信号G1为高电平。此时第四薄膜晶体管T4、第五薄膜晶体管T5和第六薄膜晶体管T6打开，将复位信号Vref的高电平写入第二薄膜晶体管T2的栅极和漏极，第二薄膜晶体管T2的源极写入低电平，实现对第二薄膜晶体管T2的复位。
之后，在补偿阶段时，数据信号Vdata为高电平，第二薄膜晶体管T2由于栅极和漏极短接而打开，持续放电，使栅极和漏极之间的电压逐渐降低。当第二薄膜晶体管T2的栅极电压Vg等于阈值电压Vth时，第二薄膜晶体管T2截止，此时的栅极电压Vg=Vdata+Vth，实现了对第二薄膜晶体管T2的补偿。
最后，在发光阶段时，第一控制信号G1为低电平。此时第四薄膜晶体管T4、第五薄膜晶体管T5和第六薄膜晶体管T6关闭，第二薄膜晶体管T2和第三薄膜晶体管T3打开，驱动管第二薄膜晶体管T2的漏极电流I符合如下公式,实现了对阈值电压的补偿。
I=K(Vgs-Vth) 2
=K（Vdata-V OLED+Vth-Vth） 2
=K(Vdata- V OLED) 2。
本申请的像素驱动电路使用的薄膜晶体管均为N型薄膜晶体管，相比于采用同时采用N型薄膜晶体管和N型薄膜晶体管的驱动电路，本申请的驱动电路的制备工艺更加简单。同时，本申请只需要一个存储电容，对应的电路时序简单，便于大规模量产。
相应的，本申请还提供了一种显示面板，所述显示面板包括如前所述的像素驱动电路。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种像素驱动电路，其中，所述像素驱动电路包括复位单元、补偿单元和驱动单元；其中，
    所述复位单元的第一输入端接入复位电压，第二输入端接入第一控制信号，输出端连接所述驱动单元，所述复位单元根据所述第一控制信号为驱动单元提供复位信号；
    所述补偿单元的输入端接入数据信号，输出端连接所述驱动单元，所述补偿单元根据所述数据信号为驱动单元提供补偿信号；
    所述驱动单元的第一输入端连接所述复位单元，第二输入端连接所述补偿单元，第三输入端接入第二控制信号，输出端连接第二电源电压。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动单元包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管；其中，
    所述第一薄膜晶体管的源极连接第一电源电压，栅极接入第二控制信号，漏极连接所述第二薄膜晶体管的源极；
    所述第二薄膜晶体管的栅极连接所述复位信号，漏极连接所述第三薄膜晶体管的源极；
    所述第三薄膜晶体管的栅极接入第二控制信号，漏极连接待驱动的有机发光二极管的输入端。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管为N型薄膜晶体管。
  4. 根据权利要求3所述的像素驱动电路，其中，所述补偿单元包括第四薄膜晶体管和存储电容；其中，
    所述第四薄膜晶体管的源极连接所述数据信号，栅极连接所述第一控制信号，漏极连接所述存储电容的一个极板和所述第二薄膜晶体管的漏极；
    所述存储电容的另一个极板连接所述第二薄膜晶体管的栅极。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第四薄膜晶体管为N型薄膜晶体管。
  6. 根据权利要求4所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管的宽长比相等且大于所述第四薄膜晶体管的宽长比。
  7. 根据权利要求2所述的像素驱动电路，其中，所述复位单元包括第五薄膜晶体管和第六薄膜晶体管；其中，
    所述第五薄膜晶体管的源极连接第二薄膜晶体管的源极，栅极连接所述第一控制信号，漏极连接所述第二薄膜晶体管的栅极；
    所述第六薄膜晶体管的源极连接所述复位电压，栅极连接所述第一控制信号，漏极连接所述第二薄膜晶体管的栅极。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第五薄膜晶体管和第六薄膜晶体管为N型薄膜晶体管。
  9. 根据权利要求2所述的像素驱动电路，其中，所述第五薄膜晶体管和第六薄膜晶体管的宽长比相等。
  10. 一种显示面板，其中，所述显示面板包括像素驱动电路，所述像素驱动电路包括复位单元、补偿单元和驱动单元；其中，
    所述复位单元的第一输入端接入复位电压，第二输入端接入第一控制信号，输出端连接所述驱动单元，所述复位单元根据所述第一控制信号为驱动单元提供复位信号；
    所述补偿单元的输入端接入数据信号，输出端连接所述驱动单元，所述补偿单元根据所述数据信号为驱动单元提供补偿信号；
    所述驱动单元的第一输入端连接所述复位单元，第二输入端连接所述补偿单元，第三输入端接入第二控制信号，输出端连接第二电源电压。
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