WO2021046999A1 - 一种oled像素补偿电路及像素补偿方法 - Google Patents

一种oled像素补偿电路及像素补偿方法 Download PDF

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Publication number
WO2021046999A1
WO2021046999A1 PCT/CN2019/115937 CN2019115937W WO2021046999A1 WO 2021046999 A1 WO2021046999 A1 WO 2021046999A1 CN 2019115937 W CN2019115937 W CN 2019115937W WO 2021046999 A1 WO2021046999 A1 WO 2021046999A1
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control signal
signal line
thin film
film transistor
node
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PCT/CN2019/115937
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English (en)
French (fr)
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田凡
王振岭
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/618,126 priority Critical patent/US11308866B2/en
Publication of WO2021046999A1 publication Critical patent/WO2021046999A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • This application relates to the field of display technology, and in particular to an OLED pixel compensation circuit and a pixel compensation method.
  • OLED Organic Light Emitting Display, organic light-emitting diode
  • the electrical characteristics of each drive transistor are different, and the drive transistors are unstable during operation and are easily affected by factors such as temperature and light.
  • Characteristic drift the difference in electrical characteristics of the drive transistor in space and the characteristic drift in time will all cause uneven display of the display.
  • OLED Organic Light Emitting Display, organic light-emitting diode
  • the electrical characteristics of each drive transistor are different, and the drive transistors are unstable during operation and are easily affected by factors such as temperature and light.
  • Characteristic drift the difference in electrical characteristics of the drive transistor in space and the characteristic drift in time will all cause uneven display of the display.
  • the purpose of this application is to provide an OLED pixel compensation circuit and a pixel compensation method to solve the technical problem of uneven brightness of the display panel.
  • the OLED pixel compensation circuit includes: an organic light emitting diode, the anode of the organic light emitting diode is connected to the third node, and the cathode Connected to a low-level line; a driving transistor, the driving transistor is a double-gate thin film transistor for driving the organic light emitting diode, the top gate of the driving transistor is electrically connected to the first node, and the bottom gate is electrically connected
  • the second node the source is electrically connected to the third node, and the drain is electrically connected to the high-level line
  • the first thin film transistor, the gate of the first thin film transistor is connected to the first control signal line, the first The second terminal is connected to the data line, the second terminal is connected to the second node; the second thin film transistor, the gate of the second thin film transistor is connected to the second control signal line, the first terminal is connected to the data line, and the second thin film transistor is
  • the two ends are connected to the third node; the third thin film transistor, the gate of the third thin film transistor is connected to the third control signal line, the first end is connected to the constant voltage power supply through the first switch, and the second end is connected to The first node; a fourth thin film transistor, the gate of the fourth thin film transistor is connected to a fourth control signal line, the first end is connected to the constant voltage power supply through the first switch, and the second end is connected to The third node; a first capacitor, the first capacitor is connected between the second node and the third node; and a second capacitor, the second capacitor is connected between the first node and the Between the third node.
  • the OLED pixel compensation method includes: providing an OLED pixel compensation circuit; wherein the OLED pixel compensation circuit includes: a driver
  • the driving transistor is a double-gate thin film transistor for driving the organic light emitting diode.
  • the top gate of the driving transistor is electrically connected to the first node, the bottom gate is electrically connected to the second node, and the source is electrically connected
  • the third node, the drain is electrically connected to the high-level line;
  • the first thin film transistor, the gate of the first thin film transistor is connected to the first control signal line, the first end is connected to the data line, and the second end is connected to The second node;
  • a second thin film transistor, the gate of the second thin film transistor is connected to a second control signal line, a first end is connected to the data line, and a second end is connected to the third node;
  • Three thin film transistors the gate of the third thin film transistor is connected to the third control signal line, the first end is connected to the constant voltage power supply through the first switch, and the second end is connected to the first node;
  • the fourth thin film transistor The gate of the fourth thin film transistor is connected to the fourth control signal line, the first end is connected to the constant voltage power supply through the first switch, and the second end is connected to
  • the driving transistor When the voltage difference between the gate and the source of the driving transistor is equal to the threshold voltage of the driving transistor, the driving transistor is turned off. At this time, The threshold voltage of the driving transistor is stored in the first capacitor; the threshold voltage dump phase is entered; the first control signal line and the second control signal line provide a high level, and the first thin film transistor and The second thin film transistor is turned on, the third control signal line and the fourth control signal line provide a low level, and the third The thin film transistor and the fourth thin film transistor are turned off, the first switch is turned off, the data line provides a preset potential, and the source voltage of the driving transistor is the preset potential.
  • the threshold of the driving transistor is The voltage is transferred to the second capacitor; enters the data writing stage; the first control signal line provides a high level, the first thin film transistor is turned on, the second control signal line, the third control signal line, and the The fourth control signal line provides a low level, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned off, the first switch is turned off, and the data line provides a data signal with a high potential, The high level of the data signal is written at the second node; the light-emitting phase is entered; the first control signal line, the second control signal line, the third control signal line, and the fourth control signal line are all low power At the same time, the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned off, the first switch is turned off, the driving transistor is turned on, and the organic light emitting diode emits light.
  • the beneficial effect of the present application is: different from the prior art, the OLED pixel compensation circuit and pixel compensation method provided by the present application use the 5T2C structure and the internal driving circuit of the pixel with the double-gate thin film transistor to compensate the threshold. Voltage drift, thereby improving the brightness uniformity of the display panel, thereby extending the service life of the product.
  • the OLED pixel compensation circuit and pixel compensation method provided in this application use a 5T2C structure and an internal driving circuit of a pixel with a double-gate thin film transistor as the driving transistor to compensate for threshold voltage drift, thereby enhancing the display panel The uniformity of brightness, thereby prolonging the service life of the product.
  • FIG. 1 is a circuit diagram of the OLED pixel compensation circuit of the present application
  • FIG. 2 is a working principle diagram of the driving transistor in FIG. 1;
  • FIG. 3 is a timing diagram of the OLED pixel compensation circuit of the present application.
  • FIG. 5 is a circuit diagram of the OLED pixel compensation circuit of the present application in the initialization stage
  • FIG. 6 is a circuit diagram of the OLED pixel compensation circuit of the present application in the detection phase
  • FIG. 7 is a schematic circuit diagram of the OLED pixel compensation circuit of the present application in the threshold voltage transfer stage
  • FIG. 8 is a circuit diagram of the OLED pixel compensation circuit of the present application in the data writing stage
  • FIG. 9 is a circuit diagram of the OLED pixel compensation circuit of the present application in the light-emitting stage.
  • FIG. 1 is a circuit diagram of the OLED pixel compensation circuit of the present application.
  • the pixel compensation circuit includes an organic light-emitting diode D1, a driving transistor DT, a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, and a second thin film transistor.
  • the anode of the organic light emitting diode D1 is connected to the third node n, and the cathode is connected to a low level line VSS.
  • the driving transistor DT is a double-gate thin film transistor for driving the organic light emitting diode D1.
  • the top gate of the driving transistor DT is electrically connected to the first node p
  • the bottom gate is electrically connected to the second node m
  • the source is electrically connected to the third node n
  • the drain is electrically connected to the high level line VDD.
  • the gate of the first thin film transistor T1 is connected to the first control signal line G1, the first end is connected to the data line, and the second end is connected to the second node m.
  • the gate of the second thin film transistor T2 is connected to the second control signal line G2, the first end is connected to the data line, and the second end is connected to the third node n.
  • the gate of the third thin film transistor T3 is connected to the third control signal line G3, the first end is connected to the constant voltage power supply V ini through the first switch K1, and the second end is connected to the first node p.
  • the gate of the fourth thin film transistor T4 is connected to the fourth control signal line G4, the first end is connected to the constant voltage power supply V ini through the first switch K1, and the second end is connected to the third node n.
  • the first capacitor C1 is connected between the second node m and the third node n.
  • the second capacitor C2 is connected between the first node p and the third node n.
  • the high-level line VDD is 20V
  • the low-level line VSS is -5V.
  • the high-level line VDD and the low-level line VSS can also be flexibly set as required, which is not specifically limited in this application.
  • This application increases the top gate voltage of the drive transistor DT by using the 5T2C structure and the drive transistor DT is a double-gate thin film transistor pixel internal drive circuit to compensate for the threshold voltage drift of the drive transistor DT, thereby improving the brightness uniformity of the display panel , Thereby extending the service life of the product.
  • FIG. 2 is a working principle diagram of the driving transistor in FIG. 1.
  • the voltage difference between the gate and the source of the driving transistor DT and the current characteristic curve are proportional to the magnitude of the top gate voltage.
  • the proportion gradually decreases. That is, the voltage difference between the gate and the source of the driving transistor DT has a negative correlation with the top gate voltage.
  • the higher the top gate voltage the smaller the voltage difference between the gate and the source of the driving transistor DT. Therefore, in this embodiment, the top gate voltage of the driving transistor DT is increased to compensate for the threshold voltage of the driving transistor DT.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 may all be N-type transistors or P-type transistors, which are not specifically limited in this application.
  • the signals in the first control signal line G1, the second control signal line G2, the third control signal line G3, the fourth control signal line G4, and the switching control signal of the first switch K1 are all provided by an external timing drive circuit.
  • FIG. 3 is a timing diagram of the OLED pixel compensation circuit of the present application.
  • the signals on the first control signal line G1, the second control signal line G2, the third control signal line G3, the fourth control signal line G4, and the switch control signal of the first switch K1 are combined with each other, and then enter the initialization phase, the detection Phase, threshold voltage dump phase, data writing phase, and light-emitting phase.
  • the first control signal line G1, the third control signal line G3, and the fourth control signal line G4 are at a high level, the second control signal line G2 is at a low level, and the switch control signal of the first switch K1 is closed .
  • the first control signal line G1 and the third control signal line G3 are at a high level, the second control signal line G2 and the fourth control signal line G4 are at a low level, and the switch control signal of the first switch K1 is closure.
  • the first control signal line G1 and the second control signal line G2 are at a high level
  • the third control signal line G3 and the fourth control signal line G4 are at a low level
  • the switching control of the first switch K1 is The signal is on.
  • the first control signal line G1 is at a high level
  • the second control signal line G2, the third control signal line G3, and the fourth control signal line G4 are at a low level
  • the switch control signal of the first switch K1 For opening.
  • the first control signal line G1, the second control signal line G2, the third control signal line G3, and the fourth control signal line G4 are all low level
  • the switch control signal of the first switch K1 is on.
  • the OLED pixel compensation circuit further includes an external detection circuit, and the external detection circuit is connected in parallel with the first switch K1 and the constant voltage power supply V ini through a second switch K2.
  • the first control signal line G1, the third control signal line G3, and the fourth control signal line G4 are at a high level, the first thin film transistor T1, the third thin film transistor T3, and the fourth thin film transistor T4 are all turned on, and the first thin film transistor T1, the third thin film transistor T3, and the fourth thin film transistor T4 are all turned on.
  • the second control signal line G2 is at low level, the second thin film transistor T2 is turned off, the data line provides the preset potential V ref , and the second node m writes the preset potential V ref .
  • the switch control signal of the first switch K1 is closed, the first switch K1 is closed, and the first node p and the third node n are written with the voltage V ini of the constant power supply.
  • the voltage V ini of the constant voltage power supply is smaller than the threshold voltage V OLED of the organic light emitting diode D1, and V ref -V ini >V th-TFT , where V th-TFT represents the threshold of the driving transistor DT Voltage. Therefore, during the initialization phase, the OLED does not emit light.
  • the first control signal line G1 and the third control signal line G3 are high, the first thin film transistor T1 and the third thin film transistor T3 are turned on, and the second control signal line G2 and the fourth control signal line G4 are Low level, the second thin film transistor T2 and the fourth thin film transistor T4 are turned off, the data line provides the preset potential V ref , the second node m writes the preset potential V ref , the switch control signal of the first switch K1 is closed, A switch K1 is closed, and the first node p writes the voltage V ini of the constant power supply.
  • V ref -V ini >V th-TFT the driving transistor DT is turned on, the voltage of the third node n continues to increase with time, and the voltage difference between the gate and source of the driving transistor DT continues to decrease.
  • the driving transistor DT is turned off.
  • the voltage of the third node n is V ref -V th-TFT
  • the threshold voltage V th-TFT of the driving transistor DT is stored in the first capacitor C1
  • the voltage difference between the first node p and the third node n is V ini -(V ref -V th-TFT) .
  • the first control signal line G1 and the second control signal line G2 are at a high level, the first thin film transistor T1 and the second thin film transistor T2 are turned on, and the third control signal line G3 and the fourth control signal line G4 is at a low level, the third thin film transistor T3 and the fourth thin film transistor T4 are turned off, the data line provides a preset potential V ref , and the second node m and the third node n write the preset potential V ref .
  • the switch control signal of the first switch K1 is on, and the first switch K1 is off.
  • the voltage difference between the first node p and the third node n is V ini -(V ref -V th-TFT )
  • the voltage of the third node n is V ref , according to the capacitive coupling effect
  • the voltage of the first node p is V ini +V th-TFT
  • the threshold voltage V th-TFT of the driving transistor DT is transferred to the second capacitor C2.
  • the first control signal line G1 is at high level, the first thin film transistor T1 is turned on, the second control signal line G2, the third control signal line G3, and the fourth control signal line G4 are at low level, and the first The two thin film transistors T2, the third thin film transistor T3, and the fourth thin film transistor T4 are turned off, the data line provides the data signal high potential V data , and the data signal high potential V data is written in the second node m.
  • the switch control signal of the first switch K1 is on, and the first switch K1 is off.
  • the first control signal line G1, the second control signal line G2, the third control signal line G3, and the fourth control signal line G4 are all low level, the first thin film transistor T1, the second thin film transistor T2, and the second The three thin film transistors T3 and the fourth thin film transistor T4 are turned off, the switch control signal of the first switch K1 is turned on, the first switch K1 is turned off, the driving transistor DT is turned on, and the organic light emitting diode D1 emits light.
  • FIG. 4 is a schematic flowchart of the OLED pixel compensation method of the present application.
  • the OLED pixel compensation method includes the following steps:
  • S10 Provide OLED pixel compensation circuit.
  • the OLED pixel compensation circuit includes an organic light emitting diode D1, a driving transistor DT, a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first capacitor C1, and a second capacitor C2.
  • the anode of the organic light emitting diode D1 is connected to the third node n, and the cathode is connected to a low level line VSS.
  • the driving transistor DT is a double-gate thin film transistor for driving the organic light emitting diode D1.
  • the top gate of the driving transistor DT is electrically connected to the first node p
  • the bottom gate is electrically connected to the second node m
  • the source is electrically connected to the third node n
  • the drain is electrically connected to the high level line VDD.
  • the gate of the first thin film transistor T1 is connected to the first control signal line G1, the first end is connected to the data line, and the second end is connected to the second node m.
  • the gate of the second thin film transistor T2 is connected to the second control signal line G2, the first end is connected to the data line, and the second end is connected to the third node n.
  • the gate of the third thin film transistor T3 is connected to the third control signal line G3, the first end is connected to the constant voltage power supply V ini through the first switch K1, and the second end is connected to the first node p.
  • the gate of the fourth thin film transistor T4 is connected to the fourth control signal line G4, the first end is connected to the constant voltage power supply V ini through the first switch K1, and the second end is connected to the third node n.
  • the first capacitor C1 is connected between the second node m and the third node n.
  • the second capacitor C2 is connected between the first node p and the third node n.
  • FIG. 5 is a schematic circuit diagram of the OLED pixel compensation circuit of the present application in the initialization phase.
  • the first control signal line G1, the third control signal line G3, and the fourth control signal line G4 are at a high level, the first thin film transistor T1, the third thin film transistor T3, and the fourth thin film transistor T4 are all turned on, and the second control signal line G2 is low, the second thin film transistor T2 is turned off, the data line provides the preset potential V ref , and the second node m writes the preset potential V ref .
  • the switch control signal of the first switch K1 is closed, the first switch K1 is closed, and the first node p and the third node n are written with the voltage V ini of the constant power supply.
  • the voltage V ini of the constant voltage power supply is smaller than the threshold voltage V OLED of the organic light emitting diode D1, and V ref -V ini >V th-TFT , where V th-TFT represents the threshold of the driving transistor DT Voltage. Therefore, during the initialization phase, the OLED does not emit light.
  • FIG. 6 is a circuit diagram of the OLED pixel compensation circuit of the present application in the detection phase.
  • the first control signal line G1 and the third control signal line G3 are at high level, the first thin film transistor T1 and the third thin film transistor T3 are turned on, the second control signal line G2 and the fourth control signal line G4 are at low level, and the second control signal line G2 and the fourth control signal line G4 are at low level.
  • the second thin film transistor T2 and the fourth thin film transistor T4 are turned off, the data line provides the preset potential V ref , the second node m writes the preset potential V ref , the switch control signal of the first switch K1 is closed, and the first switch K1 is closed.
  • the first node p writes the voltage V ini of the constant power supply. Since V ref -V ini >V th-TFT , the driving transistor DT is turned on, the voltage of the third node n continues to increase with time, and the voltage difference between the gate and source of the driving transistor DT continues to decrease. When the voltage difference between the gate and source of the transistor DT is V th-TFT , the driving transistor DT is turned off.
  • the voltage of the third node n is V ref -V th-TFT
  • the threshold voltage V th-TFT of the driving transistor DT is stored in the first capacitor C1
  • the voltage difference between the first node p and the third node n is V ini -(V ref -V th-TFT) .
  • FIG. 7 is a circuit diagram of the OLED pixel compensation circuit of the present application in the threshold voltage transfer stage.
  • the first control signal line G1 and the second control signal line G2 are at high level, the first thin film transistor T1 and the second thin film transistor T2 are turned on, the third control signal line G3 and the fourth control signal line G4 are at low level, and the first The three thin film transistors T3 and the fourth thin film transistor T4 are turned off, the data line provides the preset potential V ref , and the second node m and the third node n write the preset potential V ref .
  • the switch control signal of the first switch K1 is on, and the first switch K1 is off.
  • the voltage difference between the first node p and the third node n is V ini -(V ref -V th-TFT )
  • the voltage of the third node n is V ref , according to the capacitive coupling effect
  • the voltage of the first node p is V ini +V th-TFT
  • the threshold voltage V th-TFT of the driving transistor DT is transferred to the second capacitor C2.
  • FIG. 8 is a schematic circuit diagram of the OLED pixel compensation circuit of the present application in the data writing stage.
  • the first control signal line G1 is at high level, the first thin film transistor T1 is turned on, the second control signal line G2, the third control signal line G3, and the fourth control signal line G4 are at low level, the second thin film transistor T2, the first The three thin film transistors T3 and the fourth thin film transistor T4 are turned off, the data line provides the data signal high potential V data , and the data signal high potential V data is written in the second node m.
  • the switch control signal of the first switch K1 is on, and the first switch K1 is off.
  • FIG. 9 is a circuit diagram of the OLED pixel compensation circuit of the present application in the light-emitting stage.
  • the first control signal line G1, the second control signal line G2, the third control signal line G3, and the fourth control signal line G4 are all low level, the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 And the fourth thin film transistor T4 is turned off, the switch control signal of the first switch K1 is turned on, the first switch K1 is turned off, the driving transistor DT is turned on, and the organic light emitting diode D1 emits light.
  • the signals in the first control signal line G1, the second control signal line G2, the third control signal line G3, the fourth control signal line G4, and the switching control signal of the first switch K1 are all provided by an external timing drive circuit.
  • the OLED pixel compensation circuit further includes an external detection circuit, the external detection circuit is connected in parallel with the first switch K1 and the constant voltage power supply through a second switch K2, and the external detection circuit is configured to input an external compensation signal.
  • the external compensation circuit is used when external compensation is required.
  • the external compensation circuit can be set in a drive integrated circuit (IC) chip or drive system to assist the internal compensation circuit to perform threshold voltage compensation.
  • the present application uses a 5T2C structure and the driving transistor DT is a double-gate thin film transistor pixel internal driving circuit to increase the top gate voltage of the driving transistor DT, thereby compensating for the threshold voltage drift of the driving transistor DT, thereby improving the display The brightness uniformity of the panel, thereby extending the service life of the product.

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Abstract

本申请公开了一种OLED像素补偿电路及其像素补偿方法，该像素补偿电路包括：有机发光二极管、驱动晶体管、第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一电容以及第二电容。本申请通过使用5T2C结构且驱动晶体管DT为双栅极薄膜晶体管的像素内部驱动电路来增大驱动晶体管DT的顶栅电压，进而补偿驱动晶体管DT的阈值电压漂移，从而提升显示面板的亮度均匀性，进而延长产品的使用寿命。

Description

一种OLED像素补偿电路及像素补偿方法 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED像素补偿电路及像素补偿方法。
背景技术
OLED(Organic Light Emitting Display，有机发光二极管)显示面板中，由于制造工艺限制，每个驱动晶体管的电气特性存在一定差异，且驱动晶体管在工作过程中不稳定，易受温度、光照等因素影响发生特性漂移，驱动晶体管在空间上的电气特性差异和时间上的特性漂移都会造成显示器显示不均现象。
技术问题
OLED(Organic Light Emitting Display，有机发光二极管)显示面板中，由于制造工艺限制，每个驱动晶体管的电气特性存在一定差异，且驱动晶体管在工作过程中不稳定，易受温度、光照等因素影响发生特性漂移，驱动晶体管在空间上的电气特性差异和时间上的特性漂移都会造成显示器显示不均现象。
技术解决方案
本申请的目的在于提供一种OLED像素补偿电路及像素补偿方法，以解决显示面板亮度不均的技术问题。
为解决上述技术问题，本实用新型采用的一个技术方案是：提供 一种OLED像素补偿电路，所述OLED像素补偿电路包括：有机发光二极管，所述有机发光二极管的阳极连接于第三节点，阴极连接于一低电平线；驱动晶体管，所述驱动晶体管为双栅极薄膜晶体管，用于驱动所述有机发光二极管，所述驱动晶体管的顶栅电性连接第一节点，底栅电性连接第二节点，源极电性连接所述第三节点，漏极电性连接于高电平线；第一薄膜晶体管，所述第一薄膜晶体管的栅极连接于第一控制信号线，第一端连接于数据线，第二端连接于所述第二节点；第二薄膜晶体管，所述第二薄膜晶体管的栅极连接于第二控制信号线，第一端连接于所述数据线，第二端连接于所述第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极连接于第三控制信号线，第一端通过第一开关连接于恒压电源，第二端连接于所述第一节点；第四薄膜晶体管，所述第四薄膜晶体管的栅极连接于第四控制信号线，第一端通过所述第一开关连接于所述恒压电源，第二端连接于所述第三节点；第一电容，所述第一电容连接于所述第二节点和所述第三节点之间；以及第二电容，所述第二电容连接于所述第一节点和所述第三节点之间。
为解决上述技术问题，本实用新型采用的另一个技术方案是：提供一种OLED像素补偿方法，所述OLED像素补偿方法包括：提供OLED像素补偿电路；其中，所述OLED像素补偿电路包括：驱动晶体管，所述驱动晶体管为双栅极薄膜晶体管，用于驱动所述有机发光二极管，所述驱动晶体管的顶栅电性连接第一节点，底栅电性连接第二节点，源极电性连接第三节点，漏极电性连接于高电平线；第一薄膜晶体管，所述第一薄膜晶体管的栅极连接于第一控制信号线，第一端连接于数据线，第二端连接于所述第二节点；第二薄膜晶体管，所述第二薄膜晶体管的栅极连接于第二控制信号线，第一端连接于所述数据线，第二端连接于所述第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极连接于第三控制信号线，第一端通过第一开关连接于恒压电源，第二端连接于所述第一节点；第四薄膜晶体管，所述第四薄膜晶体管的栅极连接于第四控制信号线，第一端通过所述第一开关连接于所述 恒压电源，第二端连接于所述第三节点；第一电容，所述第一电容连接于所述第二节点和所述第三节点之间；第二电容，所述第二电容连接于所述第一节点和所述第三节点之间；以及有机发光二极管，所述有机发光二极管的阳极连接于所述第三节点，阴极连接于一低电平线；进入初始化阶段；所述第一控制信号线、第三控制信号线以及所述第四控制信号线提供高电平，所述第一薄膜晶体管、第三薄膜晶体管以及所述第四薄膜晶体管打开，所述第二控制信号线提供低电平，所述第二薄膜晶体管关闭，所述数据线提供预设电位，所述第二节点写入预设电位，所述第一开关闭合，所述第一节点写入所述恒压电源的电压；进入侦测阶段；所述第一控制信号线和所述第三控制信号线提供高电平，所述第一薄膜晶体管和所述第三薄膜晶体管打开，所述第二控制信号线和所述第四控制信号线提供低电平，所述第二薄膜晶体管和所述第四薄膜晶体管关闭，所述第一开关闭合，所述数据线提供预设电位，所述驱动晶体管导通，所述第三节点的电压随时间不断升高，所述驱动晶体管的栅极和源极之间的压差不断降低，当所述驱动晶体管的栅极和源极之间的压差等于所述驱动晶体管的阈值电压时，所述驱动晶体管截止，此时，所述驱动晶体管的阈值电压存储在所述第一电容中；进入阈值电压转存阶段；所述第一控制信号线和所述第二控制信号线提供高电平，所述第一薄膜晶体管和所述第二薄膜晶体管打开，所述第三控制信号线和所述第四控制信号线提供低电平，所述第三薄膜晶体管和所述第四薄膜晶体管关闭，所述第一开关断开，所述数据线提供预设电位，所述驱动晶体管的源极电压为预设电位，此时，所述驱动晶体管的阈值电压转存在所述第二电容中；进入数据写入阶段；所述第一控制信号线提供高电平，所述第一薄膜晶体管打开，所述第二控制信号线、第三控制信号线以及所述第四控制信号线提供低电平，所述第二薄膜晶体管、第三薄膜晶体管以及所述第四薄膜晶体管关闭，所述第一开关断开，所述数据线提供数据信号高电位，所述数据信号高电位写入在所述第二节点；进入发光阶段；所述第一控制信号线、第二控制信号线、第三控制信号线以及所述第四控制信号线 均为低电平，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及所述第四薄膜晶体管关闭，所述第一开关断开，所述驱动晶体管导通，所述有机发光二极管发光。
本申请的有益效果是：区别于现有技术的情况，本申请提供的一种OLED像素补偿电路及像素补偿方法，使用5T2C结构且驱动晶体管为双栅极薄膜晶体管的像素内部驱动电路来补偿阈值电压漂移，从而提升显示面板的亮度均匀性，进而延长产品的使用寿命。
有益效果
区别于现有技术的情况，本申请提供的一种OLED像素补偿电路及像素补偿方法，使用5T2C结构且驱动晶体管为双栅极薄膜晶体管的像素内部驱动电路来补偿阈值电压漂移，从而提升显示面板的亮度均匀性，进而延长产品的使用寿命。
附图说明
为了更清楚地说明本实用新型实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1是本申请的OLED像素补偿电路的电路图；
图2是图1中的驱动晶体管的工作原理图；
图3是本申请的OLED像素补偿电路的时序图；
图4是本申请的OLED像素补偿方法的流程示意图；
图5是本申请的OLED像素补偿电路在初始化阶段的电路示意图；
图6是本申请的OLED像素补偿电路在侦测阶段的电路示意图；
图7是本申请的OLED像素补偿电路在阈值电压转存阶段的电路示意图；
图8是本申请的OLED像素补偿电路在数据写入阶段的电路示意图；
图9是本申请的OLED像素补偿电路在发光阶段的电路示意图。
本发明的最佳实施方式
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本实用新型的一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本实用新型保护的范围。
请参阅图1，图1是本申请的OLED像素补偿电路的电路图。本申请首先提供一种OLED像素补偿电路，该像素补偿电路包括有机发光二极管D1、驱动晶体管DT、第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第一电容C1以及第二电容C2。有机发光二极管D1的阳极连接于第三节点n，阴极连接于一低电平线VSS。驱动晶体管DT为双栅极薄膜晶体管，用于驱动有机发光二极管D1，驱动晶体管DT的顶栅电性连接第一节点p，底栅电性连接第二节点m，源极电性连接第三节点n，漏极电性连接于高电平线VDD。第一薄膜晶体管T1的栅极连接于第一控制信号线G1，第一端连接于数据线，第二端连接于第二节点m。第二薄膜晶体管T2的栅极连接于第二控制信号线G2，第一端连接于数据线，第二端连接于第三节点n。第三薄膜晶体管T3的栅极连接于第三控制信号线 G3，第一端通过第一开关K1连接于恒压电源V ini，第二端连接于第一节点p。第四薄膜晶体管T4的栅极连接于第四控制信号线G4，第一端通过第一开关K1连接于恒压电源V ini，第二端连接于第三节点n。第一电容C1连接于第二节点m和第三节点n之间。第二电容C2连接于第一节点p和第三节点n之间。
其中，在本实施例中，高电平线VDD为20V，低电平线VSS为-5V。当然，在其它实施例中，高电平线VDD和低电平线VSS还可以根据需要灵活设置，本申请不做具体限定。
本申请通过使用5T2C结构且驱动晶体管DT为双栅极薄膜晶体管的像素内部驱动电路来增大驱动晶体管DT的顶栅电压，进而补偿驱动晶体管DT的阈值电压漂移，从而提升显示面板的亮度均匀性，进而延长产品的使用寿命。
如图2所示，图2是图1中的驱动晶体管的工作原理图。其中，在本实施例中，当施加至驱动晶体管DT的顶栅的电压Vg2逐渐增大时，驱动晶体管DT的栅极与源极之间的压差和电流特性曲线与顶栅电压的大小成比例地逐渐减小。即，驱动晶体管DT的栅极与源极之间的压差与顶栅电压呈负相关趋势，顶栅电压越大，驱动晶体管DT的栅极与源极之间的压差越小。故而，在本实施例中，通过增大驱动晶体管DT的顶栅电压，以补偿驱动晶体管DT的阈值电压。
其中，在本实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3及第四薄膜晶体管T4均可以为N型晶体管或P型晶体管，本申请不做具体限定。
其中，第一控制信号线G1、第二控制信号线G2、第三控制信号线G3、第四控制信号线G4中的信号以及第一开关K1的开关控制信号均通过外部时序驱动电路提供。
请参阅图3，图3是本申请的OLED像素补偿电路的时序图。第一控制信号线G1、第二控制信号线G2、第三控制信号线G3、第四控制信号线G4上的信号以及第一开关K1的开关控制信号相互组合，并依次进入初始化阶段、侦测阶段、阈值电压转存阶段、数据写入阶段 以及发光阶段。
在初始化阶段，第一控制信号线G1、第三控制信号线G3以及第四控制信号线G4为高电平，第二控制信号线G2为低电平，第一开关K1的开关控制信号为闭合。在侦测阶段，第一控制信号线G1和第三控制信号线G3为高电平，第二控制信号线G2和第四控制信号线G4为低电平，第一开关K1的开关控制信号为闭合。在阈值电压转存阶段，第一控制信号线G1和第二控制信号线G2为高电平，第三控制信号线G3和第四控制信号线G4为低电平，第一开关K1的开关控制信号为打开。在数据写入阶段，第一控制信号线G1为高电平，第二控制信号线G2、第三控制信号线G3以及第四控制信号线G4为低电平，第一开关K1的开关控制信号为打开。在发光阶段，第一控制信号线G1、第二控制信号线G2、第三控制信号线G3以及第四控制信号线G4均为低电平，第一开关K1的开关控制信号为打开。
可选地，在本实施例中，如图1所示，OLED像素补偿电路还包括外部侦测电路，外部侦测电路通过一第二开关K2与第一开关K1及恒压电源V ini并联。
请结合图1和图3，本申请的OLED像素补偿电路的工作过程如下：
在初始化阶段，第一控制信号线G1、第三控制信号线G3以及第四控制信号线G4为高电平，第一薄膜晶体管T1、第三薄膜晶体管T3以及第四薄膜晶体管T4均打开，第二控制信号线G2为低电平，第二薄膜晶体管T2关闭，数据线提供预设电位V ref，第二节点m写入预设电位V ref。第一开关K1的开关控制信号为闭合，第一开关K1关闭，第一节点p和第三节点n写入恒定电源的电压V ini。在本实施例中，恒压电源的电压V ini小于有机发光二极管D1的阈值电压V OLED，且V ref-V ini>V th-TFT，其中，V th-TFT表示的是驱动晶体管DT的阈值电压。故而，在初始化阶段，OLED不发光。
在侦测阶段，第一控制信号线G1和第三控制信号线G3为高电平，第一薄膜晶体管T1和第三薄膜晶体管T3打开，第二控制信号线G2 和第四控制信号线G4为低电平，第二薄膜晶体管T2和第四薄膜晶体管T4关闭，数据线提供预设电位V ref，第二节点m写入预设电位V ref，第一开关K1的开关控制信号为闭合，第一开关K1关闭，第一节点p写入恒定电源的电压V ini。由于V ref-V ini>V th-TFT，故驱动晶体管DT导通，第三节点n的电压随时间不断升高，驱动晶体管DT的栅极和源极之间的压差不断降低，当驱动晶体管DT的栅极和源极之间的压差为V th-TFT时，驱动晶体管DT截止。此时，第三节点n的电压为V ref-V th-TFT，驱动晶体管DT的阈值电压V th-TFT存储在第一电容C1中，第一节点p与第三节点n的压差为V ini-(V ref-V th-TFT)。
在阈值电压转存阶段，第一控制信号线G1和第二控制信号线G2为高电平，第一薄膜晶体管T1和第二薄膜晶体管T2打开，第三控制信号线G3和第四控制信号线G4为低电平，第三薄膜晶体管T3和第四薄膜晶体管T4关闭，数据线提供预设电位V ref，第二节点m和第三节点n写入预设电位V ref。第一开关K1的开关控制信号为打开，第一开关K1断开。由于在侦测阶段时，第一节点p与第三节点n的压差为V ini-(V ref-V th-TFT)，此时，第三节点n的电压为V ref，根据电容耦合效应，第一节点p的电压为V ini+V th-TFT，驱动晶体管DT的阈值电压V th-TFT转存在第二电容C2中。
在数据写入阶段，第一控制信号线G1为高电平，第一薄膜晶体管T1打开，第二控制信号线G2、第三控制信号线G3以及第四控制信号线G4为低电平，第二薄膜晶体管T2、第三薄膜晶体管T3以及第四薄膜晶体管T4关闭，数据线提供数据信号高电位V data，数据信号高电位V data写入在第二节点m。第一开关K1的开关控制信号为打开，第一开关K1断开。
在发光阶段，第一控制信号线G1、第二控制信号线G2、第三控制信号线G3以及第四控制信号线G4均为低电平，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3以及第四薄膜晶体管T4关闭，第一开关K1的开关控制信号为打开，第一开关K1断开，驱动晶体管DT导通，有机发光二极管D1发光。
本申请另一方面提供一种OLED像素补偿方法，如图4所示，图4是本申请的OLED像素补偿方法的流程示意图。OLED像素补偿方法包括如下步骤：
S10：提供OLED像素补偿电路。
其中，OLED像素补偿电路包括有机发光二极管D1、驱动晶体管DT、第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第一电容C1以及第二电容C2。有机发光二极管D1的阳极连接于第三节点n，阴极连接于一低电平线VSS。驱动晶体管DT为双栅极薄膜晶体管，用于驱动有机发光二极管D1，驱动晶体管DT的顶栅电性连接第一节点p，底栅电性连接第二节点m，源极电性连接第三节点n，漏极电性连接于高电平线VDD。第一薄膜晶体管T1的栅极连接于第一控制信号线G1，第一端连接于数据线，第二端连接于第二节点m。第二薄膜晶体管T2的栅极连接于第二控制信号线G2，第一端连接于数据线，第二端连接于第三节点n。第三薄膜晶体管T3的栅极连接于第三控制信号线G3，第一端通过第一开关K1连接于恒压电源V ini，第二端连接于第一节点p。第四薄膜晶体管T4的栅极连接于第四控制信号线G4，第一端通过第一开关K1连接于恒压电源V ini，第二端连接于第三节点n。第一电容C1连接于第二节点m和第三节点n之间。第二电容C2连接于第一节点p和第三节点n之间。
S20：进入初始化阶段。
其中，如图3和图5所示，图5是本申请的OLED像素补偿电路在初始化阶段的电路示意图。第一控制信号线G1、第三控制信号线G3以及第四控制信号线G4为高电平，第一薄膜晶体管T1、第三薄膜晶体管T3以及第四薄膜晶体管T4均打开，第二控制信号线G2为低电平，第二薄膜晶体管T2关闭，数据线提供预设电位V ref，第二节点m写入预设电位V ref。第一开关K1的开关控制信号为闭合，第一开关K1关闭，第一节点p和第三节点n写入恒定电源的电压V ini。在本实施例中，恒压电源的电压V ini小于有机发光二极管D1的阈值电压 V OLED，且V ref-V ini>V th-TFT，其中，V th-TFT表示的是驱动晶体管DT的阈值电压。故而，在初始化阶段，OLED不发光。
S30：进入侦测阶段。
如图3和图6所示，图6是本申请的OLED像素补偿电路在侦测阶段的电路示意图。第一控制信号线G1和第三控制信号线G3为高电平，第一薄膜晶体管T1和第三薄膜晶体管T3打开，第二控制信号线G2和第四控制信号线G4为低电平，第二薄膜晶体管T2和第四薄膜晶体管T4关闭，数据线提供预设电位V ref，第二节点m写入预设电位V ref，第一开关K1的开关控制信号为闭合，第一开关K1关闭，第一节点p写入恒定电源的电压V ini。由于V ref-V ini>V th-TFT，故驱动晶体管DT导通，第三节点n的电压随时间不断升高，驱动晶体管DT的栅极和源极之间的压差不断降低，当驱动晶体管DT的栅极和源极之间的压差为V th-TFT时，驱动晶体管DT截止。此时，第三节点n的电压为V ref-V th-TFT，驱动晶体管DT的阈值电压V th-TFT存储在第一电容C1中，第一节点p与第三节点n的压差为V ini-(V ref-V th-TFT)。
S40：进入阈值电压转存阶段。
如图3和图7所示，图7是本申请的OLED像素补偿电路在阈值电压转存阶段的电路示意图。第一控制信号线G1和第二控制信号线G2为高电平，第一薄膜晶体管T1和第二薄膜晶体管T2打开，第三控制信号线G3和第四控制信号线G4为低电平，第三薄膜晶体管T3和第四薄膜晶体管T4关闭，数据线提供预设电位V ref，第二节点m和第三节点n写入预设电位V ref。第一开关K1的开关控制信号为打开，第一开关K1断开。由于在侦测阶段时，第一节点p与第三节点n的压差为V ini-(V ref-V th-TFT)，此时，第三节点n的电压为V ref，根据电容耦合效应，第一节点p的电压为V ini+V th-TFT，驱动晶体管DT的阈值电压V th-TFT转存在第二电容C2中。
S50：进入数据写入阶段。
如图3和图8所示，图8是本申请的OLED像素补偿电路在数据写入阶段的电路示意图。第一控制信号线G1为高电平，第一薄膜晶 体管T1打开，第二控制信号线G2、第三控制信号线G3以及第四控制信号线G4为低电平，第二薄膜晶体管T2、第三薄膜晶体管T3以及第四薄膜晶体管T4关闭，数据线提供数据信号高电位V data，数据信号高电位V data写入在第二节点m。第一开关K1的开关控制信号为打开，第一开关K1断开。
S60：进入发光阶段。
如图3和图9所示，图9是本申请的OLED像素补偿电路在发光阶段的电路示意图。第一控制信号线G1、第二控制信号线G2、第三控制信号线G3以及第四控制信号线G4均为低电平，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3以及第四薄膜晶体管T4关闭，第一开关K1的开关控制信号为打开，第一开关K1断开，驱动晶体管DT导通，有机发光二极管D1发光。
其中，第一控制信号线G1、第二控制信号线G2、第三控制信号线G3、第四控制信号线G4中的信号以及第一开关K1的开关控制信号均通过外部时序驱动电路提供。
进一步地，OLED像素补偿电路还包括外部侦测电路，外部侦测电路通过一第二开关K2与第一开关K1及恒压电源并联，外部侦测电路设置为用于输入外部补偿信号。外部补偿电路在需要进行外部补偿时使用，外部补偿电路可以设置在驱动集成电路(integrated circuit，IC)芯片或者驱动系统中，以辅助内部补偿电路来进行阈值电压补偿。
综上所述，本申请通过使用5T2C结构且驱动晶体管DT为双栅极薄膜晶体管的像素内部驱动电路来增大驱动晶体管DT的顶栅电压，进而补偿驱动晶体管DT的阈值电压漂移，从而提升显示面板的亮度均匀性，进而延长产品的使用寿命。
以上所述仅为本实用新型的实施例，并非因此限制本实用新型的专利范围，凡是利用本实用新型说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包 括在本实用新型的专利保护范围内。

Claims (11)

  1. 一种OLED像素补偿电路，其中，所述OLED像素补偿电路包括：
    有机发光二极管，所述有机发光二极管的阳极连接于第三节点，阴极连接于一低电平线；
    驱动晶体管，所述驱动晶体管为双栅极薄膜晶体管，用于驱动所述有机发光二极管，所述驱动晶体管的顶栅电性连接第一节点，底栅电性连接第二节点，源极电性连接所述第三节点，漏极电性连接于高电平线；
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接于第一控制信号线，第一端连接于数据线，第二端连接于所述第二节点；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极连接于第二控制信号线，第一端连接于所述数据线，第二端连接于所述第三节点；
    第三薄膜晶体管，所述第三薄膜晶体管的栅极连接于第三控制信号线，第一端通过第一开关连接于恒压电源，第二端连接于所述第一节点；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极连接于第四控制信号线，第一端通过所述第一开关连接于所述恒压电源，第二端连接于所述第三节点；
    第一电容，所述第一电容连接于所述第二节点和所述第三节点之间；以及
    第二电容，所述第二电容连接于所述第一节点和所述第三节点之间；
    其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管及所述第四薄膜晶体管均为N型晶体管或P型晶体管；
    其中，当施加至所述驱动晶体管的顶栅的电压逐渐增大时，所述驱动晶体管的栅极与源极之间的压差和电流特性曲线与所述顶栅电压的大小成比例地逐渐减小。
  2. 一种OLED像素补偿电路，其中，所述OLED像素补偿电路包 括：
    有机发光二极管，所述有机发光二极管的阳极连接于第三节点，阴极连接于一低电平线；
    驱动晶体管，所述驱动晶体管为双栅极薄膜晶体管，用于驱动所述有机发光二极管，所述驱动晶体管的顶栅电性连接第一节点，底栅电性连接第二节点，源极电性连接所述第三节点，漏极电性连接于高电平线；
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接于第一控制信号线，第一端连接于数据线，第二端连接于所述第二节点；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极连接于第二控制信号线，第一端连接于所述数据线，第二端连接于所述第三节点；
    第三薄膜晶体管，所述第三薄膜晶体管的栅极连接于第三控制信号线，第一端通过第一开关连接于恒压电源，第二端连接于所述第一节点；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极连接于第四控制信号线，第一端通过所述第一开关连接于所述恒压电源，第二端连接于所述第三节点；
    第一电容，所述第一电容连接于所述第二节点和所述第三节点之间；以及
    第二电容，所述第二电容连接于所述第一节点和所述第三节点之间。
  3. 根据权利要求2所述的OLED像素补偿电路，其中，当施加至所述驱动晶体管的顶栅的电压逐渐增大时，所述驱动晶体管的栅极与源极之间的压差和电流特性曲线与所述顶栅电压的大小成比例地逐渐减小。
  4. 根据权利要求2所述的OLED像素补偿电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管及所述第四薄膜晶体管均为N型晶体管或P型晶体管。
  5. 根据权利要求2所述的OLED像素补偿电路，其中，所述第一 控制信号线、第二控制信号线、第三控制信号线、第四控制信号线中的信号以及所述第一开关的开关控制信号均通过外部时序驱动电路提供。
  6. 根据权利要求5所述的OLED像素补偿电路，其中，所述第一控制信号线、第二控制信号线、第三控制信号线、第四控制信号线上的信号以及所述第一开关的开关控制信号被配置如下：所述像素补偿电路依次进入初始化阶段、侦测阶段、阈值电压转存阶段、数据写入阶段以及发光阶段；
    在所述初始化阶段，所述第一控制信号线、第三控制信号线以及所述第四控制信号线为高电平，所述第二控制信号线为低电平，所述第一开关的开关控制信号为闭合；
    在所述侦测阶段，所述第一控制信号线和所述第三控制信号线为高电平，所述第二控制信号线和所述第四控制信号线为低电平，所述第一开关的开关控制信号为闭合；
    在所述阈值电压转存阶段，所述第一控制信号线和所述第二控制信号线为高电平，所述第三控制信号线和所述第四控制信号线为低电平，所述第一开关的开关控制信号为打开；
    在所述数据写入阶段，所述第一控制信号线为高电平，所述第二控制信号线、第三控制信号线以及所述第四控制信号线为低电平，所述第一开关的开关控制信号为打开；
    在所述发光阶段，所述第一控制信号线、第二控制信号线、第三控制信号线以及所述第四控制信号线均为低电平，所述第一开关的开关控制信号为打开。
  7. 根据权利要求6所述的OLED像素补偿电路，其中，所述OLED像素补偿电路还包括外部侦测电路，所述外部侦测电路通过一第二开关与所述第一开关及所述恒压电源并联。
  8. 一种OLED像素补偿方法，其中，所述OLED像素补偿方法包括：
    提供OLED像素补偿电路；
    其中，所述OLED像素补偿电路包括：
    驱动晶体管，所述驱动晶体管为双栅极薄膜晶体管，用于驱动所述有机发光二极管，所述驱动晶体管的顶栅电性连接第一节点，底栅电性连接第二节点，源极电性连接第三节点，漏极电性连接于高电平线；
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接于第一控制信号线，第一端连接于数据线，第二端连接于所述第二节点；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极连接于第二控制信号线，第一端连接于所述数据线，第二端连接于所述第三节点；
    第三薄膜晶体管，所述第三薄膜晶体管的栅极连接于第三控制信号线，第一端通过第一开关连接于恒压电源，第二端连接于所述第一节点；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极连接于第四控制信号线，第一端通过所述第一开关连接于所述恒压电源，第二端连接于所述第三节点；
    第一电容，所述第一电容连接于所述第二节点和所述第三节点之间；
    第二电容，所述第二电容连接于所述第一节点和所述第三节点之间；以及
    有机发光二极管，所述有机发光二极管的阳极连接于所述第三节点，阴极连接于一低电平线；
    进入初始化阶段；
    所述第一控制信号线、第三控制信号线以及所述第四控制信号线提供高电平，所述第一薄膜晶体管、第三薄膜晶体管以及所述第四薄膜晶体管打开，所述第二控制信号线提供低电平，所述第二薄膜晶体管关闭，所述数据线提供预设电位，所述第二节点写入预设电位，所述第一开关闭合，所述第一节点写入所述恒压电源的电压；
    进入侦测阶段；
    所述第一控制信号线和所述第三控制信号线提供高电平，所述第 一薄膜晶体管和所述第三薄膜晶体管打开，所述第二控制信号线和所述第四控制信号线提供低电平，所述第二薄膜晶体管和所述第四薄膜晶体管关闭，所述第一开关闭合，所述数据线提供预设电位，所述驱动晶体管导通，所述第三节点的电压随时间不断升高，所述驱动晶体管的栅极和源极之间的压差不断降低，当所述驱动晶体管的栅极和源极之间的压差等于所述驱动晶体管的阈值电压时，所述驱动晶体管截止，此时，所述驱动晶体管的阈值电压存储在所述第一电容中；
    进入阈值电压转存阶段；
    所述第一控制信号线和所述第二控制信号线提供高电平，所述第一薄膜晶体管和所述第二薄膜晶体管打开，所述第三控制信号线和所述第四控制信号线提供低电平，所述第三薄膜晶体管和所述第四薄膜晶体管关闭，所述第一开关断开，所述数据线提供预设电位，所述驱动晶体管的源极电压为预设电位，此时，所述驱动晶体管的阈值电压转存在所述第二电容中；
    进入数据写入阶段；
    所述第一控制信号线提供高电平，所述第一薄膜晶体管打开，所述第二控制信号线、第三控制信号线以及所述第四控制信号线提供低电平，所述第二薄膜晶体管、第三薄膜晶体管以及所述第四薄膜晶体管关闭，所述第一开关断开，所述数据线提供数据信号高电位，所述数据信号高电位写入在所述第二节点；
    进入发光阶段；
    所述第一控制信号线、第二控制信号线、第三控制信号线以及所述第四控制信号线均为低电平，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及所述第四薄膜晶体管关闭，所述第一开关断开，所述驱动晶体管导通，所述有机发光二极管发光。
  9. 根据权利要求8所述的OLED像素补偿方法，其中，所述恒压电源的电压小于所述有机发光二极管的阈值电压，且所述预设电位与所述恒压电源的电压的差值大于所述驱动晶体管的阈值电压。
  10. 根据权利要求8所述的OLED像素补偿方法，其中，所述第 一控制信号线、第二控制信号线、第三控制信号线、第四控制信号线中的信号以及所述第一开关的开关控制信号均通过外部时序驱动电路提供。
  11. 根据权利要求8所述的OLED像素补偿方法，其中，所述OLED像素补偿电路还包括外部侦测电路，所述外部侦测电路通过一第二开关与所述第一开关及所述恒压电源并联，所述外部侦测电路设置为用于输入外部补偿信号。
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