WO2018098877A1 - Oled驱动电路及oled显示面板 - Google Patents

Oled驱动电路及oled显示面板 Download PDF

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Publication number
WO2018098877A1
WO2018098877A1 PCT/CN2016/112303 CN2016112303W WO2018098877A1 WO 2018098877 A1 WO2018098877 A1 WO 2018098877A1 CN 2016112303 W CN2016112303 W CN 2016112303W WO 2018098877 A1 WO2018098877 A1 WO 2018098877A1
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Prior art keywords
thin film
film transistor
level
scan
oled
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PCT/CN2016/112303
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English (en)
French (fr)
Inventor
李骏
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武汉华星光电技术有限公司
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Priority to US15/328,157 priority Critical patent/US10115342B2/en
Publication of WO2018098877A1 publication Critical patent/WO2018098877A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of display, and in particular, to an OLED driving circuit and an OLED display panel.
  • FIG. 1 is a schematic diagram of an OLED driving circuit in the prior art.
  • the driving circuit is used to drive an OLED.
  • the driving circuit includes a switching TFT (T1), a driving thin film transistor (T2), and a storage capacitor Cst. This structure is also referred to as a 2T1C structure.
  • the gate of the switching thin film transistor T1 receives the scan information SCAN
  • the drain of the switching thin film transistor T1 receives the data signal Data
  • the source of the switching thin film transistor T1 is electrically connected to the gate of the driving thin film transistor T2.
  • the source of the switching thin film transistor T1 and the drain of the switching thin film transistor T1 are turned on or off under the control of the scan signal SCAN.
  • the data signal Data is transmitted to the gate of the driving thin film transistor T2.
  • the source of the driving thin film transistor T2 is electrically connected to a high potential VDD, and the drain of the driving thin film transistor T2 is electrically connected to the anode of the OLED.
  • the anode of the OLED is electrically connected to a low potential VSS.
  • Both ends of the storage capacitor Cst are electrically connected to the gate of the driving thin film transistor T2 and the drain of the driving thin film transistor T2, respectively.
  • the I OLED is a current flowing through the OLED, which is also referred to as a driving current of the OLED; k is a current amplification factor of the driving thin film transistor T2, which is determined by characteristics of the driving thin film transistor T2 itself; V gs The voltage between the gate and the source of the driving thin film transistor T2; Vth is the threshold voltage of the driving thin film transistor T2. It can be seen that the current flowing through the OLED is related to the threshold voltage Vth of the driving thin film transistor T2.
  • the threshold voltage V th of the driving thin film transistor T2 tend to drift, leading to changes in current I OLED flowing through the OLED, the change in current I OLED flowing through the OLED may result in changes in luminance of the OLED emission occurs, and further Affecting the image quality of the OLED display panel.
  • the present invention provides an OLED driving circuit for generating a driving current to drive an OLED.
  • the OLED driving circuit includes a switching thin film transistor, a driving thin film transistor, a storage capacitor, and a compensation circuit, and the switching thin film transistor and the driving thin film transistor are both a first terminal of the switching thin film transistor receives a data signal, and a gate of the switching thin film transistor receives an nth-level scan signal (SCAN[n]), the switching film a second end of the transistor is electrically connected to the first end of the driving thin film transistor, a gate of the driving thin film transistor is electrically connected to a voltage source through the storage capacitor, and a second end of the driving thin film transistor passes the compensation Some of the components in the circuit are electrically connected to the anode of the OLED, the cathode of the OLED is loaded with a low level, and the compensation circuit is configured to compensate for the flow due to the drift of the threshold voltage of the driving thin film transistor. a change in driving current of the OLED; wherein the first
  • the driving thin film transistor is referred to as a first thin film transistor
  • the switching thin film transistor is referred to as a third thin film transistor
  • the compensation circuit includes a second thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor
  • the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor each include a gate, a first end, and a second end, and the gate of the sixth thin film transistor receives An enable signal (EM), the first end of the sixth thin film transistor is loaded with a second level, and the second end of the sixth thin film transistor is electrically connected to the first end of the third thin film transistor, the third thin film transistor
  • the second end receives the data signal (Data), the gate of the third thin film transistor receives the nth stage scan signal (SCAN[n]), and the first end of the first thin film transistor is electrically connected to the sixth film a second end of the transistor, the second end of the first thin film transistor is electrically connected to the first
  • the (n-1)th scan signal (SCAN[n-1]) is at a first level, and the fourth thin film transistor is turned on, a gate of the first thin film transistor Resetting to the first level by the fourth thin film transistor;
  • the nth stage scan signal (SCAN[n]) is a second level, and the second thin film transistor and the third thin film transistor are turned off;
  • the enable signal (EM) is at a second level, and the fifth thin film transistor and the sixth thin film transistor are both turned off;
  • the (n-1)th scan signal (SCAN[n-1]) is at a second level, and the fourth thin film transistor is turned off;
  • the nth scan signal (SCAN[n ])) being a first level, the second thin film transistor and the third thin film transistor being turned on, the data signal (Data) being written by the first end of the first thin film transistor via the third thin film transistor
  • the enable signal (EM) is at a second level, and the fifth thin film transistor and the sixth thin film transistor are turned off;
  • the (n-1)th scan signal (SCAN[n-1]) is at a second level, and the fourth thin film transistor is turned off;
  • the nth scan signal (SCAN[ n]) is a second level, the second thin film transistor and the third thin film transistor are turned off;
  • the enable signal (EM) is at a first level, the fifth thin film transistor and the sixth thin film
  • the transistor is turned on to drive the OLED to emit light, wherein the nth stage scan signal (SCAN[n]) is delayed by T compared to the (n-1)th stage scan signal (SCAN[n-1]) /M, where M is a positive integer and T is the period of the scan signal.
  • the gate of the first thin film transistor is loaded with a compensation leakage current for compensating for the existence of leakage currents of the second thin film transistor and the fourth thin film transistor in the third period of time. The resulting decrease in the gate potential of the first thin film transistor is caused.
  • the compensation circuit further includes a seventh thin film transistor, the seventh thin film transistor includes a gate, a first end and a second end, and the second end of the seventh thin film transistor is electrically connected to the first thin film transistor
  • the gate of the seventh thin film transistor and the first end of the seventh thin film transistor are each loaded with a second level to maintain the seventh thin film transistor in a normally off state.
  • the first end of the sixth thin film transistor is electrically connected to the first end, the first end is loaded with the second level, and the first end of the seventh thin film transistor is electrically connected to the first end Point, the gate of the seventh thin film transistor is electrically connected to the second end point, wherein the second end point loads the second level.
  • the first end of the seventh thin film transistor and the gate of the seventh thin film transistor are both electrically connected to the second end point, wherein the second end point loads the second level.
  • the first end of the seventh thin film transistor and the gate of the seventh thin film transistor are both electrically connected to the second end point, wherein the second end point is loaded with the (n-2)th level scanning signal (SCAN[ N-2]), wherein the (n-1)th scanning signal (SCAN[n-1]) is delayed compared to the (n-2)th scanning signal (SCAN[n-2]) T/M, in the third period of time, the (n-2)th level scan signal (SCAN[n-2]) is at a second level.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all PTFTs, One level is low and the second level is high.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all NTFTs, One level is high and the second level is low.
  • the OLED driving circuit of the present invention is capable of compensating for a change in the driving current of the OLED due to a threshold voltage variation of the driving thin film transistor, stabilizing the driving current of the OLED, and improving the OLED display panel to which the OLED driving circuit is applied. Picture quality.
  • the present invention also provides an OLED display panel comprising the OLED driving circuit of any of the foregoing embodiments.
  • FIG. 1 is a schematic diagram of an OLED driving circuit in the prior art.
  • FIG. 2 is a schematic diagram of an OLED driving circuit according to a first preferred embodiment of the present invention.
  • FIG. 3 is a timing diagram of respective signals of the OLED drive circuit shown in FIG.
  • FIG. 4 is a schematic diagram of an OLED driving circuit according to a second preferred embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an OLED driving circuit according to a third preferred embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an OLED driving circuit according to a fourth preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an OLED driving circuit according to a fifth preferred embodiment of the present invention.
  • FIG. 8 is a timing chart of respective signals of the OLED drive circuit shown in FIG.
  • FIG. 9 is a schematic diagram of an OLED display panel according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an OLED driving circuit according to a first preferred embodiment of the present invention
  • FIG. 3 is a timing diagram of respective signals of the OLED driving circuit shown in FIG. 2.
  • the OLED driving circuit 100 is configured to generate a driving current to drive an Organic Light-Emitting Diode (OLED).
  • the OLED driving circuit includes a switching thin film transistor (Switch TFT) T3, a driving thin film transistor (Driver TFT) T1, a storage capacitor Cst, and a compensation circuit 110.
  • the switching thin film transistor T3 and the driving thin film transistor T1 each include a gate, a first end, and a second end.
  • the first end of the switching thin film transistor T3 receives a data signal (indicated by Data in the figure), the gate of the switching thin film transistor T3 receives an nth-level scan signal (SCAN[n]), and the switching thin film transistor T3 The second end is electrically connected to the first end of the driving thin film transistor T1.
  • a gate of the driving thin film transistor T3 is electrically connected to a voltage source VDD through the storage capacitor Cst, and a second end of the driving thin film transistor T3 is electrically connected to a positive electrode of the OLED through a part of the compensation circuit .
  • the negative electrode of the OLED is loaded with a low level.
  • the compensation circuit 110 is for compensating for a change in the driving current flowing through the OLED due to the drift of the threshold voltage of the driving thin film transistor T1.
  • the drift of the threshold voltage of the driving thin film transistor T1 may bring the driving current of the OLED (also referred to as the current flowing through the OLED). Change, thereby affecting the OLED The brightness of the light, which in turn affects the image quality of the OLED display panel to which the OLED is applied.
  • the compensation circuit 110 is used to compensate for the change of the driving current of the OLED due to the threshold voltage variation of the driving thin film transistor T1, thereby stabilizing the driving current of the OLED, and improving the OLED display panel applied by the OLED driving circuit.
  • the quality of the picture is a source, the second end is a drain; or the first end is a drain, and the second end is a source.
  • the driving thin film transistor is referred to as a first thin film transistor T1
  • the switching thin film transistor is referred to as a third thin film transistor T3.
  • the compensation circuit 110 includes a second thin film transistor T2, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 each include a gate, a first end, and a second end. The first end is a source, the second end is a drain; or the first end is a drain, and the second end is a source.
  • a gate of the sixth thin film transistor T6 receives an enable signal EM, a first end of the sixth thin film transistor T6 is loaded with a second level, and a second end of the sixth thin film transistor T6 is electrically connected to the third thin film transistor The first end of T3.
  • the second end of the third thin film transistor T3 receives the data signal Data, and the gate of the third thin film transistor T3 receives the nth-th scan signal SCAN[n].
  • the first end of the first thin film transistor T1 is electrically connected to the second end of the sixth thin film transistor T6, and the second end of the first thin film transistor T1 is electrically connected to the first end of the second thin film transistor T2.
  • the gate of the first thin film transistor T1 is connected to the first end of the sixth thin film transistor T6 through the storage capacitor electric Cst.
  • the second end of the second thin film transistor T2 is electrically connected to the gate of the first thin film transistor T1, and the gate of the second thin film transistor T2 receives the nth-th scan signal SCAN[n].
  • the gate of the fourth thin film transistor T4 receives the (n-1)th scan signal SCAN[n-1], and the first end of the fourth thin film transistor T4 is electrically connected to the gate of the first thin film transistor T1.
  • the second end of the fourth thin film transistor T4 is loaded with a first level.
  • the first end of the fifth thin film transistor T5 is electrically connected to the second end of the first thin film transistor T1, and the second end of the fifth thin film transistor T5 is electrically connected to the positive electrode of the OLED, the fifth The gate of the thin film transistor T5 receives the enable signal EM, and the negative electrode of the OLED is loaded with a low level.
  • the first end is a source and the second end is a drain; or in another embodiment, the first end is a drain and the second end is a source.
  • the (n-1)th stage scanning signal SCAN[n-1] is at a first level
  • the fourth thin film transistor T4 Turning on, the gate of the first thin film transistor T1 is reset to the first level by the fourth thin film transistor T4
  • the nth stage scan signal SCAN[n] is a second level
  • the first The second thin film transistor T2 and the third thin film crystal T3 are turned off
  • the enable signal EM is at a second level
  • the fifth thin film transistor T5 and the sixth thin film transistor T6 are both turned off.
  • the n-1th-th scan signal SCAN[n-1] is at a second level
  • the fourth thin film transistor T4 The n-th scan signal SCAN[n] is at a first level, the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the data signal Data passes through the third thin film transistor T3 Writing from the first end of the first thin film transistor T1; the enable signal EM is at a second level, and the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned off.
  • the gate and the second end of the first thin film transistor T1 are short-circuited to form a diode connection structure, and the data signal Data passes through the third thin film transistor T3 from the first film.
  • the first terminal of the transistor T1 is written to charge the gate potential of the first thin film transistor T1 to V data -
  • V data is the voltage of the data signal Data;
  • V th is the threshold voltage of the first thin film transistor T1.
  • the (n-1)th stage scanning signal SCAN[n-1] is at a second level, the fourth thin film transistor T4 is turned off; the nth stage scanning signal SCAN[n a second level, the second thin film transistor T2 and the third thin film transistor T3 are turned off; the enable signal EM is at a first level, the fifth thin film transistor T5 and the sixth thin film transistor T6 is turned on to drive the OLED to emit light.
  • the n-th scan signal SCAN[n] is delayed by T/M compared to the (n-1)-th scan signal SCAN[n-1], where M is a positive integer and T is a scan signal SCAN. [n] and the period of SCAN[n-1].
  • ] 2 k( V DD -V data ) 2 .
  • I OLED represents a driving current of the OLED; k is a current amplification factor of the driving thin film transistor (ie, the first thin film transistor) T1, which is determined by characteristics of the driving thin film transistor T1 itself; V DD is a voltage of the voltage source VDD ; V data is the voltage of the data signal Data. It can be seen that the driving current I OLED of the OLED is independent of the threshold voltage V th of the driving thin film transistor T1.
  • the driving current of the OLED generated by the OLED driving circuit of the present invention does not change with the drift of the threshold voltage V th of the driving thin film transistor T1, thereby stabilizing the driving current of the OLED.
  • the stability of the OLED driving current does not affect the luminance of the OLED, thereby improving the image quality of the OLED display panel to which the OLED driving circuit is applied.
  • the thin film transistor T6 is a PTFT (P Thin Film Transistor), the first level is a low level, and the second level is a high level.
  • the electrical characteristic of the PTFT is that when the gate of the PTFT is loaded with a high level, the PTFT is turned off; when the gate of the PTFT is loaded with a low level, the PTFT is turned on.
  • the sixth thin film transistor T6 is an NTFT (N Thin Film Transistor), the first level is a high level, and the second level is a low level.
  • the electrical characteristic of the NTFT is that when the gate of the NTFT is loaded with a high level, the NTFT is turned on; when the gate of the NTFT is loaded with a low level, the NTFT is turned off.
  • FIG. 4 is a schematic diagram of an OLED driving circuit according to a second preferred embodiment of the present invention
  • FIG. 5 is a OLED driving circuit according to a third preferred embodiment of the present invention
  • FIG. 6 is a schematic diagram of an OLED driving circuit according to a fourth preferred embodiment of the present invention
  • FIG. 7 is a schematic diagram of an OLED driving circuit according to a fifth preferred embodiment of the present invention
  • FIG. 8 is an OLED driving circuit shown in FIG. Timing diagram of each signal.
  • the gate of the first thin film transistor T1 is loaded with a compensation leakage current for compensating for leakage currents of the second thin film transistor T2 and the fourth thin film transistor T4 during the third time period t3.
  • the leakage current of the second thin film transistor T2 and the fourth thin film transistor T4 may cause the gate potential of the first thin film transistor T1 to gradually decrease, thereby causing the OLED display applied by the OLED driving circuit Gray scale shift occurs in the panel, which in turn affects the image quality of the OLED display panel. Therefore, in the first thin film crystal a compensation leakage current is applied to the tube T1 for compensating for the presence of the leakage current of the second thin film transistor T2 and the fourth thin film transistor T4 during the third time period t3.
  • the decrease in the gate potential of the first thin film transistor T1 further reduces or avoids the gray scale drift of the OLED display panel to which the OLED driving circuit is applied, and reduces the influence on the image quality of the OLED display panel.
  • the compensation circuit 110 further includes a seventh thin film transistor T7 including a gate, a first end, and a second end.
  • the second end of the seventh thin film transistor T7 is electrically connected to the gate of the first thin film transistor T1, and the gate of the seventh thin film transistor T7 and the first end of the seventh thin film transistor T7 are loaded with The two levels are such that the seventh thin film transistor T7 maintains a normally off state.
  • the first end is a source, and the second end is a drain; or in other embodiments, the first end is a drain and the second end is a source.
  • the seventh thin film transistor T7 is a PTFT
  • the second level is a high level.
  • the seventh thin film transistor T7 is an NTFT
  • the second level is a low level.
  • the first end of the sixth thin film transistor T6 is electrically connected to the first end point Port1, the first end point is loaded with the second level, and the seventh thin film transistor T7
  • the first end and the gate of the seventh thin film transistor T7 are electrically connected to the first end point
  • the second end of the seventh thin film transistor T7 is electrically connected to the gate of the first thin film transistor T1.
  • the first end of the sixth thin film transistor T6 is electrically connected to the first end point Port1, and the first end point Port1 is loaded with the second level
  • the seventh The first end of the thin film transistor T7 is electrically connected to the first end point Port1
  • the gate of the seventh thin film transistor T7 is electrically connected to the second end point Port2, wherein the second end point Port2 is loaded with the second level
  • the second thin terminal of the seventh thin film transistor T7 is electrically connected to the gate of the first thin film transistor T1, as indicated by VGH in the figure.
  • the first end of the seventh thin film transistor T7 and the gate of the seventh thin film transistor T7 are electrically connected to the second end point Port2, wherein the second end point Port 2 loads the second level (indicated by VGH in the figure), and the second end of the seventh thin film transistor T7 is electrically connected to the gate of the first thin film transistor T1.
  • the first end of the seventh thin film transistor T7 and the seventh thin The gate of the film transistor T7 is electrically connected to the second terminal Port2, wherein the second terminal Port2 is loaded with the (n-2)th scanning signal SCAN[n-2], wherein the (n-1)th The stage scan signal SCAN[n-1] is delayed by T/M compared to the (n-2)th stage scan signal SCAN[n-2].
  • the third (n-2)th stage scan signal SCAN[n-2] is at a second level during the third time period t3.
  • leakage current may exist in the second thin film transistor T2 and the fourth thin film transistor T4, and leakage currents existing in the second thin film transistor T2 and the fourth thin film transistor T4 may cause
  • the technical means is to apply a compensation current to the gate of the first thin film transistor T1, and the seventh thin film transistor T7 is used to set the seventh thin film transistor T7.
  • the second end electrically connects the gate of the first thin film transistor T1, and maintains the seventh thin film transistor in a normally off state to compensate for a decrease in the gate potential of the first thin film transistor T1.
  • the second thin film transistor T2 and the fourth thin film transistor T4 are not designed as a dual gate structure, respectively, and the number of thin film transistors used can be reduced, thereby comparing the OLED driving circuits of the present invention. Compact and space saving.
  • FIG. 9 is a schematic diagram of an OLED display panel according to a preferred embodiment of the present invention.
  • the OLED display panel 10 of the present invention includes the OLED driving circuit 100 described in any of the foregoing embodiments, and details are not described herein again.

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Abstract

一种OLED驱动电路(100)及OLED显示面板(10)。OLED驱动电路(100)包括开关薄膜晶体管(T3)、驱动薄膜晶体管(T1)、存储电容(Cst)以及补偿电路(110)，开关薄膜晶体管(T3)及驱动薄膜晶体管(T1)均包括栅极、第一端及第二端，开关薄膜晶体管(T3)的第一端接收数据信号(Data)，开关薄膜晶体管(T3)的栅极接收第n级扫描信号(SCAN[n])，开关薄膜晶体管(T3)的第二端电连接驱动薄膜晶体管(T1)的第一端，驱动薄膜晶体管(T1)的栅极通过存储电容(Cst)电连接至一电压源(VDD)，驱动薄膜晶体管(T1)的第二端通过补偿电路(110)中的部分元件电连接至OLED的正极，OLED的负极加载低电平(VSS)，补偿电路(110)用于补偿由于驱动薄膜晶体管(T1)的阈值电压（V th）的漂移而带来的流经OLED的驱动电流(I OLED)的变化；其中，第一端为源极，第二端为漏极；或者第一端为漏极，第二端为源极。

Description

OLED驱动电路及OLED显示面板
本发明要求2016年12月2日递交的发明名称为“OLED驱动电路及OLED显示面板”的申请号201611097271.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种OLED驱动电路及OLED显示面板。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板因具有因为具备轻薄、节能、宽视角、色域广、对比度高等特性而备受人们的青睐。OLED的基本驱动电路如图1所示，图1为现有技术中OLED驱动电路的示意图。所述驱动电路用于驱动OLED，所述驱动电路包括一个开关薄膜晶体管(Switch TFT)T1、一个驱动薄膜晶体管(Driver TFT)T2以及一个存储电容Cst，这种结构也被称为2T1C结构。所述开关薄膜晶体管T1的栅极接收扫描信息SCAN，所述开关薄膜晶体管T1的漏极接收数据信号Data，所述开关薄膜晶体管T1的源极电连接至所述驱动薄膜晶体管T2的栅极。所述开关薄膜晶体管T1的源极和所述开关薄膜晶体管T1漏极在所述扫描信号SCAN的控制下导通或者截止。当所述开关薄膜晶体管T1的源极和所述开关薄膜晶体管T1漏极在所述扫描信号SCAN的控制下导通时，所述数据信号Data被传输至所述驱动薄膜晶体管T2的栅极。所述驱动薄膜晶体管T2的源极电连接至一高电位VDD，所述驱动薄膜晶体管T2的漏极电连接至所述OLED的正极。所述OLED的正极电连接至一低电位VSS。所述存储电容Cst的两端分别电连接至所述驱动薄膜晶体管T2的栅极及所述驱动薄膜晶体管T2的漏极。流经所述OLED的电流为：IOLED＝k(Vgs-Vth)2。其中，IOLED为流经所述OLED的电流，也称为所述OLED的驱动电流；k为所述驱动薄膜晶体管T2的电流放大系数，由所述驱动薄膜晶体管T2自身的特性决定；Vgs为所述驱动薄膜晶体管T2的栅极与源极之间的电压；Vth为所述驱动薄膜晶体管T2的阈值电压。由此可见，流经所述OLED的电流与所述驱动薄膜晶体管T2的阈值电压Vth 有关。由于所述驱动薄膜晶体管T2的阈值电压Vth容易漂移，从而导致流经所述OLED的电流IOLED变动，流经所述OLED的电流IOLED变动会导致所述OLED的发光亮度发生变化，进而影响所述OLED显示面板的画质质量。
发明内容
本发明提供一种OLED驱动电路，用于产生驱动电流以驱动OLED，所述OLED驱动电路包括开关薄膜晶体管、驱动薄膜晶体管、存储电容以及补偿电路，所述开关薄膜晶体管及所述驱动薄膜晶体管均包括栅极、第一端及第二端，所述开关薄膜晶体管的第一端接收数据信号，所述开关薄膜晶体管的栅极接收第n级扫描信号(SCAN[n])，所述开关薄膜晶体管的第二端电连接所述驱动薄膜晶体管的第一端，所述驱动薄膜晶体管的栅极通过所述存储电容电连接至一电压源，所述驱动薄膜晶体管的第二端通过所述补偿电路中的部分元件电连接至所述OLED的正极，所述OLED的负极加载低电平，所述补偿电路用于补偿由于所述驱动薄膜晶体管的阈值电压的漂移而带来的流经所述OLED的驱动电流的变化；其中，所述第一端为源极，第二端为漏极；或者所述第一端为漏极，所述第二端为源极。
其中，所述驱动薄膜晶体管记为第一薄膜晶体管，所述开关薄膜晶体管记为第三薄膜晶体管，所述补偿电路包括第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管及第六薄膜晶体管所述第二薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均包括栅极、第一端及第二端，所述第六薄膜晶体管的栅极接收使能信号(EM)，所述第六薄膜晶体管的第一端加载第二电平，所述第六薄膜晶体管的第二端电连接第三薄膜晶体管的第一端，所述第三薄膜晶体管的第二端接收数据信号(Data)，所述第三薄膜晶体管的栅极接收第n级扫描信号(SCAN[n])，所述第一薄膜晶体管的第一端电连接所述第六薄膜晶体管的第二端，所述第一薄膜晶体管的第二端电连接第二薄膜晶体管的第一端，所述第一薄膜晶体管的栅极通过所述存储电容电连接至所述第六薄膜晶体管的第一端，所述第二薄膜晶体管的第二端电连接所述第一薄膜晶体管的栅极，所述第二薄膜晶体管的栅极接收所述第n级扫描信号(SCAN[n])，所述第四薄膜晶体管的栅极接收第(n-1)级扫描信号(SCAN[n-1])， 所述第四薄膜晶体管的第一端电连接所述第一薄膜晶体管的栅极，所述第四薄膜晶体管的第二端加载第一电平，所述第五薄膜晶体管的第一端电连接至所述第一薄膜晶体管的第二端，所述第五薄膜晶体管的第二端电连接至所述OLED的正极，所述第五薄膜晶体管的栅极接收所述使能信号(EM)，所述OLED的负极加载低电平；其中，所述第一端为源极，第二端为漏极；或者所述第一端为漏极，所述第二端为源极；
在第一时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第一电平，所述第四薄膜晶体管导通，所述第一薄膜晶体管的栅极通过所述第四薄膜晶体管复位到所述第一电平；所述第n级扫描信号(SCAN[n])为第二电平，所述第二薄膜晶体管及所述第三薄膜晶体管截止；所述使能信号(EM)为第二电平，所述第五薄膜晶体管及所述第六薄膜晶体管均截止；
在第二时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第二电平，所述第四薄膜晶体管截止；所述n级扫描信号(SCAN[n])为第一电平，所述第二薄膜晶体管及所述第三薄膜晶体管导通，所述数据信号(Data)经所述第三薄膜晶体管由所述第一薄膜晶体管的第一端写入；所述使能信号(EM)为第二电平，所述第五薄膜晶体管及所述第六薄膜晶体管截止；
在第三时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第二电平，所述第四薄膜晶体管截止；所述第n级扫描信号(SCAN[n])为第二电平，所述第二薄膜晶体管及所述第三薄膜晶体管截止；所述使能信号(EM)为第一电平，所述第五薄膜晶体管及所述第六薄膜晶体管导通，以驱动所述OLED发光，其中，所述第n级扫描信号(SCAN[n])相较于所述第(n-1)级扫描信号(SCAN[n-1])延迟T/M，其中，M为正整数，T为扫描信号的周期。
其中，所述第一薄膜晶体管的栅极加载补偿漏电流，所述补偿漏电流用于补偿在所述第三时间段内由于所述第二薄膜晶体管及所述第四薄膜晶体管的漏电流的存在而导致的所述第一薄膜晶体管的栅极电位的下降。
其中，所述补偿电路还包括第七薄膜晶体管，所述第七薄膜晶体管包括栅极、第一端及第二端，所述第七薄膜晶体管的第二端电连接至所述第一薄膜晶体管的栅极，所述第七薄膜晶体管的栅极及所述第七薄膜晶体管的第一端均加载第二电平，以使得所述第七薄膜晶体管维持常关闭状态。
其中，所述第六薄膜晶体管的第一端电连接至第一端点，所述第一端点加载所述第二电平，所述第七薄膜晶体管的第一端电连接至第一端点，所述第七薄膜晶体管的栅极电连接至第二端点，其中，所述第二端点加载所述第二电平。
其中，所述第七薄膜晶体管的第一端及所述第七薄膜晶体管的栅极均电连接至第二端点，其中，所述第二端点加载所述第二电平。
其中，所述第七薄膜晶体管的第一端及所述第七薄膜晶体管的栅极均电连接至第二端点，其中，所述第二端点加载第(n-2)级扫描信号(SCAN[n-2])，其中，所述第(n-1)级扫描信号(SCAN[n-1])相较于所述第(n-2)级扫描信号(SCAN[n-2])延迟T/M，在所述第三时间段内，所述第(n-2)级扫描信号(SCAN[n-2])为第二电平。
其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均为PTFT，所述第一电平为低电平，所述第二电平为高电平。
其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均为NTFT，所述第一电平为高电平，所述第二电平为低电平。
本发明的OLED驱动电路能够补偿由于驱动薄膜晶体管管的阈值电压变化而导致的OLED的驱动电流的变化，稳定了所述OLED的驱动电流，提升了所述OLED驱动电路所应用的OLED显示面板的画质。
本发明还提供了一种OLED显示面板，所述OLED显示面板包括前述任意一实施方式所述的OLED驱动电路。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中OLED驱动电路的示意图。
图2为本发明第一较佳实施方式的OLED驱动电路的示意图。
图3为图2所示的OLED驱动电路的各个信号的时序图。
图4为本发明第二较佳实施方式的OLED驱动电路的示意图。
图5为本发明第三较佳实施方式的OLED驱动电路的示意图。
图6为本发明第四较佳实施方式的OLED驱动电路的示意图。
图7为本发明第五较佳实施方式的OLED驱动电路的示意图。
图8为图7所示的OLED驱动电路的各个信号的时序图。
图9为本发明一较佳实施方式的OLED显示面板的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图2及图3，图2为本发明第一较佳实施方式的OLED驱动电路的示意图；图3为图2所示的OLED驱动电路的各个信号的时序图。所述OLED驱动电路100用于产生驱动电流以驱动有机发光二极管(Organic Light-Emitting Diode，OLED)。所述OLED驱动电路包括开关薄膜晶体管(Switch TFT)T3，驱动薄膜晶体管(Driver TFT)T1，存储电容Cst以及补偿电路110。所述开关薄膜晶体管T3及所述驱动薄膜晶体管T1均包括栅极、第一端及第二端。所述开关薄膜晶体管T3的第一端接收数据信号(在图中以Data表示)，所述开关薄膜晶体管T3的栅极接收第n级扫描信号(SCAN[n])，所述开关薄膜晶体管T3的第二端电连接所述驱动薄膜晶体管T1的第一端。所述驱动薄膜晶体管T3的栅极通过所述存储电容Cst电连接至一电压源VDD，所述驱动薄膜晶体管T3的第二端通过所述补偿电路中的部分元件电连接至所述OLED的正极。所述OLED的负极加载低电平。所述补偿电路110用于补偿由于所述驱动薄膜晶体管T1的阈值电压的漂移而带来的流经所述OLED的驱动电流的变化。换句话说，假如所述OLED驱动电路100中不设置所述补偿电路110，则，所述驱动薄膜晶体管T1的阈值电压的漂移会带来OLED的驱动电流(也称为流经OLED的电流)的变化，从而影响到所述OLED 的发光亮度，进而影响所述OLED所应用到的OLED显示面板的画质。所述补偿电路110用于补偿这种由于驱动薄膜晶体管T1的阈值电压变化而导致的OLED的驱动电流的变化，进而稳定所述OLED的驱动电流，提升所述OLED驱动电路所应用的OLED显示面板的画质。其中，所述第一端为源极，所述第二端为漏极；或者所述第一端为漏极，所述第二端为源极。
为了方便描述，所述驱动薄膜晶体管记为第一薄膜晶体管T1，所述开关薄膜晶体管记为第三薄膜晶体管T3。所述补偿电路110包括第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5及第六薄膜晶体管T6。所述第二薄膜晶体管T2、所述第四薄膜晶体管T4、所述第五薄膜晶体管T5及所述第六薄膜晶体管T6均包括栅极、第一端及第二端。其中，所述第一端为源极，所述第二端为漏极；或者所述第一端为漏极，所述第二端为源极。所述第六薄膜晶体管T6的栅极接收使能信号EM，所述第六薄膜晶体管T6的第一端加载第二电平，所述第六薄膜晶体管T6的第二端电连接第三薄膜晶体管T3的第一端。所述第三薄膜晶体管T3的第二端接收数据信号Data，所述第三薄膜晶体管T3的栅极接收第n级扫描信号SCAN[n]。所述第一薄膜晶体管T1的第一端电连接所述第六薄膜晶体管T6的第二端，所述第一薄膜晶体管T1的第二端电连接第二薄膜晶体管T2的第一端，所述第一薄膜晶体管T1的栅极通过所述存储电容电Cst连接至所述第六薄膜晶体管T6的第一端。所述第二薄膜晶体管T2的第二端电连接所述第一薄膜晶体管T1的栅极，所述第二薄膜晶体管T2的栅极接收所述第n级扫描信号SCAN[n]。所述第四薄膜晶体管T4的栅极接收第(n-1)级扫描信号SCAN[n-1]，所述第四薄膜晶体管T4的第一端电连接所述第一薄膜晶体管T1的栅极，所述第四薄膜晶体管T4的第二端加载第一电平。所述第五薄膜晶体管T5的第一端电连接至所述第一薄膜晶体管T1的第二端，所述第五薄膜晶体管T5的第二端电连接至所述OLED的正极，所述第五薄膜晶体管T5的栅极接收所述使能信号EM，所述OLED的负极加载低电平。其中，在一实施方式中，所述第一端为源极，第二端为漏极；或者在另外实施方式中，所述第一端为漏极，所述第二端为源极。
下面结合图2及图3对本发明的第一较佳实施方式的OLED驱动电路的工作原理进行介绍。
在第一时间段t1内(也称为驱动薄膜晶体管栅极复位阶段)：所述第(n-1)级扫描信号SCAN[n-1]为第一电平，所述第四薄膜晶体管T4导通，所述第一薄膜晶体管T1的栅极通过所述第四薄膜晶体管T4复位到所述第一电平；所述第n级扫描信号SCAN[n]为第二电平，所述第二薄膜晶体管T2及所述第三薄膜晶体T3管截止；所述使能信号EM为第二电平，所述第五薄膜晶体管T5及所述第六薄膜晶体管T6均截止。
在第二时间段t2内(也称为数据信号写入及阈值电压补偿阶段)：所述第n-1级扫描信号SCAN[n-1]为第二电平，所述第四薄膜晶体管T4截止；所述n级扫描信号SCAN[n]为第一电平，所述第二薄膜晶体管T2及所述第三薄膜晶体管T3导通，，所述数据信号Data经所述第三薄膜晶体管T3由所述第一薄膜晶体管T1的第一端写入；所述使能信号EM为第二电平，所述第五薄膜晶体管T5及所述第六薄膜晶体管T6截止。在此阶段内，所述第一薄膜晶体管T1的栅极和第二端短接，形成二极管连接(diode connect)结构，所述数据信号Data经所述第三薄膜晶体管T3由所述第一薄膜晶体管T1的第一端写入，将所述第一薄膜晶体管T1的栅极电位充电至Vdata-|Vth|。Vdata为数据信号Data的电压；Vth为第一薄膜晶体管T1的阈值电压。
在第三时间段t3内：所述第(n-1)级扫描信号SCAN[n-1]为第二电平，所述第四薄膜晶体管T4截止；所述第n级扫描信号SCAN[n]为第二电平，所述第二薄膜晶体管T2及所述第三薄膜晶体管T3截止；所述使能信号EM为第一电平，所述第五薄膜晶体管T5及所述第六薄膜晶体管T6导通，以驱动所述OLED发光。其中，所述第n级扫描信号SCAN[n]相较于所述第(n-1)级扫描信号SCAN[n-1]延迟T/M，其中，M为正整数，T为扫描信号SCAN[n]及SCAN[n-1]的周期。
则本发明第一较佳实施方式的OLED驱动电路产生的所述OLED的驱动电流为：IOLED＝k[VDD-(Vdata-|Vth|)-|Vth|]2＝k(VDD-Vdata)2。其中，IOLED表示OLED的驱动电流；k为所述驱动薄膜晶体管(即第一薄膜晶体管)T1的电流放大系数，由所述驱动薄膜晶体管T1自身的特性决定；VDD为电压源VDD的电压；Vdata为数据信号Data的电压。由此可见，OLED的驱动电流IOLED与所述驱动薄膜晶体管T1的阈值电压Vth无关。因此，相较于现有技术，本发明的OLED 驱动电路产生的OLED的驱动电流不会随着驱动薄膜晶体管T1的阈值电压Vth的漂移而发生变化，进而了稳定所述OLED的驱动电流，OLED驱动电流的稳定不会影响到所述OLED的发光亮度，进而提升所述OLED驱动电路所应用的OLED显示面板的画质。
在本实施方式中，所述第一薄膜晶体管T1、所述第二薄膜晶体管T2、所述第三薄膜晶体管T3、所述第四薄膜晶体管T4、所述第五薄膜晶体管T5及所述第六薄膜晶体管T6均为PTFT(P Thin Film Transistor)，所述第一电平为低电平，所述第二电平为高电平。所述PTFT的电学特性为当所述PTFT的栅极加载高电平的时候，所述PTFT截止；当所述PTFT的栅极加载低电平的时候，所述PTFT导通。
可以理解地，在其他实施方式中，所述第一薄膜晶体管T1、所述第二薄膜晶体管T2、所述第三薄膜晶体管T3、所述第四薄膜晶体管T4、所述第五薄膜晶体管T5及所述第六薄膜晶体管T6均为NTFT(N Thin Film Transistor)，所述第一电平为高电平，所述第二电平为低电平。所述NTFT的电学特性为当所述NTFT的栅极加载高电平的时候，所述NTFT导通；当所述NTFT的栅极加载低电平的时候，所述NTFT截止。
请参阅图4、图5、图6、图7及图8，图4为本发明第二较佳实施方式的OLED驱动电路的示意图；图5为本发明第三较佳实施方式的OLED驱动电路的示意图；图6为本发明第四较佳实施方式的OLED驱动电路的示意图；图7为本发明第五较佳实施方式的OLED驱动电路的示意图；图8为图7所示的OLED驱动电路的各个信号的时序图。所述第一薄膜晶体管T1的栅极加载补偿漏电流，所述补偿漏电流用于补偿在所述第三时间段t3内由于所述第二薄膜晶体管T2及所述第四薄膜晶体管T4的漏电流的存在而导致的所述第一薄膜晶体管T1的栅极电位的下降。具体地，在所述第三时间段t3内，所述第二薄膜晶体管T2及所述第四薄膜晶体管T4均截止，所述第二薄膜晶体管T2及所述第四薄膜晶体管T4均会存在漏电流，所述第二薄膜晶体管T2及所述第四薄膜晶体管T4存在的漏电流会导致所述第一薄膜晶体管T1的栅极电位逐渐下降，从而会导致所述OLED驱动电路所应用的OLED显示面板出现灰阶漂移，进而影响到所述OLED显示面板的画质。因此，在所述第一薄膜晶体 管T1上加载补偿漏电流，所述补偿漏电流用于补偿在所述第三时间段t3内由于所述第二薄膜晶体管T2及所述第四薄膜晶体管T4的漏电流的存在而导致的所述第一薄膜晶体管T1的栅极电位的下降，进而减小或者避免所述OLED驱动电路所应用的OLED显示面板的灰阶漂移，减小对所述OLED显示面板的画质的影响。
具体地，所述补偿电路110还包括第七薄膜晶体管T7，所述第七薄膜晶体管T7包括栅极、第一端及第二端。所述第七薄膜晶体管T7的第二端电连接至所述第一薄膜晶体管T1的栅极，所述第七薄膜晶体管T7的栅极及所述第七薄膜晶体管T7的第一端均加载第二电平，以使得所述第七薄膜晶体管T7维持常关闭状态。。其中，所述第一端为源极，所述第二端为漏极；或者在其他实施方式中，所述第一端为漏极，所述第二端为源极。在本实施方式(图4至图8描述的实施方式)中，所述第七薄膜晶体管T7为PTFT，所述第二电平为高电平。可以理解地，在其他实施方式中，所述第七薄膜晶体管T7为NTFT，所述第二电平为低电平。
在一实施方式中，请参阅图4，所述第六薄膜晶体管T6的第一端电连接至第一端点Port1，所述第一端点加载第二电平，所述第七薄膜晶体管T7的第一端及所述第七薄膜晶体管T7的栅极电连接至所述第一端点，所述第七薄膜晶体管T7的第二端电连接至所述第一薄膜晶体管T1的栅极。
在一实施方式中，请参阅图5，所述第六薄膜晶体管T6的第一端电连接至第一端点Port1，所述第一端点Port1加载所述第二电平，所述第七薄膜晶体管T7的第一端电连接至第一端点Port1，所述第七薄膜晶体管T7的栅极电连接至第二端点Port2，其中，所述第二端点Port2加载所述第二电平(在图中用VGH表示)，所述第七薄膜晶体管T7的第二端电连接至所述第一薄膜晶体管T1的栅极。
在另一实施方式中，请参阅图6，所述第七薄膜晶体管T7的第一端及所述第七薄膜晶体管T7的栅极均电连接至第二端点Port2，其中，所述第二端点Port2加载所述第二电平(在图中用VGH表示)，所述第七薄膜晶体管T7的第二端电连接至所述第一薄膜晶体管T1的栅极。
请一并参阅图7及图8，所述第七薄膜晶体管T7的第一端及所述第七薄 膜晶体管T7的栅极均电连接至第二端点Port2，其中，所述第二端点Port2加载第(n-2)级扫描信号SCAN[n-2]，其中，所述第(n-1)级扫描信号SCAN[n-1]相较于所述第(n-2)级扫描信号SCAN[n-2]延迟T/M。在所述第三时间段t3内，所述第(n-2)级扫描信号SCAN[n-2]为第二电平。
本发明的OLED驱动电路在所述第二薄膜晶体管T2及所述第四薄膜晶体管T4均会存在漏电流，所述第二薄膜晶体管T2及所述第四薄膜晶体管T4存在的漏电流会导致所述第一薄膜晶体管T1的栅极电位逐渐下降时，采用的技术手段为在第一薄膜晶体管T1的栅极加载补偿电流，且采用设置第七薄膜晶体管T7的方案，将第七薄膜晶体管T7的第二端电连接所述第一薄膜晶体管T1的栅极，且使所述第七薄膜晶体管维持常关闭状态，对所述第一薄膜晶体管T1的栅极电位的下降进行补偿。此时，不用将所述第二薄膜晶体管T2及所述第四薄膜晶体管T4分别设计成双栅(dual gate)结构，可以减小所使用的薄膜晶体管的数量，从而使得本案的OLED驱动电路比较紧凑，节约空间。
下面结合本发明的OLED驱动电路，对本发明的OLED显示面板进行介绍。请参阅图9，图9为本发明一较佳实施方式的OLED显示面板的示意图。本发明的OLED显示面板10包括前述任意一实施方式介绍的OLED驱动电路100，在此不再赘述。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种OLED驱动电路，用于产生驱动电流以驱动OLED，其中，所述OLED驱动电路包括开关薄膜晶体管、驱动薄膜晶体管、存储电容以及补偿电路，所述开关薄膜晶体管及所述驱动薄膜晶体管均包括栅极、第一端及第二端，所述开关薄膜晶体管的第一端接收数据信号，所述开关薄膜晶体管的栅极接收第n级扫描信号(SCAN[n])，所述开关薄膜晶体管的第二端电连接所述驱动薄膜晶体管的第一端，所述驱动薄膜晶体管的栅极通过所述存储电容电连接至一电压源，所述驱动薄膜晶体管的第二端通过所述补偿电路中的部分元件电连接至所述OLED的正极，所述OLED的负极加载低电平，所述补偿电路用于补偿由于所述驱动薄膜晶体管的阈值电压的漂移而带来的流经所述OLED的驱动电流的变化；其中，所述第一端为源极，第二端为漏极；或者所述第一端为漏极，所述第二端为源极。
  2. 如权利要求1所述的OLED驱动电路，其中，所述驱动薄膜晶体管记为第一薄膜晶体管，所述开关薄膜晶体管记为第三薄膜晶体管，所述补偿电路包括第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管及第六薄膜晶体管所述第二薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均包括栅极、第一端及第二端，所述第六薄膜晶体管的栅极接收使能信号(EM)，所述第六薄膜晶体管的第一端加载第二电平，所述第六薄膜晶体管的第二端电连接第三薄膜晶体管的第一端，所述第三薄膜晶体管的第二端接收数据信号(Data)，所述第三薄膜晶体管的栅极接收第n级扫描信号(SCAN[n])，所述第一薄膜晶体管的第一端电连接所述第六薄膜晶体管的第二端，所述第一薄膜晶体管的第二端电连接第二薄膜晶体管的第一端，所述第一薄膜晶体管的栅极通过所述存储电容电连接至所述第六薄膜晶体管的第一端，所述第二薄膜晶体管的第二端电连接所述第一薄膜晶体管的栅极，所述第二薄膜晶体管的栅极接收所述第n级扫描信号(SCAN[n])，所述第四薄膜晶体管的栅极接收第(n-1)级扫描信号(SCAN[n-1])，所述第四薄膜晶体管的第一端电连接所述第一薄膜晶体管的栅极，所述第四薄膜晶体管的第二端加载第一电平，所述第五薄膜晶 体管的第一端电连接至所述第一薄膜晶体管的第二端，所述第五薄膜晶体管的第二端电连接至所述OLED的正极，所述第五薄膜晶体管的栅极接收所述使能信号(EM)，所述OLED的负极加载低电平；其中，所述第一端为源极，第二端为漏极；或者所述第一端为漏极，所述第二端为源极；
    在第一时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第一电平，所述第四薄膜晶体管导通，所述第一薄膜晶体管的栅极通过所述第四薄膜晶体管复位到所述第一电平；所述第n级扫描信号(SCAN[n])为第二电平，所述第二薄膜晶体管及所述第三薄膜晶体管截止；所述使能信号(EM)为第二电平，所述第五薄膜晶体管及所述第六薄膜晶体管均截止；
    在第二时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第二电平，所述第四薄膜晶体管截止；所述n级扫描信号(SCAN[n])为第一电平，所述第二薄膜晶体管及所述第三薄膜晶体管导通，所述数据信号(Data)经所述第三薄膜晶体管由所述第一薄膜晶体管的第一端写入；所述使能信号(EM)为第二电平，所述第五薄膜晶体管及所述第六薄膜晶体管截止；
    在第三时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第二电平，所述第四薄膜晶体管截止；所述第n级扫描信号(SCAN[n])为第二电平，所述第二薄膜晶体管及所述第三薄膜晶体管截止；所述使能信号(EM)为第一电平，所述第五薄膜晶体管及所述第六薄膜晶体管导通，以驱动所述OLED发光，其中，所述第n级扫描信号(SCAN[n])相较于所述第(n-1)级扫描信号(SCAN[n-1])延迟T/M，其中，M为正整数，T为扫描信号的周期。
  3. 如权利要求2所述的OLED驱动电路，其中，所述第一薄膜晶体管的栅极加载补偿漏电流，所述补偿漏电流用于补偿在所述第三时间段内由于所述第二薄膜晶体管及所述第四薄膜晶体管的漏电流的存在而导致的所述第一薄膜晶体管的栅极电位的下降。
  4. 如权利要求3所述的OLED驱动电路，其中，所述补偿电路还包括第七薄膜晶体管，所述第七薄膜晶体管包括栅极、第一端及第二端，所述第七薄膜晶体管的第二端电连接至所述第一薄膜晶体管的栅极，所述第七薄膜晶体管的 栅极及所述第七薄膜晶体管的第一端均加载第二电平，以使得所述第七薄膜晶体管维持常关闭状态。
  5. 如权利要求4所述的OLED驱动电路，其中，所述第六薄膜晶体管的第一端电连接至第一端点，所述第一端点加载所述第二电平，所述第七薄膜晶体管的第一端电连接至第一端点，所述第七薄膜晶体管的栅极电连接至第二端点，其中，所述第二端点加载所述第二电平。
  6. 如权利要求4所述的OLED驱动电路，其中，所述第七薄膜晶体管的第一端及所述第七薄膜晶体管的栅极均电连接至第二端点，其中，所述第二端点加载所述第二电平。
  7. 如权利要求4所述的OLED驱动电路，其中，所述第七薄膜晶体管的第一端及所述第七薄膜晶体管的栅极均电连接至第二端点，其中，所述第二端点加载第(n-2)级扫描信号(SCAN[n-2])，其中，所述第(n-1)级扫描信号(SCAN[n-1])相较于所述第(n-2)级扫描信号(SCAN[n-2])延迟T/M，在所述第三时间段内，所述第(n-2)级扫描信号(SCAN[n-2])为第二电平。
  8. 如权利要求2所述的OLED驱动电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均为PTFT，所述第一电平为低电平，所述第二电平为高电平。
  9. 如权利要求2所述的OLED驱动电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均为NTFT，所述第一电平为高电平，所述第二电平为低电平。
  10. 一种OLED显示面板，其中，所述OLED显示面板包括OLED驱动电 路，所述OLED驱动电路用于产生驱动电流以驱动OLED，所述OLED驱动电路包括开关薄膜晶体管、驱动薄膜晶体管、存储电容以及补偿电路，所述开关薄膜晶体管及所述驱动薄膜晶体管均包括栅极、第一端及第二端，所述开关薄膜晶体管的第一端接收数据信号，所述开关薄膜晶体管的栅极接收第n级扫描信号(SCAN[n])，所述开关薄膜晶体管的第二端电连接所述驱动薄膜晶体管的第一端，所述驱动薄膜晶体管的栅极通过所述存储电容电连接至一电压源，所述驱动薄膜晶体管的第二端通过所述补偿电路中的部分元件电连接至所述OLED的正极，所述OLED的负极加载低电平，所述补偿电路用于补偿由于所述驱动薄膜晶体管的阈值电压的漂移而带来的流经所述OLED的驱动电流的变化；其中，所述第一端为源极，第二端为漏极；或者所述第一端为漏极，所述第二端为源极。
  11. 如权利要求10所述的OLED显示面板，其中，所述驱动薄膜晶体管记为第一薄膜晶体管，所述开关薄膜晶体管记为第三薄膜晶体管，所述补偿电路包括第二薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管及第六薄膜晶体管所述第二薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均包括栅极、第一端及第二端，所述第六薄膜晶体管的栅极接收使能信号(EM)，所述第六薄膜晶体管的第一端加载第二电平，所述第六薄膜晶体管的第二端电连接第三薄膜晶体管的第一端，所述第三薄膜晶体管的第二端接收数据信号(Data)，所述第三薄膜晶体管的栅极接收第n级扫描信号(SCAN[n])，所述第一薄膜晶体管的第一端电连接所述第六薄膜晶体管的第二端，所述第一薄膜晶体管的第二端电连接第二薄膜晶体管的第一端，所述第一薄膜晶体管的栅极通过所述存储电容电连接至所述第六薄膜晶体管的第一端，所述第二薄膜晶体管的第二端电连接所述第一薄膜晶体管的栅极，所述第二薄膜晶体管的栅极接收所述第n级扫描信号(SCAN[n])，所述第四薄膜晶体管的栅极接收第(n-1)级扫描信号(SCAN[n-1])，所述第四薄膜晶体管的第一端电连接所述第一薄膜晶体管的栅极，所述第四薄膜晶体管的第二端加载第一电平，所述第五薄膜晶体管的第一端电连接至所述第一薄膜晶体管的第二端，所述第五薄膜晶体管的第二端电连接至所述OLED的正极，所述第五薄膜晶体管的 栅极接收所述使能信号(EM)，所述OLED的负极加载低电平；其中，所述第一端为源极，第二端为漏极；或者所述第一端为漏极，所述第二端为源极；
    在第一时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第一电平，所述第四薄膜晶体管导通，所述第一薄膜晶体管的栅极通过所述第四薄膜晶体管复位到所述第一电平；所述第n级扫描信号(SCAN[n])为第二电平，所述第二薄膜晶体管及所述第三薄膜晶体管截止；所述使能信号(EM)为第二电平，所述第五薄膜晶体管及所述第六薄膜晶体管均截止；
    在第二时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第二电平，所述第四薄膜晶体管截止；所述n级扫描信号(SCAN[n])为第一电平，所述第二薄膜晶体管及所述第三薄膜晶体管导通，所述数据信号(Data)经所述第三薄膜晶体管由所述第一薄膜晶体管的第一端写入；所述使能信号(EM)为第二电平，所述第五薄膜晶体管及所述第六薄膜晶体管截止；
    在第三时间段内：所述第(n-1)级扫描信号(SCAN[n-1])为第二电平，所述第四薄膜晶体管截止；所述第n级扫描信号(SCAN[n])为第二电平，所述第二薄膜晶体管及所述第三薄膜晶体管截止；所述使能信号(EM)为第一电平，所述第五薄膜晶体管及所述第六薄膜晶体管导通，以驱动所述OLED发光，其中，所述第n级扫描信号(SCAN[n])相较于所述第(n-1)级扫描信号(SCAN[n-1])延迟T/M，其中，M为正整数，T为扫描信号的周期。
  12. 如权利要求11所述的OLED显示面板，其中，所述第一薄膜晶体管的栅极加载补偿漏电流，所述补偿漏电流用于补偿在所述第三时间段内由于所述第二薄膜晶体管及所述第四薄膜晶体管的漏电流的存在而导致的所述第一薄膜晶体管的栅极电位的下降。
  13. 如权利要求12所述的OLED显示面板，其中，所述补偿电路还包括第七薄膜晶体管，所述第七薄膜晶体管包括栅极、第一端及第二端，所述第七薄膜晶体管的第二端电连接至所述第一薄膜晶体管的栅极，所述第七薄膜晶体管的栅极及所述第七薄膜晶体管的第一端均加载第二电平，以使得所述第七薄膜晶体管维持常关闭状态。
  14. 如权利要求13所述的OLED显示面板，其中，所述第六薄膜晶体管的第一端电连接至第一端点，所述第一端点加载所述第二电平，所述第七薄膜晶体管的第一端电连接至第一端点，所述第七薄膜晶体管的栅极电连接至第二端点，其中，所述第二端点加载所述第二电平。
  15. 如权利要求13所述的OLED显示面板，其中，所述第七薄膜晶体管的第一端及所述第七薄膜晶体管的栅极均电连接至第二端点，其中，所述第二端点加载所述第二电平。
  16. 如权利要求13所述的OLED显示面板，其中，所述第七薄膜晶体管的第一端及所述第七薄膜晶体管的栅极均电连接至第二端点，其中，所述第二端点加载第(n-2)级扫描信号(SCAN[n-2])，其中，所述第(n-1)级扫描信号(SCAN[n-1])相较于所述第(n-2)级扫描信号(SCAN[n-2])延迟T/M，在所述第三时间段内，所述第(n-2)级扫描信号(SCAN[n-2])为第二电平。
  17. 如权利要求11所述的OLED显示面板，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均为PTFT，所述第一电平为低电平，所述第二电平为高电平。
  18. 如权利要求11所述的OLED显示面板，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管及所述第六薄膜晶体管均为NTFT，所述第一电平为高电平，所述第二电平为低电平。
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