WO2016070477A1 - 有机发光显示器像素驱动电路 - Google Patents

有机发光显示器像素驱动电路 Download PDF

Info

Publication number
WO2016070477A1
WO2016070477A1 PCT/CN2014/092656 CN2014092656W WO2016070477A1 WO 2016070477 A1 WO2016070477 A1 WO 2016070477A1 CN 2014092656 W CN2014092656 W CN 2014092656W WO 2016070477 A1 WO2016070477 A1 WO 2016070477A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
signal
capacitor
driving
driving signal
Prior art date
Application number
PCT/CN2014/092656
Other languages
English (en)
French (fr)
Inventor
徐向阳
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/423,672 priority Critical patent/US20160343298A1/en
Publication of WO2016070477A1 publication Critical patent/WO2016070477A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of organic light emitting display, and more particularly to an organic light emitting display pixel driving circuit.
  • OLED organic light emitting display
  • OLEDs are primarily made from thinner organic coatings and glass substrates, and do not require a backlight. Therefore, when there is a current path, these organic materials will actively emit light.
  • the luminance of the OLED is related to the magnitude of the current flowing through the OLED. Therefore, the electrical performance of the thin film transistor (TFT) as a driving device directly affects the display effect of the OLED, especially The threshold voltage of the TFT often drifts, causing a problem of uneven brightness of the entire OLED display device.
  • TFT thin film transistor
  • the existing OLED pixel compensation circuit needs to adopt different wiring inputs, and the above data voltage signal and the reference voltage signal respectively require a TFT for timing control output. Therefore, the existing OLED pixel compensation circuit needs to use more components (such as transistors), which not only increases the wiring cost, but also increases the complexity of the circuit.
  • the invention provides an organic light emitting display pixel driving circuit, which uses fewer components, not only reduces the wiring cost of the whole circuit, but also has a simple circuit structure, and increases the panel aperture ratio by reducing wiring.
  • An aspect of the present invention provides an OLED display pixel driving circuit, the OLED display pixel driving circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitor;
  • the first transistor is controlled by a scan driving signal for controlling transmission of the data signal and the reference voltage signal to the first plate of the capacitor;
  • the second transistor is electrically connected to the second plate of the capacitor for determining a magnitude of a driving current, the driving current being determined by a voltage difference between a gate and a drain of the second transistor;
  • the third transistor is electrically connected to the second plate of the capacitor and the second transistor, and is controlled by a first driving signal for controlling the conduction of the gate and the drain of the second transistor. Or disconnected;
  • the fourth transistor is electrically connected to the second transistor and the third transistor, and is controlled by a second driving signal for controlling transmission of a driving current from the second transistor to an organic light emitting device .
  • the first transistor is a scan transistor, and the first electrode as a signal input terminal is electrically connected to the signal line, and receives the input data signal and the reference voltage signal, and the second electrode of the first transistor and the capacitor
  • the first plate is electrically connected, and the gate of the first transistor is controlled by a scan driving signal for controlling transmission of the data signal and the reference voltage signal to the first plate of the capacitor.
  • the second transistor may be a driving transistor, the first electrode thereof is electrically connected to the power voltage signal line, and receives the input power voltage signal, and the second electrode of the second transistor and the third transistor The first electrode of the second electrode and the fourth transistor are electrically connected, and the gate of the second transistor is electrically connected to the second electrode of the capacitor and the first electrode of the third transistor.
  • the third transistor may be a compensation circuit transistor, the first electrode of which is electrically connected to the gate of the second transistor and the second plate of the capacitor, and the second electrode of the third transistor The second electrode of the second transistor and the first electrode of the fourth transistor are electrically connected.
  • the fourth transistor is a node reset control transistor, and the first electrode is electrically connected to the second electrode of the second transistor and the second electrode of the third transistor, and the second electrode of the fourth transistor is The organic light emitting element is electrically connected, and the organic light emitting element emits light in response to the driving current.
  • first transistor, the second transistor, the third transistor, and the fourth transistor are P-type transistors; or
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type transistors; or
  • the first transistor, the third transistor, and the fourth transistor are all N-type transistors, and the second transistor is a P-type transistor.
  • the driving sequence of the pixel driving circuit includes: a node voltage reset phase, a threshold voltage detecting phase, a reference voltage signal writing phase, a voltage stabilization phase, and an illumination phase.
  • the node voltage reset phase the first The scan driving signal of the transistor gate is at a low level, the first driving signal is a low level, the first transistor, the third transistor, and the fourth transistor are turned on, and the second driving signal is Low level, the second transistor is in an off state.
  • the scan driving signal of the first transistor gate is a low level
  • the first driving signal is a low level
  • the first transistor and the third transistor are
  • the second driving signal is at a high level
  • the second transistor and the fourth transistor are in an off state
  • the first plate and the second plate of the capacitor are
  • the voltage difference between the second transistor includes a threshold voltage of the second transistor, and the threshold voltage is stored on the capacitor.
  • the scan driving signal of the first transistor gate is at a low level, the first driving signal is at a high level, and the third transistor is in an off state, the first The transistor is turned on; the second driving signal is at a high level, the second transistor and the fourth transistor are in an off state; and the data signal is coupled to the second plate of the capacitor through the capacitor .
  • the scan driving signal of the first transistor gate is at a high level, the first transistor is in an off state, that is, the first plate of the capacitor is turned off;
  • the driving signal is at a high level, the third transistor is in an off state;
  • the second driving signal is at a high level, and the second transistor and the fourth transistor are in an off state;
  • the scan driving signal of the first transistor gate is at a high level, the first transistor is in an off state; the first driving signal is at a high level, and the third transistor is in an off state; The second driving signal is at a low level, the second transistor and the fourth transistor are turned on; and the driving current is transmitted to the organic light emitting element through the fourth transistor to drive the organic light emitting A piece of light is displayed.
  • Another aspect of the present invention provides a method for driving a pixel of an organic light emitting display, wherein the pixel driving method of the organic light emitting display is performed by using a pixel driving circuit, and the pixel driving circuit includes: a first transistor, a first a second transistor, a third transistor, a fourth transistor, and a capacitor; the first transistor, the second transistor, the third transistor, and the fourth transistor are P-type transistors; and the pixel driving method
  • the steps include the following steps: node voltage reset; threshold voltage detection; reference voltage signal input; voltage regulation balance;
  • the scan driving signal of the first transistor gate is a low level
  • a first driving signal is a low level
  • the first transistor, the third transistor, and the fourth The transistor is turned on;
  • a second driving signal is at a low level, the second transistor is in an off state; and
  • a data signal is transmitted through the first transistor to a first plate of a capacitor.
  • the scan driving signal of the first transistor gate is a low level, the first driving signal is a low level, and the first transistor and the third transistor are turned on;
  • the second driving signal is at a high level, the second transistor and the fourth transistor are in an off state; when a gate voltage of the second transistor is pulled high to a voltage difference from the source voltage thereof is less than or equal to When the threshold voltage of the second transistor is reached, then the second transistor will be in an off state and the threshold voltage will be stored on the capacitor.
  • the scan driving signal of the first transistor gate is at a low level, the first driving signal is at a high level, and the third transistor is in an off state, the first The transistor is turned on; the second driving signal is at a high level, the second transistor and the fourth transistor are in an off state; and a reference voltage signal is transmitted through the first transistor to the first plate of the capacitor
  • the second transistor, the third transistor, and the fourth transistor are both in an off state, and the data signal is coupled to the second plate of the capacitor through the capacitor.
  • the scan driving signal of the first transistor gate is at a high level, the first transistor is in an off state, the first driving signal is at a high level, and the third transistor is at An off state; the second driving signal is at a high level, and the second transistor and the fourth transistor are in an off state;
  • the scan driving signal of the first transistor gate is at a high level, the first transistor is in an off state; the first driving signal is at a high level, and the third transistor is in a cutoff state
  • the second driving signal is at a low level, the second transistor and the fourth transistor are turned on, and a driving current generated by the fourth transistor is transmitted to an organic light emitting element.
  • the first transistor is a scan transistor
  • the second transistor can be a drive transistor
  • the third transistor can be a compensation circuit transistor
  • the fourth transistor is a node reset control transistor
  • the capacitor is a storage capacitor.
  • an organic light emitting display including an organic light emitting device, wherein the organic light emitting display further includes a pixel driving circuit, and the organic light emitting display pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor and a capacitor; the first transistor is controlled by a scan driving signal for controlling transmission of the data signal and the reference voltage signal to the first plate of the capacitor; The second transistor is electrically connected to the second plate of the capacitor for determining a magnitude of a driving current, the driving current being determined by a voltage difference between a gate and a drain of the second transistor; The third transistor is electrically connected to the second plate of the capacitor and the second transistor, and is controlled by a first driving signal for controlling the conduction of the gate and the drain of the second transistor or Disconnecting; the fourth transistor is electrically connected to the second transistor and the third transistor, and is controlled by a second driving signal, and the control is to be from Transmitting the driving current of said second transistor to the organic light emitting element,
  • the data voltage signal and the reference voltage signal F are input to the transistor through the same line, and only one film is required to be driven.
  • a thin-film transistor (TFT) performs timing control output on the data voltage signal and the reference voltage signal, thereby reducing the use of circuit components (such as transistors), simplifying the circuit structure, and reducing the wiring cost of the entire circuit.
  • the panel aperture ratio is increased by reducing wiring.
  • FIG. 1 is a schematic diagram of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention.
  • FIG. 2 is a timing chart of driving signals of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a current path of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention in a node voltage reset phase t1.
  • FIG. 4 is a schematic diagram of a current path of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention in a threshold voltage detecting phase t2.
  • FIG. 5 is a schematic diagram of a current path of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention in a reference voltage signal writing phase t3.
  • FIG. 6 is a schematic diagram of a current path of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention in an emission phase t5.
  • FIG. 7 is a flowchart of a pixel driving method of an organic light emitting display according to another embodiment of the present invention.
  • FIG. 1 is a schematic diagram of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention.
  • the OLED display pixel driving circuit 100 of the embodiment of the present invention includes at least: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a capacitor Cst, and an organic light emitting device OLED (organic) Light-emitting display).
  • the pixel driving circuit 100 may be an AMOLED (active matrix/organic light emitting diode) driving circuit.
  • the capacitor Cst is a storage capacitor.
  • the first transistor M1 may be a scan transistor electrically connected to the signal line as a first electrode of the signal input end, and receive the input data signal VDATA and the reference voltage signal VREF, a second electrode of the first transistor M1 is electrically connected to the first plate of the capacitor Cst; a gate of the first transistor M1 is controlled by a scan driving signal, The body is configured to control the data signal VDATA and the reference voltage signal VREF to be transmitted to the first plate of the capacitor Cst.
  • the first electrode of the first transistor M1 is a source and the second electrode is a drain.
  • the second transistor M2 may be a driving transistor, and the first electrode as a signal input terminal is electrically connected to the power voltage signal line, and receives the input power voltage signal VDD; the second transistor a second electrode of M2 is electrically connected to a second electrode of the third transistor M3 and a first electrode of the fourth transistor M4; a gate of the second transistor M2 and a second plate of the capacitor Cst And electrically connecting the first electrode of the third transistor M3.
  • the second transistor M2 is configured to determine a magnitude of a driving current determined by a voltage difference between a gate of the second transistor M2 and the first electrode.
  • the first electrode of the second transistor M2 is a source, and the second electrode thereof is a drain.
  • the third transistor M3 may be a compensation circuit transistor, and a first electrode thereof is electrically connected to a gate of the second transistor M2 and a second plate of the capacitor Cst;
  • the second electrode of the third transistor M3 is electrically connected to the second electrode of the second transistor M2 and the first electrode of the fourth transistor M4.
  • the gate of the third transistor M3 is controlled by the first driving signal S1, specifically for controlling the on or off of the gate and the drain (ie, the second electrode) of the second transistor M2.
  • the first electrode of the third transistor M3 is a source, and the second electrode thereof is a drain.
  • the fourth transistor M4 may be a node reset control transistor, and the first electrode thereof is electrically connected to the second electrode of the second transistor M2 and the second electrode of the third transistor M3.
  • the second electrode of the fourth transistor M4 is electrically connected to the organic light emitting element OLED.
  • the gate of the fourth transistor M4 is controlled by the second driving signal S2, specifically for controlling the driving current from the second electrode of the second transistor M2 to the organic light emitting element OLED, then the organic The light emitting element OLED emits light in response to the driving current.
  • the first electrode of the fourth transistor M4 is a source, and the second electrode thereof is a drain.
  • FIG. 2 is a timing diagram of driving signals of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention.
  • the driving signal timing diagram shown in FIG. 2 is only one of the embodiments, which corresponds to the case where the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are P-type transistors.
  • a P-channel metal-oxide semiconductor field effect transistor metal-oxide semiconductor field effect transistor, referred to as MOS-FET.
  • MOS-FET metal-oxide semiconductor field effect transistor
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may also be other types of transistors (for example, an N-type transistor, specifically an N-channel MOS-FET). ), and according to the actual circuit wiring needs to adjust the circuit connection mode, signal input mode, signal transmission direction and size and other related parameters, and will not repeat them here.
  • the first driving signal S1 controls the third transistor M3 to further control the on or off of the gate and the drain of the second transistor M2, the second driving The signal S2 controls the fourth transistor M4 to transmit a driving current from the second transistor M2 to the organic light emitting element OLED.
  • the VDATA represents a data signal and the VREF represents a reference voltage signal.
  • the first driving signal S1 and the second driving signal S2 are both provided by a gate driving line of the organic light emitting display.
  • the driving sequence of the pixel driving circuit of the embodiment of the present invention includes: a node voltage reset phase, a threshold voltage detecting phase, a reference voltage signal VREF writing phase, a voltage stabilization phase, and an illumination phase, and the above five phases.
  • a node voltage reset phase a threshold voltage detecting phase
  • a reference voltage signal VREF writing phase a reference voltage signal
  • a voltage stabilization phase a voltage stabilization phase
  • an illumination phase and the above five phases.
  • the first transistor M1, the third transistor M3, and the fourth transistor M4 are in an on state, which is the second node N2 of the capacitor Cst (that is, the second of the capacitor Cst) a node voltage reset phase of the plate; in the threshold voltage detecting phase t2, the first transistor M1 and the third transistor M3 are in an on state, and the second transistor M2 and the fourth transistor M4 are in an off state,
  • the first node N1 of the capacitor Cst (that is, the first substrate of the capacitor Cst) and the voltage of the second node N2 are VDD-Vth and VDATA, respectively; when the reference voltage signal VREF is written to the stage t3, the first transistor M1 is in an on state, the second transistor M2, the third transistor M2, and the fourth transistor M4 are in an off state; in the illumination phase t5, the first transistor M1 and the third transistor M3 are in an off state, the second The transistor M2 and the fourth transistor M4 are in an on state
  • FIG. 3 is a schematic diagram of a current path of a pixel driving circuit of an organic light emitting display in a node voltage resetting stage t1 according to an embodiment of the present invention
  • FIG. 4 is a current of a pixel driving circuit of the organic light emitting display according to an embodiment of the present invention in a threshold voltage detecting phase t2
  • FIG. 5 is a schematic diagram of a current path of a pixel driving circuit of an organic light emitting display according to an embodiment of the present invention at a reference voltage signal writing stage t3.
  • 6 is a current of an OLED display pixel driving circuit in an illuminating phase t5 according to an embodiment of the invention. Schematic diagram of the pathway. For convenience of explanation, the paths of currents at different stages are marked by arrows in FIGS. 3 to 6, and the transistor is marked with a symbol "X" to indicate that the transistor is in an off state.
  • the scan driving signal of the gate of the first transistor M1 is at a low level, and the first driving signal S1 is at a low level, the first The one transistor M1, the third transistor M3, and the fourth transistor M4 are turned on; the second driving signal S2 is at a low level, and the second transistor M2 is in an off state.
  • the data signal VDATA is transmitted through the first transistor M1 to the first node N1 of the capacitor Cst, and a gap is formed between the third transistor M3 and the fourth transistor M4.
  • a cathode low potential VEE of the organic light emitting element OLED is applied to the second node N2 of the capacitor Cst through the current path, and a gate of the second transistor M2 is also at a low level, thus, the entire pixel
  • the node voltage reset process of the drive circuit 100 is completed.
  • the scan driving signal of the gate of the first transistor M1 is at a low level, and the first driving signal S1 is at a low level.
  • the first transistor M1 and the third transistor M3 are turned on; the second driving signal S2 is at a high level, and the second transistor M2 and the fourth transistor M4 are in an off state.
  • the second transistor M2 since the gate of the second transistor M2 is at a low potential in the node voltage reset phase t1, so that the second transistor M2 is in an on state, the second transistor M2 is A current path is formed between the third transistor M3, and the power supply voltage signal VDD reaches the second node N2 through the current path, and the potential of the second node N2 is gradually pulled up by the power voltage signal VDD.
  • the transistor when the voltage difference between the gate voltage and the source voltage of the transistor is less than the threshold voltage of the transistor, the transistor is turned off, that is, when the gate of the second transistor M2 is When the pole voltage is pulled high until the voltage difference from the source voltage thereof is less than or equal to the threshold voltage Vth of the second transistor M2, the second transistor M2 is in an off state.
  • the source of the second transistor M2 and the power supply voltage signal line are electrically connected, the source potential thereof remains VDD, so when the second transistor M2 is turned off, the gate voltage of the second transistor M2 (VDD-Vth), where VDD is the power supply voltage and Vth is the threshold voltage of the second transistor M2.
  • VDD-Vth the gate voltage of the second transistor M2
  • V2 represents the potential of the second node N2 of the capacitor Cst
  • V1 represents the potential of the first node N1 of the capacitor Cst
  • the scan driving signal of the gate of the first transistor M1 is at a low level, and the first driving signal S1 is at a high level.
  • the third transistor M3 is in an off state, the first transistor M1 is turned on; the second driving signal S2 is at a high level, and the second transistor M2 and the fourth transistor M4 are in an off state.
  • the reference voltage signal VREF is transmitted through the first transistor M1 to the first node N1 of the capacitor Cst (ie, the first plate of the capacitor Cst) while the second transistor M2, the third transistor M3 and the fourth transistor M4 are both in an off state, that is, the second plate of the capacitor Cst is disconnected, so between the first plate and the second plate of the capacitor Cst
  • the voltage difference Vc remains unchanged.
  • the potential of the first node N1 becomes VREF
  • the data signal VDATA is coupled to the second plate of the capacitor Cst via the capacitor Cst.
  • the scan driving signal of the gate of the first transistor M1 is at a high level, the first transistor M1 is in an off state, that is, the first plate of the capacitor Cst is turned off;
  • the first driving signal S1 is at a high level, the third transistor M3 is in an off state;
  • the second driving signal S2 is at a high level, and the second transistor M2 and the fourth transistor M4 are in an off state. Therefore, the potential of the second node N2 of the capacitor Cst remains unchanged, thus completing the voltage stabilization process.
  • the scan driving signal of the gate of the first transistor M1 is at a high level, the first transistor M1 is in an off state; and the first driving signal S1 is The high level, the third transistor M3 is in an off state; the second driving signal S2 is at a low level, and the second transistor M2 and the fourth transistor M4 are turned on.
  • a current path is formed between the second transistor M2 and the fourth transistor M4.
  • I is the drive current generated by the second transistor M2
  • K is a constant
  • VREF is a reference voltage signal
  • VDATA is a data signal.
  • the driving current generated by the second transistor M2 is transmitted to the fourth transistor M4, and since the fourth transistor M4 operates in a linear region, the driving current I can be transmitted to the organic light emitting element OLED to drive Its light display.
  • the first transistor M1, the third transistor M3, and the fourth transistor M4 may be N-type transistors, and the second transistor M2 is a P-type transistor, and the first transistor M1 is changed accordingly.
  • the second transistor M2, the connection relationship of the third transistor M3 and the fourth transistor M4, and the input direction of the signal can realize the functions of the above steps.
  • the embodiment of the present invention does not specifically limit this, and the specific process is described in detail. .
  • the data voltage signal VDATA and the reference voltage signal VREF are input to the transistor through the same line, and only one thin film transistor (Thin-film) is required as a driving.
  • the transistor (TFT) performs timing control output on the data voltage signal VDATA and the reference voltage signal VREF, thereby reducing the use of circuit components (such as transistors), simplifying the circuit structure, reducing the wiring cost of the entire circuit, and reducing Wiring increases the panel aperture ratio.
  • the threshold voltage and the power line voltage drop are realized.
  • FIG. 7 is a flowchart of a pixel driving method of an organic light emitting display according to another embodiment of the present invention.
  • the fourth transistor M4 is a P-type transistor (such as a P-channel MOS-FET). It can be understood that the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may also be Other types of transistors (for example, N-channel MOS-FETs) will not be described herein.
  • the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all P-type transistors as an example.
  • the organic light emitting display pixel driving method includes the following steps.
  • the scan driving signal of the gate of the first transistor M1 is a low level
  • the first driving signal S1 is a low level
  • the first transistor M1 and the third transistor M3 are
  • the fourth transistor M4 is turned on;
  • the second driving signal S2 is at a low level, and the second transistor M2 is in an off state.
  • the data signal VDATA is transmitted through the first transistor M1 to the first plate of a capacitor Cst (that is, the first node N1 of the capacitor Cst).
  • the scan driving signal of the gate of the first transistor M1 is a low level
  • the first driving signal S1 is a low level
  • the first transistor M1 and the first The three transistors M3 are turned on
  • the second driving signal S2 is at a high level
  • the second transistor M2 and the fourth transistor M4 are in an off state. Since the gate of the second transistor M2 is at a low potential in the step node voltage reset, so that the second transistor M2 is in an on state, a current is formed between the second transistor M2 and the third transistor M3.
  • a power supply voltage signal VDD reaches the second plate of the capacitor Cst (that is, the second node N2 of the capacitor Cst) through the current path, and the potential of the second plate is gradually used by the power voltage signal VDD is pulled high.
  • the second transistor M2 when the gate voltage of the second transistor M2 is pulled high to a voltage difference from the source voltage thereof that is less than or equal to the threshold voltage of the second transistor M2, then the second transistor M2 It is in an off state and stores the threshold voltage on the capacitor Cst.
  • the scan driving signal of the gate of the first transistor M1 is at a low level, the first driving signal S1 is at a high level, and the third transistor M3 is in an off state.
  • the first transistor M1 is turned on; the second driving signal S2 is at a high level, and the second transistor M2 and the fourth transistor M4 are in an off state.
  • a reference voltage signal VREF through the first A transistor M1 is transmitted to the first plate of the capacitor Cst while the second transistor M2, the third transistor M3, and the fourth transistor M4 are both in an off state, that is, the capacitor Cst
  • the second plate is disconnected, so that the voltage difference Vc between the first plate and the second plate of the capacitor Cst remains unchanged.
  • the data signal VDATA is coupled to the second plate of the capacitor Cst via the capacitor Cst.
  • the scan driving signal of the gate of the first transistor M1 is at a high level, and the first transistor M1 is in an off state, that is, the first plate of the capacitor Cst is broken.
  • the first driving signal S1 is at a high level, the third transistor M3 is in an off state; the second driving signal S2 is at a high level, and the second transistor M2 and the fourth transistor M4 are at Cutoff status.
  • the scan driving signal of the gate of the first transistor M1 is at a high level, the first transistor M1 is in an off state; and the first driving signal S1 is at a high level.
  • the third transistor M3 is in an off state; the second driving signal S2 is at a low level, and the second transistor M2 and the fourth transistor M4 are turned on. Since the second transistor M2 operates in a saturation region, the driving current flowing through the second transistor M2 is determined by the voltage difference between its gate and source.
  • the driving current generated by the second transistor M2 is transmitted to the fourth transistor M4, and since the fourth transistor M4 operates in a linear region, the driving current can be transmitted to an organic light emitting element OLED for driving display .
  • the first transistor M1, the third transistor M3, and the fourth transistor M4 may be N-type transistors, and the second transistor M2 is a P-type transistor, and the first transistor M1 is changed accordingly.
  • the second transistor M2, the connection relationship of the third transistor M3 and the fourth transistor M4, and the input direction of the signal can realize the functions of the above steps.
  • the embodiment of the present invention does not specifically limit this, and the specific process is described in detail. .
  • the data voltage signal VDATA and the reference voltage signal VREF are input to the transistor through the same line, and only one pair of thin film-transistor (TFT) pairs is required.
  • the data voltage signal VDATA and the reference voltage signal VREF are outputted in time series, thus reducing circuit components (such as crystal).
  • circuit components such as crystal

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种有机发光显示器像素驱动电路（100），包括：一第一晶体管（M1），由一扫描驱动信号控制，用于控制数据信号（VDATA）和参考电压信号（VREF）传输至一电容器（Cst）的第一极板；一第二晶体管（M2），与电容器（Cst）的第二极板电性连接，用于确定驱动电流的大小，驱动电流由第二晶体管（M2）的栅极和漏极之间的电压差决定；一第三晶体管（M3），与电容器（Cst）的第二极板及第二晶体管（M2）电性连接，并由一第一驱动信号（S1）控制，用于控制第二晶体管（M2）的栅极和漏极的导通或断开；一第四晶体管（M4），与第二晶体管（M2）及第三晶体管（M3）电性连接，并由一第二驱动信号（S2）控制，用于控制将来自于第二晶体管（M2）的驱动电流传输至一有机发光元件（OLED）。

Description

有机发光显示器像素驱动电路
本发明要求2014年11月04日递交的发明名称为“有机发光显示器像素驱动电路”的申请号为201410614776.2的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及有机发光显示领域，尤其涉及一种有机发光显示器像素驱动电路。
背景技术
有机发光显示器(organic light emitting display，OLED)是一种利用有机半导体材料制成的、且使用直流电压驱动的薄膜发光器件，其具有自发光的特性。OLED主要采用较薄的有机材料涂层和玻璃基板制成，而且无需背光源。因此，当有电流通路时，这些有机材料就会主动发光。
由于OLED依赖于电流驱动，因此OLED的发光亮度与流经该OLED的电流大小有关，所以作为驱动的薄膜晶体管(Thin-film transistor，TFT)的电学性能会直接影响上述OLED的显示效果，尤其是TFT的阈值电压经常会发生漂移，使得整个OLED显示器件出现了亮度不均匀的问题。
为了改善上述OLED的显示效果，一般都要通过驱动电路对OLED进行像素补偿。然而，现有的OLED像素补偿电路的数据电压信号和参考电压信号需要采用不同的布线输入，而且上述数据电压信号和参考电压信号分别需要一个TFT进行时序控制输出。因此，现有的OLED像素补偿电路需要使用较多的元件(如晶体管)，如此不但增加了布线成本，而且增加了线路的复杂度。
发明内容
本发明提供一种有机发光显示器像素驱动电路，其使用较少的元件，不但降低了整个电路的布线成本，而且电路结构简单，通过减少布线而增加面板开口率。
本发明一方面提供了一种有机发光显示器像素驱动电路，所述有机发光显示器像素驱动电路包括：一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管及一电容器；
所述第一晶体管由一扫描驱动信号控制，用于控制数据信号和参考电压信号传输至所述电容器的第一极板；
所述第二晶体管与所述电容器的第二极板电性连接，用于确定驱动电流的大小，所述驱动电流由所述第二晶体管的栅极和漏极之间的电压差决定；
所述第三晶体管与所述电容器的第二极板及所述第二晶体管电性连接，并由一第一驱动信号控制，用于控制所述第二晶体管的栅极和漏极的导通或断开；以及
所述第四晶体管与所述第二晶体管及所述第三晶体管电性连接，并由一第二驱动信号控制，用于控制将来自于所述第二晶体管的驱动电流传输至一有机发光元件。
其中，所述第一晶体管为扫描晶体管，其作为信号输入端的第一电极与信号线电性连接，并接收输入的数据信号和参考电压信号，所述第一晶体管的第二电极与所述电容器的第一极板电性连接，所述第一晶体管的栅极由扫描驱动信号控制，用于控制所述数据信号和参考电压信号传输至所述电容器的第一极板。
其中，所述第二晶体管可为驱动晶体管，其第一电极与电源电压信号线电性连接，并接收输入的电源电压信号，所述第二晶体管的第二电极与所述第三晶体管的第二电极及所述第四晶体管的第一电极电性连接，所述第二晶体管的栅极与所述电容器的第二极板及所述第三晶体管的第一电极电性连接。
其中，所述第三晶体管可为补偿电路晶体管，其第一电极与所述第二晶体管的栅极及所述电容器的第二极板电性连接，所述第三晶体管的第二电极与所述第二晶体管的第二电极及所述第四晶体管的第一电极电性连接。
其中，所述第四晶体管为节点复位控制晶体管，其第一电极与所述第二晶体管的第二电极及所述第三晶体管的第二电极电性连接，该第四晶体管的第二电极与所述有机发光元件电性连接，所述有机发光元件响应所述驱动电流而发光显示。
其中，所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管均为P型晶体管；或
所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管均为N型晶体管；或
所述第一晶体管、所述第三晶体管及所述第四晶体管均为N型晶体管，所述第二晶体管为P型晶体管。
其中，所述像素驱动电路的驱动时序包括：节点电压复位阶段、阈值电压侦测阶段、参考电压信号写入阶段、稳压平衡阶段及发光阶段，在所述节点电压复位阶段，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为低电平，所述第一晶体管、所述第三晶体管及所述第四晶体管导通，所述第二驱动信号为低电平，所述第二晶体管处于截止状态。
其中，在所述阈值电压侦测阶段，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为低电平，所述第一晶体管及所述第三晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；在所述阈值侦测阶段，所述电容器的第一极板与第二极板之间的电压差中包含有所述第二晶体管的阈值电压，并将该阈值电压存储于所述电容器上。
其中，在参考电压信号写入阶段，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为高电平，所述第三晶体管处于截止状态，所述第一晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；所述数据信号通过所述电容器耦合至所述该电容器的第二极板上。
其中，在稳压平衡阶段，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态，即所述电容器的第一极板被断开；所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；
在发光阶段，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态；所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为低电平，所述第二晶体管及所述第四晶体管导通；所述驱动电流通过所述第四晶体管传输至所述有机发光元件，以驱动该有机发光 件发光显示。
本发明另一方面提供了一种有机发光显示器像素驱动方法，其特征在于，所述有机发光显示器像素驱动方法利用一像素驱动电路进行像素驱动，该像素驱动电路包括：一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管及一电容器；所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管均为P型晶体管；所述像素驱动方法包括以下步骤：节点电压复位；阈值电压侦测；参考电压信号输入；稳压平衡；发光。
其中，在节点电压复位步骤，所述第一晶体管栅极的扫描驱动信号为低电平，一第一驱动信号为低电平，所述第一晶体管、所述第三晶体管及所述第四晶体管导通；一第二驱动信号为低电平，所述第二晶体管处于截止状态；数据信号通过所述第一晶体管传输至一电容器的第一极板。
其中，在阈值电压侦测步骤，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为低电平，所述第一晶体管及所述第三晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；当所述第二晶体管的栅极电压被拉高到与其源极电压的电压差小于等于该第二晶体管的阈值电压时，则所述第二晶体管将处于截止状态，并将所述阈值电压存储于所述电容器上。
其中，在参考电压信号写入步骤，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为高电平，所述第三晶体管处于截止状态，所述第一晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；一参考电压信号通过所述第一晶体管传输至所述电容器的第一极板，所述第二晶体管、所述第三晶体管所述和第四晶体管都处于截止状态，所述数据信号通过所述电容器耦合至所述该电容器的第二极板上。
其中，在稳压平衡步骤，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态，所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；
在发光步骤，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态；所述第一驱动信号为高电平，所述第三晶体管处于截止状 态；所述第二驱动信号为低电平，所述第二晶体管及所述第四晶体管导通，流经所述第四晶体管产生的驱动电流传输至一有机发光元件。
其中，所述第一晶体管为扫描晶体管，所述第二晶体管可为驱动晶体管，所述第三晶体管可为补偿电路晶体管，所述第四晶体管为节点复位控制晶体管，所述电容器为存储电容。
本发明另一方面还提供一种有机发光显示器，包括一有机发光元件，其特征在于，所述有机发光显示器还包括一像素驱动电路，所述有机发光显示器像素驱动电路包括：一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管及一电容器；所述第一晶体管由一扫描驱动信号控制，用于控制数据信号和参考电压信号传输至所述电容器的第一极板；所述第二晶体管与所述电容器的第二极板电性连接，用于确定驱动电流的大小，所述驱动电流由所述第二晶体管的栅极和漏极之间的电压差决定；所述第三晶体管与所述电容器的第二极板及所述第二晶体管电性连接，并由一第一驱动信号控制，用于控制所述第二晶体管的栅极和漏极的导通或断开；所述第四晶体管与所述第二晶体管及所述第三晶体管电性连接，并由一第二驱动信号控制，用于控制将来自于所述第二晶体管的驱动电流传输至所述有机发光元件，该有机发光元件响应所述驱动电流而发光。
相较于现有技术，在本发明实施例的有机发光显示器像素驱动电路及像素驱动方法中，所述数据电压信号和参考电压信号F通过同一个线路输入晶体管，而且仅需要一个作为驱动的薄膜晶体管(Thin-film transistor，TFT)对该数据电压信号和参考电压信号进行时序控制输出，如此，不但减少了电路元件(如晶体管)的使用，简化了电路结构，降低了整个电路的布线成本，而且通过减少布线增加了面板开口率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施例的有机发光显示器像素驱动电路的示意图。
图2是本发明一实施例的有机发光显示器像素驱动电路的驱动信号时序图。
图3是本发明一实施例的有机发光显示器像素驱动电路在节点电压复位阶段t1的电流通路示意图。
图4是本发明一实施例的有机发光显示器像素驱动电路在阈值电压侦测阶段t2的电流通路示意图。
图5是本发明一实施例的有机发光显示器像素驱动电路在参考电压信号写入阶段t3的电流通路示意图。
图6是本发明一实施例的有机发光显示器像素驱动电路在发光阶段t5的电流通路示意图。
图7是本发明另一实施例的有机发光显示器像素驱动方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1是本发明一实施例的有机发光显示器像素驱动电路的示意图。如图2所示，本发明实施例的有机发光显示器像素驱动电路100至少包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、电容器Cst及有机发光元件OLED(organic light-emitting display)。在本发明的实施例中，所述像素驱动电路100可为AMOLED(active matrix/organic light emitting diode，有源矩阵有机发光二极管)驱动电路。所述电容器Cst为存储电容。
在本发明的实施例中，所述第一晶体管M1可为扫描晶体管，其作为信号输入端的第一电极与信号线电性连接，并接收所输入的数据信号VDATA和参考电压信号VREF，所述第一晶体管M1的第二电极与所述电容器Cst的第一极板电性连接；所述第一晶体管M1的栅极(Gate)由扫描驱动信号控制，具 体用于控制所述数据信号VDATA和参考电压信号VREF传输至所述电容器Cst的第一极板。在本发明实施例中，所述第一晶体管M1的第一电极为源极(Source)，其第二电极为漏极(Drain)。
在本发明的实施例中，所述第二晶体管M2可为驱动晶体管，其作为信号输入端的第一电极与电源电压信号线电性连接，并接收输入的电源电压信号VDD；所述第二晶体管M2的第二电极与所述第三晶体管M3的第二电极及所述第四晶体管M4的第一电极电性连接；所述第二晶体管M2的栅极与所述电容器Cst的第二极板及所述第三晶体管M3的第一电极电性连接。所述第二晶体管M2用于确定驱动电流的大小，所述驱动电流由所述第二晶体管M2栅极与第一电极之间的电压差决定的。在本发明实施例中，所述第二晶体管M2的第一电极为源极，其第二电极为漏极。
在本发明的实施例中，所述第三晶体管M3可为补偿电路晶体管，其第一电极与所述第二晶体管M2的栅极及所述电容器Cst的第二极板电性连接；所述第三晶体管M3的第二电极与所述第二晶体管M2的第二电极及所述第四晶体管M4的第一电极电性连接。所述第三晶体管M3的栅极由第一驱动信号S1控制，具体用于控制所述第二晶体管M2的栅极和漏极(即第二电极)的导通或断开。在本发明实施例中，所述第三晶体管M3的第一电极为源极，其第二电极为漏极。
在本发明的实施例中，所述第四晶体管M4可为节点复位控制晶体管，其第一电极与所述第二晶体管M2的第二电极及所述第三晶体管M3的第二电极电性连接，该第四晶体管M4的第二电极与所述有机发光元件OLED电性连接。所述第四晶体管M4的栅极由第二驱动信号S2控制，具体用于控制将来自于所述第二晶体管M2的第二电极的驱动电流传输至所述有机发光元件OLED，则所述有机发光元件OLED响应所述驱动电流而发光显示。在本发明实施例中，所述第四晶体管M4的第一电极为源极，其第二电极为漏极。
请参阅图2，图2是本发明一实施例的有机发光显示器像素驱动电路的驱动信号时序图。图2所示的驱动信号时序图仅为其中一种实施例，其对应于所述第一晶体管M1、第二晶体管M2、第三晶体管M3及所述第四晶体管M4均为P型晶体管的情况，例如P沟道的金属-氧化物半导体场效应管 (metal-oxide semiconductor field effect transistor，简称MOS-FET)。可以理解，所述第一晶体管M1、第二晶体管M2、第三晶体管M3及所述第四晶体管M4也可以为其他类型的晶体管(例如，N型晶体管，具体可为N沟道的MOS-FET)，并可根据实际电路布线需要相应地调整电路连接方式、信号输入方式、信号传输方向及大小等相关参数即可，在此不再赘述。
请参阅图2，具体地，所述第一驱动信号S1控制所述第三晶体管M3，以进一步控制所述第二晶体管M2的栅极和漏极的导通或断开，所述第二驱动信号S2控制所述第四晶体管M4，以将来自于所述第二晶体管M2的驱动电流传输至所述有机发光元件OLED。所述VDATA代表数据信号，所述VREF代表参考电压信号。所述第一驱动信号S1和第二驱动信号S2均由有机发光显示器的栅极驱动线提供。
如图2所示，本发明实施例的像素驱动电路的驱动时序包括：节点电压复位阶段、阈值电压侦测阶段、参考电压信号VREF写入阶段、稳压平衡阶段及发光阶段，上述五个阶段分别对应图2中的t1、t2、t3、t4及t5时间段。其中，节点电压复位阶段t1时，所述第一晶体管M1、第三晶体管M3及第四晶体管M4处于导通状态，为所述电容器Cst的第二节点N2(也即为该电容器Cst的第二极板)的节点电压复位阶段；阈值电压侦测阶段t2时，所述第一晶体管M1和第三晶体管M3处于导通状态，所述第二晶体管M2和第四晶体管M4处于截止状态，则所述电容器Cst的第一节点N1(也即为该电容器Cst的第一基板)和第二节点N2的电压分别为VDD-Vth和VDATA；参考电压信号VREF写入阶段t3时，所述第一晶体管M1处于导通状态，所述第二晶体管M2、第三晶体管M2和第四晶体管M4处于截止状态；发光阶段t5时，所述第一晶体管M1和第三晶体管M3处于截止状态，所述第二晶体管M2和第四晶体管M4处于导通状态。
图3是本发明一实施例的有机发光显示器像素驱动电路在节点电压复位阶段t1的电流通路示意图；图4是本发明一实施例的有机发光显示器像素驱动电路在阈值电压侦测阶段t2的电流通路示意图；图5是本发明一实施例的有机发光显示器像素驱动电路在参考电压信号写入阶段t3的电流通路示意图。图6是本发明一实施例的有机发光显示器像素驱动电路在发光阶段t5的电流 通路示意图。为了便于说明，图3至图6中采用箭头的方式标出了不同阶段的电流的通路，并将晶体管上打上符号“X”来表示该晶体管处于截止状态。
以下结合图1至图6来具体说明本发明的实施例的有机发光显示器像素驱动电路100的工作原理。
如图2及图3所示，在所述节点电压复位阶段t1，所述第一晶体管M1栅极的扫描驱动信号为低电平，所述第一驱动信号S1为低电平，所述第一晶体管M1、第三晶体管M3及第四晶体管M4导通；所述第二驱动信号S2为低电平，所述第二晶体管M2处于截止状态。从图3中可以看出，所述数据信号VDATA通过所述第一晶体管M1传输至所述电容器Cst的第一节点N1，同时所述第三晶体管M3与所述第四晶体管M4之间形成一条电流通路，所述有机发光元件OLED的阴极低电位VEE通过上述电流通路施加至所述电容器Cst的第二节点N2，则所述第二晶体管M2的栅极也为低电平，如此，整个像素驱动电路100的节点电压复位过程完成。
如图2和图4所示，在所述阈值电压侦测阶段t2，所述第一晶体管M1栅极的扫描驱动信号为低电平，所述第一驱动信号S1为低电平，所述第一晶体管M1及第三晶体管M3导通；所述第二驱动信号S2为高电平，所述第二晶体管M2及所述第四晶体管M4处于截止状态。从图4中可以看出，由于在所述节点电压复位阶段t1，所述第二晶体管M2的栅极为低电位，使得该第二晶体管M2处于导通状态，则所述第二晶体管M2与所述第三晶体管M3之间形成一条电流通路，电源电压信号VDD通过上述电流通路达到所述第二节点N2，则该第二节点N2的电位逐渐被所述电源电压信号VDD拉高。根据晶体管的电压-电流特性，当晶体管的栅极电压和源极电压之间的电压差小于该晶体管的阈值电压时，则该晶体管截止，也即是说，当所述第二晶体管M2的栅极电压被拉高到与其源极电压的电压差小于等于该第二晶体管M2的阈值电压Vth时，则所述第二晶体管M2将处于截止状态。又由于所述第二晶体管M2的源极和电源电压信号线电性连接，因此其源极电位保持VDD不变，因此当所述第二晶体管M2截止时，该第二晶体管M2的栅极电压为(VDD-Vth)，其中，VDD为电源电压，Vth为所述第二晶体管M2的阈值电压。此时，所述电容器Cst的第一极板与第二极板之间的电压差Vc为： Vc＝V2-V1＝VDD-Vth-VTATA  (1)。
其中，V2代表所述电容器Cst的第二节点N2的电位，V1代表该电容器Cst的第一节点N1的电位。由上述可知，在所述阈值侦测阶段t2，所述电容器Cst的第一极板与第二极板之间的电压差Vc中包含有所述第二晶体管M2的阈值电压Vth，并将该阈值电压Vth存储于所述电容器Cst上。
如图2及图5所示，在参考电压信号VREF写入阶段t3，所述第一晶体管M1栅极的扫描驱动信号为低电平，所述第一驱动信号S1为高电平，所述第三晶体管M3处于截止状态，第一晶体管M1导通；所述第二驱动信号S2为高电平，所述第二晶体管M2及所述第四晶体管M4处于截止状态。从图5中可以看出，所述参考电压信号VREF通过所述第一晶体管M1传输至所述电容器Cst的第一节点N1(即该电容器Cst的第一极板)，同时所述第二晶体管M2、第三晶体管M3和第四晶体管M4都处于截止状态，也即是说，所述电容器Cst的第二极板被断开，所以该电容器Cst的第一极板与第二极板之间的电压差Vc保持不变。但是由于所述第一节点N1的电位变为VREF，因此相应地所述第二节点N2的电位V2’变为：V2’＝Vc+VREF＝VDD-Vth-VDATA+VREF  (2)
由上述可知，所述数据信号VDATA通过所述电容器Cst耦合至所述该电容器Cst的第二极板上。
在稳压平衡阶段t4，所述第一晶体管M1栅极的扫描驱动信号为高电平，所述第一晶体管M1处于截止状态，即所述电容器Cst的第一极板被断开；所述第一驱动信号S1为高电平，所述第三晶体管M3处于截止状态；所述第二驱动信号S2为高电平，所述第二晶体管M2及所述第四晶体管M4处于截止状态。因此，所述电容器Cst的第二节点N2的电位保持不变，如此完成了稳压平衡过程。
如图2及图图6所示，在发光阶段t5，所述第一晶体管M1栅极的扫描驱动信号为高电平，所述第一晶体管M1处于截止状态；所述第一驱动信号S1为高电平，所述第三晶体管M3处于截止状态；所述第二驱动信号S2为低电平，所述第二晶体管M2及所述第四晶体管M4导通。从图6中可以看出，所述第二晶体管M2与所述第四晶体管M4之间形成一电流通路，此时，该第二 晶体管M2的栅极与源极之间的电压差Vgs为：Vgs＝V2’-VDD＝VREF-Vth-VDATA  (3)
由于所述第二晶体管M2工作在饱和区，则流经该第二晶体管M2的驱动电流由其栅极与源极之间的电压差决定，根据晶体管在饱和区的电学特性，可以得到该第二晶体管M2的驱动电流I为：I＝K(Vsg-Vth)2＝K(VREF-VDATA)2(6)
其中，I为所述第二晶体管M2产生的驱动电流，K为常数，VREF为参考电压信号，VDATA为数据信号。所述第二晶体管M2产生的驱动电流传输至所述第四晶体管M4，又由于该第四晶体管M4工作在线性区，其可将所述驱动电流I传输至所述有机发光元件OLED，以驱动其发光显示。
可以理解的是，所述第一晶体管M1、所述第三晶体管M3及第四晶体管M4可以为N型晶体管，同时所述第二晶体管M2为P型晶体管，相应地改变上述第一晶体管M1、第二晶体管M2、所述第三晶体管M3及第四晶体管M4的连接关系、信号输入方向等参数即可实现上述各个步骤的功能，本发明实施例对此不作具体限制，其具体过程在在赘述。
由上述可知，在本发明实施例的有机发光显示器像素驱动电路100中，所述数据电压信号VDATA和参考电压信号VREF通过同一个线路输入晶体管，而且仅需要一个作为驱动的薄膜晶体管(Thin-film transistor，TFT)对该数据电压信号VDATA和参考电压信号VREF进行时序控制输出，如此，不但减少了电路元件(如晶体管)的使用，简化了电路结构，降低了整个电路的布线成本，而且通过减少布线增加了面板开口率。此外，由于驱动电路I的大小仅与所述数据电压信号VDATA和参考电压信号VREF相关，而与所述驱动晶体管M2的阈值电压和电源电压信号无关，实现了对阈值电压和电源线电压降的补偿作用，并且在整个驱动过程中确保电容器Cst的两端电压始终只有一端单独变化，减少了寄生电容耦合效应对节点电位的影响，解决了阈值侦测不准确的问题，从而对OLED进行精确的像素效果，获得较佳的显示效果。
请参阅图7，图7是本发明另一实施例的有机发光显示器像素驱动方法的流程图。在本实施例中的第一晶体管M1、第二晶体管M2、第三晶体管M3 及第四晶体管M4均为P型晶体管(如P沟道的MOS-FET)，可以理解，所述第一晶体管M1、第二晶体管M2、第三晶体管M3及所述第四晶体管M4也可以为其他类型的晶体管(例如N沟道的MOS-FET)，在此不再赘述。本发明实施例以所述第一晶体管M1、第二晶体管M2、第三晶体管M3及第四晶体管M4均为P型晶体管为例加以说明。如图7所示，所述有机发光显示器像素驱动方法包括如下步骤。
S701：节点电压复位。
在本发明的实施例中，具体为，所述第一晶体管M1栅极的扫描驱动信号为低电平，第一驱动信号S1为低电平，所述第一晶体管M1、第三晶体管M3及第四晶体管M4导通；第二驱动信号S2为低电平，所述第二晶体管M2处于截止状态。数据信号VDATA通过所述第一晶体管M1传输至一电容器Cst的第一极板(也即为该电容器Cst的第一节点N1)。
S702：阈值电压侦测。
在本发明的实施例中，具体为，所述第一晶体管M1栅极的扫描驱动信号为低电平，所述第一驱动信号S1为低电平，所述第一晶体管M1及所述第三晶体管M3导通；所述第二驱动信号S2为高电平，所述第二晶体管M2及所述第四晶体管M4处于截止状态。由于在步骤节点电压复位中，所述第二晶体管M2的栅极为低电位，使得该第二晶体管M2处于导通状态，则所述第二晶体管M2与所述第三晶体管M3之间形成一条电流通路，一电源电压信号VDD通过上述电流通路到达所述电容器Cst的第二极板(也即为该电容器Cst的第二节点N2)，则该第二极板的电位逐渐被所述电源电压信号VDD拉高。根据晶体管的电压-电流特性，当所述第二晶体管M2的栅极电压被拉高到与其源极电压的电压差小于等于该第二晶体管M2的阈值电压时，则所述第二晶体管M2将处于截止状态，并将所述阈值电压存储于所述电容器Cst上。
S703：参考电压信号写入。
在本发明的实施例中，具体为，所述第一晶体管M1栅极的扫描驱动信号为低电平，所述第一驱动信号S1为高电平，所述第三晶体管M3处于截止状态，第一晶体管M1导通；所述第二驱动信号S2为高电平，所述第二晶体管M2及所述第四晶体管M4处于截止状态。一参考电压信号VREF通过所述第 一晶体管M1传输至所述电容器Cst的第一极板，同时所述第二晶体管M2、所述第三晶体管M3所述和第四晶体管M4都处于截止状态，也即是说，所述电容器Cst的第二极板被断开，因此该电容器Cst的第一极板与第二极板之间的电压差Vc保持不变。所述数据信号VDATA通过所述电容器Cst耦合至所述该电容器Cst的第二极板上。
S704：稳压平衡。
在本发明的实施例中，具体为，所述第一晶体管M1栅极的扫描驱动信号为高电平，所述第一晶体管M1处于截止状态，即所述电容器Cst的第一极板被断开；所述第一驱动信号S1为高电平，所述第三晶体管M3处于截止状态；所述第二驱动信号S2为高电平，所述第二晶体管M2及所述第四晶体管M4处于截止状态。
S705：发光。
在本发明实施例中，具体为，所述第一晶体管M1栅极的扫描驱动信号为高电平，所述第一晶体管M1处于截止状态；所述第一驱动信号S1为高电平，所述第三晶体管M3处于截止状态；所述第二驱动信号S2为低电平，所述第二晶体管M2及所述第四晶体管M4导通。由于所述第二晶体管M2工作在饱和区，则流经该第二晶体管M2的驱动电流由其栅极与源极之间的电压差决定。所述第二晶体管M2产生的驱动电流传输至所述第四晶体管M4，又由于该第四晶体管M4工作在线性区，其可将所述驱动电流传输至一有机发光元件OLED，以驱动器发光显示。
可以理解的是，所述第一晶体管M1、所述第三晶体管M3及第四晶体管M4可以为N型晶体管，同时所述第二晶体管M2为P型晶体管，相应地改变上述第一晶体管M1、第二晶体管M2、所述第三晶体管M3及第四晶体管M4的连接关系、信号输入方向等参数即可实现上述各个步骤的功能，本发明实施例对此不作具体限制，其具体过程在在赘述。
在本发明实施例的有机发光显示器像素驱动方法中，所述数据电压信号VDATA和参考电压信号VREF通过同一个线路输入晶体管，而且仅需要一个作为驱动的薄膜晶体管(Thin-film transistor，TFT)对该数据电压信号VDATA和参考电压信号VREF进行时序控制输出，如此，不但减少了电路元件(如晶 体管)的使用，简化了电路结构，降低了整个电路的布线成本，而且通过减少布线增加了面板开口率。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (17)

  1. 一种有机发光显示器像素驱动电路，其特征在于，所述有机发光显示器像素驱动电路包括：一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管及一电容器；
    所述第一晶体管由一扫描驱动信号控制，用于控制数据信号和参考电压信号传输至所述电容器的第一极板；
    所述第二晶体管与所述电容器的第二极板电性连接，用于确定驱动电流的大小，所述驱动电流由所述第二晶体管的栅极和漏极之间的电压差决定；
    所述第三晶体管与所述电容器的第二极板及所述第二晶体管电性连接，并由一第一驱动信号控制，用于控制所述第二晶体管的栅极和漏极的导通或断开；以及
    所述第四晶体管与所述第二晶体管及所述第三晶体管电性连接，并由一第二驱动信号控制，用于控制将来自于所述第二晶体管的驱动电流传输至一有机发光元件。
  2. 如权利要求1所述的有机发光显示器像素驱动电路，其特征在于，所述第一晶体管为扫描晶体管，其作为信号输入端的第一电极与信号线电性连接，并接收输入的数据信号和参考电压信号，所述第一晶体管的第二电极与所述电容器的第一极板电性连接，所述第一晶体管的栅极由扫描驱动信号控制，用于控制所述数据信号和参考电压信号传输至所述电容器的第一极板。
  3. 如权利要求1所述的有机发光显示器像素驱动电路，其特征在于，所述第二晶体管可为驱动晶体管，其第一电极与电源电压信号线电性连接，并接收输入的电源电压信号，所述第二晶体管的第二电极与所述第三晶体管的第二电极及所述第四晶体管的第一电极电性连接，所述第二晶体管的栅极与所述电容器的第二极板及所述第三晶体管的第一电极电性连接。
  4. 如权利要求1所述的有机发光显示器像素驱动电路，其特征在于，所 述第三晶体管可为补偿电路晶体管，其第一电极与所述第二晶体管的栅极及所述电容器的第二极板电性连接，所述第三晶体管的第二电极与所述第二晶体管的第二电极及所述第四晶体管的第一电极电性连接。
  5. 如权利要求1所述的有机发光显示器像素驱动电路，其特征在于，所述第四晶体管为节点复位控制晶体管，其第一电极与所述第二晶体管的第二电极及所述第三晶体管的第二电极电性连接，该第四晶体管的第二电极与所述有机发光元件电性连接，所述有机发光元件响应所述驱动电流而发光显示。
  6. 如权利要求1所述的有机发光显示器像素驱动电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管均为P型晶体管；或
    所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管均为N型晶体管；或
    所述第一晶体管、所述第三晶体管及所述第四晶体管均为N型晶体管，所述第二晶体管为P型晶体管。
  7. 如权利要求1所述的有机发光显示器像素驱动电路，其特征在于，所述像素驱动电路的驱动时序包括：节点电压复位阶段、阈值电压侦测阶段、参考电压信号写入阶段、稳压平衡阶段及发光阶段，在所述节点电压复位阶段，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为低电平，所述第一晶体管、所述第三晶体管及所述第四晶体管导通，所述第二驱动信号为低电平，所述第二晶体管处于截止状态。
  8. 如权利要求7所述的有机发光显示器像素驱动电路，其特征在于，在所述阈值电压侦测阶段，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为低电平，所述第一晶体管及所述第三晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；在所述阈值侦测阶段，所述电容器的第一极板与第二极板之间的电压差中包含有所述第 二晶体管的阈值电压，并将该阈值电压存储于所述电容器上。
  9. 如权利要求7所述的有机发光显示器像素驱动电路，其特征在于，在参考电压信号写入阶段，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为高电平，所述第三晶体管处于截止状态，所述第一晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；所述数据信号通过所述电容器耦合至所述该电容器的第二极板上。
  10. 如权利要求7所述的有机发光显示器像素驱动电路，其特征在于，在稳压平衡阶段，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态，即所述电容器的第一极板被断开；所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；
    在发光阶段，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态；所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为低电平，所述第二晶体管及所述第四晶体管导通；所述驱动电流通过所述第四晶体管传输至所述有机发光元件，以驱动该有机发光件发光显示。
  11. 一种有机发光显示器像素驱动方法，其特征在于，所述有机发光显示器像素驱动方法利用一像素驱动电路进行像素驱动，该像素驱动电路包括：一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管及一电容器；所述第一晶体管、所述第二晶体管、所述第三晶体管及所述第四晶体管均为P型晶体管；所述像素驱动方法包括以下步骤：节点电压复位；阈值电压侦测；参考电压信号输入；稳压平衡；发光。
  12. 如权利要求11所述的有机发光显示器像素驱动方法，其特征在于，在节点电压复位步骤，所述第一晶体管栅极的扫描驱动信号为低电平，一第一驱动信号为低电平，所述第一晶体管、所述第三晶体管及所述第四晶体管导通； 一第二驱动信号为低电平，所述第二晶体管处于截止状态；数据信号通过所述第一晶体管传输至一电容器的第一极板。
  13. 如权利要求12所述的有机发光显示器像素驱动方法，其特征在于，在阈值电压侦测步骤，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为低电平，所述第一晶体管及所述第三晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；当所述第二晶体管的栅极电压被拉高到与其源极电压的电压差小于等于该第二晶体管的阈值电压时，则所述第二晶体管将处于截止状态，并将所述阈值电压存储于所述电容器上。
  14. 如权利要求12所述的有机发光显示器像素驱动方法，其特征在于，在参考电压信号写入步骤，所述第一晶体管栅极的扫描驱动信号为低电平，所述第一驱动信号为高电平，所述第三晶体管处于截止状态，所述第一晶体管导通；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；一参考电压信号通过所述第一晶体管传输至所述电容器的第一极板，所述第二晶体管、所述第三晶体管所述和第四晶体管都处于截止状态，所述数据信号通过所述电容器耦合至所述该电容器的第二极板上。
  15. 如权利要求12所述的有机发光显示器像素驱动方法，其特征在于，在稳压平衡步骤，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态，所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为高电平，所述第二晶体管及所述第四晶体管处于截止状态；
    在发光步骤，所述第一晶体管栅极的扫描驱动信号为高电平，所述第一晶体管处于截止状态；所述第一驱动信号为高电平，所述第三晶体管处于截止状态；所述第二驱动信号为低电平，所述第二晶体管及所述第四晶体管导通，流经所述第四晶体管产生的驱动电流传输至一有机发光元件。
  16. 如权利要求11所述的有机发光显示器像素驱动方法，其特征在于，所述第一晶体管为扫描晶体管，所述第二晶体管可为驱动晶体管，所述第三晶体管可为补偿电路晶体管，所述第四晶体管为节点复位控制晶体管，所述电容器为存储电容。
  17. 一种有机发光显示器，包括一有机发光元件，其特征在于，所述有机发光显示器还包括一像素驱动电路，所述有机发光显示器像素驱动电路包括：一第一晶体管、一第二晶体管、一第三晶体管、一第四晶体管及一电容器；所述第一晶体管由一扫描驱动信号控制，用于控制数据信号和参考电压信号传输至所述电容器的第一极板；所述第二晶体管与所述电容器的第二极板电性连接，用于确定驱动电流的大小，所述驱动电流由所述第二晶体管的栅极和漏极之间的电压差决定；所述第三晶体管与所述电容器的第二极板及所述第二晶体管电性连接，并由一第一驱动信号控制，用于控制所述第二晶体管的栅极和漏极的导通或断开；所述第四晶体管与所述第二晶体管及所述第三晶体管电性连接，并由一第二驱动信号控制，用于控制将来自于所述第二晶体管的驱动电流传输至所述有机发光元件，该有机发光元件响应所述驱动电流而发光。
PCT/CN2014/092656 2014-11-04 2014-12-01 有机发光显示器像素驱动电路 WO2016070477A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/423,672 US20160343298A1 (en) 2014-11-04 2014-12-01 Pixel driving circuit of organic light emitting display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410614776.2 2014-11-04
CN201410614776.2A CN104361857A (zh) 2014-11-04 2014-11-04 有机发光显示器像素驱动电路

Publications (1)

Publication Number Publication Date
WO2016070477A1 true WO2016070477A1 (zh) 2016-05-12

Family

ID=52529114

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/092656 WO2016070477A1 (zh) 2014-11-04 2014-12-01 有机发光显示器像素驱动电路

Country Status (3)

Country Link
US (1) US20160343298A1 (zh)
CN (1) CN104361857A (zh)
WO (1) WO2016070477A1 (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104933993B (zh) * 2015-07-17 2017-12-08 合肥鑫晟光电科技有限公司 像素驱动电路及其驱动方法、显示装置
CN105528996B (zh) 2016-01-29 2018-04-10 深圳市华星光电技术有限公司 像素补偿电路、方法、扫描驱动电路及平面显示装置
CN107093404A (zh) 2016-02-17 2017-08-25 上海和辉光电有限公司 像素补偿电路和显示装置
CN106531067B (zh) 2016-12-23 2019-08-30 上海天马有机发光显示技术有限公司 一种像素电路及其显示装置
CN107170412B (zh) * 2017-07-11 2018-01-05 深圳市华星光电半导体显示技术有限公司 一种amoled像素驱动电路及像素驱动方法
CN109256086A (zh) * 2017-07-12 2019-01-22 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板
TWI623927B (zh) * 2017-07-20 2018-05-11 友達光電股份有限公司 顯示面板及其畫素的驅動方法
CN109935207B (zh) * 2017-12-15 2021-04-13 京东方科技集团股份有限公司 像素驱动电路、像素电路和显示装置及其驱动方法
US10475385B2 (en) 2018-02-28 2019-11-12 Shenzhen China Star Optoelectronics Technology Co., Ltd. AMOLED pixel driving circuit and driving method capable of ensuring uniform brightness of the organic light emitting diode and improving the display effect of the pictures
CN108335671B (zh) * 2018-02-28 2019-10-11 深圳市华星光电技术有限公司 Amoled像素驱动电路及驱动方法
KR102480426B1 (ko) * 2018-03-15 2022-12-22 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN108447447B (zh) * 2018-05-25 2023-08-08 南京微芯华谱信息科技有限公司 适用于共阳极的自发光电流型像素单元电路、驱动电流的产生方法
CN113366562A (zh) * 2019-07-12 2021-09-07 深圳市柔宇科技股份有限公司 像素单元、阵列基板与显示终端
CN110890055A (zh) * 2019-11-25 2020-03-17 南京中电熊猫平板显示科技有限公司 一种自发光显示装置以及像素内补偿电路
CN111682058B (zh) * 2020-07-08 2022-11-25 京东方科技集团股份有限公司 显示面板、显示装置
CN112837656A (zh) * 2021-01-11 2021-05-25 武汉华星光电半导体显示技术有限公司 像素驱动电路、显示面板及其驱动方法
CN114664255B (zh) * 2022-04-20 2023-05-30 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路及显示面板
CN115312004A (zh) * 2022-08-24 2022-11-08 厦门天马显示科技有限公司 一种显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200511183A (en) * 2003-09-08 2005-03-16 Toppoly Optoelectronics Corp Circuit and method for driving active matrix OLED pixel with threshold voltage compensation
CN203179476U (zh) * 2013-04-24 2013-09-04 京东方科技集团股份有限公司 像素驱动电路、阵列基板以及显示装置
CN103295528A (zh) * 2013-05-14 2013-09-11 友达光电股份有限公司 发光二极管模块
CN103915057A (zh) * 2013-01-04 2014-07-09 友达光电股份有限公司 像素驱动电路及使用其的有机发光显示器
CN104050914A (zh) * 2014-05-19 2014-09-17 京东方科技集团股份有限公司 像素驱动电路、显示装置和像素驱动方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229506B1 (en) * 1997-04-23 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
US7456810B2 (en) * 2001-10-26 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and driving method thereof
KR100502912B1 (ko) * 2003-04-01 2005-07-21 삼성에스디아이 주식회사 발광 표시 장치 및 그 표시 패널과 구동 방법
US8378930B2 (en) * 2004-05-28 2013-02-19 Sony Corporation Pixel circuit and display device having symmetric pixel circuits and shared voltage lines
KR101162853B1 (ko) * 2010-06-01 2012-07-06 삼성모바일디스플레이주식회사 화소를 포함하는 유기전계발광 표시장치 및 이를 이용한 구동방법
JP5890656B2 (ja) * 2011-11-09 2016-03-22 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． 電気光学装置の駆動方法および電気光学装置
KR101411619B1 (ko) * 2012-09-27 2014-06-25 엘지디스플레이 주식회사 화소 회로와 그 구동 방법 및 이를 이용한 유기 발광 표시 장치
KR101973125B1 (ko) * 2012-12-04 2019-08-16 엘지디스플레이 주식회사 화소 회로와 그 구동 방법 및 이를 이용한 유기발광표시장치
KR101970574B1 (ko) * 2012-12-28 2019-08-27 엘지디스플레이 주식회사 Oled 표시 장치
KR101985501B1 (ko) * 2013-01-08 2019-06-04 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치, 및 그 구동 방법
CN103927975B (zh) * 2013-12-30 2016-02-10 上海天马微电子有限公司 一种有机发光显示器的像素补偿电路及方法
CN203760053U (zh) * 2014-04-02 2014-08-06 京东方科技集团股份有限公司 像素电路和显示装置
CN104050916B (zh) * 2014-06-04 2016-08-31 上海天马有机发光显示技术有限公司 一种有机发光显示器的像素补偿电路及方法
CN105206221B (zh) * 2014-06-13 2018-06-22 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200511183A (en) * 2003-09-08 2005-03-16 Toppoly Optoelectronics Corp Circuit and method for driving active matrix OLED pixel with threshold voltage compensation
CN103915057A (zh) * 2013-01-04 2014-07-09 友达光电股份有限公司 像素驱动电路及使用其的有机发光显示器
CN203179476U (zh) * 2013-04-24 2013-09-04 京东方科技集团股份有限公司 像素驱动电路、阵列基板以及显示装置
CN103295528A (zh) * 2013-05-14 2013-09-11 友达光电股份有限公司 发光二极管模块
CN104050914A (zh) * 2014-05-19 2014-09-17 京东方科技集团股份有限公司 像素驱动电路、显示装置和像素驱动方法

Also Published As

Publication number Publication date
US20160343298A1 (en) 2016-11-24
CN104361857A (zh) 2015-02-18

Similar Documents

Publication Publication Date Title
WO2016070477A1 (zh) 有机发光显示器像素驱动电路
US9633603B2 (en) Pixel compensating circuit and method of organic light emitting display
US9607545B2 (en) Organic light emitting display and pixel compensation circuit and method for organic light emitting display
TWI566221B (zh) A pixel circuit and a driving method thereof and an organic light emitting display
WO2019237735A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
KR101401606B1 (ko) 화소 유닛 회로, 화소 어레이, 패널 및 패널 구동방법
TWI573117B (zh) 主動式有機發光二極體顯示器的像素電路
WO2016023311A1 (zh) 像素驱动电路及其驱动方法和显示装置
WO2018000982A1 (zh) 像素电路及驱动方法和显示设备
US20160321988A1 (en) Pixel circuit, display panel, and display device
WO2017117940A1 (zh) 像素驱动电路、像素驱动方法、显示面板和显示装置
WO2016050021A1 (zh) 一种像素驱动电路及其驱动方法、像素单元、显示装置
WO2015180352A1 (zh) 像素电路及其驱动方法、有机发光显示面板及显示装置
WO2016165529A1 (zh) 像素电路及其驱动方法、显示装置
US8937489B2 (en) Inverter and scan driver using the same
US20190228708A1 (en) Pixel circuit, pixel driving method and display device
WO2015169006A1 (zh) 一种像素驱动电路及其驱动方法和显示装置
WO2017012075A1 (zh) 像素电路及其驱动方法、显示面板
WO2013127189A1 (zh) 像素单元驱动电路、像素单元驱动方法以及像素单元
WO2013127188A1 (zh) 像素单元驱动电路、像素单元驱动方法及像素单元
WO2017045376A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
TWI685831B (zh) 畫素電路及其驅動方法
WO2014134869A1 (zh) 像素电路、有机电致发光显示面板以及显示装置
WO2017128467A1 (zh) 像素补偿电路、方法及平面显示装置
CN111312173A (zh) 一种像素电路及像素驱动的方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14423672

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14905539

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14905539

Country of ref document: EP

Kind code of ref document: A1