WO2017128467A1 - 像素补偿电路、方法及平面显示装置 - Google Patents

像素补偿电路、方法及平面显示装置 Download PDF

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Publication number
WO2017128467A1
WO2017128467A1 PCT/CN2016/074552 CN2016074552W WO2017128467A1 WO 2017128467 A1 WO2017128467 A1 WO 2017128467A1 CN 2016074552 W CN2016074552 W CN 2016074552W WO 2017128467 A1 WO2017128467 A1 WO 2017128467A1
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Prior art keywords
controllable switch
switch
voltage
controllable
driving
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PCT/CN2016/074552
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English (en)
French (fr)
Inventor
吴小玲
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深圳市华星光电技术有限公司
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Priority to US15/023,381 priority Critical patent/US9966005B2/en
Publication of WO2017128467A1 publication Critical patent/WO2017128467A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel compensation circuit, method, and flat display device.
  • the current Organic Light Emitting Diode (OLED) display has the advantages of small size, simple structure, autonomous illumination, high brightness, large viewing angle, and short response time, and has attracted wide attention.
  • the existing organic light emitting diode display there is a transistor as a driving transistor for controlling the current passing through the organic light emitting diode OLED, so the importance of the threshold voltage of the driving transistor is very obvious, and the positive or negative drift of the threshold voltage will be Therefore, different currents pass through the organic light emitting diode under the same data signal, and current transistors in the process of use, such as illumination in the oxide semiconductor, voltage stress of the source and drain electrodes, etc., may cause the threshold voltage to drift, resulting in organic light emission.
  • the current of the diode is unstable, which causes the panel brightness to be uneven.
  • the technical problem to be solved by the present invention is to provide a pixel compensation circuit, a method and a flat display device, so as to avoid the instability of the current of the organic light emitting diode caused by the threshold voltage drift, thereby achieving uniform display of the brightness of the panel.
  • a technical solution adopted by the present invention is to provide a pixel compensation circuit, including:
  • the first controllable switch includes a control end, a first end, and a second end, wherein the control end of the first controllable switch is connected to a first scan line, and the first controllable switch The first end is connected to a data line to receive a data voltage from the data line;
  • the second controllable switch includes a control end, a first end and a second end, wherein the control end of the second controllable switch is connected to a second scan line, and the second controllable switch The first end is connected to the second end of the first controllable switch;
  • Driving a switch comprising a control end, a first end and a second end, the driving switch The control end is connected to the second end of the second controllable switch, the first end of the drive switch is connected to a first voltage end to receive the first voltage from the first voltage end;
  • the third controllable switch includes a control end, a first end and a second end, wherein the control end of the third controllable switch is connected to a third scan line, and the third controllable switch The first end is connected to the second end of the first controllable switch and the first end of the second controllable switch, and the second end of the third controllable switch is connected to the first end of the drive switch;
  • the storage capacitor includes a first end and a second end, the first end of the storage capacitor is connected to the second end of the first controllable switch, and the second end of the storage capacitor is connected to the drive switch Second end
  • An organic light emitting diode comprising an anode and a cathode, an anode of the organic light emitting diode being connected to a second end of the driving switch, and a cathode of the organic light emitting diode being grounded;
  • the fourth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fourth controllable switch is connected to a fourth scan line, and the fourth controllable switch The first end is connected to a second voltage terminal to receive a second voltage from the second voltage terminal, and the second end of the fourth controllable switch is connected to the second end of the driving switch.
  • the driving switch, the first controllable switch to the fourth controllable switch are all NMOS type thin film transistors or all PMOS type thin film transistors or a combination of NMOS type thin film transistors and PMOS type thin film transistors.
  • the control switch, the first controllable switch to the control terminal, the first end and the second end of the fourth controllable switch respectively correspond to a gate, a drain and a source of the thin film transistor.
  • a pixel compensation method including:
  • the driving switch and the fourth controllable switch are turned on, the first to third controllable switches are turned off, and the voltage Vb of the second end of the driving switch is equal to the second voltage VL outputted by the second voltage terminal because of the storage
  • the coupling of the capacitor, the voltage Va of the first end of the storage capacitor is lowered, thereby clearing the influence of the data of the previous frame;
  • the driving switch, the second controllable switch, and the third controllable switch are both turned on, and the first controllable switch and the fourth controllable switch are both turned off,
  • the storage capacitor is charged, and the voltage Vb of the second end of the driving switch is equal to the difference between the first voltage VDD outputted by the first voltage terminal and the threshold voltage Vth of the driving switch, and the voltage Va of the first end of the storage capacitor is equal to Said first voltage VDD;
  • the driving switch and the second controllable switch are both turned on, the first controllable switch, the third and fourth controllable switches are all turned off, and the storage capacitor is discharged,
  • the driving switch, the first controllable switch to the fourth controllable switch are all NMOS type thin film transistors or all PMOS type thin film transistors or a combination of NMOS type thin film transistors and PMOS type thin film transistors.
  • the control switch, the first controllable switch to the control terminal, the first end and the second end of the fourth controllable switch respectively correspond to a gate, a drain and a source of the thin film transistor.
  • the flat display device includes a scan driving circuit, the scan driving circuit includes a pixel compensation circuit, and the pixel compensation circuit includes:
  • the first controllable switch includes a control end, a first end, and a second end, wherein the control end of the first controllable switch is connected to a first scan line, and the first controllable switch The first end is connected to a data line to receive a data voltage from the data line;
  • the second controllable switch includes a control end, a first end and a second end, wherein the control end of the second controllable switch is connected to a second scan line, and the second controllable switch The first end is connected to the second end of the first controllable switch;
  • a driving switch the driving end, the first end and the second end, the control end of the driving switch is connected to the second end of the second controllable switch, and the first end of the driving switch is connected to the first end a voltage terminal for receiving a first voltage from the first voltage terminal;
  • the third controllable switch includes a control end, a first end and a second end, wherein the control end of the third controllable switch is connected to a third scan line, and the third controllable switch The first end is connected to the second end of the first controllable switch and the first end of the second controllable switch, and the second end of the third controllable switch is connected to the first end of the drive switch;
  • the storage capacitor includes a first end and a second end, the first end of the storage capacitor is connected to the second end of the first controllable switch, and the second end of the storage capacitor is connected to the drive switch First Two ends
  • An organic light emitting diode comprising an anode and a cathode, an anode of the organic light emitting diode being connected to a second end of the driving switch, and a cathode of the organic light emitting diode being grounded;
  • the fourth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fourth controllable switch is connected to a fourth scan line, and the fourth controllable switch The first end is connected to a second voltage terminal to receive a second voltage from the second voltage terminal, and the second end of the fourth controllable switch is connected to the second end of the driving switch.
  • the driving switch, the first controllable switch to the fourth controllable switch are all NMOS type thin film transistors or all PMOS type thin film transistors or a combination of NMOS type thin film transistors and PMOS type thin film transistors.
  • the control switch, the first controllable switch to the control terminal, the first end and the second end of the fourth controllable switch respectively correspond to a gate, a drain and a source of the thin film transistor.
  • the flat display device is an OLED or an LCD.
  • the beneficial effects of the present invention are: different from the prior art, the pixel compensation circuit and method of the present invention act to drive a transistor by using a plurality of thin film transistors in combination, thereby avoiding threshold voltage drift of the driving transistor.
  • the current of the organic light emitting diode is unstable, thereby achieving uniform display of panel brightness.
  • FIG. 1 is a schematic structural view of a pixel compensation circuit of the present invention
  • FIG. 2 is a waveform diagram of a pixel compensation circuit of the present invention.
  • FIG. 3 is a simulation result diagram of a pixel compensation circuit of the present invention.
  • Figure 4 is a schematic view of a scan driving circuit of the present invention.
  • Figure 5 is a schematic illustration of a flat display device of the present invention.
  • FIG. 1 is a schematic structural diagram of a pixel compensation circuit of the present invention.
  • the pixel compensation circuit of the present invention includes a first controllable switch T1 , the first controllable switch T1 includes a control end, a first end and a second end, and the control of the first controllable switch T1 Connected to a first scan line S4, the first end of the first controllable switch T1 is connected to a data line Data to receive the data voltage Vdata from the data line Data;
  • the second controllable switch T2 includes a control end, a first end, and a second end, The control end of the second controllable switch T2 is connected to a second scan line S3, and the first end of the second controllable switch T2 is connected to the second end of the first controllable switch T1;
  • the driving switch T0 includes a control end, a first end and a second end, and a control end of the driving switch T0 is connected to a second end of the second controllable switch T2, and the driving switch T0 is One end is connected to a first voltage terminal VDD1 to receive a first voltage VDD from the first voltage terminal VDD1;
  • the third controllable switch T3, the third controllable switch T3 includes a control end, a first end and a second end, and the control end of the third controllable switch T3 is connected to a third scan line S2, the third The first end of the controllable switch T3 is connected to the second end of the first controllable switch T1 and the first end of the second controllable switch T2, and the second end of the third controllable switch T3 is connected to the Driving the first end of the switch T0;
  • the storage capacitor C1 includes a first end and a second end, the first end of the storage capacitor C1 is connected to the second end of the first controllable switch T1, and the second end of the storage capacitor C1 is Connecting the second end of the driving switch T0;
  • An organic light emitting diode D1 the organic light emitting diode D1 includes an anode and a cathode, an anode of the organic light emitting diode D1 is connected to a second end of the driving switch T0, and a cathode of the organic light emitting diode D1 is grounded;
  • the fourth controllable switch T4, the fourth controllable switch T4 includes a control end, a first end and a second end, and the control end of the fourth controllable switch T4 is connected to a fourth scan line S1, the fourth The first end of the controllable switch T4 is connected to a second voltage terminal VL1 to receive the second voltage VL from the second voltage terminal VL1, and the second end of the fourth controllable switch T4 is connected to the first switch driver T0. Two ends.
  • the driving switch T0, the first controllable switch T1 to the fourth controllable switch T4 are all NMOS type thin film transistors or all PMOS type thin film transistors or NMOS type thin film transistors and PMOS a combination of the thin film transistors, the control switch T0, the control terminals, the first end and the second end of the first controllable switch T1 to the fourth controllable switch T4 respectively corresponding to the gate of the thin film transistor, Drain and source.
  • FIG. 2 is a waveform diagram of the pixel compensation circuit of the above embodiment of the present invention.
  • Fig. 3 is a view showing a simulation result of the pixel compensation circuit of the above embodiment of the present invention.
  • the working principle of the pixel compensation circuit obtained according to FIG. 1 to FIG. 3 is as follows (ie, the pixel compensation method):
  • the driving switch T0 and the fourth controllable switch T4 are turned on, the first to third controllable switches T1-T3 are turned off, and the voltage Vb of the second end of the driving switch T0 is equal to the output of the second voltage terminal VL1.
  • the second voltage VL because of the coupling effect of the storage capacitor C1, the voltage Va at the first end of the storage capacitor C1 is lowered, thereby clearing the influence of the data of the previous frame;
  • the driving switch T0, the second controllable switch T2, and the third controllable switch T3 are all turned on, the first controllable switch T1 and the fourth controllable switch T4
  • the storage capacitor C1 is charged, and the voltage Vb of the second terminal of the driving switch T0 is equal to the difference between the first voltage VDD outputted by the first voltage terminal VDD1 and the threshold voltage Vth of the driving switch T0, the storing The voltage Va of the first end of the capacitor C1 is equal to the first voltage VDD;
  • the driving switch T0 and the first controllable switch T1 are both turned on, the second to fourth controllable switches T2-T4 are all turned off, and the storage capacitor C1 is charged,
  • the voltage Va of the first end of the storage capacitor C1 is equal to the data voltage Vdata output by the data line Data, and the voltage Vb of the second end of the drive switch T0 satisfies the following relationship:
  • Vb VDD-Vth+ ⁇ V (Equation 1)
  • VDD is the first voltage
  • Vth is the threshold voltage of the driving switch T0
  • ⁇ V is the voltage increment of the second end of the driving switch T0, which is due to the voltage Va of the first end of the storage capacitor C1.
  • the change (the amount of change is Vdata-VDD), the coupling effect of the capacitor (including the storage capacitor C1, the capacitance of the LED D1, the second controllable switch T2, and the parasitic capacitance of the drive switch T0)
  • the voltage Vb at the second end of the drive switch T0 also changes (the amount of change is ⁇ V);
  • the driving switch T0 and the second controllable switch T2 are both turned on, and the first controllable switch T1, the third and fourth controllable switches T3 and T4 are all turned off,
  • the storage capacitor C1 is discharged, and the voltage difference Vgs between the control terminal and the second terminal of the driving switch T0 is equal to the voltage difference across the storage capacitor C1, that is, Vgs satisfies the following relationship:
  • Vgs Vdata-VDD+Vth- ⁇ V (Equation 2)
  • ⁇ is an electron mobility
  • Cox is a thin film transistor insulating layer capacitance per unit area
  • L and W are effective channel lengths and widths of the driving switch T0, respectively.
  • the pixel compensation circuit prevents the threshold voltage Vth of the driving switch T0 from drifting to cause the current of the organic light emitting diode D1 to be unstable, thereby achieving uniform display of panel brightness.
  • FIG. 4 is a schematic diagram of a scan driving circuit of the present invention.
  • the scan driving circuit includes the pixel compensation circuit for preventing a threshold voltage drift of the driving transistor in the scan driving circuit, thereby causing unevenness of panel brightness display.
  • FIG. 5 is a schematic diagram of a flat display device according to the present invention.
  • the flat display device may be, for example, an OLED or an LCD including the scan drive circuit and the pixel compensation circuit, and the scan drive circuit having the pixel compensation circuit is disposed at the periphery of the flat display device, for example, disposed on the flat display device. Both ends.
  • the pixel compensation circuit and method act as a driving transistor by using a plurality of thin film transistors in combination, thereby preventing the threshold voltage drift of the driving transistor from causing instability of current of the organic light emitting diode, thereby achieving uniform display of panel brightness.

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Abstract

本发明提供一种像素补偿电路、方法及平面显示装置。像素补偿电路包括第一至第四可控开关的控制端分别连第一至第四扫描线，第一可控开关的第一端连数据线；第二可控开关的第一端连第一可控开关的第二端；驱动开关的控制端连第二可控开关的第二端，第一端连第一电压端；第三可控开关的第一端连第一可控开关的第二端，第二端连驱动开关的第一端；第一可控开关的第二端经存储电容连驱动开关的第二端；有机发光二极管的阳极连驱动开关的第二端，阴极接地；第四可控开关的第一端连第二电压端，第二端连驱动开关的第二端，以避免阈值电压漂移造成有机发光二极管的电流不稳定，以此实现面板亮度显示均匀。

Description

像素补偿电路、方法及平面显示装置 【技术领域】
本发明涉及显示技术领域，特别是涉及一种像素补偿电路、方法及平面显示装置。
【背景技术】
目前的有机发光二极管(Organic Light Emitting diode，OLED)显示器具有体积小、结构简单、自主发光、亮度高、可视角度大、响应时间短等优点，吸引了广泛的注意。
现有的有机发光二极管显示器中有一个晶体管作为驱动晶体管用于控制通过有机发光二极管OLED的电流，因此驱动晶体管的阈值电压的重要性便十分明显，所述阈值电压的正向或负向漂移都会使得在相同数据信号下有不同的电流通过有机发光二极管，目前的晶体管在使用过程中如氧化物半导体中的照光、源漏电极电压应力作用等因素，都可能导致阈值电压漂移，造成通过有机发光二极管的电流不稳定，进而引起面板亮度显示不均匀。
【发明内容】
本发明主要解决的技术问题是提供一种像素补偿电路、方法及平面显示装置，以避免阈值电压漂移造成有机发光二极管的电流不稳定，以此实现面板亮度显示均匀。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素补偿电路，包括：
第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的控制端连接一第一扫描线，所述第一可控开关的第一端连接一数据线以从所述数据线接收数据电压；
第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接一第二扫描线，所述第二可控开关的第一端连接所述第一可控开关的第二端；
驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的 控制端连接所述第二可控开关的第二端，所述驱动开关的第一端连接一第一电压端以从所述第一电压端接收第一电压；
第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端连接一第三扫描线，所述第三可控开关的第一端连接所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述驱动开关的第一端；
存储电容，所述存储电容包括第一端及第二端，所述存储电容的第一端连接所述第一可控开关的第二端，所述存储电容的第二端连接所述驱动开关的第二端；
有机发光二极管，所述有机发光二极管包括阳极及阴极，所述有机发光二极管的阳极连接所述驱动开关的第二端，所述有机发光二极管的阴极接地；及
第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端连接一第四扫描线，所述第四可控开关的第一端连接一第二电压端以从所述第二电压端接收第二电压，所述第四可控开关的第二端连接所述驱动开关的第二端。
其中，所述驱动开关、所述第一可控开关至所述第四可控开关均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关、所述第一可控开关至所述第四可控开关的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种像素补偿方法，包括：
在重置阶段，驱动开关及第四可控开关导通，第一至第三可控开关截止，所述驱动开关的第二端的电压Vb等于第二电压端输出的第二电压VL，因为存储电容的耦合作用，所述存储电容第一端的电压Va降低，以此清除前一帧的数据的影响；
在阈值电压提取阶段，所述驱动开关、所述第二可控开关及所述第三可控开关均导通，所述第一可控开关及所述第四可控开关均截止，所述存储电容被充电，所述驱动开关的第二端的电压Vb等于第一电压端输出的第一电压VDD与所述驱动开关的阈值电压Vth之差，所述存储电容第一端的电压Va等于所述第一电压VDD；
在数据写入阶段，所述驱动开关及所述第一可控开关均导通，所述第二至 第四可控开关均截止，所述存储电容被充电，所述存储电容第一端的电压Va等于数据线输出的数据电压Vdata，所述驱动开关第二端的电压Vb＝VDD-Vth+ΔV，其中，VDD为所述第一电压，Vth为所述驱动开关的阈值电压，ΔV为所述驱动开关的第二端的电压增量；及
在驱动发光阶段，所述驱动开关及所述第二可控开关均导通，所述第一可控开关、所述第三及第四可控开关均截止，所述存储电容放电，所述驱动开关的控制端与第二端之间的电压差Vgs等于所述存储电容两端的电压差，即Vgs＝Vdata-VDD+Vth-ΔV，通过所述有机发光二极管的电流I＝K*(Vgs-Vth)2＝K*(Vdata-VDD-ΔV)2，其中K为系数。
其中，所述驱动开关、所述第一可控开关至所述第四可控开关均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关、所述第一可控开关至所述第四可控开关的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种平面显示装置，所述平面显示装置包括扫描驱动电路，所述扫描驱动电路包括像素补偿电路，所述像素补偿电路包括：
第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的控制端连接一第一扫描线，所述第一可控开关的第一端连接一数据线以从所述数据线接收数据电压；
第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接一第二扫描线，所述第二可控开关的第一端连接所述第一可控开关的第二端；
驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第二可控开关的第二端，所述驱动开关的第一端连接一第一电压端以从所述第一电压端接收第一电压；
第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端连接一第三扫描线，所述第三可控开关的第一端连接所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述驱动开关的第一端；
存储电容，所述存储电容包括第一端及第二端，所述存储电容的第一端连接所述第一可控开关的第二端，所述存储电容的第二端连接所述驱动开关的第 二端；
有机发光二极管，所述有机发光二极管包括阳极及阴极，所述有机发光二极管的阳极连接所述驱动开关的第二端，所述有机发光二极管的阴极接地；及
第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端连接一第四扫描线，所述第四可控开关的第一端连接一第二电压端以从所述第二电压端接收第二电压，所述第四可控开关的第二端连接所述驱动开关的第二端。
其中，所述驱动开关、所述第一可控开关至所述第四可控开关均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关、所述第一可控开关至所述第四可控开关的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
其中，所述平面显示装置为OLED或LCD。
本发明的有益效果是：区别于现有技术的情况，本发明的所述像素补偿电路及方法通过组合使用多个薄膜晶体管来作用驱动晶体管，以此来避免所述驱动晶体管的阈值电压漂移造成所述有机发光二极管的电流不稳定，以此实现面板亮度显示均匀。
【附图说明】
图1是本发明的像素补偿电路的结构示意图；
图2是本发明的像素补偿电路的波形图；
图3是本发明的像素补偿电路的模拟结果图；
图4是本发明的扫描驱动电路的示意图；
图5是本发明的平面显示装置的示意图。
【具体实施方式】
请参阅图1，是本发明的像素补偿电路的结构示意图。如图1所示，本发明的像素补偿电路包括第一可控开关T1，所述第一可控开关T1包括控制端、第一端及第二端，所述第一可控开关T1的控制端连接一第一扫描线S4，所述第一可控开关T1的第一端连接一数据线Data以从所述数据线Data接收数据电压Vdata；
第二可控开关T2，所述第二可控开关T2包括控制端、第一端及第二端， 所述第二可控开关T2的控制端连接一第二扫描线S3，所述第二可控开关T2的第一端连接所述第一可控开关T1的第二端；
驱动开关T0，所述驱动开关T0包括控制端、第一端及第二端，所述驱动开关T0的控制端连接所述第二可控开关T2的第二端，所述驱动开关T0的第一端连接一第一电压端VDD1以从所述第一电压端VDD1接收第一电压VDD；
第三可控开关T3，所述第三可控开关T3包括控制端、第一端及第二端，所述第三可控开关T3的控制端连接一第三扫描线S2，所述第三可控开关T3的第一端连接所述第一可控开关T1的第二端及所述第二可控开关T2的第一端，所述第三可控开关T3的第二端连接所述驱动开关T0的第一端；
存储电容C1，所述存储电容C1包括第一端及第二端，所述存储电容C1的第一端连接所述第一可控开关T1的第二端，所述存储电容C1的第二端连接所述驱动开关T0的第二端；
有机发光二极管D1，所述有机发光二极管D1包括阳极及阴极，所述有机发光二极管D1的阳极连接所述驱动开关T0的第二端，所述有机发光二极管D1的阴极接地；及
第四可控开关T4，所述第四可控开关T4包括控制端、第一端及第二端，所述第四可控开关T4的控制端连接一第四扫描线S1，所述第四可控开关T4的第一端连接一第二电压端VL1以从所述第二电压端VL1接收第二电压VL，所述第四可控开关T4的第二端连接所述驱动开关T0的第二端。
在本实施例中，所述驱动开关T0、所述第一可控开关T1至所述第四可控开关T4均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关T0、所述第一可控开关T1至所述第四可控开关T4的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
请参阅图2，是本发明上述实施例的所述像素补偿电路的波形图。图3是本发明上述实施例的所述像素补偿电路的模拟结果图。根据图1至图3获得所述像素补偿电路的工作原理如下(即所述像素补偿方法)：
在重置阶段，驱动开关T0及第四可控开关T4导通，第一至第三可控开关T1-T3截止，所述驱动开关T0的第二端的电压Vb等于第二电压端VL1输出的第二电压VL，因为存储电容C1的耦合作用，所述存储电容C1第一端的电压Va降低，以此清除前一帧的数据的影响；
在阈值电压提取阶段，所述驱动开关T0、所述第二可控开关T2及所述第三可控开关T3均导通，所述第一可控开关T1及所述第四可控开关T4均截止，所述存储电容C1被充电，所述驱动开关T0的第二端的电压Vb等于第一电压端VDD1输出的第一电压VDD与所述驱动开关T0的阈值电压Vth之差，所述存储电容C1第一端的电压Va等于所述第一电压VDD；
在数据写入阶段，所述驱动开关T0及所述第一可控开关T1均导通，所述第二至第四可控开关T2-T4均截止，所述存储电容C1被充电，所述存储电容C1第一端的电压Va等于数据线Data输出的数据电压Vdata，所述驱动开关T0第二端的电压Vb满足如下关系：
Vb＝VDD-Vth+ΔV  (公式1)
其中，VDD为所述第一电压，Vth为所述驱动开关T0的阈值电压，ΔV为所述驱动开关T0的第二端的电压增量，它是由于所述存储电容C1第一端的电压Va的变化(变化量为Vdata-VDD)，通过电容(包括所述存储电容C1、所述发光二极管D1的电容、所述第二可控开关T2及所述驱动开关T0的寄生电容)的耦合作用导致所述驱动开关T0的第二端的电压Vb也发生变化(变化量为ΔV)；及
在驱动发光阶段，所述驱动开关T0及所述第二可控开关T2均导通，所述第一可控开关T1、所述第三及第四可控开关T3及T4均截止，所述存储电容C1放电，所述驱动开关T0的控制端与第二端之间的电压差Vgs等于所述存储电容C1两端的电压差，即Vgs满足如下关系：
Vgs＝Vdata-VDD+Vth-ΔV  (公式2)
通过所述有机发光二极管D1的电流I满足如下关系：
I＝K*(Vgs-Vth)2＝K*(Vdata-VDD-ΔV)2  (公式3)
其中K为系数且满足如下关系：
K＝μCoxW/(2*L)  (公式4)
其中，μ为电子迁移率，Cox为单位面积的薄膜晶体管绝缘层电容；L及W分别为所述驱动开关T0的有效沟道长度及宽度。
由上述公式3及4并结合如下所示的表1可以看出，通过所述有机发光二极管D1的电流与所述驱动开关T0的阈值电压Vth无关。
表1
Figure PCTCN2016074552-appb-000001
Figure PCTCN2016074552-appb-000002
因此，所述像素补偿电路避免了所述驱动开关T0的阈值电压Vth漂移造成所述有机发光二极管D1的电流不稳定，以此实现面板亮度显示均匀。
请参阅图4，为本发明一种扫描驱动电路的示意图。所述扫描驱动电路中包括所述像素补偿电路，用于避免所述扫描驱动电路中的驱动晶体管发生阈值电压漂移，从而造成面板亮度显示不均匀。
请参阅图5，为本发明一种平面显示装置的示意图。所述平面显示装置例如可为OLED或LCD，其包括前述的扫描驱动电路及像素补偿电路，所述具有像素补偿电路的扫描驱动电路设置在所述平面显示装置的周边，例如设置在平面显示装置的两端。
所述像素补偿电路及方法通过组合使用多个薄膜晶体管来作用驱动晶体管，以此来避免所述驱动晶体管的阈值电压漂移造成所述有机发光二极管的电流不稳定，以此实现面板亮度显示均匀。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (7)

  1. 一种像素补偿电路，其中，所述像素补偿电路包括：
    第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的控制端连接一第一扫描线，所述第一可控开关的第一端连接一数据线以从所述数据线接收数据电压；
    第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接一第二扫描线，所述第二可控开关的第一端连接所述第一可控开关的第二端；
    驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第二可控开关的第二端，所述驱动开关的第一端连接一第一电压端以从所述第一电压端接收第一电压；
    第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端连接一第三扫描线，所述第三可控开关的第一端连接所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述驱动开关的第一端；
    存储电容，所述存储电容包括第一端及第二端，所述存储电容的第一端连接所述第一可控开关的第二端，所述存储电容的第二端连接所述驱动开关的第二端；
    有机发光二极管，所述有机发光二极管包括阳极及阴极，所述有机发光二极管的阳极连接所述驱动开关的第二端，所述有机发光二极管的阴极接地；及
    第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端连接一第四扫描线，所述第四可控开关的第一端连接一第二电压端以从所述第二电压端接收第二电压，所述第四可控开关的第二端连接所述驱动开关的第二端。
  2. 根据权利要求1所述的像素补偿电路，其中，所述驱动开关、所述第一可控开关至所述第四可控开关均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关、所述第一可控开关至所述第四可控开关的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
  3. 一种像素补偿方法，其中，所述像素补偿方法包括：
    在重置阶段，驱动开关及第四可控开关导通，第一至第三可控开关截止，所述驱动开关的第二端的电压Vb等于第二电压端输出的第二电压VL，因为存储电容的耦合作用，所述存储电容第一端的电压Va降低，以此清除前一帧的数据的影响；
    在阈值电压提取阶段，所述驱动开关、所述第二可控开关及所述第三可控开关均导通，所述第一可控开关及所述第四可控开关均截止，所述存储电容被充电，所述驱动开关的第二端的电压Vb等于第一电压端输出的第一电压VDD与所述驱动开关的阈值电压Vth之差，所述存储电容第一端的电压Va等于所述第一电压VDD；
    在数据写入阶段，所述驱动开关及所述第一可控开关均导通，所述第二至第四可控开关均截止，所述存储电容被充电，所述存储电容第一端的电压Va等于数据线输出的数据电压Vdata，所述驱动开关第二端的电压Vb＝VDD-Vth+ΔV，其中，VDD为所述第一电压，Vth为所述驱动开关的阈值电压，ΔV为所述驱动开关的第二端的电压增量；及
    在驱动发光阶段，所述驱动开关及所述第二可控开关均导通，所述第一可控开关、所述第三及第四可控开关均截止，所述存储电容放电，所述驱动开关的控制端与第二端之间的电压差Vgs等于所述存储电容两端的电压差，即Vgs＝Vdata-VDD+Vth-ΔV，通过所述有机发光二极管的电流I＝K*(Vgs-Vth)2＝K*(Vdata-VDD-ΔV)2，其中K为系数。
  4. 根据权利要求3所述的像素补偿方法，其中，所述驱动开关、所述第一可控开关至所述第四可控开关均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关、所述第一可控开关至所述第四可控开关的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
  5. 一种平面显示装置，其中，所述平面显示装置包括像素补偿电路，所述像素补偿电路包括：
    第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的控制端连接一第一扫描线，所述第一可控开关的第一端连接一数据线以从所述数据线接收数据电压；
    第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接一第二扫描线，所述第二可控开关的第一端连接所述 第一可控开关的第二端；
    驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第二可控开关的第二端，所述驱动开关的第一端连接一第一电压端以从所述第一电压端接收第一电压；
    第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端连接一第三扫描线，所述第三可控开关的第一端连接所述第一可控开关的第二端及所述第二可控开关的第一端，所述第三可控开关的第二端连接所述驱动开关的第一端；
    存储电容，所述存储电容包括第一端及第二端，所述存储电容的第一端连接所述第一可控开关的第二端，所述存储电容的第二端连接所述驱动开关的第二端；
    有机发光二极管，所述有机发光二极管包括阳极及阴极，所述有机发光二极管的阳极连接所述驱动开关的第二端，所述有机发光二极管的阴极接地；及
    第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端连接一第四扫描线，所述第四可控开关的第一端连接一第二电压端以从所述第二电压端接收第二电压，所述第四可控开关的第二端连接所述驱动开关的第二端。
  6. 根据权利要求5所述的平面显示装置，其中，所述驱动开关、所述第一可控开关至所述第四可控开关均为NMOS型薄膜晶体管或均为PMOS型薄膜晶体管或为NMOS型薄膜晶体管与PMOS型薄膜晶体管的组合，所述驱动开关、所述第一可控开关至所述第四可控开关的控制端、第一端及第二端分别对应所述薄膜晶体管的栅极、漏极及源极。
  7. 根据权利要求5所述的平面显示装置，其中，所述平面显示装置为OLED或LCD。
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