WO2016180110A1 - 驱动电路及其驱动方法、显示基板及其驱动方法、显示装置 - Google Patents

驱动电路及其驱动方法、显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2016180110A1
WO2016180110A1 PCT/CN2016/078669 CN2016078669W WO2016180110A1 WO 2016180110 A1 WO2016180110 A1 WO 2016180110A1 CN 2016078669 W CN2016078669 W CN 2016078669W WO 2016180110 A1 WO2016180110 A1 WO 2016180110A1
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Prior art keywords
transistor
input terminal
input
terminal inputs
high level
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PCT/CN2016/078669
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English (en)
French (fr)
Inventor
孙拓
马占洁
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京东方科技集团股份有限公司
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Priority to US15/511,748 priority Critical patent/US10109234B2/en
Publication of WO2016180110A1 publication Critical patent/WO2016180110A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a driving circuit and a driving method thereof, a display substrate, a driving method thereof, and a display device.
  • the driving method of the existing Active-Matrix Organic Light Emitting Diode is to output a data voltage by a driving circuit, and the data voltage is directly written into the pixel circuit, thereby controlling the brightness of the pixel.
  • AMOLED Active-Matrix Organic Light Emitting Diode
  • embodiments of the present invention provide a driving circuit and a driving method thereof, a display substrate, a driving method thereof, and a display device, which are used to solve the problem that the output precision of the driving circuit in the prior art is low, the power consumption is high, and uniform. Poor sex.
  • An embodiment of the present invention provides a driving circuit, including a converting unit, where the converting unit is provided with a first input end, a second input end, a third input end, a fourth input end, and an output end, and the fourth input end is a DC power connection, the output being connected to the pixel circuit;
  • the first input is for inputting a voltage signal
  • the second input is for inputting a first driving signal
  • the third input is for inputting a second driving signal
  • the output is for outputting a current signal
  • the conversion unit is configured to convert the voltage signal into the current signal.
  • the conversion unit may include a first transistor, a second transistor, a third transistor, and a first capacitor;
  • a gate of the first transistor is coupled to the second input, the first crystal a first pole of the body tube is connected to the first input end, and a second pole of the first transistor is connected to a gate of the second transistor;
  • a first pole of the second transistor is connected to the fourth input terminal, and a second pole of the second transistor is connected to a first pole of the third transistor;
  • a gate of the third transistor is connected to the third input terminal, and a second pole of the third transistor is connected to the output terminal;
  • the first capacitor is connected in parallel between the gate of the second transistor and the first pole.
  • the driving circuit may further include a source driving unit, the source driving unit is connected to the first input terminal, and the source driving unit is configured to output the voltage signal.
  • the transistor may be set in a first mode or a second mode in which the transistors are all set as N-type transistors, and in the second mode, the transistors are all provided as P-type transistors.
  • An embodiment of the present invention further provides a driving method of a driving circuit, where the driving circuit includes any one of the above driving circuits, and the driving method includes first to third stages,
  • the driving method includes:
  • the first input terminal inputs a high level
  • the second input terminal inputs a high level
  • the third input terminal inputs a low level
  • the first input terminal inputs a low level
  • the second input terminal inputs a low level
  • the third input terminal inputs a high level
  • the first input terminal inputs a high level
  • the second input terminal inputs a low level
  • the third input terminal inputs a low level
  • the driving method When set in the second mode, the driving method includes:
  • the first input terminal inputs a high level
  • the second input terminal inputs a low level
  • the third input terminal inputs a high level
  • the first input terminal inputs a low level
  • the second input terminal inputs a high level
  • the third input terminal inputs a low level
  • the first input inputs a high level
  • the second input inputs a high level
  • the third input inputs a high level
  • An embodiment of the present invention further provides a display substrate, including a pixel circuit and the foregoing a driving circuit, the pixel circuit is provided with a fifth input terminal, a sixth input terminal, a seventh input terminal and an eighth input terminal, wherein the fifth input terminal is connected to the output terminal;
  • the fifth input is for inputting the current signal
  • the sixth input is for inputting a scan signal
  • the seventh input is for inputting a high level
  • the eighth input is for inputting a low power level.
  • the pixel circuit may include a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a second capacitor, a first node, a second node, and a light emitting device;
  • a gate of the fourth transistor is connected to the sixth input terminal, a first pole of the fourth transistor is connected to the fifth input terminal, and a second pole of the fourth transistor is connected to the first node connection;
  • a gate of the fifth transistor is connected to the sixth input terminal, a first pole of the fifth transistor is connected to the fifth input terminal, and a second pole of the fifth transistor is connected to the second node connection;
  • a gate of the sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to the second node, and a second pole of the sixth transistor is connected to an anode of the light emitting device ;
  • a gate of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the second node, and a second pole of the seventh transistor is connected to the seventh input ;
  • the second capacitor is connected in parallel between the gate and the second pole of the seventh transistor
  • a negative electrode of the light emitting device is coupled to the eighth input terminal.
  • the first transistor, the second transistor, and the third transistor are disposed as N-type transistors, and the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are disposed as P-type transistors;
  • the first transistor, the second transistor, and the third transistor are disposed as P-type transistors, and the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are disposed as N-type transistors.
  • the conversion unit may be disposed at an end of the display panel fan-out structure
  • the conversion unit may be disposed between an output end of the source driving unit and a bonding area of the display panel.
  • An embodiment of the present invention further provides a driving method of a display substrate, where the display substrate includes any one of the above driving circuits, and the driving method includes first to third stages,
  • the driving method includes:
  • the first input terminal inputs a high level
  • the second input terminal inputs a high level
  • the third input terminal inputs a low level
  • the sixth input terminal inputs a high level
  • the first input terminal inputs a low level
  • the second input terminal inputs a low level
  • the third input terminal inputs a high level
  • the sixth input terminal inputs a low level
  • the first input terminal inputs a high level
  • the second input terminal inputs a low level
  • the third input terminal inputs a low level
  • the sixth input terminal inputs a high level
  • the driving method When set in the second mode, the driving method includes:
  • the first input terminal inputs a high level
  • the second input terminal inputs a low level
  • the third input terminal inputs a high level
  • the sixth input terminal inputs a low level
  • the first input terminal inputs a low level
  • the second input terminal inputs a high level
  • the third input terminal inputs a low level
  • the sixth input terminal inputs a high level
  • the first input terminal inputs a high level
  • the second input terminal inputs a high level
  • the third input terminal inputs a high level
  • the sixth input terminal inputs a low level.
  • the embodiment of the invention further provides a display device comprising any of the above display substrates.
  • the driving circuit includes a conversion unit, and the conversion unit is provided with a first input end, a second input end, and a third input end.
  • the fourth input end and the output end are connected to a DC power source, and the output end is connected to the pixel circuit.
  • the first input is for inputting a voltage signal
  • the second input is for inputting a first drive signal
  • the third input is for inputting a second drive signal
  • the output is for outputting a current signal.
  • the conversion unit converts the voltage signal output by the source driving unit into a current signal, and drives the pixel circuit through the current signal.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a flowchart of a driving method of a driving circuit according to Embodiment 2 of the present invention.
  • FIG. 3 is a timing chart showing the operation of the driving circuit corresponding to the driving method provided by the second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a driving circuit according to Embodiment 3 of the present invention.
  • FIG. 5 is a schematic structural diagram of a driving circuit and a pixel circuit in a display substrate according to Embodiment 4 of the present invention.
  • FIG. 6 is a schematic structural diagram of a driving circuit and a pixel circuit in a display substrate according to Embodiment 4 of the present invention.
  • FIG. 7 is a flowchart of a driving method of a display substrate according to Embodiment 5 of the present invention.
  • FIG. 8 is a timing chart showing an operation of a display substrate corresponding to the driving method provided in Embodiment 5 of the present invention.
  • FIG. 9 is a schematic diagram of a current path corresponding to the first stage shown in FIG. 8.
  • FIG. 10 is a schematic diagram of a current path corresponding to the second stage shown in FIG. 8;
  • FIG. 11 is a schematic diagram of a current path corresponding to the third stage shown in FIG.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to Embodiment 1 of the present invention.
  • the driving circuit includes a conversion unit and a source driving unit (not shown), and the conversion unit is provided with a first input terminal DATA, a second input terminal VCG, a third input terminal VCE, a fourth input terminal VCC and an output terminal OUTPUT, the first input terminal DATA is connected to the source driving unit, and the fourth input terminal VCC is connected to a DC power source (not shown), and the output terminal OUTPUT Connected to a pixel circuit (not shown).
  • the fourth input terminal VCC The input current is from the DC power supply of the display panel. Since the load of the driving circuit is small, the power consumption of the driving circuit powered by the DC power source is low.
  • the source driving unit is configured to output a voltage signal
  • the converting unit is configured to convert the voltage signal into a corresponding current signal.
  • the first input terminal DATA of the conversion unit is configured to provide a voltage signal output by the source driving unit to the conversion unit
  • the second input terminal VCG is configured to input a first driving signal.
  • the third input terminal VCE is configured to input a second driving signal
  • the output terminal OUTPUT is configured to output the converted current signal to the pixel circuit.
  • the conversion unit converts a voltage signal output by the source driving unit into a current signal, and the pixel signal is driven by the current signal.
  • the conversion unit includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1, and the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors.
  • the gate of the first transistor T1 is connected to the second input terminal VCG
  • the first pole of the first transistor T1 is connected to the first input terminal DATA
  • the first transistor T1 is The second pole is connected to the gate of the second transistor T2.
  • the first pole of the second transistor T2 is connected to the fourth input terminal VCC
  • the second pole of the second transistor T2 is connected to the first pole of the third transistor T3.
  • the gate of the third transistor T3 is connected to the third input terminal VCE, and the second pole of the third transistor T3 is connected to the output terminal OUTPUT.
  • the first capacitor C1 is connected in parallel between the gate of the second transistor T2 and the first pole.
  • the conversion unit may be disposed at the end of a fan-out structure of the display panel.
  • the conversion unit is disposed between an output end of the source driving unit and a bonding area of the display panel.
  • the conversion unit converts the voltage signal output by the source driving unit into a current signal, and drives the pixel circuit through the current signal.
  • the technical solution provided by the embodiment provides high output precision and low power consumption of the driving circuit, and can also improve the uniformity of the display screen of the display panel and increase the dynamics of the display panel. range.
  • FIG. 2 is a flowchart of a driving method of a driving circuit according to Embodiment 2 of the present invention
  • FIG. 3 is a timing chart of operation of the driving circuit corresponding to the driving method.
  • the driving circuit may include the driving circuit provided in the first embodiment.
  • the driving method of the driving circuit provided in this embodiment will be described in detail below with reference to FIG. 1 to FIG. As shown in FIG. 2, the driving method includes the following steps 2001 to 2003.
  • step 2001 the first input terminal inputs a high level, the second input terminal inputs a high level, and the third input terminal inputs a low level.
  • This step corresponds to the first phase I in the operational timing diagram shown in FIG.
  • the first phase I is a charging phase of the conversion unit.
  • the voltage signal input by the first input terminal DATA of the conversion unit is a high level
  • the second input The first driving signal input by the terminal VCG is at a high level, and at this time, the first transistor T1 and the second transistor T2 are turned on, and the voltage signal charges the first capacitor C1.
  • the voltage signal charged to the first capacitor C1 is a data signal required for the pixel circuit of the drive circuit.
  • the second driving signal input by the third input terminal VCE of the conversion unit is at a low level, so that the third transistor T3 is turned off, and therefore, the output terminal OUTPUT of the conversion unit does not output a current signal.
  • step 2002 the first input terminal inputs a low level, the second input terminal inputs a low level, and the third input terminal inputs a high level.
  • This step corresponds to the second phase II in the operational timing diagram shown in FIG.
  • the second phase II is a charging phase of the pixel circuit corresponding to the driving circuit.
  • the voltage signal input by the first input terminal DATA of the converting unit is a low level.
  • the first driving signal input by the second input terminal VCG is a low level, and the first transistor T1 is turned off and the second transistor T2 is kept turned on.
  • the second driving signal input by the third input terminal VCE of the converting unit is at a high level, so that the third transistor T3 is turned on, and the output terminal OUTPUT of the converting unit outputs a current signal.
  • the second transistor T2 and the third transistor T3 are simultaneously turned on, and the second transistor T2 controls the current of the entire charging path, and the current signal I signal is
  • ⁇ n is the carrier mobility
  • C is the gate insulating layer capacitance value per unit area
  • W/L is the width to length ratio of the second transistor T2
  • Vgs is the gate-source voltage of the second transistor T2
  • Vth is the second The threshold voltage of transistor T2.
  • the source of the second transistor T2 is a first pole
  • the voltage, Vcc is the voltage input to the fourth input terminal VCC. At this time, the voltage signal V data is converted into a current signal I signal output to the corresponding pixel circuit.
  • the process of converting the voltage signal outputted by the source driving unit that is, the voltage signal input by the first input terminal DATA of the converting unit) V data into the current signal I signal occurs in the first One phase I and second phase II.
  • step 2003 the first input terminal inputs a high level, the second input terminal inputs a low level, and the third input terminal inputs a low level. This step corresponds to the third phase III in the working sequence diagram.
  • the third stage III is an illumination stage of the pixel circuit corresponding to the driving circuit.
  • the voltage signal input by the first input end DATA of the conversion unit is a high level.
  • the first driving signal input by the second input terminal VCG is a low level, and the first transistor T1 and the second transistor T2 are turned off.
  • the second driving signal input by the third input terminal VCE of the conversion unit is at a low level, so that the third transistor T3 is turned off, and the output terminal OUTPUT of the conversion unit does not output a current signal.
  • the converting unit converts the voltage signal outputted by the source driving unit into a current signal, and drives the phase through the current signal.
  • the pixel circuit should be.
  • the technical solution provided by the embodiment provides high output precision and low power consumption of the driving circuit, and can also improve the uniformity of the display screen of the display panel and increase the dynamic range of the display panel.
  • FIG. 4 is a schematic structural diagram of a driving circuit according to Embodiment 3 of the present invention.
  • the driving circuit includes a converting unit and a source driving unit (not shown), and the converting unit is provided with a first input terminal DATA, a second input terminal VCG, a third input terminal VCE, a fourth input terminal VCC and an output terminal OUTPUT, the first input terminal DATA is connected to the source driving unit, and the fourth input terminal VCC is connected to a DC power source (not shown), and the output terminal OUTPUT Connected to a pixel circuit (not shown).
  • the conversion unit includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1.
  • a gate of the first transistor T1 is connected to the second input terminal VCG, a first pole of the first transistor T1 is connected to the first input terminal DATA, and a second pole of the first transistor T1 is The gate of the second transistor T2 is connected.
  • the first pole of the second transistor T2 is connected to the fourth input terminal VCC, and the second pole of the second transistor T2 is connected to the first pole of the third transistor T3.
  • the gate of the third transistor T3 is connected to the third input terminal VCE, and the second pole of the third transistor T3 is connected to the output terminal OUTPUT.
  • the first capacitor C1 is connected in parallel between the gate of the second transistor T2 and the first pole.
  • the driving circuit provided in this embodiment is different from the driving circuit provided in the first embodiment in that the first transistor T1 to the third transistor T3 in the driving circuit of the first embodiment are all N-type transistors, and the first in this embodiment The transistors T1 to T3 are all P-type transistors. Accordingly, when a driving method similar to that of the second embodiment is used to drive the driving circuit provided in the embodiment, the high level of the signal input by the second input terminal and the third input terminal becomes low in each stage. Flat, low level goes high.
  • the conversion unit converts the voltage signal output by the source driving unit into a current signal, and drives the pixel circuit through the current signal.
  • FIG. 5 is a schematic structural diagram of a driving circuit and a pixel circuit in a display substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a driving circuit and a pixel circuit in a display substrate according to the embodiment.
  • the display substrate includes a driving circuit 101 and a pixel circuit 102, and the driving circuit 101 includes a source driving unit 103 and a converting unit 104.
  • the number of the conversion units 104 may be plural.
  • the display substrate provided in this embodiment is provided with three conversion units 104 connected side by side.
  • the conversion unit 104 is provided with a first input terminal DATA, a second input terminal VCG, a third input terminal VCE, a fourth input terminal VCC, and an output terminal OUTPUT, and the first input terminal DATA and the source driver A unit 103 (not shown in FIG. 6) is connected, the fourth input terminal VCC is connected to a DC power source (not shown), and the output terminal OUTPUT is connected to the pixel circuit 102.
  • the first input terminal DATA is used to supply the voltage signal output by the source driving unit 103 to the conversion unit 104
  • the second input terminal VCG is used to input a first driving signal
  • the third input terminal VCE is used for inputting And a second driving signal
  • the output terminal OUTPUT is configured to output the converted current signal to the pixel circuit 102.
  • the conversion unit 104 converts the voltage signal output from the source driving unit 103 into a current signal through which the pixel circuit 102 is driven.
  • the conversion unit 104 includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors. .
  • the gate of the first transistor T1 is connected to the second input terminal VCG of the conversion unit 104
  • the first pole of the first transistor T1 is connected to the first input terminal DATA
  • the second pole of the first transistor T1 is connected to the gate of the second transistor T2.
  • the first pole of the second transistor T2 is connected to the fourth input terminal VCC
  • the second pole of the second transistor T2 is connected to the first pole of the third transistor T3.
  • the gate of the third transistor T3 is connected to the third input terminal VCE of the conversion unit 104, and the second pole of the third transistor T3 is connected to the output terminal OUTPUT of the conversion unit 104.
  • the first capacitor C1 is connected in parallel between the gate of the second transistor T2 and the first pole.
  • the pixel circuit 102 is provided with a fifth input terminal, a sixth input terminal SCAN, a seventh input terminal VDD and an eighth input terminal VSS, and the fifth input terminal is connected to the output terminal OUTPUT of the conversion unit 104.
  • the fifth input terminal is configured to input the current signal obtained by the conversion unit 104
  • the sixth input terminal SCAN is used to input a scan signal
  • the seventh input terminal VDD is used to input a high level signal
  • the eighth input terminal VSS is used to input a low level signal.
  • the pixel circuit 102 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second capacitor C2, a first node A, a second node B, and a light emitting device.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the second capacitor C2 constitute a current mirror pixel circuit.
  • the gate of the fourth transistor T4 is connected to the sixth input terminal SCAN of the pixel circuit 102, and the first pole of the fourth transistor T4 is connected to the fifth input terminal, the fourth A second pole of the transistor T4 is coupled to the first node A.
  • a gate of the fifth transistor T5 is connected to the sixth input terminal SCAN, a first pole of the fifth transistor T5 is connected to the fifth input terminal, and a second pole of the fifth transistor T5 is The second node B is connected.
  • a gate of the sixth transistor T6 is connected to the first node A, a first pole of the sixth transistor T6 is connected to the second node B, and a second pole of the sixth transistor T6 is The positive connection of the light emitting device.
  • a gate of the seventh transistor T7 is connected to the first node A, a first pole of the seventh transistor T7 is connected to the second node B, and a second pole of the seventh transistor T7 is The seventh input terminal VDD Pick up.
  • the second capacitor C2 is connected in parallel between the gate and the second pole of the seventh transistor T7.
  • the negative electrode of the light emitting device is connected to the eighth input terminal VSS.
  • the first to third transistors T1 to T3 are provided as N-type transistors, and the fourth to seventh transistors T4 to T7 are provided as P-type transistors, but the embodiment is not limited thereto.
  • the first to third transistors T1 to T3 may be disposed as P-type transistors, and the fourth to seventh transistors T4 to T7 may be disposed as N-type transistors.
  • the conversion unit converts the voltage signal output by the source driving unit into a current signal, and drives the pixel circuit through the current signal.
  • the technical solution provided by the embodiment provides high output precision and low power consumption of the driving circuit, and can also improve the uniformity of the display screen of the display panel and enlarge the dynamic range of the display panel.
  • FIG. 7 is a flowchart of a driving method of a display substrate according to Embodiment 5 of the present invention
  • FIG. 8 is a timing chart of operation of the display substrate corresponding to the driving method
  • FIG. 9 is FIG. A schematic diagram of the current path corresponding to the first stage I to the third stage III shown.
  • the display substrate may include the display substrate provided in the above-mentioned fourth embodiment.
  • the driving method of the display substrate provided in this embodiment is described in detail below by taking the display substrate provided in the fourth embodiment as an example and referring to FIG. 7 to FIG. As shown in FIG. 7, the driving method includes the following steps 7001 to 7003.
  • Step 7001 The first input terminal inputs a high level, the second input terminal inputs a high level, the third input terminal inputs a low level, and the sixth input terminal inputs a high level. This step corresponds to the first phase I in the operational timing diagram shown in FIG.
  • the first phase I is a charging phase of the conversion unit, as shown in FIG. 8, the voltage signal input by the first input terminal DATA of the conversion unit is a high level, and the second input The first driving signal input by the terminal VCG is at a high level, and at this time, the first transistor T1 and the second transistor T2 are turned on, thereby realizing charging of the first capacitor C1.
  • the current is converted by the first input of the conversion unit
  • the ingress DATA flows to the first capacitor C1, thereby completing charging of the first capacitor C1.
  • the second driving signal input by the third input terminal VCE of the conversion unit is a low level, so the third transistor T3 is turned off; the sixth input terminal SCAN of the pixel circuit is input.
  • the scan signal is at a high level, so the fourth transistor T4 and the fifth transistor T5 are turned off, and the potential of the first node A is at a low level, at which time the sixth transistor T6 and the seventh transistor T7 maintain the state of the previous frame of the display picture.
  • Step 7002 The first input terminal inputs a low level, the second input terminal inputs a low level, the third input terminal inputs a high level, and the sixth input terminal inputs a low level. This step corresponds to the second phase II in the operational timing diagram shown in FIG.
  • the second phase II is a charging phase of the pixel circuit, as shown in FIG. 8 , the voltage signal input by the first input terminal DATA of the conversion unit is a low level, and the second input The first driving signal input by the terminal VCG is at a low level, at which time the first transistor T1 is turned off and the second transistor T2 is kept turned on.
  • the second driving signal input by the third input terminal VCE of the conversion unit is at a high level, so that the third transistor T3 is turned on, and the conversion unit outputs a current signal to the pixel circuit.
  • the scan signal input by the sixth input terminal SCAN of the pixel circuit is a low level
  • the fourth transistor T4 and the fifth transistor T5 are turned on
  • the gate voltage of the sixth transistor T6 is the same as the first pole voltage.
  • the sixth transistor T6 is turned off, and the light emitting device does not emit light.
  • the potential of the first node A changes from a low level to a high level
  • charging of the second capacitor C2 is implemented by the first node A.
  • Step 7003 The first input terminal inputs a high level, the second input terminal inputs a low level, the third input terminal inputs a low level, and the sixth input terminal inputs a high level. This step corresponds to the third phase III in the operational timing diagram shown in FIG.
  • the third stage III is an illumination stage of the pixel circuit, as shown in FIG. 8, the voltage signal input by the first input end DATA of the conversion unit
  • the first driving signal input by the second input terminal VCG is a low level
  • the first transistor T1 and the second transistor T2 are turned off.
  • the second driving signal input by the third input terminal VCE is a low level
  • the third transistor T3 is turned off
  • the scan signal input by the sixth input terminal SCAN of the pixel circuit is a high level
  • the fourth transistor T4 and The fifth transistor T5 is turned off, and the potential of the first node A is maintained at a high level.
  • the gate voltages of the sixth transistor T6 and the seventh transistor T7 are the same, and the sixth transistor T6 and the seventh transistor T7 are turned on. As shown in FIG. 11, the current passes through the seventh input terminal VDD through the sixth transistor T6 and the seventh.
  • the transistor T7 flows to the light emitting device of the pixel circuit, and the light emitting device emits light.
  • the conversion unit converts the voltage signal output by the source driving unit into a current signal, and drives the pixel circuit by the current signal.
  • Table 1 shows the difference in currents output by the conversion unit under different data voltages and different threshold voltages Vth, wherein the data voltage is the voltage input to the first input terminal DATA of the conversion unit, the offset reflects different threshold voltages.
  • Table 1 Differences in current output from the conversion unit for different data voltages and different threshold voltages
  • the driving method of the display substrate is described by taking the first transistor T1 to the third transistor T3 as the N-type transistor and the fourth transistor T4 to the seventh transistor T7 as the P-type transistor as an example.
  • the embodiment is not limited to this.
  • the first to third transistors T1 to T3 are set as P-type transistors and the fourth to seventh transistors T4 to T7 are set as N-type transistors, in each stage, the second input, the third input, and the The high level of the signal input to the six inputs goes low and the low level goes high.
  • the conversion unit converts the voltage signal output from the source driving unit into a current signal, and drives the pixel circuit through the current signal.
  • the technical solution provided by the embodiment provides high output precision and low power consumption of the driving circuit, and can also improve the uniformity of the display screen of the display panel and increase the dynamic range of the display panel.

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Abstract

一种驱动电路（101）及其驱动方法、显示基板及其驱动方法、显示装置，所述驱动电路（101）包括转换单元（104）和源极驱动单元（103），所述转换单元（104）设置有第一输入端（DATA）、第二输入端（VCG）、第三输入端（VCE）、第四输入端（VCC）以及输出端（OUTPUT），所述第四输入端（VCC）与直流电源连接，所述输出端（OUTPUT）与像素电路（102）连接。所述第一输入端（DATA）用于将所述源极驱动单元（103）输出的电压信号（V data）提供给所述转换单元（104），所述第二输入端（VCG）用于输入第一驱动信号，所述第三输入端（VCE）用于输入第二驱动信号，所述输出端（OUTPUT）用于输出电流信号（I signal）。所述转换单元（104）将源极驱动单元（103）输出的电压信号（V data）转换为电流信号（I signal），通过电流信号（I signal）驱动像素电路（102）。

Description

驱动电路及其驱动方法、显示基板及其驱动方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种驱动电路及其驱动方法、显示基板及其驱动方法、显示装置。
背景技术
现有的有源矩阵有机发光二极体(Active-Matrix Organic Light Emitting Diode，AMOLED)的驱动方式是由驱动电路输出数据电压，所述数据电压直接写入像素电路，从而控制像素的亮度。然而，随着发光器件性能和显示面板分辨率的提高，相邻灰阶所对应的数据电压之间的差异越来越小，从而对驱动电路的输出精度的要求越来越高。这种情况下，现有技术中驱动电路的输出精度较低，并且其功耗较高而且均匀性较差。
发明内容
为解决上述问题，本发明实施例提供一种驱动电路及其驱动方法、显示基板及其驱动方法、显示装置，用于解决现有技术中驱动电路的输出精度较低、功耗较高而且均匀性较差的问题。
本发明实施例提供一种驱动电路，包括转换单元，所述转换单元设置有第一输入端、第二输入端、第三输入端、第四输入端以及输出端，所述第四输入端与直流电源连接，所述输出端与像素电路连接；
所述第一输入端用于输入电压信号，所述第二输入端用于输入第一驱动信号，所述第三输入端用于输入第二驱动信号，所述输出端用于输出电流信号，所述转换单元用于将所述电压信号转换为所述电流信号。
所述转换单元可以包括第一晶体管、第二晶体管、第三晶体管和第一电容；
所述第一晶体管的栅极与所述第二输入端连接，所述第一晶 体管的第一极与所述第一输入端连接，所述第一晶体管的第二极与所述第二晶体管的栅极连接；
所述第二晶体管的第一极与所述第四输入端连接，所述第二晶体管的第二极与所述第三晶体管的第一极连接；
所述第三晶体管的栅极与所述第三输入端连接，所述第三晶体管的第二极与所述输出端连接；
所述第一电容并联于所述第二晶体管的栅极与第一极之间。
所述驱动电路还可以包括源极驱动单元，所述源极驱动单元与所述第一输入端连接，所述源极驱动单元用于输出所述电压信号。
可以以第一模式或第二模式设置所述晶体管，所述第一模式中所述晶体管全部被设置为N型晶体管，所述第二模式中所述晶体管全部被设置为P型晶体管。
本发明实施例还提供一种驱动电路的驱动方法，所述驱动电路包括上述任一驱动电路，所述驱动方法包括第一至第三阶段，
在以第一模式设置时，所述驱动方法包括：
在第一阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入低电平；
在第二阶段，第一输入端输入低电平，第二输入端输入低电平，第三输入端输入高电平；
在第三阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入低电平
在以第二模式设置时，所述驱动方法包括：
在第一阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入高电平；
在第二阶段，第一输入端输入低电平，第二输入端输入高电平，第三输入端输入低电平；
在第三阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入高电平。
本发明实施例还提供一种显示基板，包括像素电路和上述任 一驱动电路，所述像素电路设置有第五输入端、第六输入端、第七输入端以及第八输入端，所述第五输入端与所述输出端连接；
所述第五输入端用于输入所述电流信号，所述第六输入端用于输入扫描信号，所述第七输入端用于输入高电平，所述第八输入端用于输入低电平。
所述像素电路可以包括第四晶体管、第五晶体管、第六晶体管、第七晶体管、第二电容、第一节点、第二节点以及发光器件；
所述第四晶体管的栅极与所述第六输入端连接，所述第四晶体管的第一极与所述第五输入端连接，所述第四晶体管的第二极与所述第一节点连接；
所述第五晶体管的栅极与所述第六输入端连接，所述第五晶体管的第一极与所述第五输入端连接，所述第五晶体管的第二极与所述第二节点连接；
所述第六晶体管的栅极与所述第一节点连接，所述第六晶体管的第一极与所述第二节点连接，所述第六晶体管的第二极与所述发光器件的正极连接；
所述第七晶体管的栅极与所述第一节点连接，所述第七晶体管的第一极与所述第二节点连接，所述第七晶体管的第二极与所述第七输入端连接；
所述第二电容并联于所述第七晶体管的栅极与第二极之间；
所述发光器件的负极与所述第八输入端连接。
在第一模式中，所述第一晶体管、第二晶体管和第三晶体管被设置为N型晶体管，所述第四晶体管、第五晶体管、第六晶体管和第七晶体管被设置为P型晶体管；
在第二模式中，所述第一晶体管、第二晶体管和第三晶体管被设置为P型晶体管，所述第四晶体管、第五晶体管、第六晶体管和第七晶体管被设置为N型晶体管。
所述转换单元可以设置在显示面板扇出结构的末端；或者
所述转换单元可以设置在所述源极驱动单元的输出端与显示面板邦定区域之间。
本发明实施例还提供一种显示基板的驱动方法，所述显示基板包括上述任一驱动电路，所述驱动方法包括第一至第三阶段，
在以第一模式设置时，所述驱动方法包括：
在第一阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入低电平，第六输入端输入高电平；
在第二阶段，第一输入端输入低电平，第二输入端输入低电平，第三输入端输入高电平，第六输入端输入低电平；
在第三阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入低电平，第六输入端输入高电平，
在以第二模式设置时，所述驱动方法包括：
在第一阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入高电平，第六输入端输入低电平；
在第二阶段，第一输入端输入低电平，第二输入端输入高电平，第三输入端输入低电平，第六输入端输入高电平；
在第三阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入高电平，第六输入端输入低电平。
本发明实施例还提供一种显示装置，包括上述任一显示基板。
在本发明实施例提供的驱动电路、显示基板及其驱动方法、显示装置中，所述驱动电路包括转换单元，所述转换单元设置有第一输入端、第二输入端、第三输入端、第四输入端以及输出端，所述第四输入端与直流电源连接，所述输出端与像素电路连接。所述第一输入端用于输入电压信号，所述第二输入端用于输入第一驱动信号，所述第三输入端用于输入第二驱动信号，所述输出端用于输出电流信号。所述转换单元将源极驱动单元输出的电压信号转换为电流信号，通过电流信号驱动像素电路。本发明实施例提供的技术方案输出精度高、功耗低，而且还能够提高显示画面的均匀性，放大显示面板的动态范围。
附图说明
图1为本发明实施例一提供的一种驱动电路的结构示意图；
图2为本发明实施例二提供的一种驱动电路的驱动方法的流程图；
图3为与本发明实施例二提供的驱动方法对应的驱动电路工作时序图；
图4为本发明实施例三提供的一种驱动电路的结构示意图；
图5为本发明实施例四提供的一种显示基板中的驱动电路和像素电路的结构示意图；
图6为本发明实施例四提供的一种显示基板中的驱动电路和像素电路的具体结构示意图；
图7为本发明实施例五提供的一种显示基板的驱动方法的流程图；
图8为与本发明实施例五提供的驱动方法对应的显示基板的工作时序图；
图9为图8所示的第一阶段对应的电流路径的示意图；
图10为图8所示的第二阶段对应的电流路径的示意图；
图11为图8所示的第三阶段对应的电流路径的示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明提供的驱动电路及其驱动方法、显示基板及其驱动方法、显示装置进行详细描述。
实施例一
图1为本发明实施例一提供的一种驱动电路的结构示意图。如图1所示，所述驱动电路包括转换单元和源极驱动单元(图中未示出)，所述转换单元设置有第一输入端DATA、第二输入端VCG、第三输入端VCE、第四输入端VCC以及输出端OUTPUT，所述第一输入端DATA与所述源极驱动单元连接，所述第四输入端VCC与直流电源(图中未示出)连接，所述输出端OUTPUT与像素电路(图中未示出)连接。可选的，所述第四输入端VCC 输入的电流来自于显示面板的直流电源。由于所述驱动电路的负载较小，因此由所述直流电源供电的所述驱动电路的功耗较低。
本实施例中，所述源极驱动单元用于输出电压信号，所述转换单元用于将所述电压信号转换为对应的电流信号。具体来说，所述转换单元的所述第一输入端DATA用于将所述源极驱动单元输出的电压信号提供给所述转换单元，所述第二输入端VCG用于输入第一驱动信号，所述第三输入端VCE用于输入第二驱动信号，所述输出端OUTPUT用于向所述像素电路输出转换后的电流信号。所述转换单元将源极驱动单元输出的电压信号转换为电流信号，通过所述电流信号驱动像素电路。本实施例提供的技术方案使得驱动电路的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，增大显示面板的动态范围。
参见图1，所述转换单元包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1，所述第一晶体管T1、第二晶体管T2和第三晶体管T3为N型晶体管。具体来说，所述第一晶体管T1的栅极与所述第二输入端VCG连接，所述第一晶体管T1的第一极与所述第一输入端DATA连接，所述第一晶体管T1的第二极与所述第二晶体管T2的栅极连接。所述第二晶体管T2的第一极与所述第四输入端VCC连接，所述第二晶体管T2的第二极与所述第三晶体管T3的第一极连接。所述第三晶体管T3的栅极与所述第三输入端VCE连接，所述第三晶体管T3的第二极与所述输出端OUTPUT连接。所述第一电容C1并联于所述第二晶体管T2的栅极与第一极之间。在实际应用中，所述转换单元可以设置在显示面板扇出(fan-out)结构的末端。可选的，所述转换单元设置在所述源极驱动单元的输出端与显示面板邦定(bonding)区域之间。
本实施例提供的驱动电路中，转换单元将源极驱动单元输出的电压信号转换为电流信号，通过电流信号来驱动像素电路。本实施例提供的技术方案使得驱动电路的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，增大显示面板的动态 范围。
实施例二
图2为本发明实施例二提供的一种驱动电路的驱动方法的流程图，图3为与所述驱动方法对应的该驱动电路的工作时序图。该驱动电路可以包括上述实施例一提供的驱动电路，具体内容可参照上述实施例一的描述，此处不再赘述。下面以实施例一提供的驱动电路为例，结合图1-图3对本实施例提供的驱动电路的驱动方法进行详细描述。如图2所示，所述驱动方法包括如下步骤2001至2003。
步骤2001、第一输入端输入高电平，第二输入端输入高电平，第三输入端输入低电平。该步骤对应于图3所示工作时序图中的第一阶段I。
本实施例中，第一阶段I为所述转换单元的充电阶段，如图3所示，所述转换单元的所述第一输入端DATA输入的电压信号为高电平，所述第二输入端VCG输入的第一驱动信号为高电平，此时第一晶体管T1和第二晶体管T2导通，所述电压信号对第一电容C1充电。此时，充入第一电容C1的电压信号即是对应于所述驱动电路的像素电路所需要的数据信号。另外，所述转换单元的所述第三输入端VCE输入的第二驱动信号为低电平，使得第三晶体管T3截止，因此，所述转换单元的输出端OUTPUT不输出电流信号。
步骤2002、第一输入端输入低电平，第二输入端输入低电平，第三输入端输入高电平。该步骤对应于图3所示工作时序图中的第二阶段II。
本实施例中，第二阶段II为对应于所述驱动电路的像素电路的充电阶段，如图3所示，所述转换单元的所述第一输入端DATA输入的电压信号为低电平，所述第二输入端VCG输入的第一驱动信号为低电平，此时第一晶体管T1截止而第二晶体管T2保持导通。另外，所述转换单元的所述第三输入端VCE输入的第二驱动 信号为高电平，使得第三晶体管T3导通，所述转换单元的输出端OUTPUT输出电流信号。此时，所述第二晶体管T2与所述第三晶体管T3同时导通，并且所述第二晶体管T2控制整条充电路径的电流，该电流信号Isignal为
Figure PCTCN2016078669-appb-000001
其中，μn为载流子迁移率，C为单位面积的栅绝缘层电容值，W/L为第二晶体管T2的宽长比，Vgs为第二晶体管T2的栅源电压，Vth为第二晶体管T2的阈值电压。本实施例中，所述第二晶体管T2的源极为第一极，所述第二晶体管T2的栅源电压Vgs＝Vdata-VCC，其中Vdata为转换单元的第一输入端DATA输入的电压，Vcc为第四输入端VCC输入的电压。此时，电压信号Vdata转化为电流信号Isignal输出给相应的像素电路。
本实施例提供的驱动电路的驱动方法中，将源极驱动单元输出的电压信号(也即转换单元的第一输入端DATA输入的电压信号)Vdata转换为电流信号Isignal的过程发生在第一阶段I和第二阶段II。
步骤2003、第一输入端输入高电平，第二输入端输入低电平，第三输入端输入低电平。该步骤对应于工作时序图中的第三阶段III。
本实施例中，第三阶段III为与所述驱动电路对应的像素电路的发光阶段，如图3所示，所述转换单元的所述第一输入端DATA输入的电压信号为高电平，所述第二输入端VCG输入的第一驱动信号为低电平，此时第一晶体管T1和第二晶体管T2截止。另外，所述转换单元的所述第三输入端VCE输入的第二驱动信号为低电平，使得第三晶体管T3截止，所述转换单元的输出端OUTPUT不输出电流信号。
本实施例提供的驱动电路的驱动方法中，转换单元将源极驱动单元输出的电压信号转换为电流信号，通过电流信号来驱动相 应的像素电路。本实施例提供的技术方案使得驱动电路的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，增大显示面板的动态范围。
实施例三
图4为本发明实施例三提供的一种驱动电路的结构示意图。如图4所示，所述驱动电路包括转换单元和源极驱动单元(图中未示出)，所述转换单元设置有第一输入端DATA、第二输入端VCG、第三输入端VCE、第四输入端VCC以及输出端OUTPUT，所述第一输入端DATA与所述源极驱动单元连接，所述第四输入端VCC与直流电源(图中未示出)连接，所述输出端OUTPUT与像素电路(图中未示出)连接。所述转换单元包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1。所述第一晶体管T1的栅极与所述第二输入端VCG连接，所述第一晶体管T1的第一极与所述第一输入端DATA连接，所述第一晶体管T1的第二极与所述第二晶体管T2的栅极连接。所述第二晶体管T2的第一极与所述第四输入端VCC连接，所述第二晶体管T2的第二极与所述第三晶体管T3的第一极连接。所述第三晶体管T3的栅极与所述第三输入端VCE连接，所述第三晶体管T3的第二极与所述输出端OUTPUT连接。所述第一电容C1并联于所述第二晶体管T2的栅极与第一极之间。
本实施例提供的驱动电路与实施例一提供的驱动电路的不同之处在于，实施例一的驱动电路中第一晶体管T1至第三晶体管T3全部为N型晶体管，而本实施例中第一晶体管T1至第三晶体管T3全部为P型晶体管。相应地，当使用类似于实施例二的驱动方法来驱动本实施例提供的驱动电路时，在各个阶段中，第二输入端和第三输入端所输入的信号的高电平变为低电平，低电平变为高电平。
本实施例提供的驱动电路中，转换单元将源极驱动单元输出的电压信号转换为电流信号，通过电流信号来驱动像素电路。本 实施例提供的技术方案使得驱动电路的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，增大显示面板的动态范围。
实施例四
本实施例提供了一种显示基板，所述显示基板包括驱动电路和像素电路。图5为本实施例提供的显示基板中的驱动电路和像素电路的结构示意图，图6为本实施例提供的显示基板中的驱动电路和像素电路的具体结构示意图。如图5-6所示，所述显示基板包括驱动电路101和像素电路102，所述驱动电路101包括源极驱动单元103和转换单元104。所述转换单元104的个数可以为多个。本实施例提供的显示基板设置有并排连接的3个转换单元104。
参见图6，所述转换单元104设置有第一输入端DATA、第二输入端VCG、第三输入端VCE、第四输入端VCC以及输出端OUTPUT，所述第一输入端DATA与源极驱动单元103(图6未示出)连接，所述第四输入端VCC与直流电源(图中未示出)连接，所述输出端OUTPUT与像素电路102连接。所述第一输入端DATA用于将源极驱动单元103输出的电压信号提供给转换单元104，所述第二输入端VCG用于输入第一驱动信号，所述第三输入端VCE用于输入第二驱动信号，所述输出端OUTPUT用于向所述像素电路102输出转换后的电流信号。所述转换单元104将源极驱动单元103输出的电压信号转换为电流信号，通过所述电流信号驱动像素电路102。本实施例提供的技术方案使得驱动电路101的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，增大显示面板的动态范围。
参见图6，所述转换单元104包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第一电容C1，所述第一晶体管T1、第二晶体管T2和第三晶体管T3为N型晶体管。具体来说，所述第一晶体管T1的栅极与转换单元104的所述第二输入端VCG连接， 所述第一晶体管T1的第一极与所述第一输入端DATA连接，所述第一晶体管T1的第二极与所述第二晶体管T2的栅极连接。所述第二晶体管T2的第一极与所述第四输入端VCC连接，所述第二晶体管T2的第二极与所述第三晶体管T3的第一极连接。所述第三晶体管T3的栅极与转换单元104的所述第三输入端VCE连接，所述第三晶体管T3的第二极与转换单元104的所述输出端OUTPUT连接。所述第一电容C1并联于所述第二晶体管T2的栅极与第一极之间。
所述像素电路102设置有第五输入端、第六输入端SCAN、第七输入端VDD以及第八输入端VSS，所述第五输入端与转换单元104的所述输出端OUTPUT连接。所述第五输入端用于输入通过转换单元104得到的所述电流信号，所述第六输入端SCAN用于输入扫描信号，所述第七输入端VDD用于输入高电平信号，所述第八输入端VSS用于输入低电平信号。
参见图6，所述像素电路102包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第二电容C2、第一节点A、第二节点B以及发光器件，所述第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7为P型晶体管。所述第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第二电容C2构成电流镜像素电路。具体来说，所述第四晶体管T4的栅极与像素电路102的所述第六输入端SCAN连接，所述第四晶体管T4的第一极与所述第五输入端连接，所述第四晶体管T4的第二极与所述第一节点A连接。所述第五晶体管T5的栅极与所述第六输入端SCAN连接，所述第五晶体管T5的第一极与所述第五输入端连接，所述第五晶体管T5的第二极与所述第二节点B连接。所述第六晶体管T6的栅极与所述第一节点A连接，所述第六晶体管T6的第一极与所述第二节点B连接，所述第六晶体管T6的第二极与所述发光器件的正极连接。所述第七晶体管T7的栅极与所述第一节点A连接，所述第七晶体管T7的第一极与所述第二节点B连接，所述第七晶体管T7的第二极与所述第七输入端VDD连 接。所述第二电容C2并联于所述第七晶体管T7的栅极与第二极之间。所述发光器件的负极与所述第八输入端VSS连接。
在图6中，第一晶体管T1至第三晶体管T3被设置为N型晶体管，第四晶体管T4至第七晶体管T7被设置为P型晶体管，但是本实施例不限于此。可替换地，可以将第一晶体管T1至第三晶体管T3设置为P型晶体管，并且将第四晶体管T4至第七晶体管T7设置为N型晶体管。
本实施例提供的显示基板中，转换单元将源极驱动单元输出的电压信号转换为电流信号，通过电流信号驱动像素电路。本实施例提供的技术方案使得驱动电路的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，放大显示面板的动态范围。
实施例五
图7为本发明实施例五提供的一种显示基板的驱动方法的流程图，图8为与所述驱动方法对应的该显示基板的工作时序图，图9-图11为分别为与图8所示的第一阶段I至第三阶段III对应的电流路径示意图。该显示基板可以包括上述实施例四提供的显示基板，具体内容可参照上述实施例四的描述，此处不再赘述。下面以实施例四提供的显示基板为例，结合图7-图11对本实施例提供的显示基板的驱动方法进行详细描述。如图7所示，所述驱动方法包括如下步骤7001至7003。
步骤7001、第一输入端输入高电平，第二输入端输入高电平，第三输入端输入低电平，第六输入端输入高电平。该步骤对应于图8所示工作时序图中的第一阶段I。
本实施例中，第一阶段I为所述转换单元的充电阶段，如图8所示，所述转换单元的所述第一输入端DATA输入的电压信号为高电平，所述第二输入端VCG输入的第一驱动信号为高电平，此时第一晶体管T1和第二晶体管T2导通，从而实现对第一电容C1的充电。在这个过程中，如图9所示，电流由转换单元的第一输 入端DATA流向第一电容C1，从而完成对第一电容C1的充电。另外，在第一阶段I，所述转换单元的所述第三输入端VCE输入的第二驱动信号为低电平，因此第三晶体管T3截止；所述像素电路的第六输入端SCAN输入的扫描信号为高电平，因此第四晶体管T4和第五晶体管T5截止，第一节点A的电位为低电平，此时第六晶体管T6和第七晶体管T7保持显示画面的上一帧状态。在这个过程中，如图9所示，电流由所述像素单元的第七输入端VDD通过第六晶体管T6和第七晶体管T7流向发光器件。
步骤7002、第一输入端输入低电平，第二输入端输入低电平，第三输入端输入高电平，第六输入端输入低电平。该步骤对应于图8所示工作时序图中的第二阶段II。
本实施例中，第二阶段II为所述像素电路的充电阶段，如图8所示，所述转换单元的所述第一输入端DATA输入的电压信号为低电平，所述第二输入端VCG输入的第一驱动信号为低电平，此时第一晶体管T1截止、第二晶体管T2保持导通。另外，所述转换单元的所述第三输入端VCE输入的第二驱动信号为高电平，使得第三晶体管T3导通，所述转换单元向所述像素电路输出电流信号。所述像素电路的所述第六输入端SCAN输入的扫描信号为低电平，第四晶体管T4和第五晶体管T5导通，第六晶体管T6的栅极电压与第一极电压相同，所述第六晶体管T6截止，发光器件不发光。此时第一节点A的电位由低电平变为高电平，通过第一节点A实现对所述第二电容C2的充电。在这个过程中，如图10所示，电流由第七输入端VDD通过第七晶体管T7和第五晶体管T5流向所述转换单元，同时通过第四晶体管T4向所述第二电容C2充电。
步骤7003、第一输入端输入高电平，第二输入端输入低电平，第三输入端输入低电平，第六输入端输入高电平。该步骤对应于图8所示工作时序图中的第三阶段III。
本实施例中，第三阶段III为所述像素电路的发光阶段，如图8所示，所述转换单元的所述第一输入端DATA输入的电压信号 为高电平，所述第二输入端VCG输入的第一驱动信号为低电平，此时第一晶体管T1和第二晶体管T2截止。另外，所述第三输入端VCE输入的第二驱动信号为低电平，第三晶体管T3截止，所述像素电路的第六输入端SCAN输入的扫描信号为高电平，第四晶体管T4和第五晶体管T5截止，第一节点A的电位保持为高电平。此时第六晶体管T6和第七晶体管T7的栅极电压相同，第六晶体管T6和第七晶体管T7导通，如图11所示，电流由第七输入端VDD通过第六晶体管T6和第七晶体管T7流向所述像素电路的发光器件，发光器件发光。
本实施例中，所述转换单元将源极驱动单元输出的电压信号转换为电流信号，通过所述电流信号驱动像素电路。下面通过电路仿真的实验数据验证本发明的有益效果。表1为不同数据电压和不同阈值电压Vth下所述转换单元输出的电流的差异，其中数据电压为所述转换单元的第一输入端DATA输入的电压，所述偏移量反映了不同阈值电压Vth下的电流与电流平均值之间的差异：
Figure PCTCN2016078669-appb-000002
Figure PCTCN2016078669-appb-000003
表1：不同数据电压和不同阈值电压下转换单元输出的电流的差异
通过表1可以看出，在第六晶体管T6和第七晶体管T7的性能相同的前提下，本实施例提供的技术方案在不同数据电压不同阈值电压Vth下转换单元输出电流的偏移量较小，能够获得较好的补偿效果。
在本实施例中，以第一晶体管T1至第三晶体管T3被设置为N型晶体管、第四晶体管T4至第七晶体管T7被设置为P型晶体管为例说明了显示基板的驱动方法，但是本实施例不限于此。当第一晶体管T1至第三晶体管T3被设置为P型晶体管并且第四晶体管T4至第七晶体管T7被设置为N型晶体管时，在各个阶段中，第二输入端、第三输入端和第六输入端所输入的信号的高电平变为低电平，低电平变为高电平。
本实施例提供的显示基板的驱动方法中，转换单元将源极驱动单元输出的电压信号转换为电流信号，通过电流信号驱动像素电路。本实施例提供的技术方案使得驱动电路的输出精度高、功耗低，而且还能够提高显示面板显示画面的均匀性，增大显示面板的动态范围。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

  1. 一种驱动电路，包括转换单元，所述转换单元设置有第一输入端、第二输入端、第三输入端、第四输入端以及输出端，所述第四输入端与直流电源连接，所述输出端与像素电路连接；
    所述第一输入端用于输入电压信号，所述第二输入端用于输入第一驱动信号，所述第三输入端用于输入第二驱动信号，所述输出端用于输出电流信号，所述转换单元用于将所述电压信号转换为所述电流信号。
  2. 根据权利要求1所述的驱动电路，其中，所述转换单元包括第一晶体管、第二晶体管、第三晶体管和第一电容；
    所述第一晶体管的栅极与所述第二输入端连接，所述第一晶体管的第一极与所述第一输入端连接，所述第一晶体管的第二极与所述第二晶体管的栅极连接；
    所述第二晶体管的第一极与所述第四输入端连接，所述第二晶体管的第二极与所述第三晶体管的第一极连接；
    所述第三晶体管的栅极与所述第三输入端连接，所述第三晶体管的第二极与所述输出端连接；
    所述第一电容并联于所述第二晶体管的栅极与第一极之间。
  3. 根据权利要求2所述的驱动电路，其中，所述驱动电路还包括源极驱动单元，所述源极驱动单元与所述第一输入端连接，所述源极驱动单元用于输出所述电压信号。
  4. 根据权利要求3所述的驱动电路，其中，以第一模式或第二模式设置所述晶体管，所述第一模式中所述晶体管全部被设置为N型晶体管，在第二模式中所述晶体管全部被设置为P型晶体管。
  5. 一种权利要求4所述驱动电路的驱动方法，包括第一至第三阶段，其中，
    在以第一模式设置时，所述驱动方法包括：
    在第一阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入低电平；
    在第二阶段，第一输入端输入低电平，第二输入端输入低电平，第三输入端输入高电平；
    在第三阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入低电平，
    在以第二模式设置时，所述驱动方法包括：
    在第一阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入高电平；
    在第二阶段，第一输入端输入低电平，第二输入端输入高电平，第三输入端输入低电平；
    在第三阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入高电平。
  6. 一种显示基板，包括像素电路和权利要求1-4任一所述的驱动电路，所述像素电路设置有第五输入端、第六输入端、第七输入端以及第八输入端，所述第五输入端与所述驱动电路的所述输出端连接；
    所述第五输入端用于输入所述电流信号，所述第六输入端用于输入扫描信号，所述第七输入端用于输入高电平，所述第八输入端用于输入低电平。
  7. 根据权利要求6所述的显示基板，其中，所述像素电路包括第四晶体管、第五晶体管、第六晶体管、第七晶体管、第二电容、第一节点、第二节点以及发光器件；
    所述第四晶体管的栅极与所述第六输入端连接，所述第四晶体管的第一极与所述第五输入端连接，所述第四晶体管的第二极 与所述第一节点连接；
    所述第五晶体管的栅极与所述第六输入端连接，所述第五晶体管的第一极与所述第五输入端连接，所述第五晶体管的第二极与所述第二节点连接；
    所述第六晶体管的栅极与所述第一节点连接，所述第六晶体管的第一极与所述第二节点连接，所述第六晶体管的第二极与所述发光器件的正极连接；
    所述第七晶体管的栅极与所述第一节点连接，所述第七晶体管的第一极与所述第二节点连接，所述第七晶体管的第二极与所述第七输入端连接；
    所述第二电容并联于所述第七晶体管的栅极与第二极之间；
    所述发光器件的负极与所述第八输入端连接。
  8. 根据权利要求7所述的显示基板，其中，以第一模式或第二模式设置所述晶体管，
    在所述第一模式中，所述第一晶体管、第二晶体管和第三晶体管被设置为N型晶体管，所述第四晶体管、第五晶体管、第六晶体管和第七晶体管被设置为P型晶体管；
    在所述第二模式中，所述第一晶体管、第二晶体管和第三晶体管被设置为P型晶体管，所述第四晶体管、第五晶体管、第六晶体管和第七晶体管被设置为N型晶体管。
  9. 根据权利要求6所述的显示基板，其中，所述转换单元设置在显示面板扇出结构的末端；或者
    所述转换单元设置在所述源极驱动单元的输出端与显示面板的邦定区域之间。
  10. 一种权利要求8所述显示基板的驱动方法，包括第一至第三阶段，其中，
    在以第一模式设置时，所述驱动方法包括：
    在第一阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入低电平，第六输入端输入高电平；
    在第二阶段，第一输入端输入低电平，第二输入端输入低电平，第三输入端输入高电平，第六输入端输入低电平；
    在第三阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入低电平，第六输入端输入高电平，
    在以第二模式设置时，所述驱动方法包括：
    在第一阶段，第一输入端输入高电平，第二输入端输入低电平，第三输入端输入高电平，第六输入端输入低电平；
    在第二阶段，第一输入端输入低电平，第二输入端输入高电平，第三输入端输入低电平，第六输入端输入高电平；
    在第三阶段，第一输入端输入高电平，第二输入端输入高电平，第三输入端输入高电平，第六输入端输入低电平。
  11. 一种显示装置，包括权利要求6-9任一所述的显示基板。
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