WO2021196020A1 - 像素电路及其驱动方法以及显示面板 - Google Patents

像素电路及其驱动方法以及显示面板 Download PDF

Info

Publication number
WO2021196020A1
WO2021196020A1 PCT/CN2020/082575 CN2020082575W WO2021196020A1 WO 2021196020 A1 WO2021196020 A1 WO 2021196020A1 CN 2020082575 W CN2020082575 W CN 2020082575W WO 2021196020 A1 WO2021196020 A1 WO 2021196020A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
signal
circuit
light
Prior art date
Application number
PCT/CN2020/082575
Other languages
English (en)
French (fr)
Inventor
冯佑雄
陈文波
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/082575 priority Critical patent/WO2021196020A1/zh
Priority to CN202080000449.1A priority patent/CN113748454B/zh
Priority to US17/259,983 priority patent/US11410604B2/en
Priority to DE112020005555.8T priority patent/DE112020005555T5/de
Publication of WO2021196020A1 publication Critical patent/WO2021196020A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a pixel circuit, a driving method thereof, and a display panel.
  • OLED Organic Light Emitting Diode
  • LTPS Low Temperature Poly Silicon
  • the embodiments of the present disclosure provide a pixel circuit and a driving method thereof, and a display panel.
  • a pixel driving circuit configured to drive a light-emitting element to emit light.
  • the pixel driving circuit shown includes: a driving sub-circuit configured to generate a current for causing the light-emitting element to emit light.
  • a light-emitting control sub-circuit electrically connected to the driving sub-circuit and the first end of the light-emitting element, configured to receive a light-emitting control signal, and under the control of the light-emitting control signal, will be used to make the light-emitting
  • the current that the element emits light is provided to the first end of the light-emitting element;
  • the drive control sub-circuit is electrically connected to the drive sub-circuit, and is configured to receive a data signal and a gate drive signal.
  • the data signal is provided to the driving sub-circuit;
  • the reset sub-circuit is electrically connected to the first end of the driving sub-circuit and the light-emitting element, and is electrically connected to the first end of the driving sub-circuit.
  • a node configured to receive a first reset signal and a second reset signal, and under the control of the first reset signal and the second reset signal, perform a control on the first node and the first end of the light-emitting element Resetting; and a compensation sub-circuit, electrically connected to the first node, configured to receive a compensation control signal, and under the control of the compensation control signal, compensate the voltage of the first node.
  • the compensation sub-circuit includes a first transistor, the gate of the first transistor is electrically connected to receive the compensation control signal, and the first electrode of the first transistor is electrically connected to receive a first voltage Signal, the second electrode of the first transistor is electrically connected to the first node.
  • the first transistor is a P-type transistor.
  • the compensation control signal has a first level, and the first transistor is in an off state under the control of the compensation control signal.
  • the channel width to length ratio of the first transistor is greater than or equal to 10/3.5.
  • the driving sub-circuit includes a driving transistor, a second transistor, and a storage capacitor, wherein the gate of the driving transistor is electrically connected to the first node, and the first electrode of the driving transistor is connected to the light-emitting control sub-circuit.
  • the circuit is electrically connected to the second node, the second pole of the driving transistor and the light emission control sub-circuit are electrically connected to the third node; the gate of the second transistor is electrically connected to receive the gate driving signal, so
  • the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the third node; and the first end of the storage capacitor is electrically connected to receive the first node. Voltage signal, the second terminal is electrically connected to the first node.
  • the driving transistor is a P-type transistor.
  • the channel width to length ratio of the second transistor is less than or equal to 2/3.5.
  • the drive control sub-circuit includes a third transistor, the gate of the third transistor is electrically connected to receive the gate drive signal, and the first electrode of the third transistor is electrically connected to receive the gate drive signal.
  • the second electrode of the third transistor and the light-emitting control sub-circuit are electrically connected to the second node.
  • the light emission control sub-circuit includes a fourth transistor and a fifth transistor, wherein
  • the gate of the fourth transistor is electrically connected to receive the light emission control signal, the first electrode of the fourth transistor is electrically connected to receive a first voltage signal, and the second electrode of the fourth transistor is electrically connected to the light emission control sub-circuit Is electrically connected to the second node; the gate of the fifth transistor is electrically connected to receive the light emission control signal, the first electrode of the fifth transistor and the light emission control sub-circuit are electrically connected to the third node, and the fifth transistor The second terminal of the transistor is electrically connected to the first terminal of the light-emitting element.
  • the reset sub-circuit includes a sixth transistor and a seventh transistor, wherein the gate of the sixth transistor is electrically connected to receive the first reset signal, and the first electrode of the sixth transistor is electrically connected. Is connected to the first node, the second electrode of the sixth transistor is electrically connected to receive a reset reference signal; the gate of the seventh transistor is electrically connected to receive the second reset signal, and the second electrode of the seventh transistor is electrically connected to receive the second reset signal. One electrode is electrically connected to receive the reset reference signal, and the second electrode of the seventh transistor is electrically connected to the first end of the light-emitting element.
  • the reset sub-circuit includes a sixth transistor and a seventh transistor, wherein the gate of the sixth transistor is electrically connected to receive the first reset signal, and the first electrode of the sixth transistor is electrically connected. Is connected to the first node, the second electrode of the sixth transistor is electrically connected to receive a reset reference signal; the gate of the seventh transistor is electrically connected to receive the second reset signal, and the second electrode of the seventh transistor is electrically connected to receive the second reset signal. One electrode is electrically connected to receive the reset reference signal, and the second electrode of the seventh transistor is electrically connected to the first end of the light-emitting element; wherein, the second reset signal is used as the compensation control signal.
  • the channel width to length ratio of the sixth transistor is less than or equal to 2/3.5.
  • a display panel including: a plurality of scan lines; a plurality of data lines arranged to cross the plurality of scan lines; and a plurality of pixel units arranged in a matrix.
  • each pixel unit includes a light-emitting element and a pixel drive circuit according to an embodiment of the present disclosure, wherein the pixel drive circuit is The received data signal is provided by the corresponding data line of the pixel unit, and the gate driving signal received by the pixel drive circuit is provided by the corresponding scan line of the pixel unit.
  • a method for driving a pixel driving circuit including: providing a light emission control signal and a gate driving signal having a first level in a first period; The first reset signal and the second reset signal are flat; in the second period, the first reset signal and the second reset signal of the light-emitting control signal with the first level are provided, and the gate drive signal with the second level is provided; In the third period, the first reset signal, the second reset signal, and the gate drive signal with the first level are provided, and the light emission control signal with the second level is provided.
  • the compensation control signal having the first level is always provided in the first period, the second period, and the third period.
  • a second reset signal with a first level is always provided if the second reset signal is used as the compensation control signal, in the first, second, and third periods.
  • FIG. 1 shows a schematic block diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 2a and 2b show circuit diagrams of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of the node voltage retention capability of the pixel driving circuit according to an embodiment of the present disclosure within the allowable range of process variation
  • FIG. 4 shows a flowchart of a driving method of a pixel driving circuit according to an embodiment of the present disclosure
  • 5a and 5b show signal timing diagrams of a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the term “electrically connected” may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components. In addition, these two components can be electrically connected or coupled in a wired or wireless manner.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged. In the embodiments of the present disclosure, one of the source electrode and the drain electrode is referred to as a first electrode, and the other of the source electrode and the drain electrode is referred to as a second electrode.
  • first level and second level are only used to distinguish the two levels from being different in amplitude.
  • the "first level” may be a high level
  • the “second level” may be a low level.
  • the driving transistor is exemplified as a P-type thin film transistor
  • the "first level” is exemplified as a high level
  • the “second level” is exemplified as a low level.
  • OLED display technology is widely used in portable or handheld devices, so reducing the power consumption of OLED displays is very important.
  • the display frequency can be appropriately reduced, that is, for the static picture, the frequency reduction display can be performed.
  • Down-frequency display means that the time interval between each refresh of the OLED drive circuit needs to be extended, which is very disadvantageous for nodes that require high voltage retention, especially for the gate of the drive transistor which is closely related to the generation of current flowing through the OLED. Extreme voltage.
  • FIG. 1 shows a schematic block diagram of a pixel driving circuit 10 according to an embodiment of the present disclosure.
  • the pixel driving circuit 10 is configured to drive the light emitting element to emit light.
  • the light-emitting element is illustrated in the form of an OLED, but this is only an example, and the light-emitting element may also be other current-driven devices, and the embodiments of the present disclosure are not limited thereto.
  • the light-emitting element OLED is shown in the form of a dotted line. As shown in FIG.
  • the first end of the light-emitting element OLED is electrically connected to the pixel driving circuit 10, and the second end is electrically connected to the fixed voltage VSS.
  • the first end may be the anode of the light-emitting element OLED, and the second end may be the cathode of the light-emitting element OLED.
  • the pixel driving circuit 10 includes a driving sub-circuit 11 configured to generate a current for causing the light-emitting element OLED to emit light.
  • the pixel driving circuit 10 further includes a light-emitting control sub-circuit 12, the light-emitting control sub-circuit 12 and the driving sub-circuit 11 are electrically connected to the second node N2, and the light-emitting control sub-circuit 12 is simultaneously connected to the first terminal of the light-emitting element OLED Electrically connected to the third node.
  • the light emission control sub-circuit 12 is configured to receive the light emission control signal CON1, and under the control of the light emission control signal CON1, provide a current for causing the light emitting element OLED to emit light to the first end of the light emitting element OLED.
  • the pixel driving circuit 10 further includes a driving control sub-circuit 13, and the driving control sub-circuit 13 and the driving sub-circuit 11 are electrically connected to the second node N2.
  • the driving control sub-circuit 13 is configured to receive the data signal Vdata and the gate driving signal CON2, and provide the data signal Vdata to the driving sub-circuit 11 under the control of the gate driving signal CON2.
  • the pixel driving circuit 10 further includes a reset sub-circuit 14, and the reset sub-circuit 14 is electrically connected to the driving sub-circuit 11 and the first end of the light-emitting element OLED.
  • the reset sub-circuit 14 and the driving sub-circuit 11 are electrically connected to the first node N1.
  • the reset sub-circuit 14 is configured to receive the first reset signal CON3, the second reset signal CON4, and the reset reference signal Vref, and use the reset signal under the control of the first reset signal CON3 and the second reset signal CON4.
  • the reference signal Vref resets the first node N1 and the first end of the light-emitting element OLED.
  • the pixel driving circuit 10 further includes a compensation sub-circuit 15, and the compensation sub-circuit 15 and the driving sub-circuit 11 are electrically connected to the first node N1.
  • the compensation sub-circuit 15 is configured to compensate the voltage of the first node N1.
  • FIGS. 2a and 2b are circuit diagrams of a pixel driving circuit 20 according to an embodiment of the present disclosure.
  • the driving sub-circuit 21 includes a driving transistor Td, a second transistor T2 and a storage capacitor Cst.
  • the gate of the driving transistor Td is electrically connected to the first node N1
  • the first electrode of the driving transistor Td and the light emission control sub-circuit 22 are electrically connected to the second node N2
  • the second electrode of the driving transistor Td is electrically connected to the light emission control sub-circuit 22 is electrically connected to the third node N3.
  • the gate of the second transistor T2 is electrically connected to receive the gate driving signal CON2
  • the first electrode of the second transistor T2 is electrically connected to the first node N1
  • the second electrode of the second transistor T2 is electrically connected to the third node N3.
  • the first terminal of the storage capacitor Cst is electrically connected to receive the first voltage signal VDD, and the second terminal is electrically connected to the first node N1.
  • the light emission control sub-circuit 22 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is electrically connected to receive the light emission control signal CON1
  • the first electrode of the fourth transistor T4 is electrically connected to receive the first voltage signal VDD
  • the second electrode of the fourth transistor T4 is electrically connected to the second Node N2.
  • the gate of the fifth transistor T5 is electrically connected to receive the light emission control signal CON1
  • the first electrode of the fifth transistor T5 is electrically connected to the third node N3, and the second electrode of the fifth transistor T5 is electrically connected to the first end of the light emitting element OLED.
  • the fourth transistor T4 and the fifth transistor T5 may both be P-type transistors or both may be N-type transistors.
  • the driving control sub-circuit 23 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to receive the gate drive signal CON1
  • the first electrode of the third transistor T3 is electrically connected to receive the data signal Vdata
  • the second electrode of the third transistor T3 is electrically connected to the second node N2.
  • the reset sub-circuit 24 includes a sixth transistor T6 and a seventh transistor T7.
  • the gate of the sixth transistor T6 is electrically connected to receive the first reset signal CON3
  • the first electrode of the sixth transistor T6 is electrically connected to the first node N1
  • the second electrode of the sixth transistor T6 is electrically connected to receive the reset reference Signal Vref.
  • the gate of the seventh transistor T7 is electrically connected to receive the second reset signal CON4
  • the first electrode of the seventh transistor T7 is electrically connected to receive the reset reference signal Vref
  • the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the light emitting element OLED.
  • the sixth transistor T6 and the seventh transistor T7 may both be P-type transistors or both may be N-type transistors.
  • the driving transistor Td is a P-type transistor, and the gate of the driving transistor Td (ie, the first node N1) is electrically connected to the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6.
  • the second transistor T2 and the sixth transistor T6 are both in the off state. Because the transistor made by the LTPS process has a large leakage current, there will be current flowing out of the first transistor. Node N1, the current flowing out of the first node N1 is indicated by the dashed lines 1 and 2 with arrows in Figure 2a.
  • the dashed line 1 of the arrow indicates that the leakage current I off2 of the second transistor T2 flows from the first node N1 (the second transistor T2 of the second transistor T2). One pole) flows through the second transistor T2 to the second pole of the second transistor T2.
  • the dotted line 2 of the arrow represents the leakage current I off6 of the sixth transistor T6 from the first node N1 (the first pole of the sixth transistor T6) through the sixth node.
  • the transistor T6 flows to the second pole of the sixth transistor T6. This will cause the gate voltage of the driving transistor Td to change, thereby affecting the current flowing through the light-emitting element OLED, and degrading the image quality of the display.
  • a compensation sub-circuit 25 is provided in the pixel driving circuit 20 to compensate the voltage of the first node N1, so as to maintain the stability of the voltage of the first node N1.
  • the compensation sub-circuit 25 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to receive the compensation control signal CON5, and the first pole of the first transistor T1 is electrically connected to receive the first voltage signal VDD,
  • the second electrode of the first transistor T1 is electrically connected to the first node N1.
  • the compensation control signal CON5 having the first level may be provided, and the first transistor T1 may be in an off state under the control of the compensation control signal CON5 having the first level.
  • the leakage current I off1 of the first transistor T1 in the off state can flow from the first pole to the second pole of the first transistor T1, that is, the leakage current I off1 flows from the first voltage VDD to the second pole through the first transistor T1.
  • a node N1 as shown by the dashed line 3 with an arrow in Figure 2a.
  • the leakage current I off1 flowing into the first node N1 can supplement the leakage current I off2 and the leakage current I off6 flowing out of the first node N1, so as to maintain the stability of the voltage of the first node N1.
  • the second reset signal can be used as a compensation control signal, thereby saving signal lines and thus saving layout space.
  • the compensation sub-circuit 25 includes a first transistor T1.
  • the gate of the first transistor T1 is electrically connected to receive the compensation control signal, that is, the second reset signal CON4, and the first pole of the first transistor T1 is electrically connected to receive With the first voltage signal VDD, the second electrode of the first transistor T1 is electrically connected to the first node N1.
  • the second reset signal CON4 having the first level may be provided, and the first transistor T1 may be in the off state under the control of the second reset signal CON4 having the first level.
  • the leakage current I off1 of the first transistor T1 in the off state can flow from the first pole to the second pole of the first transistor T1, that is, the leakage current I off1 flows from the first voltage VDD to the second pole through the first transistor T1.
  • a node N1 as shown by the dashed line 3 with an arrow in Figure 2b.
  • the leakage current I off1 flowing into the first node N1 can supplement the leakage current I off2 and the leakage current I off6 flowing out of the first node N1, so as to maintain the stability of the voltage of the first node N1.
  • the second reset signal CON4 is always at the first level, and the seventh transistor T7 is also kept in the off state.
  • the seventh transistor T7 in the off state shunts the leakage current flowing through the OLED in the black screen display state, so as to better display the black screen.
  • the leakage currents I off1 , I off2 and I off6 can be adjusted by adjusting the channel width to length ratios of the first transistor T1, the second transistor T2 and the sixth transistor T6, so as to obtain the required voltage holding capability .
  • the voltage retention capability of the first node N1 decreases as the channel aspect ratio of the second transistor T2 and the sixth transistor T6 increases, and increases as the channel aspect ratio of the first transistor T1 increases . Therefore, appropriately increasing the channel aspect ratio of the first transistor T1, or appropriately reducing the channel aspect ratio of the second transistor T2, or appropriately reducing the channel aspect ratio of the sixth transistor T6 can increase the first node N1.
  • the voltage holding ability It is easy to understand that at the same time, the channel width-to-length ratio of the first transistor T1 is appropriately increased, and the channel width-to-length ratio of the second transistor T2 and the sixth transistor T6 is appropriately reduced, or any two of the transistors can meet the corresponding conditions. Increase the voltage holding capability of the first node N1.
  • the leakage current of a transistor is related to the channel width-to-length ratio of the transistor and the voltage applied to the source and drain of the transistor when the transistor is in the off state.
  • the leakage current flowing out of the first node N1 generated by the six transistor T6 is smaller.
  • the channel width to length ratios of the second transistor T2 and the sixth transistor T6 are both less than or equal to 2/3.5, a better voltage retention capability can be obtained at the first node N1.
  • the greater the channel width-to-length ratio of the first transistor T1 the greater the voltage applied to the source and drain of the first transistor T1, and the greater the voltage generated by the first transistor T1 The greater the leakage current flowing into the first node N1.
  • the smaller the channel aspect ratio of the first transistor T1 the smaller the voltage applied to the source and drain of the first transistor T1, and the smaller the leakage current generated by the first transistor T1 flowing into the first node N1.
  • the channel width to length ratio of the first transistor T1 is greater than or equal to 10/3.5, a better voltage holding capability can be obtained at the first node N1.
  • the frequency of 30 Hz and the frequency of 60 Hz are respectively The voltage at the first node N1 is recorded at the frequency.
  • the change in the voltage at the first node N1 is 3.86% during the period from the current OLED reaching stable light emission to the next re-driving of the current OLED to emit light.
  • the amount of change in the voltage of the first node N1 is only 2.07%. In both cases, it is far less than the 8.6% change in voltage when the first transistor T1 is not increased.
  • the first transistor T1 is exemplified as a P-type transistor. This is because for the LTPS process, the P-type transistor has a larger leakage current than the N-type transistor, and the more the leakage current of the first transistor T1 is Larger, the more favorable it is to inject more current into the first node N1, that is, the greater the adjustment effect on the voltage holding capability of the first node N1.
  • the second transistor T2 and the sixth transistor T6 are also shown as P-type transistors. In other embodiments, the second transistor T2 and the sixth transistor T6 may also be N-type transistors.
  • the first transistor T1 is required to inject the first node N1 into the second transistor.
  • Those skilled in the art can select the types of the first transistor T1, the second transistor T2, and the sixth transistor T6 according to the concept of the embodiments of the present disclosure and the desired adjustment effect.
  • the compensation control signal CON5 can be maintained at a high level, so that the first transistor T1 is always kept in the off state.
  • the compensation control signal CON4 can be maintained at a high level, so that the first transistor T1 and the seventh transistor T7 are always kept in the off state.
  • the ability to maintain the gate voltage of the driving transistor can be improved, thereby stabilizing the current flowing through the light-emitting element OLED, avoiding the flicker phenomenon of the screen during low-frequency display, and improving the display effect.
  • the embodiments of the present disclosure it is possible to provide a larger allowable range of process variation, thereby widening the process window.
  • the widening of the process manufacturing window helps to increase the yield of the production and reduce the production cost.
  • FIG. 3 shows a schematic diagram of the node voltage retention capability of the pixel driving circuit according to an embodiment of the present disclosure within the allowable range of process variation.
  • the channel aspect ratio of the first transistor T1 is (10 ⁇ 1)/3.5
  • the channel aspect ratio of the second transistor T2 and the sixth transistor T6 is (2 ⁇ 1)/3.5, that is, the first transistor T1
  • the aspect ratios of the first transistor T1, the second transistor T2, and the sixth transistor T6 all have a variation of ⁇ 1, which provides a relatively loose window for the process of the transistor.
  • the channel width-to-length ratio of the second transistor T2 and the sixth transistor T6 may be the same or different, and it is only required that at least one of T2 and T6 is approximately located where the channel width-to-length ratio of the transistor is less than or equal to 2. /3.5.
  • the abscissa of the graph shown in FIG. 3 is the change (%) of the voltage of the first node N1, and the ordinate is the process parameter ratio (%). It can be seen from the graph that the voltage variation range of the first node N1 is approximately -15.12% to 10.46% at 60 Hz, and approximately -27.5% to 18.02% at 30 Hz. Calculate the voltage variation range of the first node N1 under the condition that the channel aspect ratio variation is ⁇ 1. The voltage variation of the first node N1 is better than 2.07%. The voltage value accounts for all the voltage variation of the first node N1. The ratio of the voltage value is close to 50%, and the voltage value whose voltage change amount of the first node N1 is better than 8.6% accounts for more than 90% of the voltage value of all the voltage values of the first node N1.
  • FIG. 4 shows a flowchart of a driving method 400 of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 5a shows a signal timing diagram of a driving method 400 of a pixel driving circuit according to an embodiment of the present disclosure
  • Figures 2b, 4, and 5a and 5b illustrate a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
  • the driving method 400 of the pixel driving circuit includes the following steps.
  • step S410 in the first time period, a light-emitting control signal and a gate driving signal having a first level are provided, and a first reset signal and a second reset signal having a second level are provided.
  • step S420 in the second period, a light emission control signal having a first level, a first reset signal, and a second reset signal are provided, and a gate driving signal having a second level is provided.
  • step S430 in the third period, a first reset signal, a second reset signal, and a gate driving signal having a first level are provided, and a light emission control signal having a second level is provided.
  • the light-emitting control signal CON1 and the gate driving signal CON2 having a first level are provided, and the light emission control signal CON1 and a gate drive signal CON2 having a second level (ie, a low level) are provided.
  • VL the first reset signal CON3 and the second reset signal CON4.
  • the fourth transistor T4 and the fifth transistor T5 are turned off.
  • the second transistor T2 and the third transistor T3 are turned off.
  • the sixth transistor T6 is turned on, and when the sixth transistor T6 is turned on, the reset reference signal Vref is transmitted to the first node N1.
  • the seventh transistor T7 is turned on, and when the seventh transistor T7 is turned on, the reset reference signal Vref is transmitted to the first end of the light emitting element 150.
  • the reset reference signal Vref may be at the second level (ie, the low level VL). Therefore, the reset reference signal Vref may cause the gate of the driving transistor Td to become a low level, which will turn on the driving transistor Td. .
  • the anode of the light-emitting element 150 also becomes a low level. As a result, both the driving transistor Td and the anode of the light emitting element 150 are reset to a low level.
  • the light-emitting control signal CON1, the first reset signal CON3, and the second reset signal CON4 having the first level (ie, the high level VH) are provided, and the second power level is provided.
  • the gate drive signal CON2 is flat (ie, low level VL).
  • the fourth transistor T4 and the fifth transistor T5 are turned off.
  • the sixth transistor T6 and the seventh transistor T7 are turned off.
  • the second transistor T2 and the third transistor T3 are turned on.
  • the third transistor T3 when the third transistor T3 is turned on, the high-level data signal Vdata is transmitted to the second node N2. Since the driving transistor Td is in the on state during the t1 period, the driving transistor Td is still in the on state at this time, so that the high-level data signal Vdata continues to be transmitted to the third node N3. When the second transistor T2 is turned on, the high-level data signal Vdata continues to be transmitted to the first node N1, and the first node N1 at the low level is charged.
  • Vdata may have a first level (ie, a high level VH).
  • the gate drive signal CON2, the first reset signal CON3, and the second reset signal CON4 having the first level (ie, the high level VH) are provided, and the second reset signal CON4 is provided.
  • the fourth transistor T4 and the fifth transistor T5 are turned on.
  • the second transistor T2 and the third transistor T3 are turned off.
  • the sixth transistor T6 and the seventh transistor T7 are turned off.
  • the driving current Id generated by the driving transistor Td is applied to the anode of the light-emitting element OLED, and the light-emitting element OLED is driven to emit light.
  • the driving current Id flowing through the light-emitting element OLED can be expressed by the following formula:
  • K is the current constant associated with the driving transistor Td, which is related to the process parameters and geometric dimensions of the driving transistor Td. It can be seen from the above formula that the driving current Id used to drive the light-emitting element OLED to emit light has nothing to do with the threshold voltage Vth of the driving transistor Td.
  • the threshold voltage of the driving transistor Td can also be compensated, so as to stabilize the current flowing through the light-emitting element OLED and improve the display effect.
  • the light-emitting brightness of the OLED will be maintained during the process of driving and displaying the light-emitting element OLED by other row pixel drive circuits. That is to keep the current flowing through the OLED unchanged.
  • the first node N1 since the leakage current I off2 of the second transistor T2 and the leakage current I off6 of the sixth transistor T6 respectively flow out from the first node N1, the first node N1 will be caused. The voltage drops. On the other hand, since the leakage current I off1 of the first transistor T1 flows into the first node N1, the voltage of the first node N1 will increase. By adjusting the channel width-to-length ratios of the first transistor T1, the second transistor T2, and the sixth transistor T6, the voltage of the first node N1 can be basically maintained unchanged, thereby maintaining the current flowing through the OLED unchanged.
  • the second reset signal CON4 is used as the compensation control signal, in the first period t1, the second period t2, and the third period t3, the second reset signal CON4 with the first level is always provided, the corresponding timing diagram As shown in Figure 5b.
  • the first transistor T1 and the seventh transistor T7 are always in the off state, and thus, in the first period t1, only the turned-on sixth transistor T6 is passed through.
  • the reset reference signal Vref is transmitted, and the first node N1 is reset.
  • the seventh transistor T7 in the off state shunts the leakage current flowing through the OLED in the black screen display state, so as to better display the black screen.
  • FIG. 6 shows a schematic block diagram of the display panel 60 according to an embodiment of the present disclosure.
  • the display panel 60 may include a plurality of scan lines SL and a plurality of data lines DL, and the plurality of data lines DL and the plurality of scan signal lines SL are arranged crosswise and crosswise.
  • the display panel 60 may further include a plurality of pixel units 61, which are arranged in a matrix at the intersection of each scan line SL and each data line DL, and are electrically connected to the corresponding scan line SL and data line DL.
  • Each pixel unit of the plurality of pixel units 61 includes a light-emitting element OLED and a pixel driving circuit according to an embodiment of the present disclosure.
  • the structure of the pixel driving circuit is, for example, according to the pixel driving circuit 10 shown in FIG. 1 or shown in FIGS. 2a and 2b. ⁇ Pixel drive circuit 20.
  • the data signal received by the pixel drive circuit is provided by the corresponding data line DL of the pixel unit 61
  • the gate drive signal received by the pixel drive circuit is provided by the corresponding scan line SL of the pixel unit 61.
  • the display panel according to the embodiment of the present disclosure can compensate the threshold voltage of the driving transistor, and at the same time, can improve the retention of the gate voltage of the driving transistor, thereby stabilizing the current flowing through the light-emitting element OLED, and avoiding the flicker phenomenon of the screen during low-frequency display. Improve the display effect.
  • the power consumption of the display panel can be reduced by lowering the frequency of display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开实施例提供了一种像素驱动电路，被配置为驱动发光元件发光，该像素驱动电路包括：驱动子电路，被配置为产生用于使发光元件发光的电流；发光控制子电路，电连接到驱动子电路和发光元件的第一端，被配置将用于使发光元件发光的电流提供到发光元件的第一端；驱动控制子电路，电连接到驱动子电路，被配置为将数据信号提供到驱动子电路；复位子电路，电连接到驱动子电路和发光元件的第一端，并且与驱动子电路电连接于第一节点，被配置为对第一节点和发光元件的第一端进行复位；以及补偿子电路，电连接到第一节点，被配置为接收补偿控制信号，并在补偿控制信号的控制下，对第一节点的电压进行补偿。

Description

像素电路及其驱动方法以及显示面板 技术领域
本公开实施例涉及显示技术领域，具体地涉及一种像素电路及其驱动方法以及显示面板。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)具有响应速度快、易于实现高分辨率显示等优点，逐渐发展成为一种主流的显示技术，广泛应用于各种领域中。OLED显示装置的像素驱动电路一般采用LTPS(Low Temperature Poly Silicon)工艺，这使得像素驱动电路在一些关键节点处的电压保持能力较差，从而使显示的画面出现闪烁现象，影响OLED显示装置的显示效果。
发明内容
本公开实施例提供了一种像素电路及其驱动方法以及显示面板。
根据本公开实施例的一个方面，提供了一种像素驱动电路，被配置为驱动发光元件发光，所示像素驱动电路包括：驱动子电路，被配置为产生用于使所述发光元件发光的电流；发光控制子电路，电连接到所述驱动子电路和所述发光元件的第一端，被配置为接收发光控制信号，并在所述发光控制信号的控制下，将用于使所述发光元件发光的电流提供到所述发光元件的第一端；驱动控制子电路，电连接到所述驱动子电路，被配置为接收数据信号和栅极驱动信号，并在所述栅极驱动信号的控制下，将所述数据信号提供到所述驱动子电路；复位子电路，电连接到所述驱动子电路和所述发光元件的第一端，并且与所述驱动子电路电连接于第一节点，被配置为接收第一复位信号和第二复位信号，并在所述第一复位信号和所述第二复位信号的控制下，对所述第一节点和所述发光元件的第一端进行复位；以及补偿子电路，电连接到所述第一节点，被配置为接收补偿控制信号，并在所述补偿控制信号的控制下，对所述第一节点的电压进行补偿。
在一些实施例中，所述补偿子电路包括第一晶体管，所述第一晶体管的栅极电连接为所述接收补偿控制信号，所述第一晶体管的第一极电连接为接收第一电压信号，所述 第一晶体管的第二极电连接所述第一节点。
在一些实施例中，所述第一晶体管为P型晶体管。
在一些实施例中，所述补偿控制信号具有第一电平，所述第一晶体管在所述补偿控制信号的控制下处于关断状态。
在一些实施例中，所述第一晶体管的沟道宽长比大于或等于10/3.5。
在一些实施例中，所述驱动子电路包括驱动晶体管、第二晶体管和存储电容，其中所述驱动晶体管的栅极电连接所述第一节点，所述驱动晶体管的第一极与发光控制子电路电连接于第二节点，所述驱动晶体管的第二极与所述发光控制子电路电连接于第三节点；所述第二晶体管的栅极电连接为接收所述栅极驱动信号，所述第二晶体管的第一极电连接所述第一节点，所述第二晶体管的第二极电连接所述第三节点；以及所述存储电容的第一端电连接为接收所述第一电压信号，第二端电连接所述第一节点。
在一些实施例中，所述驱动晶体管为P型晶体管。
在一些实施例中，所述第二晶体管的沟道宽长比小于或等于2/3.5。
在一些实施例中，所述驱动控制子电路包括第三晶体管，所述第三晶体管的栅极电连接为接收所述栅极驱动信号，所述第三晶体管的第一极电连接为接收所述数据信号，所述第三晶体管的第二极与发光控制子电路电连接于第二节点。
在一些实施例中，所述发光控制子电路包括第四晶体管和第五晶体管，其中
所述第四晶体管的栅极电连接为接收所述发光控制信号，所述第四晶体管的第一极电连接为接收第一电压信号，所述第四晶体管的第二极与发光控制子电路电连接于第二节点；所述第五晶体管的栅极电连接为接收所述发光控制信号，所述第五晶体管的第一极与发光控制子电路电连接于第三节点，所述第五晶体管的第二极电连接到所述发光元件的第一端。
在一些实施例中，所述复位子电路包括第六晶体管和第七晶体管，其中所述第六晶体管的栅极电连接为接收所述第一复位信号，所述第六晶体管的第一极电连接所述第一节点，所述第六晶体管的第二极电连接为接收复位参考信号；所述第七晶体管的栅极电连接为接收所述第二复位信号，所述第七晶体管的第一极电连接为接收所述复位参考信号，所述第七晶体管的第二极电连接到所述发光元件的第一端。
在一些实施例中，所述复位子电路包括第六晶体管和第七晶体管，其中所述第六晶体管的栅极电连接为接收所述第一复位信号，所述第六晶体管的第一极电连接所述 第一节点，所述第六晶体管的第二极电连接为接收复位参考信号；所述第七晶体管的栅极电连接为接收所述第二复位信号，所述第七晶体管的第一极电连接为接收所述复位参考信号，所述第七晶体管的第二极电连接到所述发光元件的第一端；其中，利用所述第二复位信号充当所述补偿控制信号。
在一些实施例中，所述第六晶体管的沟道宽长比小于或等于2/3.5。
根据本公开的另一方面，还提供了一种显示面板，包括：多条扫描线；多条数据线，与所述多条扫描线交叉设置；以及多个像素单元，以矩阵的形式设置在每个数据线和每个扫描线交叉处，并与对应的数据线和扫描线电连接，每个像素单元包括发光元件和根据本公开实施例的像素驱动电路，其中，所述像素驱动电路所接收的数据信号由所述像素单元的对应数据线提供，所述像素驱动电路所接收的栅极驱动信号由所述像素单元的对应扫描线提供。
根据本公开的另一方面，还提供了一种对像素驱动电路进行驱动的方法，包括：在第一时段，提供具有第一电平的发光控制信号、栅极驱动信号，提供具有第二电平的第一复位信号、第二复位信号；在第二时段，提供具有第一电平的发光控制信号第一复位信号和第二复位信号，提供具有第二电平的栅极驱动信号；在第三时段，提供具有第一电平的第一复位信号、第二复位信号和栅极驱动信号，提供具有第二电平的发光控制信号。
在一些实施例中，在所述第一时段、第二时段和第三时段中，始终提供具有第一电平的补偿控制信号。
在一些实施例中，如果利用所述第二复位信号充当所述补偿控制信号，则在所述第一时段、第二时段和第三时段中，始终提供具有第一电平的第二复位信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了根据本公开实施例的像素驱动电路的示意性框图；
图2a和图2b示出了根据本公开实施例的像素驱动电路的电路图；
图3示出了对根据本公开实施例的像素驱动电路在工艺制程变化量容许范围内的节点电压保持能力的示意图；
图4示出了根据本公开实施例的像素驱动电路的驱动方法的流程图；
图5a和图5b示出了根据本公开实施例的像素驱动电路的驱动方法的信号时序图；以及
图6示出了根据本公开实施例的显示面板的示意性框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其他组件电连接。此外，这两个组件可以通过有线或无线方式电连接或耦接。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据在电路中的作用，本公开实施例使用的晶体管主要为开关晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。在一些实施例中，“第一电平”可以是高电平，“第二电平”可以是低电平。下文中，由于驱动晶体管被示例为P型薄膜晶体管，因此“第一电平”被示例 为高电平，“第二电平”被示例为低电平。
OLED显示技术被广泛用于便携式或手持式设备，因此降低OLED显示屏的功耗就显得至关重要。为了降低OLED显示屏的功耗，在利用OLED显示屏显示静态画面时，可以适当降低显示的频率，即对于静态画面，可以进行降频显示。降频显示意味着需要延长OLED驱动电路每次刷新的时间间隔，这对于对电压保持能力要求较高的节点来说非常不利，特别是对于与流过OLED的电流的产生密切相关的驱动晶体管栅极的电压。
以下参考附图对本公开的实施例进行具体描述。
图1示出了根据本公开实施例的像素驱动电路10的示意性框图。像素驱动电路10被配置为驱动发光元件发光。在图1中，发光元件被例示为OLED的形式，但这仅为示例，发光元件也可以是其他电流驱动型器件，本公开实施例不限于此。为了更加清楚的表明像素驱动电路10与发光元件OLED之间的连接关系，以虚线的形式示出了发光元件OLED。如图1所示，发光元件OLED的第一端与像素驱动电路10电连接，第二端与固定电压VSS电连接。第一端可以是发光元件OLED的阳极，第二端可以是发光元件OLED的阴极。
如图1所示，像素驱动电路10包括驱动子电路11，驱动子电路11被配置为产生用于使发光元件OLED发光的电流。
如图1所示，像素驱动电路10还包括发光控制子电路12，发光控制子电路12与驱动子电路11电连接于第二节点N2，发光控制子电路12同时与发光元件OLED的第一端电连接于第三节点。根据实施例，发光控制子电路12被配置为接收发光控制信号CON1，并在发光控制信号CON1的控制下，将用于使发光元件OLED发光的电流提供到发光元件OLED的第一端。
如图1所示，像素驱动电路10还包括驱动控制子电路13，驱动控制子电路13与驱动子电路11电连接于第二节点N2。根据实施例，驱动控制子电路13被配置为接收数据信号Vdata和栅极驱动信号CON2，并在栅极驱动信号CON2的控制下，将数据信号Vdata提供到驱动子电路11。
如图1所示，像素驱动电路10还包括复位子电路14，复位子电路14电连接到驱动子电路11和发光元件OLED的第一端。如图1所示，复位子电路14与驱动子电路11电连接于第一节点N1。根据实施例，复位子电路14被配置为接收第一复位信号 CON3、第二复位信号CON4和复位参考信号Vref，并在第一复位信号CON3和所述第二复位信号CON4的控制下，利用复位参考信号Vref对第一节点N1和发光元件OLED的第一端进行复位。
如图1所示，像素驱动电路10还包括补偿子电路15，补偿子电路15与驱动子电路11电连接于第一节点N1。根据实施例，补偿子电路15被配置为对第一节点N1的电压进行补偿。
图2a和图2b根据本公开实施例的像素驱动电路20的电路图。
如图2a所示，驱动子电路21包括驱动晶体管Td、第二晶体管T2和存储电容Cst。根据实施例，驱动晶体管Td的栅极电连接第一节点N1，驱动晶体管Td的第一极与发光控制子电路22电连接于第二节点N2，驱动晶体管Td的第二极与发光控制子电路22电连接于第三节点N3。第二晶体管T2的栅极电连接为接收栅极驱动信号CON2，第二晶体管T2的第一极电连接第一节点N1，第二晶体管T2的第二极电连接第三节点N3。存储电容Cst的第一端电连接为接收第一电压信号VDD，第二端电连接第一节点N1。
如图2a所示，发光控制子电路22包括第四晶体管T4第五晶体管T5。根据实施例，第四晶体管T4的栅极电连接为接收发光控制信号CON1，第四晶体管T4的第一极电连接为接收第一电压信号VDD，第四晶体管T4的第二极电连接第二节点N2。第五晶体管T5的栅极电连接为接收发光控制信号CON1，第五晶体管T5的第一极电连接第三节点N3，第五晶体管T5的第二极电连接发光元件OLED的第一端。
在示例性实施例中，第四晶体管T4和第五晶体管T5可以均为P型晶体管或均为N型晶体管。
如图2a所示，驱动控制子电路23包括第三晶体管T3。根据实施例，第三晶体管T3的栅极电连接为接收栅极驱动信号CON1，第三晶体管T3的第一极电连接为接收数据信号Vdata，第三晶体管T3的第二极电连接第二节点N2。
如图2a所示，复位子电路24包括第六晶体管T6和第七晶体管T7。根据实施例，第六晶体管T6的栅极电连接为接收第一复位信号CON3，第六晶体管T6的第一极电连接第一节点N1，第六晶体管T6的第二极电连接为接收复位参考信号Vref。第七晶体管T7的栅极电连接为接收第二复位信号CON4，第七晶体管T7的第一极电连接为接收复位参考信号Vref，第七晶体管T7的第二极电连接到发光元件OLED的第一端。
在示例性实施例中，第六晶体管T6和第七晶体管T7可以均为P型晶体管或均为N 型晶体管。
如图2a所示，驱动晶体管Td为P型晶体管，驱动晶体管Td的栅极(即第一节点N1)电连接第二晶体管T2的第一极和第六晶体管T6的第一极。在包含该像素驱动电路的像素单元的保持阶段，第二晶体管T2和第六晶体管T6均处于关断状态，由于LTPS工艺制成的晶体管具有较大的漏电流，因此将会有电流流出第一节点N1，流出第一节点N1的电流如图2a中带箭头的虚线1和2所指示，箭头的虚线1表示第二晶体管T2的漏电流I off2从第一节点N1(第二晶体管T2的第一极)经由第二晶体管T2流向第二晶体管T2的第二极，箭头的虚线2表示第六晶体管T6的漏电流I off6从第一节点N1(第六晶体管T6的第一极)经由第六晶体管T6流向第六晶体管T6的第二极。这将导致驱动晶体管Td的栅极电压的改变，从而影响流经发光元件OLED的电流，使显示的画面画质降低。
根据本公开的实施例，在像素驱动电路20中设置补偿子电路25，以对第一节点N1的电压进行补偿，从而维持第一节点N1的电压的稳定。
如图2a所示，补偿子电路25包括第一晶体管T1，第一晶体管T1的栅极电连接为接收补偿控制信号CON5，第一晶体管T1的第一极电连接为接收第一电压信号VDD，第一晶体管T1的第二极电连接第一节点N1。根据实施例，可以提供具有第一电平的补偿控制信号CON5，并且使第一晶体管T1在具有第一电平的补偿控制信号CON5的控制下处于关断状态。这样，处于关断状态的第一晶体管T1的漏电流I off1可以从第一晶体管T1的第一极向第二极流动，即有漏电流I off1从第一电压VDD经由第一晶体管T1流入第一节点N1，如图2a中带箭头的虚线3所示。流入第一节点N1的漏电流I off1可以对流出第一节点N1的漏电流I off2和漏电流I off6进行补充，从而保持第一节点N1的电压的稳定。
在一些其他的实施例中，可以利用第二复位信号来充当补偿控制信号，由此可以节约信号线，从而节约布局空间。如图2b所示，补偿子电路25包括第一晶体管T1，第一晶体管T1的栅极电连接为接收补偿控制信号，即第二复位信号CON4，第一晶体管T1的第一极电连接为接收第一电压信号VDD，第一晶体管T1的第二极电连接第一节点N1。根据实施例，可以提供具有第一电平的第二复位信号CON4，并且使第一晶体管T1在具有第一电平的第二复位信号CON4的控制下处于关断状态。这样，处于关断状态的第一晶体管T1的漏电流I off1可以从第一晶体管T1的第一极向第二极流动，即有漏 电流I off1从第一电压VDD经由第一晶体管T1流入第一节点N1，如图2b中带箭头的虚线3所示。流入第一节点N1的漏电流I off1可以对流出第一节点N1的漏电流I off2和漏电流I off6进行补充，从而保持第一节点N1的电压的稳定。
由于第一晶体管T1需要始终保持在关断状态，因此对于P型的第一晶体管T1，第二复位信号CON4始终为第一电平，则第七晶体管T7也始终保持在关断状态。处于关断状态的第七晶体管T7将黑画面显示状态下流过OLED的漏电流分流，以便更好地进行黑画面的显示。
根据实施例，可以通过调整第一晶体管T1、第二晶体管T2和第六晶体管T6的沟道宽长比来调节漏电流I off1、I off2和I off6的大小，从而得到满足要求的电压保持能力。
根据实施例，第一节点N1的电压保持能力随第二晶体管T2和第六晶体管T6的沟道宽长比的增加而减小，并随第一晶体管T1的沟道宽长比的增加而增加。因此，适当增加第一晶体管T1的沟道宽长比，或者适当减小第二晶体管T2的沟道宽长比，或者适当减小第六晶体管T6的沟道宽长比可以增加第一节点N1的电压保持能力。容易理解，同时适当增加第一晶体管T1的沟道宽长比，并适当减小第二晶体管T2和第六晶体管T6的沟道宽长比，或者使其中任意两个晶体管满足对应的条件均可以增加第一节点N1的电压保持能力。
本领域技术人员可以理解，晶体管的漏电流与晶体管的沟道宽长比以及晶体管在关断状态时施加在晶体管的源极和漏极的电压有关。如图2a和图2b所示，第二晶体管T2和第六晶体管T6的沟道宽长比越大，随着施加在第二晶体管T2和第六晶体管T6的源极和漏极的电压增大，则由第二晶体管T2和第六晶体管T6产生的流出第一节点N1的漏电流越大。反之，第二晶体管T2和第六晶体管T6的沟道宽长比越小，施加在第二晶体管T2和第六晶体管T6的源极和漏极的电压越小，则由第二晶体管T2和第六晶体管T6产生的流出第一节点N1的漏电流越小。根据实施例，当第二晶体管T2和第六晶体管T6的沟道宽长比均小于或等于2/3.5时，可以在第一节点N1处获得较好的电压保持能力。同样地，如图2a和图2b所示，第一晶体管T1的沟道宽长比越大，施加在第一晶体管T1的源极和漏极的电压越大，则由第一晶体管T1产生的流入第一节点N1的漏电流越大。反之，第一晶体管T1的沟道宽长比越小，施加在第一晶体管T1的源极和漏极的电压越小，则由第一晶体管T1产生的流入第一节点N1的漏电流越小。根据实施例，当第一晶体管T1的沟道宽长比大于或等于10/3.5时，可以在第一节点N1处获得 较好的电压保持能力。例如，当第一晶体管T1的沟道宽长比为10/3.5，，且第二晶体管T2和第六晶体管T6的沟道宽长比均为2/3.5时，分别在30Hz的频率和60Hz的频率下对第一节点N1处的电压进行记录，在30Hz时，在从当前OLED达到稳定发光到当前OLED下一次重新驱动进行发光的时段内，第一节点N1的电压的变化量为3.86％，在60Hz时，第一节点N1的电压的变化量仅为2.07％。两种情况下，均远远小于不增加第一晶体管T1时的电压的变化量8.6％。
此外，在图2a和图2b中，第一晶体管T1被例示为P型晶体管，这是因为对于LTPS工艺，P型晶体管具有比N型晶体管更大的漏电流，第一晶体管T1的漏电流越大，越有利于向第一节点N1注入更多的电流，即对第一节点N1的电压保持能力的调节作用越大。在图2a和图2b中，第二晶体管T2和第六晶体管T6也被示出为P型晶体管。在其他实施例中，第二晶体管T2和第六晶体管T6也可以是N型晶体管，第二晶体管T2和第六晶体管T6从第一节点N1导出的电流越少，则需要第一晶体管T1注入第一节点N1的电流就越少。本领域技术人员能够根据本公开实施例的构思和期望的调节效果对第一晶体管T1、第二晶体管T2和第六晶体管T6的类型进行选择。
当第一晶体管T1为P型晶体管时，如图2a所示，可以将补偿控制信号CON5维持为高电平，从而使第一晶体管T1始终保持在关断状态。或者如图2b所示，可以将补偿控制信号CON4维持为高电平，从而使第一晶体管T1和第七晶体管T7始终保持在关断状态。
根据本公开的实施例，能够提高驱动晶体管栅极电压的保持能力，从而稳定流经发光元件OLED的电流，避免在低频显示时画面出现闪烁现象，改进显示效果。
根据本公开的实施例，能够提供工艺制程变化量的更大容许范围,从而使工艺制程窗口变宽。工艺制成窗口变宽有助于提高生产的成品率，并降低生产成本。
图3示出了对根据本公开实施例的像素驱动电路在工艺制程变化量容许范围内的节点电压保持能力的示意图。基于如下工艺参数：第一晶体管T1的沟道宽长比为(10±1)/3.5，第二晶体管T2和第六晶体管T6的沟道宽长比为(2±1)/3.5，即第一晶体管T1、第二晶体管T2和第六晶体管T6的宽长比均具有±1的变化量，这为晶体管的工艺制程提供了较宽松的窗口。本领域技术人员可以理解，第二晶体管T2和第六晶体管T6的沟道宽长比可以相同也可以不同，只需要T2和T6中的至少一个大致位于晶体管的沟道宽长比小于或等于2/3.5的范围内即可。
如图3所示，图3所示图表的横坐标为第一节点N1的电压的变化量(％)，纵坐标为工艺参数比例(％)。从该图表中可以看出，第一节点N1的电压变化范围在60Hz时大致为-15.12％～10.46％，在30Hz时大致为-27.5％～18.02％。对在沟道宽长比变化量为±1的条件下第一节点N1的电压变化范围进行统计，第一节点N1的电压变化量优于2.07％的电压值占所有第一节点N1电压变化的电压值的比例接近50％，第一节点N1的电压变化量优于8.6％的电压值占所有第一节点N1电压变化的电压值的比例大于90％。
图4示出了根据本公开实施例的像素驱动电路的驱动方法400的流程图，图5a示出了根据本公开实施例的像素驱动电路的驱动方法400的信号时序图，下面结合图2a和图2b、图4和图5a和图5b说明根据本公开实施例的像素驱动电路的驱动方法。
如图4所示，像素驱动电路的驱动方法400包括如下步骤。
在步骤S410中，在第一时段，提供具有第一电平的发光控制信号、栅极驱动信号，提供具有第二电平的第一复位信号、第二复位信号。
在步骤S420中，在第二时段，提供具有第一电平的发光控制信号、第一复位信号和第二复位信号，提供具有第二电平的栅极驱动信号。
在步骤S430中，在第三时段，提供具有第一电平的第一复位信号、第二复位信号和栅极驱动信号，提供具有第二电平的发光控制信号。
如图5a所示，在第一时段t1期间，提供具有第一电平(即高电平VH)的发光控制信号CON1和栅极驱动信号CON2，并提供具有第二电平(即低电平VL)的第一复位信号CON3和第二复位信号CON4。
由此，在第一阶段t1期间，在发光控制信号CON1的控制下，第四晶体管T4和第五晶体管T5关断。在栅极驱动信号CON2的控制下，第二晶体管T2和第三晶体管T3关断。在第一复位信号CON3的控制下，第六晶体管T6导通，并且在第六晶体管T6导通的情况下，复位参考信号Vref传输到第一节点N1。在第二复位信号CON4的控制下，第七晶体管T7导通，并且在第七晶体管T7导通的情况下，复位参考信号Vref传输到发光元件150的第一端。
根据实施例，复位参考信号Vref可以为第二电平(即低电平VL)，因此，复位参考信号Vref可以使驱动晶体管Td的栅极变为低电平，这将使得驱动晶体管Td导通。并且，发光元件150的阳极也变为低电平。从而驱动晶体管Td和发光元件150的阳极均被低电平复位。
如图5a所示，在第二时段t2期间，提供具有第一电平(即高电平VH)的发光控制信号CON1、第一复位信号CON3和第二复位信号CON4，并提供具有第二电平(即低电平VL)的栅极驱动信号CON2。
由此，在第二时段t2期间，在发光控制信号CON1的控制下，第四晶体管T4和第五晶体管T5关断。在第一复位信号CON3和第二复位信号CON4的控制下，第六晶体管T6和第七晶体管T7关断。在栅极驱动信号CON2的控制下，第二晶体管T2和第三晶体管T3导通。
如图2a所示，在第三晶体管T3导通的情况下，高电平的数据信号Vdata传输到第二节点N2。由于在t1时段中驱动晶体管Td处于导通状态，因此此时驱动晶体管Td仍处于导通状态，从而高电平的数据信号Vdata继续传输到第三节点N3。在第二晶体管T2导通的情况下，高电平的数据信号Vdata继续传输到第一节点N1，并对处于低电平的第一节点N1进行充电。随着第一节点N1的电压不断上升，驱动晶体管Td的栅源电压Vgs从初始的Vref-Vdata逐渐增加，直到Vgs＝Vth为止，其中Vth为驱动晶体管Td的阈值电压，对于P型驱动晶体管Td，阈值电压Vth为负值。此时，驱动晶体管Td不再导通，同时停止对第一节点N1进行充电。此时，第一节点N1处(即Td的栅极)的电压为Vg＝Vgs+Vs＝Vdata+Vth。数据信号Vdata已经写入第一节点N1。在一些实施例中，Vdata可以具有第一电平(即高电平VH)。
如图5a所示，在第三时段t3期间，提供具有第一电平(即高电平VH)的栅极驱动信号CON2、第一复位信号CON3和第二复位信号CON4，并提供具有第二电平(即低电平VL)的发光控制信号CON1。
由此，在第三时段t3期间，在发光控制信号CON1的控制下，第四晶体管T4和第五晶体管T5导通。在栅极驱动信号CON2的控制下，第二晶体管T2和第三晶体管T3关断。在第一复位信号CON3和第二复位信号CON4的控制下，第六晶体管T6和第七晶体管T7关断。
如图2a所示，在第四晶体管T4导通的情况下，第一电压信号VDD传输到第二节点N2，即驱动晶体管Td的源极电压Vs＝VDD。此时，由于电连接到第一及诶单N1处的第一晶体管T1、第二晶体管T2和第六晶体管T6均关断，因此第一节点N1处于浮置状态，其电压保持为Vdata+Vth，即驱动晶体管Td的栅极电压Vg＝Vdata+Vth，因此，Vgs＝Vdata+Vth-VDD，其小于驱动晶体管Td的阈值电压Vth，使得驱动晶体管Td导通。 在第五晶体管T5导通的情况下，驱动晶体管Td产生的驱动电流Id施加到发光元件OLED的阳极，并驱动发光元件OLED发光。流过发光元件OLED的驱动电流Id可以由下式表示：
Id＝K〃(Vgs-Vth) 2
＝K〃(Vdata+Vth-VDD-Vth) 2
＝K〃(VDD-Vdata) 2
其中，K为与驱动晶体管Td相关联的电流常数，与驱动晶体管Td的工艺参数和几何尺寸有关。由以上公式可知，用于驱动发光元件OLED进行发光的驱动电流Id与驱动晶体管Td的阈值电压Vth无关。
因此，根据本公开的实施例，还可以对驱动晶体管Td的阈值电压进行补偿，从而稳定流过发光元件OLED的电流，改善显示效果。
进一步如图2a和图2b所示，在当前行像素驱动电路实现了对发光元件OLED的驱动显示之后，将在其他行像素驱动电路对发光元件OLED进行驱动显示的过程中保持OLED的发光亮度，即保持流过OLED的电流不变。
根据本公开的实施例，在上述保持过程中，一方面，由于第二晶体管T2的漏电流I off2和第六晶体管T6的漏电流I off6分别从第一节点N1流出，将导致第一节点N1的电压降低。另一方面，由于第一晶体管T1的漏电流I off1流入第一节点N1，因此将使第一节点N1的电压升高。通过调整第一晶体管T1、第二晶体管T2和第六晶体管T6的沟道宽长比，可以基本维持第一节点N1的电压保持不变，从而保持流过OLED的电流不变。
另外，如果利用第二复位信号CON4充当补偿控制信号，则在第一时段t1、第二时段t2和第三时段t3中，始终提供具有第一电平的第二复位信号CON4，对应的时序图如图5b所示。
当始终提供具有第一电平的第二复位信号CON4时，第一晶体管T1和第七晶体管T7始终处于关断状态，由此，在第一时段t1中，仅经由导通的第六晶体管T6传输复位参考信号Vref，并对第一节点N1进行复位。而处于关断状态的第七晶体管T7将黑画面显示状态下流过OLED的漏电流分流，以便更好地进行黑画面的显示。其他操作可以参考前述第一时段t1、第二时段t2和第三时段t3中的操作，此处不再赘述。
根据本公开的实施例，还提供了一种显示面板，图6示出了根据本公开实施例的显示面板60的示意性框图。如图6所示，显示面板60可以包括多条扫描线SL和多条数 据线DL，多条数据线DL与多条扫描信号线SL纵横交叉设置。显示面板60还可以包括多个像素单元61，以矩阵的形式设置在每个扫描线SL和每个数据线DL的交叉处，并且与对应的扫描线SL和数据线DL电连接。多个像素单元61中的每个像素单元包括发光元件OLED和根据本公开实施例的像素驱动电路，像素驱动电路的结构例如根据图1所示的像素驱动电路10或图2a和图2b所示的像素驱动电路20。
在一些实施例中，像素驱动电路所接收的数据信号由像素单元61的对应数据线DL提供，像素驱动电路所接收的栅极驱动信号由像素单元61的对应扫描线SL提供。
根据本公开实施例的显示面板能够对驱动晶体管的阈值电压进行补偿，同时能够提高驱动晶体管栅极电压的保持能力，从而稳定流过发光元件OLED的电流，避免在低频显示时画面出现闪烁现象，改进显示效果。在静态画面显示时，通过降低频率进行显示，能够降低显示面板的功耗。
以上的详细描述通过使用示意图、流程图和/或示例，已经阐述了众多实施例。在这种示意图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种示意图、流程图或示例中的每一功能和/或操作可以通过各种结构、硬件、软件、固件或实质上它们的任意组合来单独和/或共同实现。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (17)

  1. 一种像素驱动电路，被配置为驱动发光元件发光，所示像素驱动电路包括：
    驱动子电路，被配置为产生用于使所述发光元件发光的电流；
    发光控制子电路，电连接到所述驱动子电路和所述发光元件的第一端，被配置为接收发光控制信号，并在所述发光控制信号的控制下，将用于使所述发光元件发光的电流提供到所述发光元件的第一端；
    驱动控制子电路，电连接到所述驱动子电路，被配置为接收数据信号和栅极驱动信号，并在所述栅极驱动信号的控制下，将所述数据信号提供到所述驱动子电路；
    复位子电路，电连接到所述驱动子电路和所述发光元件的第一端，并且与所述驱动子电路电连接于第一节点，被配置为接收第一复位信号和第二复位信号，并在所述第一复位信号和所述第二复位信号的控制下，对所述第一节点和所述发光元件的第一端进行复位；以及
    补偿子电路，电连接到所述第一节点，被配置为接收补偿控制信号，并在所述补偿控制信号的控制下，对所述第一节点的电压进行补偿。
  2. 根据权利要求1所述的像素驱动电路，其中，所述补偿子电路包括第一晶体管，所述第一晶体管的栅极电连接为接收所述补偿控制信号，所述第一晶体管的第一极电连接为接收第一电压信号，所述第一晶体管的第二极电连接所述第一节点。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第一晶体管为P型晶体管。
  4. 根据权利要求2或3所述的像素驱动电路，其中，所述补偿控制信号具有第一电平，所述第一晶体管在所述补偿控制信号的控制下处于关断状态。
  5. 根据权利要求2至4中任一项所述的像素驱动电路，其中，所述第一晶体管的沟道宽长比大于或等于10/3.5。
  6. 根据权利要求2至5中任一项所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管、第二晶体管和存储电容，其中
    所述驱动晶体管的栅极电连接所述第一节点，所述驱动晶体管的第一极与发光控制子电路电连接于第二节点，所述驱动晶体管的第二极与所述发光控制子电路电连接于第三节点；
    所述第二晶体管的栅极电连接为接收所述栅极驱动信号，所述第二晶体管的第一 极电连接所述第一节点，所述第二晶体管的第二极电连接所述第三节点；以及
    所述存储电容的第一端电连接为接收所述第一电压信号，第二端电连接所述第一节点。
  7. 根据权利要求6所述的像素驱动电路，其中，所述驱动晶体管为P型晶体管。
  8. 根据权利要求6或7所述的像素驱动电路，其中，所述第二晶体管的沟道宽长比小于或等于2/3.5。
  9. 根据权利要求2至8中任一项所述的像素驱动电路，其中，所述驱动控制子电路包括第三晶体管，所述第三晶体管的栅极电连接为接收所述栅极驱动信号，所述第三晶体管的第一极电连接为接收所述数据信号，所述第三晶体管的第二极与发光控制子电路电连接于第二节点。
  10. 根据权利要求2至9中任一项所述的像素驱动电路，所述发光控制子电路包括第四晶体管和第五晶体管，其中
    所述第四晶体管的栅极电连接为接收所述发光控制信号，所述第四晶体管的第一极电连接为接收第一电压信号，所述第四晶体管的第二极与发光控制子电路电连接于第二节点；
    所述第五晶体管的栅极电连接为接收所述发光控制信号，所述第五晶体管的第一极与发光控制子电路电连接于第三节点，所述第五晶体管的第二极电连接到所述发光元件的第一端。
  11. 根据权利要求2至10中任一项所述的像素驱动电路，其中，所述复位子电路包括第六晶体管和第七晶体管，其中
    所述第六晶体管的栅极电连接为接收所述第一复位信号，所述第六晶体管的第一极电连接所述第一节点，所述第六晶体管的第二极电连接为接收复位参考信号；
    所述第七晶体管的栅极电连接为接收所述第二复位信号，所述第七晶体管的第一极电连接为接收所述复位参考信号，所述第七晶体管的第二极电连接到所述发光元件的第一端。
  12. 根据权利要求2至10中任一项所述的像素驱动电路，其中，所述复位子电路包括第六晶体管和第七晶体管，其中
    所述第六晶体管的栅极电连接为接收所述第一复位信号，所述第六晶体管的第一极电连接所述第一节点，所述第六晶体管的第二极电连接为接收复位参考信号；
    所述第七晶体管的栅极电连接为接收所述第二复位信号，所述第七晶体管的第一极电连接为接收所述复位参考信号，所述第七晶体管的第二极电连接到所述发光元件的第一端；
    其中，利用所述第二复位信号充当所述补偿控制信号。
  13. 根据权利要求11或12所述的像素驱动电路，其中，所述第六晶体管的沟道宽长比小于或等于2/3.5。
  14. 一种显示面板，包括：
    多条扫描线；
    多条数据线，与所述多条扫描线交叉设置；以及
    多个像素单元，以矩阵的形式设置在每个数据线和每个扫描线交叉处，并与对应的数据线和扫描线电连接，每个像素单元包括发光元件和根据权利要求1-12中任一项所述的像素驱动电路，
    其中，所述像素驱动电路所接收的数据信号由所述像素单元的对应数据线提供，所述像素驱动电路所接收的栅极驱动信号由所述像素单元的对应扫描线提供。
  15. 一种对权利要求1所述的像素驱动电路进行驱动的方法，包括：
    在第一时段，提供具有第一电平的发光控制信号、栅极驱动信号，提供具有第二电平的第一复位信号、第二复位信号；
    在第二时段，提供具有第一电平的发光控制信号、第一复位信号和第二复位信号，提供具有第二电平的栅极驱动信号；
    在第三时段，提供具有第一电平的第一复位信号、第二复位信号和栅极驱动信号，提供具有第二电平的发光控制信号。
  16. 根据权利要求14所述的方法，其中，在所述第一时段、第二时段和第三时段中，始终提供具有第一电平的补偿控制信号。
  17. 根据权利要求14所述的方法，其中，如果利用所述第二复位信号充当所述补偿控制信号，则在所述第一时段、第二时段和第三时段中，始终提供具有第一电平的第二复位信号。
PCT/CN2020/082575 2020-03-31 2020-03-31 像素电路及其驱动方法以及显示面板 WO2021196020A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2020/082575 WO2021196020A1 (zh) 2020-03-31 2020-03-31 像素电路及其驱动方法以及显示面板
CN202080000449.1A CN113748454B (zh) 2020-03-31 2020-03-31 像素电路及其驱动方法以及显示面板
US17/259,983 US11410604B2 (en) 2020-03-31 2020-03-31 Pixel circuit and a method of driving the same and a display panel
DE112020005555.8T DE112020005555T5 (de) 2020-03-31 2020-03-31 Pixelschaltung und ein Verfahren zum Antreiben derselben sowie ein Anzeigepanel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/082575 WO2021196020A1 (zh) 2020-03-31 2020-03-31 像素电路及其驱动方法以及显示面板

Publications (1)

Publication Number Publication Date
WO2021196020A1 true WO2021196020A1 (zh) 2021-10-07

Family

ID=77926988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/082575 WO2021196020A1 (zh) 2020-03-31 2020-03-31 像素电路及其驱动方法以及显示面板

Country Status (4)

Country Link
US (1) US11410604B2 (zh)
CN (1) CN113748454B (zh)
DE (1) DE112020005555T5 (zh)
WO (1) WO2021196020A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023050791A (ja) * 2021-09-30 2023-04-11 セイコーエプソン株式会社 電気光学装置、電子機器および電気光学装置の駆動方法
CN115101004A (zh) * 2022-06-30 2022-09-23 厦门天马微电子有限公司 一种像素驱动电路及其驱动方法、发光面板、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106601191A (zh) * 2016-12-02 2017-04-26 武汉华星光电技术有限公司 Oled驱动电路及oled显示面板
CN110021273A (zh) * 2018-01-10 2019-07-16 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN110277060A (zh) * 2019-05-21 2019-09-24 合肥维信诺科技有限公司 一种像素电路和显示装置
WO2019186764A1 (ja) * 2018-03-28 2019-10-03 シャープ株式会社 表示装置およびその駆動方法
CN110634446A (zh) * 2018-06-20 2019-12-31 三星电子株式会社 像素和包括像素的有机发光显示设备
CN110660360A (zh) * 2019-10-12 2020-01-07 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010123619A2 (en) * 2009-04-24 2010-10-28 Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University Methods and system for on-chip decoder for array test
KR101560239B1 (ko) * 2010-11-18 2015-10-26 엘지디스플레이 주식회사 유기 발광 다이오드 표시장치와 그 구동방법
CN103295525B (zh) * 2013-05-31 2015-09-30 京东方科技集团股份有限公司 像素电路及其驱动方法、有机发光显示面板及显示装置
CN104409047B (zh) * 2014-12-18 2017-01-18 合肥鑫晟光电科技有限公司 像素驱动电路、像素驱动方法和显示装置
KR102665322B1 (ko) * 2016-06-24 2024-05-16 삼성디스플레이 주식회사 박막 트랜지스터 기판, 및 표시 장치
CN107316606B (zh) * 2017-07-31 2019-06-28 上海天马有机发光显示技术有限公司 一种像素电路、其驱动方法显示面板及显示装置
CN110751927B (zh) * 2019-10-31 2021-10-26 上海天马有机发光显示技术有限公司 像素驱动电路及其驱动方法、显示面板和显示装置
KR20210057629A (ko) * 2019-11-12 2021-05-21 엘지디스플레이 주식회사 화소 구동 회로를 포함한 전계발광 표시패널

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106601191A (zh) * 2016-12-02 2017-04-26 武汉华星光电技术有限公司 Oled驱动电路及oled显示面板
CN110021273A (zh) * 2018-01-10 2019-07-16 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
WO2019186764A1 (ja) * 2018-03-28 2019-10-03 シャープ株式会社 表示装置およびその駆動方法
CN110634446A (zh) * 2018-06-20 2019-12-31 三星电子株式会社 像素和包括像素的有机发光显示设备
CN110277060A (zh) * 2019-05-21 2019-09-24 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110660360A (zh) * 2019-10-12 2020-01-07 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板

Also Published As

Publication number Publication date
CN113748454A (zh) 2021-12-03
DE112020005555T5 (de) 2022-09-01
US11410604B2 (en) 2022-08-09
CN113748454B (zh) 2023-10-24
US20220051621A1 (en) 2022-02-17

Similar Documents

Publication Publication Date Title
CN113192460B (zh) 一种显示面板和显示装置
WO2018214419A1 (zh) 像素电路、像素驱动方法和显示装置
CN108847186B (zh) 像素电路及其驱动方法、显示面板及显示装置
WO2018188390A1 (zh) 像素电路及其驱动方法、显示装置
JP4477617B2 (ja) 有機発光ダイオード表示素子及びその駆動方法
WO2016045283A1 (zh) 像素驱动电路、方法、显示面板和显示装置
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
WO2017117938A1 (zh) 像素驱动电路、像素驱动方法和显示装置
CN111613180A (zh) Amoled像素补偿驱动电路、方法及显示面板
WO2016161896A1 (zh) 像素驱动电路、显示装置和像素驱动方法
CN111048044B (zh) 电压编程型amoled像素驱动电路及其驱动方法
CN110164378B (zh) Amoled像素电路及其驱动方法
KR100604057B1 (ko) 화소 및 이를 이용한 발광 표시장치
WO2020187158A1 (zh) 像素驱动电路和显示面板及其驱动方法、显示装置
KR20200121959A (ko) 표시 장치 및 그 구동 방법
WO2021196020A1 (zh) 像素电路及其驱动方法以及显示面板
CN112750392A (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
WO2023103038A1 (zh) 像素电路及显示面板
CN110164376A (zh) 一种有机发光显示装置的像素电路及其驱动方法
CN108470541B (zh) 像素电路及其驱动方法、显示面板及显示装置
JP2013033253A (ja) 表示システム
US11211005B2 (en) Pixel driving circuit, display device and driving method
WO2023011327A1 (zh) 像素驱动电路及其驱动方法、显示基板和显示装置
WO2023178778A1 (zh) 像素电路及背光模组、显示面板
WO2023044816A1 (zh) 一种像素电路及其驱动方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20929052

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20929052

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 15.05.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20929052

Country of ref document: EP

Kind code of ref document: A1