WO2023044816A1 - 一种像素电路及其驱动方法、显示装置 - Google Patents

一种像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2023044816A1
WO2023044816A1 PCT/CN2021/120479 CN2021120479W WO2023044816A1 WO 2023044816 A1 WO2023044816 A1 WO 2023044816A1 CN 2021120479 W CN2021120479 W CN 2021120479W WO 2023044816 A1 WO2023044816 A1 WO 2023044816A1
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Prior art keywords
transistor
control
node
circuit
signal
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PCT/CN2021/120479
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English (en)
French (fr)
Inventor
韩承佑
郑皓亮
刘冬妮
肖丽
陈亮
赵蛟
崔晓荣
玄明花
Original Assignee
京东方科技集团股份有限公司
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Priority to CN202180002662.0A priority Critical patent/CN116235238A/zh
Priority to PCT/CN2021/120479 priority patent/WO2023044816A1/zh
Publication of WO2023044816A1 publication Critical patent/WO2023044816A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present invention relates to the field of display technology, in particular to a pixel circuit, a driving method thereof, and a display device.
  • the brightness adjustment method of active display devices usually uses direct current (DC) dimming.
  • DC dimming when realizing low gray scale brightness, DC dimming has the problem of flickering and eye damage.
  • Embodiments of the present application provide a pixel circuit, a driving method thereof, and a display device.
  • an embodiment of the present application provides a pixel circuit, including: a current control circuit, a duration control circuit, and a light emitting element, wherein:
  • the current control circuit is configured to receive a data signal and a first scanning signal, and control the amplitude of the generated driving current according to the data signal and the first scanning signal;
  • the duration control circuit is used to receive the mode control signal, the pulse control signal, the light emission control signal and the driving current of the current control circuit, and the duration control circuit is configured to control the light emitting element according to the amplitude of the mode control signal The length of time that the drive current is supplied.
  • the duration control circuit includes: a duration selection subcircuit, a first duration control subcircuit, a second duration control subcircuit, and a lighting control circuit, wherein,
  • the duration selection sub-circuit is respectively connected to the first voltage terminal, the mode control signal terminal, the second scanning signal terminal, the third scanning signal terminal, the first node and the second node, and is used for the mode control signal, Under the control of the second scan signal output from the second scan signal terminal and the third scan signal output from the third scan signal terminal, write the mode control signal into the first node and the second node. node;
  • the first duration control sub-circuit is respectively connected to the first node, the third node and the pulse control signal terminal, and under the control of the signal of the first node, writes the pulse control signal of the pulse control signal terminal into to said third node;
  • the second duration control sub-circuit is respectively connected to the second node, the third node and the light-emitting control signal terminal, and is used for signal output at the second node when the mode control signal is in the second mode. Under the control of , write the light emission control signal of the light emission control signal terminal into the third node;
  • the light emission control circuit is respectively connected to the third node, the first voltage terminal, the light emission control signal terminal, the first scan signal terminal, and the current control circuit for receiving the driving current, And under the control of the signal of the third node, the light emission control signal output from the light emission control signal terminal, and the first scanning signal output from the first scanning signal terminal, control the driving current to flow through the light emitting element duration.
  • the duration selection subcircuit includes a first duration selection subcircuit and a second duration selection subcircuit, wherein,
  • the first duration selection sub-circuit is respectively connected to the first voltage terminal, the mode control signal terminal, the second scanning signal terminal and the first node, and is used for the mode control signal and the Writing the mode control signal into the first node under the control of the second scanning signal;
  • the second duration selection sub-circuit is respectively connected to the first voltage terminal, the mode control signal terminal, the third scan signal terminal and the second node, and is used for switching between the mode control signal and the Under the control of the third scan signal, the mode control signal is written into the second node.
  • the light emission control circuit is respectively connected to the current control circuit, the third node and the first voltage terminal, for receiving the driving current, and at the third node Under the control of the signal, the duration of the driving current flowing through the light emitting element is controlled.
  • the first duration control subcircuit includes a first transistor, wherein:
  • the control pole of the first transistor is connected to the first node, the first pole of the first transistor is connected to the pulse control signal terminal, and the second pole of the first transistor is connected to the third node .
  • the second duration control subcircuit includes a second transistor, wherein:
  • the control pole of the second transistor is connected to the second node, the first pole of the second transistor is connected to the light-emitting control signal terminal, and the second pole of the second transistor is connected to the third node .
  • the first duration selection subcircuit includes a first capacitor and a third transistor, wherein:
  • the control pole of the third transistor is connected to the second scanning signal terminal, the first pole of the third transistor is connected to the mode control signal terminal, and the second pole of the third transistor is connected to the first node connection; the first end of the first capacitor is connected to the first voltage end, and the second end of the first capacitor is connected to the first node.
  • the second duration selection subcircuit includes a second capacitor and a fourth transistor, wherein:
  • the control pole of the fourth transistor is connected to the third scanning signal terminal, the first pole of the fourth transistor is connected to the mode control signal terminal, and the second pole of the fourth transistor is connected to the second scanning signal terminal.
  • the nodes are connected; the first end of the second capacitor is connected to the first voltage end, and the second end of the second capacitor is connected to the second node.
  • the light emission control circuit includes a fifth transistor, wherein:
  • the control pole of the fifth transistor is connected to the third node, the first pole of the fifth transistor is connected to the current control circuit, and the second pole of the fifth transistor is connected to the first voltage terminal .
  • the current control circuit includes: a data writing circuit, a storage circuit and a driving circuit;
  • the data writing circuit is configured to write the data signal output by the data signal terminal into the fourth node under the control of the first scan signal;
  • the storage circuit is used to store the electric energy at the fourth node
  • the driving circuit is configured to generate a driving current under the control of the signal of the fourth node.
  • the data writing circuit includes an eighth transistor, the storage circuit includes a third capacitor, and the driving circuit includes a driving transistor, wherein:
  • the control electrode of the eighth transistor is connected to the first scanning signal end, the first electrode of the eighth transistor is connected to the display data signal end, and the second electrode of the eighth transistor is connected to the fourth node connection;
  • the first end of the third capacitor is connected to the fourth node, and the second end of the third capacitor is connected to the fifth node;
  • the control electrode of the driving transistor is connected to the fourth node, the first electrode of the driving transistor is connected to the light emitting element, and the second electrode of the driving transistor is connected to the fifth node.
  • the pixel circuit further includes an external compensation circuit for compensating the threshold voltage.
  • the external compensation circuit includes a sixth transistor, a seventh transistor, and a ninth transistor, the control electrode of the sixth transistor is connected to the light emission control signal terminal, and the sixth transistor of the sixth transistor One pole is connected to the current control circuit, the second pole of the sixth transistor is connected to the first pole of the seventh transistor; the control pole of the seventh transistor is connected to the first scanning signal terminal, so The second pole of the seventh transistor is connected to the first voltage terminal; the control pole of the ninth transistor is connected to the fourth scanning signal terminal, and the first pole of the ninth transistor is connected to the fifth node, The second pole of the ninth transistor is connected to the voltage output end.
  • the embodiment of the present application further provides a display device, including: the pixel circuit described in any one of the above items.
  • the embodiment of the present application also provides a pixel circuit driving method, which is used to drive the pixel circuit described in any one of the above first aspects, the pixel circuit has multiple scan periods, and in one scan period within, the drive method includes:
  • the duration control circuit receives the mode control signal, the pulse control signal, the light emission control signal and the driving current of the current control circuit, and controls the time length of providing the driving current to the light-emitting element according to the amplitude of the mode control signal.
  • the pixel circuit, its driving method, and the display device provided in the embodiments of the present application, by setting the amplitude of the data signal provided by the data signal terminal, enable the light-emitting element to work in a current path with a relatively large value, and ensure the uniformity of the light-emitting brightness of the light-emitting element High, high luminous efficiency and stable color coordinates, in the case of achieving high gray-scale brightness, the length of time for supplying driving current to the light-emitting element is the second duration; and in the case of achieving low gray-scale brightness, providing The duration of the driving current is the first duration, so that the high-amplitude driving current combined with the short light-emitting time can realize low grayscale brightness display, thereby improving the display effect of the display device under low grayscale.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in a related art provided by an embodiment of the present application
  • FIG. 2 is a timing diagram of a pixel circuit in the related art provided by the embodiment of the present application.
  • FIG. 3 is one of the structural schematic diagrams of the pixel circuit provided by the embodiment of the present application.
  • FIG. 4 is the second structural schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 5 is the third structural schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a data writing circuit provided by an embodiment of the present application.
  • FIG. 7 is the fifth structural schematic diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 8a is one of the equivalent circuit diagrams of the pixel circuit provided by the embodiment of the present application.
  • Fig. 8b is the second equivalent circuit diagram of the pixel circuit provided by the embodiment of the present application.
  • FIG. 9 is a schematic wiring diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 10 is a timing diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the operation of the pixel circuit in the T1 stage provided by the embodiment of the present application.
  • FIG. 12 is a working schematic diagram of the pixel circuit in the T2 stage provided by the embodiment of the present application.
  • FIG. 13 is one of the working schematic diagrams of the pixel circuit in the T3 stage provided by the embodiment of the present application.
  • FIG. 14 is the second working schematic diagram of the pixel circuit in the T3 stage provided by the embodiment of the present application.
  • FIG. 15 is a schematic diagram of the pixel circuit working in the compensation stage provided by the embodiment of the present application.
  • FIG. 16 is a timing diagram of the pixel circuit in the compensation stage provided by the embodiment of the present application.
  • FIG. 17 is a schematic flowchart of a driving method for a pixel circuit provided by an embodiment of the present application.
  • the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor used in the embodiment of the present application may be an oxide semiconductor transistor. Since the source and drain of the transistors used here are symmetrical, their source and drain can be interchanged. In this embodiment of the application, in order to distinguish the two poles of the transistor except the gate, one of the electrodes is called the first pole, and the other electrode is called the second pole. The first pole can be the source pole, and the second pole can be the drain.
  • Figure 1 it is a schematic structural diagram of a pixel circuit for providing signals to light-emitting diodes in the related art
  • Figure 2 is a timing diagram of the pixel circuit, which includes four transistors M5, M8, M9, Md and A capacitor C3, the circuit structure mainly relies on the voltage difference between the gate and source of the transistor Md to provide current signals of different amplitudes to the light-emitting diodes, and the light-emitting diodes can show different brightness under the control of current signals of different amplitudes
  • the micro-inorganic light-emitting diodes will have problems such as color coordinate drift, poor brightness uniformity, and luminous efficiency decline under small-amplitude current signals, which lead to the inability of the micro-inorganic light-emitting diodes to accurately or Stable rendering of low grayscale brightness.
  • the pixel circuit, its driving method, and the display device provided in the present application at least enable the light-emitting diodes to accurately display low-gray-scale brightness.
  • the pixel circuit, the driving method thereof, and the display device provided by the embodiments of the present application will be described in detail below.
  • FIG. 3 it is a schematic structural diagram of a pixel circuit according to the embodiment of the present application.
  • the pixel circuit provided by the embodiment of the present application includes: a current control circuit 301 , a duration control circuit 302 and a light emitting element 303 .
  • the current control circuit 301 is connected to the data signal terminal DI and the first scanning signal terminal GataA respectively, and is used to receive the data signal DI and the first scanning signal gataA. Under the action of the first scanning signal gataA, according to the amplitude of the data signal DI The value controls the magnitude of the drive current;
  • the duration control circuit 302 is respectively connected to the mode control signal terminal DT, the pulse control signal terminal Hf, and the luminescence control signal terminal EM_B, and is used to receive the mode control signal DT, the pulse control signal hf, the luminescence control signal em_b and the driving current of the current control circuit, According to the magnitude of the mode control signal DT, the time length for supplying the driving current to the light emitting element 303 is controlled.
  • the pixel circuit provided by the embodiment of the present application can control the time length of supplying the driving current to the light emitting element in each scanning period.
  • the pulse control signal hf provided by the pulse control signal terminal Hf includes a plurality of effective time periods in the light-emitting phase, and the effective time periods refer to the time periods that allow the light-emitting element to be in a current path state.
  • the effective pulse period included in the pulse control signal hf constitutes a first duration, and the duration of the lighting stage is a second duration, and the first duration is much shorter than the second duration.
  • the light-emitting element can work in a relatively large-amplitude current path, ensuring high uniformity of light output brightness, high luminous efficiency, and stable color coordinates of the light-emitting element.
  • the time length for supplying the driving current to the light-emitting element is the second time length
  • the time length for supplying the driving current to the light-emitting element is the first time length.
  • 256 gray scales as an example. For example, 80-255 gray scales are the range of high gray scale brightness.
  • the time length for supplying the driving current to the light-emitting element is the second time length.
  • the duration control circuit 302 provided in the embodiment of the present application includes: a duration selection subcircuit 3021 , a first duration control subcircuit 3022 , a second duration control subcircuit 3023 , a lighting control circuit 3024, wherein,
  • the duration selection sub-circuit 3021 is respectively connected to the first voltage terminal LVSS, the mode control signal terminal DT, the second scanning signal terminal GH, the third scanning signal terminal GE, the first node N1 and the second node N2, and is used for the mode control signal Write the mode control signal into the first node N1 and the second node N2 under the control of DT, the second scanning signal GH output from the second scanning signal terminal, and the third scanning signal GE output from the third scanning signal terminal;
  • the first duration control sub-circuit 3022 is respectively connected to the first node N1, the third node N3 and the pulse control signal terminal Hf, and is used to control the pulse control signal hf of the pulse control signal terminal Hf under the control of the signal of the first node N1 Write to the third node N3;
  • the second duration control sub-circuit 3023 is respectively connected to the second node N2, the third node N3 and the light emission control signal terminal EM_B, and is used to control the light emission control signal em_b of the light emission control signal terminal EM_B under the control of the signal of the second node N2 Write to the third node N3;
  • the light emission control circuit 3024 is respectively connected with the third node N3, the first voltage terminal LVSS, the light emission control signal terminal EM_B, the first scanning signal terminal GA, and the current control circuit, and is used to receive the driving current, and transmit the signal at the third node N3, Under the control of the light emission control signal em_b output from the light emission control signal terminal EM_B and the first scanning signal GA output from the first scanning signal terminal Gate_A, the duration of the driving current flowing through the light emitting element is controlled.
  • the duration selection subcircuit 3021 includes a first duration selection subcircuit 30211 and a second duration selection subcircuit 30212, wherein,
  • the first duration selection sub-circuit 30211 is respectively connected to the first voltage terminal LVSS, the mode control signal terminal DT, the second scanning signal terminal GH and the first node N1, and is used for controlling the mode control signal DT and the second scanning signal GH , write the mode control signal DT into the first node N1;
  • the second duration selection sub-circuit 30212 is respectively connected to the first voltage terminal LVSS, the mode control signal terminal DT, the third scanning signal terminal GE and the second node N2, and is used for controlling the mode control signal DT and the third scanning signal GE , write the mode control signal DT to the second node N2.
  • the first duration control subcircuit 3022 includes a first transistor M1
  • the second duration control subcircuit 3023 includes a second transistor M2
  • the first duration selection subcircuit 30211 includes a first The capacitor C1 and the third transistor M3
  • the second duration selection sub-circuit 30212 includes the second capacitor C2 and the fourth transistor M4
  • the light emission control circuit 3024 includes the fifth transistor M5.
  • control pole of the first transistor M1 is connected to the first node N1, the first pole of the first transistor M1 is connected to the pulse control signal terminal, and the second pole of the first transistor M1 is connected to the third node N3; the second transistor M2 The control pole of the second transistor M2 is connected to the second node N2, the first pole of the second transistor M2 is connected to the light-emitting control signal terminal, the second pole of the second transistor M2 is connected to the third node N3; the control pole of the third transistor M3 is connected to the second The scanning signal terminal is connected, the first pole of the third transistor M3 is connected to the mode control signal terminal, the second pole of the third transistor M3 is connected to the first node N1; the first terminal of the first capacitor C1 is connected to the first voltage terminal, The second end of the first capacitor C1 is connected to the first node N1; the control electrode of the fourth transistor M4 is connected to the third scanning signal end, the first electrode of the fourth transistor M4 is connected to the mode control signal end, and the
  • the current control circuit 301 may include: a data writing circuit 3011, a storage circuit 3012 and a driving circuit 3013;
  • a data writing circuit 3011 configured to write the data signal DI output from the data signal terminal DI into the fourth node N4 under the control of the first scan signal GA;
  • a storage circuit 3012 configured to store the electric energy at the fourth node N4;
  • the driving circuit 3013 is configured to generate a driving current under the control of the signal of the fourth node N4.
  • the data writing circuit 3011 may include an eighth transistor M8, the storage circuit 3012 may include a third capacitor C3, and the driving circuit 3013 may include a driving transistor Md.
  • the control electrode of the eighth transistor M8 is connected to the first The scan signal end is connected, the first pole of the eighth transistor M8 is connected to the data signal end, the second pole of the eighth transistor M8 is connected to the fourth node N4; the first end of the third capacitor C3 is connected to the fourth node N4, and the second pole of the eighth transistor M8 is connected to the fourth node N4.
  • the second end of the three capacitors C3 is connected to the fifth node N5; the control electrode of the driving transistor Md is connected to the fourth node N4, the first electrode of the driving transistor Md is connected to the light emitting element, and the second electrode of the driving transistor Md is connected to the fifth node N5 connection.
  • the pixel circuit provided in the embodiment of the present application may further include an external compensation circuit 304, and the external compensation circuit 304 is used to compensate the threshold voltage.
  • the external compensation circuit 304 may include a sixth transistor M6, a seventh transistor M7, and a ninth transistor M9.
  • the control electrode of the sixth transistor M6 is connected to the light-emitting control signal terminal, and the first electrode of the sixth transistor M6 is connected to the The current control circuit is connected, the second pole of the sixth transistor M6 is connected to the first pole of the seventh transistor M7; the control pole of the seventh transistor M7 is connected to the first scanning signal terminal, and the second pole of the seventh transistor M7 is connected to the first The voltage terminal is connected; the control electrode of the ninth transistor M9 is connected to the fourth scanning signal end, the first electrode of the ninth transistor M9 is connected to the fifth node N5, and the second electrode of the ninth transistor M9 is connected to the threshold voltage output terminal Rdout.
  • Figure 8a shows a data writing circuit 3011, a storage circuit 3012, a drive circuit 3013, an external compensation circuit 304, a first duration control subcircuit 3022, a second duration control subcircuit 3023, a first duration selection subcircuit 30211, a Exemplary structures of the two duration selection sub-circuit 30212 and the lighting control circuit 3024.
  • Those skilled in the art can easily understand that the implementation manners of the above circuits are not limited thereto, as long as their respective functions can be realized.
  • the control electrode of the third transistor M3 in the first duration selection sub-circuit 30211 and the control electrode of the fourth transistor M4 in the second duration selection sub-circuit 30212 can be connected to the same scanning Signal terminal GC, and the scanning signal terminal GC is a signal terminal different from the first scanning signal terminal GA or the fourth scanning signal terminal GB, and the effective level time of the scanning signal terminal GC is earlier than that of the first scanning signal terminal GA Active level time; in this case, the first pole of the third transistor M3 in the first time length selection sub-circuit 30211 and the first pole of the fourth transistor M4 in the second time length selection sub-circuit 30212 need to be connected to different data signal terminals That is, the first pole of the third transistor M3 in the first time length selection sub-circuit 30211 is connected to the first mode control signal terminal DT1, and the first pole of the fourth transistor M4 in the second time length selection sub-circuit 30212 is connected to the second mode control signal terminal DT2. Therefore, the first pole of the third transistor M3 in the first time length selection sub
  • the light emitting element can be a submillimeter light emitting diode (Mini LED), a micro light emitting diode (Micro LED), or an organic light emitting diode (OrganicLight Emitting Diode, OLED), a quantum dot light emitting diode (QLED) and other types of LEDs.
  • the structure of the light emitting element 303 needs to be designed and determined according to the actual application environment, which is not limited here. In the following description, the light emitting element 303 is taken as an example of a miniature light emitting diode.
  • the first transistor M1 to the ninth transistor M9 and the driving transistor Md may be N-type transistors or P-type transistors, and the embodiment of the present application uses N-type transistors as an example for illustration.
  • all the transistors in this embodiment of the present application may be N-type transistors, specifically, the material of the active layer of the transistor may be low temperature polysilicon or metal oxide.
  • the pulse control signal Hf output from the pulse control signal terminal Hf can be generated by an external integrated circuit (Integrated Circuit, IC).
  • IC Integrated Circuit
  • a plurality of pixel circuits when a plurality of pixel circuits are arranged in an array, it includes a plurality of first scanning signal lines GL1, a plurality of second scanning signal lines GL2, and a plurality of third scanning signal lines.
  • first scanning signal terminal GataA, the second scanning signal terminal GH, the third scanning signal terminal GE, and the fourth scanning signal terminal GB of each pixel circuit corresponding to a row of sub-pixels are respectively connected to multiple first scanning signal lines.
  • the mode control signal terminal DT and the data signal terminal DI of each pixel circuit corresponding to a column of sub-pixels , the threshold voltage output terminal Rdout are respectively coupled to a plurality of first data signal lines DL1, a plurality of second data signal lines DL2, and a plurality of compensation voltage control lines RL;
  • the light emission control signal line E1, the pulse control signal line E2, the first The voltage line LV1 and the second voltage line LV2 are common signal lines, respectively coupled to the light emission control signal terminal EM_B, the pulse control signal terminal Hf, the first voltage terminal LVSS, and the second voltage terminal LVDD corresponding to all pixel circuits.
  • Fig. 10 is a working timing diagram of the pixel circuit shown in Fig. 8a.
  • the technical solution of the embodiment of the present application is further described through the working process of the pixel circuit, as shown in Fig. 9, wherein the first voltage terminal LVSS continuously provides a low level For the signal lvss, the second voltage terminal LVDD continuously provides the high level signal lvdd.
  • the working process of the pixel circuit in each scan cycle includes:
  • the second scanning signal GH output by the second scanning signal terminal GH is a high-level signal
  • the third transistor M3 is turned on, and the mode control signal DT is written into the first node N1, charging the first capacitor C1;
  • the third scanning signal GE output from the third scanning signal terminal GE is a high-level signal
  • the fourth transistor M4 is turned on, and the mode control signal DT is written into the second node N2, charging the second capacitor C2;
  • the second scanning signal GH output from the second scanning signal terminal GH is a low-level signal
  • the third scanning signal GE output from the third scanning signal terminal GE is a low-level signal
  • the first scanning signal terminal GataA outputs
  • the first scanning signal GA is a high-level signal
  • the eighth transistor M8 is turned on, and the data signal DI provided by the data signal terminal DI is written and stored in the fourth node N4, that is, the gate of the driving transistor Md.
  • the first scanning signal GA output from the first scanning signal terminal GataA becomes a low-level signal
  • the seventh transistor M7 and the eighth transistor M8 are turned off
  • the fifth transistor M5 The potential controls the length of time that the driving current is supplied to the light emitting element.
  • the mode control signal DT in the T1 phase is a high-level signal DTH
  • the mode control signal DT in the T2 phase is a low-level signal DTL
  • the first capacitor C1 is a high-level signal.
  • the mode control signal DT in the T1 stage is a low-level signal DTL
  • the mode control signal in the T2 stage DT is a high-level signal DTH.
  • the first capacitor C1 is at a low level
  • the second capacitor C2 is at a high level
  • the second transistor M2 is turned on
  • the first transistor M1 is turned off
  • the control signal em_b is written into the third node N3 through the second transistor M2, that is, the control electrode of the fifth transistor M5, then in the light emitting stage, the light emitting element realizes high gray scale brightness.
  • the pulse control signal hf in the embodiment of the present application is a high-frequency pulse signal.
  • the frequency of the pulse control signal hf can take a value between 3000 Hz and 60000 Hz, for example, it can be 3000 Hz or 60000 Hz; the light emission control signal em_b The frequency can take a value between 60 Hz and 120 Hz, for example, it can be 60 Hz or 120 Hz.
  • the light-emitting element can work in a current path with a relatively large value, ensuring high uniformity of light output brightness, high luminous efficiency, and stable color coordinates of the light-emitting element.
  • the time length for supplying the driving current to the light-emitting element is the second time length; and in the case of realizing low gray-scale brightness, the time length for supplying the driving current to the light-emitting element is the first time length
  • the pixel circuit provided by the embodiment of the present application may not only include the aforementioned T1 phase, T2 phase, T3 phase and T4 phase, but also include a threshold voltage Vth reading phase during operation.
  • the threshold voltage output terminal Rdout can be connected to the reading circuit 40 to sample the threshold voltage Vth of the driving transistor Md, as shown in FIG. 15 ; specifically, the working timing diagram of the reading circuit 40 is shown in FIG.
  • the reading circuit 40 works during the Blanking (black screen) time between two adjacent scan cycles, and the Blanking (black screen) time is the time period when the light emission control signal em_b output from the light emission control signal terminal EM_B is at a low level , it can be understood that a Blanking (black picture) time and a scanning cycle constitute a frame, and the Blanking (black picture) time includes:
  • the first scanning signal GA provided by the first scanning signal terminal GA and the fourth scanning signal GB provided by the fourth scanning signal terminal GB are all high-level signals, and the eighth transistor M8 and the ninth transistor M9 are turned on , the switch Sw_ref is closed, the node N5 and the threshold voltage output terminal Rdout are set to 0V by the external power supply terminal, and the potential initialization is realized;
  • the first scanning signal GA provided by the first scanning signal terminal GA and the fourth scanning signal GB provided by the fourth scanning signal terminal GB are high-level signals
  • the pulse control signal hf provided by the pulse control signal end is a low-level signal
  • the eighth transistor M8 and the ninth transistor M9 are turned on
  • the switch Sw_ref is turned off
  • the fifth transistor M5 and the sixth transistor M6 are turned off
  • the second pole that is, the fifth node N5) is charged to (Vdata-Vth), and the potential of the fifth node N5 is transmitted to the threshold voltage output terminal Rdout through the ninth transistor M9;
  • the pulse control signal terminal Hf provides a low-level signal, so as to ensure accurate reading of the threshold voltage Vth of the driving transistor Md.
  • the pixel circuit can also adopt an internal compensation method to eliminate the influence of the threshold voltage Vth of the driving transistor Md on the magnitude of the driving current.
  • the driving transistor Md may be charged to the saturation region before the third stage T3 in the scan cycle, which is not limited here.
  • An embodiment of the present application further provides a display device, which includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes the pixel circuit described in any one of the foregoing embodiments.
  • the display device in the embodiments of the present disclosure may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present application also provides a pixel circuit driving method, which is used to drive the aforementioned pixel circuit.
  • the pixel circuit has multiple scanning periods. In one scanning period, as shown in the figure As shown in 17, the driving method includes steps S1700 to S1701.
  • Step S1700 the current control circuit receives the data signal and the first scanning signal, and controls the amplitude of the generated driving current according to the data signal and the first scanning signal;
  • Step S1701 the duration control circuit receives the mode control signal, the pulse control signal, the light emission control signal and the driving current of the current control circuit, and controls the time length of supplying the driving current to the light emitting element according to the amplitude of the mode control signal.
  • the light-emitting element can work in a relatively large-value current path, ensuring the light output brightness of the light-emitting element. High uniformity, high luminous efficiency, and stable color coordinates.
  • the length of time for supplying the driving current to the light-emitting element is the second duration;
  • the time length for the element to supply the driving current is the first time length, so that the high-amplitude driving current combined with the short light-emitting time can realize low-gray-scale brightness display, thereby improving the display effect of the display device under low-gray scale.

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Abstract

一种像素电路及其驱动方法、显示装置，该像素电路包括：电流控制电路（301）、时长控制电路（302）和发光元件（303）。电流控制电路（301），用于接收数据信号（DI）和第一扫描信号（gataA），根据数据信号（DI）和第一扫描信号（gataA）控制产生的驱动电流的幅值；时长控制电路（302），用于接收模式控制信号（DT）、脉冲控制信号（hf）、发光控制信号（em_b）和电流控制电路（301）的驱动电流，根据模式控制信号（DT）的幅值，控制向发光元件（303）提供驱动电流的时间长度。

Description

一种像素电路及其驱动方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
随着显示技术的发展，人们对显示装置的显示效果的要求越来越高。目前，主动式显示装置的亮度调节方式，通常使用直流(Direct Current，DC)调光，然而在实现低灰阶亮度时，DC调光存在频闪伤眼的问题。
发明内容
本申请实施例提供了一种像素电路及其驱动方法、显示装置。
第一方面，本申请实施例提供了一种像素电路，包括：电流控制电路、时长控制电路和发光元件，其中：
所述电流控制电路，用于接收数据信号和第一扫描信号，根据所述数据信号和所述第一扫描信号控制产生的驱动电流的幅值；
所述时长控制电路，用于接收模式控制信号、脉冲控制信号、发光控制信号和所述电流控制电路的驱动电流，所述时长控制电路被配置为根据模式控制信号的幅值，控制向发光元件提供所述驱动电流的时间长度。
在一些示例性实施例中，所述时长控制电路包括：时长选择子电路、第一时长控制子电路、第二时长控制子电路、发光控制电路，其中，
所述时长选择子电路分别与第一电压端、所述模式控制信号端、第二扫描信号端、第三扫描信号端、第一节点和第二节点连接，用于在所述模式控制信号、所述第二扫描信号端输出的第二扫描信号和所述第三扫描信号端输出的第三扫描信号的控制下，将所述模式控制信号写入到所述第一节点和所述第二节点；
所述第一时长控制子电路分别与所述第一节点、第三节点和脉冲控制信号端连接，在所述第一节点的信号的控制下，将所述脉冲控制信号端的脉冲控制信号写入到所述第三节点；
所述第二时长控制子电路分别与所述第二节点、所述第三节点和发光控制信号端连接，用于当所述模式控制信号为第二模式时，在所述第二节点的信号的控制下，将所述发光控制信号端的发光控制信号写入到所述第三节点；
所述发光控制电路分别与所述第三节点、所述第一电压端、所述发光控制信号端、所述第一扫描信号端、所述电流控制电路连接，用于接收所述驱动电流，并在所述第三节点的信号、所述发光控制信号端输出的发光控制信号、所述第一扫描信号端输出的第一扫描信号的控制下，控制所述驱动电流流过所述发光元件的时长。
在一些示例性实施例中，所述时长选择子电路包括第一时长选择子电路和第二时长选择子电路，其中，
所述第一时长选择子电路分别与所述第一电压端、所述模式控制信号端、所述第二扫描信号端和所述第一节点连接，用于在所述模式控制信号和所述第二扫描信号的控制下，将所述模式控制信号写入到所述第一节点；
所述第二时长选择子电路分别与所述第一电压端、所述模式控制信号端、所述第三扫描信号端和所述第二节点连接，用于在所述模式控制信号和所述第三扫描信号的控制下，将所述模式控制信号写入到所述第二节点。
在一些示例性实施例中，所述发光控制电路分别与所述电流控制电路、所述第三节点和所述第一电压端连接，用于接收所述驱动电流，并在所述第三节点的信号的控制下，控制所述驱动电流流过所述发光元件的时长。
在一些示例性实施例中，所述第一时长控制子电路包括第一晶体管，其中：
所述第一晶体管的控制极与所述第一节点连接，所述第一晶体管的第一极与所述脉冲控制信号端连接，所述第一晶体管的第二极与所述第三节点连接。
在一些示例性实施例中，所述第二时长控制子电路包括第二晶体管，其中：
所述第二晶体管的控制极与所述第二节点连接，所述第二晶体管的第一极与所述发光控制信号端连接，所述第二晶体管的第二极与所述第三节点连接。
在一些示例性实施例中，所述第一时长选择子电路包括第一电容和第三晶体管，其中：
所述第三晶体管的控制极与所述第二扫描信号端连接，所述第三晶体管的第一极与所述模式控制信号端连接，所述第三晶体管的第二极与所述第一节点连接；所述第一电容的第一端与所述第一电压端连接，所述第一电容的第二端与所述第一节点连接。
在一些示例性实施例中，所述第二时长选择子电路包括第二电容和第四晶体管，其中：
所述第四晶体管的控制极与所述第三扫描信号端连接，所述第四晶体管的第一极与所述模式控制信号端连接，所述第四晶体管的第二极与所述第二节点连接；所述第二电容的第一端与所述第一电压端连接，所述第二电容的第二端与所述第二节点连接。
在一些示例性实施例中，所述发光控制电路包括第五晶体管，其中：
所述第五晶体管的控制极与所述第三节点连接，所述第五晶体管的第一极与所述电流控制电路连接，所述第五晶体管的第二极与所述第一电压端连接。
在一些示例性实施例中，所述电流控制电路包括：数据写入电路、存储电路和驱动电路；
所述数据写入电路，用于在所述第一扫描信号的控制下，将所述数据信号端输出的数据信号写入到第四节点；
所述存储电路，用于存储所述第四节点处的电能；
所述驱动电路，用于在所述第四节点的信号的控制下，产生驱动电流。
在一些示例性实施例中，所述数据写入电路包括第八晶体管，所述存储电路包括第三电容，所述驱动电路包括驱动晶体管，其中：
所述第八晶体管的控制极与所述第一扫描信号端连接，所述第八晶体管的第一极与所述显示数据信号端连接，所述第八晶体管的第二极与所述第四节点连接；
所述第三电容的第一端与所述第四节点连接，所述第三电容的第二端与第五节点连接；
所述驱动晶体管的控制极与所述第四节点连接，所述驱动晶体管的第一极与所述发光元件连接，所述驱动晶体管的第二极与所述第五节点连接。
在一些示例性实施例中，像素电路还包括外部补偿电路，所述外部补偿电路用于对阈值电压进行补偿。
在一些示例性实施例中，所述外部补偿电路包括第六晶体管、第七晶体管和第九晶体管，所述第六晶体管的控制极与所述发光控制信号端连接，所述第六晶体管的第一极与所述电流控制电路连接，所述第六晶体管的第二极与所述第七晶体管的第一极连接；所述第七晶体管的控制极与所述第一扫描信号端连接，所述第七晶体管的第二极与所述第一电压端连接；所述第九晶体管的控制极与第四扫描信号端连接，所述第九晶体管的第一极与所述第五节点连接，所述第九晶体管的第二极与所述电压输出端连接。
第二方面，本申请实施例还提供了一种显示装置，包括：如上任一项所述的像素电路。
第三方面，本申请实施例还提供了一种像素电路的驱动方法，用于驱动如上第一方面中任一项所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，所述驱动方法包括：
接收数据信号和第一扫描信号，根据所述数据信号和所述第一扫描信号控制产生的驱动电流的幅值；
所述时长控制电路接收模式控制信号、脉冲控制信号、发光控制信号和电流控制电路的驱动电流，并根据模式控制信号的幅值，控制向发光元件提 供所述驱动电流的时间长度。
有益效果：
本申请实施例提供的像素电路及其驱动方法、显示装置，通过设置数据信号端提供的数据信号的幅值，使发光元件能够工作在较大幅值的电流通路中，保证发光元件出光亮度均一性高、发光效率高以及色坐标稳定，在实现高灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第二时长；而在实现低灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第一时长，这样高幅值的驱动电流配合较短的发光时间可以实现低灰阶亮度显示，从而可以提高显示装置在低灰阶下的显示效果。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本申请实施例提供的相关技术中像素电路的结构示意图；
图2为本申请实施例提供的相关技术中像素电路的时序图；
图3为本申请实施例提供的像素电路的结构示意图之一；
图4为本申请实施例提供的像素电路的结构示意图之二；
图5为本申请实施例提供的像素电路的结构示意图之三；
图6为本申请实施例提供的数据写入电路的结构示意图；
图7为本申请实施例提供的像素电路的结构示意图之五；
图8a为本申请实施例提供的像素电路的等效电路图之一；
图8b为本申请实施例提供的像素电路的等效电路图之二；
图9为本申请实施例提供的像素电路的布线示意图；
图10为本申请实施例提供的像素电路的时序图；
图11为本申请实施例提供的T1阶段的像素电路工作示意图；
图12为本申请实施例提供的T2阶段的像素电路工作示意图；
图13为本申请实施例提供的T3阶段的像素电路工作示意图之一；
图14为本申请实施例提供的T3阶段的像素电路工作示意图之二；
图15为本申请实施例提供的补偿阶段的像素电路工作示意图；
图16为本申请实施例提供的补偿阶段的像素电路时序图；
图17为本申请实施例提供的像素电路的驱动方法的流程示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
除非另外定义，本申请实施例公开使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本领域技术人员可以理解，本申请所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。优选地，本申请实施例中使用的薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极，第二极可以为漏极。
如图1所示为相关技术中的用于向发光二极管提供信号的像素电路的结构示意图，图2为该像素电路的时序图，该像素电路中包括4个晶体管M5、M8、M9、Md以及一个电容C3，该电路结构主要靠晶体管Md的栅极和源极的电压差来向发光二极管提供不同幅值的电流信号，发光二极管在不同幅值电流信号的控制下，能够表现出不同的亮度，然而，由于发光二极管本身的 光电特性，例如微型无机发光二极管在较小幅值电流信号下会出现色坐标漂移、亮度均一性差，和发光效率下降等问题，从而导致微型无机发光二极管无法准确或稳定地呈现低灰阶亮度。
本申请提供的像素电路及其驱动方法、显示装置，至少能够使得发光二极管准确表现低灰阶亮度。下面对本申请实施例提供的像素电路及其驱动方法、显示装置进行详细说明。
如图3所示，为本申请实施例的一种像素电路的结构示意图，图3中，本申请实施例提供的像素电路包括：电流控制电路301、时长控制电路302和发光元件303。
其中，电流控制电路301分别与数据信号端DI、第一扫描信号端GataA连接，用于接收数据信号DI和第一扫描信号gataA，在第一扫描信号gataA的作用下，根据数据信号DI的幅值控制驱动电流的幅值；
时长控制电路302分别与模式控制信号端DT、脉冲控制信号端Hf、发光控制信号端EM_B连接，用于接收模式控制信号DT、脉冲控制信号hf、发光控制信号em_b和电流控制电路的驱动电流，根据模式控制信号DT的幅值，控制向发光元件303提供驱动电流的时间长度。
本申请实施例提供的像素电路，可以在每次扫描周期内控制向发光元件提供驱动电流的时间长度。例如，脉冲控制信号端Hf提供的脉冲控制信号hf在发光阶段中包括多个有效时间段，有效时间段指的是能够让发光元件处在电流通路的状态的时间段。在发光阶段，脉冲控制信号hf所包括的有效脉冲时段构成第一时长，发光阶段的时长为第二时长，第一时长远小于第二时长。通过设置数据信号端DI提供的数据信号DI的幅值，使发光元件能够工作在较大幅值的电流通路中，保证发光元件出光亮度均一性高、发光效率高以及色坐标稳定，在实现高灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第二时长，而在实现低灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第一时长。以256个灰阶为例进行说明，例如80-255灰阶为高灰阶亮度的范围，那么在实现80-255灰阶时，向发光元件提供驱动电流 的时间长度即为第二时长，通过设置数据信号端DI提供不同的数据信号DI的幅值，实现对应的灰阶亮度；对于0-79灰阶的低灰阶的范围，向发光元件提供驱动电流的时间长度为第一时长，同时通过设置数据信号端DI提供不同的数据信号DI的幅值，实现对应的灰阶亮度。可以理解的是，实现高灰阶亮度和低灰阶亮度时，数据信号端DI提供的数据信号DI的幅值范围存在交叠，以保证发光元件的出光亮度均一性高、发光效率高以及色坐标稳定即可。
在一些示例性实施例中，如图4所示，本申请实施例提供的时长控制电路302包括：时长选择子电路3021、第一时长控制子电路3022、第二时长控制子电路3023、发光控制电路3024，其中，
时长选择子电路3021分别与第一电压端LVSS、模式控制信号端DT、第二扫描信号端GH、第三扫描信号端GE、第一节点N1和第二节点N2连接，用于在模式控制信号DT、第二扫描信号端输出的第二扫描信号GH和第三扫描信号端输出的第三扫描信号GE的控制下，将模式控制信号写入到第一节点N1和第二节点N2；
第一时长控制子电路3022分别与第一节点N1、第三节点N3和脉冲控制信号端Hf连接，用于在第一节点N1的信号的控制下，将脉冲控制信号端Hf的脉冲控制信号hf写入到第三节点N3；
第二时长控制子电路3023分别与第二节点N2、第三节点N3和发光控制信号端EM_B连接，用于在第二节点N2的信号的控制下，将发光控制信号端EM_B的发光控制信号em_b写入到第三节点N3；
发光控制电路3024分别与第三节点N3、第一电压端LVSS、发光控制信号端EM_B、第一扫描信号端GA、电流控制电路连接，用于接收驱动电流，并在第三节点N3的信号、发光控制信号端EM_B输出的发光控制信号em_b、第一扫描信号端Gate_A输出的第一扫描信号GA的控制下，控制驱动电流流过发光元件的时长。
在一些示例性实施例中，如图5所示，时长选择子电路3021包括第一时长选择子电路30211和第二时长选择子电路30212，其中，
第一时长选择子电路30211分别与第一电压端LVSS、模式控制信号端DT、第二扫描信号端GH和第一节点N1连接，用于在模式控制信号DT和第二扫描信号GH的控制下，将模式控制信号DT写入到第一节点N1；
第二时长选择子电路30212分别与第一电压端LVSS、模式控制信号端DT、第三扫描信号端GE和第二节点N2连接，用于在模式控制信号DT和第三扫描信号GE的控制下，将模式控制信号DT写入到第二节点N2。
在一些示例性实施例中，如图8a所示，第一时长控制子电路3022包括第一晶体管M1，第二时长控制子电路3023包括第二晶体管M2，第一时长选择子电路30211包括第一电容C1和第三晶体管M3，第二时长选择子电路30212包括第二电容C2和第四晶体管M4，发光控制电路3024包括第五晶体管M5。
其中，第一晶体管M1的控制极与第一节点N1连接，第一晶体管M1的第一极与脉冲控制信号端连接，第一晶体管M1的第二极与第三节点N3连接；第二晶体管M2的控制极与第二节点N2连接，第二晶体管M2的第一极与发光控制信号端连接，第二晶体管M2的第二极与第三节点N3连接；第三晶体管M3的控制极与第二扫描信号端连接，第三晶体管M3的第一极与模式控制信号端连接，第三晶体管M3的第二极与第一节点N1连接；第一电容C1的第一端与第一电压端连接，第一电容C1的第二端与第一节点N1连接；第四晶体管M4的控制极与第三扫描信号端连接，第四晶体管M4的第一极与模式控制信号端连接，第四晶体管M4的第二极与第二节点N2连接；第二电容C2的第一端与第一电压端连接，第二电容C2的第二端与第二节点N2连接；第五晶体管的控制极与第三节点N3连接，第五晶体管M5的第一极与电流控制电路连接，第五晶体管M5的第二极与第一电压端连接。
在一些示例性实施例中，如图6所示，电流控制电路301可以包括：数据写入电路3011、存储电路3012和驱动电路3013；
数据写入电路3011，用于在第一扫描信号GA的控制下，将数据信号端DI输出的数据信号DI写入到第四节点N4；
存储电路3012，用于存储第四节点N4处的电能；
驱动电路3013，用于在第四节点N4的信号的控制下，产生驱动电流。
如图8a所示，数据写入电路3011可以包括第八晶体管M8，存储电路3012可以包括第三电容C3，驱动电路3013可以包括驱动晶体管Md，具体的，第八晶体管M8的控制极与第一扫描信号端连接，第八晶体管M8的第一极与数据信号端连接，第八晶体管M8的第二极与第四节点N4连接；第三电容C3的第一端与第四节点N4连接，第三电容C3的第二端与第五节点N5连接；驱动晶体管Md的控制极与第四节点N4连接，驱动晶体管Md的第一极与发光元件连接，驱动晶体管Md的第二极与第五节点N5连接。
在一些示例性实施例中，如图7所示，本申请实施例提供的像素电路，还可以包括外部补偿电路304，外部补偿电路304用于对阈值电压进行补偿。
如图8a所示，外部补偿电路304可以包括第六晶体管M6、第七晶体管M7、第九晶体管M9，第六晶体管M6的控制极与发光控制信号端连接，第六晶体管M6的第一极与电流控制电路连接，第六晶体管M6的第二极与第七晶体管M7的第一极连接；第七晶体管M7的控制极与第一扫描信号端连接，第七晶体管M7的第二极与第一电压端连接；第九晶体管M9的控制极与第四扫描信号端连接，第九晶体管M9的第一极与第五节点N5连接，第九晶体管M9的第二极与阈值电压输出端Rdout连接。
图8a中示出了数据写入电路3011、存储电路3012、驱动电路3013、外部补偿电路304、第一时长控制子电路3022、第二时长控制子电路3023、第一时长选择子电路30211、第二时长选择子电路30212、发光控制电路3024的示例性结构。本领域技术人员容易理解的是，以上各电路的实现方式不限于此，只要能够实现其各自的功能即可。
在一些示例性实施例中，如图8b所示，第一时长选择子电路30211中第三晶体管M3的控制极和第二时长选择子电路30212中第四晶体管M4的控制极可以连接相同的扫描信号端GC，且该扫描信号端GC为异于第一扫描信号端GA或第四扫描信号端GB的信号端，且该扫描信号端GC的有效电平时间 早于第一扫描信号端GA的有效电平时间；在此情况下，第一时长选择子电路30211中第三晶体管M3的第一极和第二时长选择子电路30212中第四晶体管M4的第一极需要连接不同的数据信号端，即第一时长选择子电路30211中第三晶体管M3的第一极连接第一模式控制信号端DT1，第二时长选择子电路30212中第四晶体管M4的第一极连接第二模式控制信号端DT2。从而，可以在扫描信号端GC的有效电平时间内，向第一时长选择子电路30211、第二时长选择子电路30212同时写入对应的模式控制信号。
在一些示例性实施例中，发光元件可以为次毫米发光二极管(Mini LED)、微型发光二极管(Micro LED)，也可以为有机发光二极管(OrganicLight Emitting Diode，OLED)、量子点发光二极管(QLED)等其他类型的发光二极管。在实际应用中，发光元件303的结构需要根据实际应用环境来设计确定，在此不作限定。以下均以发光元件303为微型发光二极管为例进行说明。
在一些示例性实施例中，第一晶体管M1至第九晶体管M9、驱动晶体管Md可以为N型晶体管或P型晶体管，本申请实施例以N型晶体管为例进行说明。
在一些示例性实施例中，本申请实施例所有晶体管均可以为N型晶体管，具体的，晶体管的有源层材料可以为低温多晶硅或者金属氧化物。
在一些示例性实施例中，脉冲控制信号端Hf输出的脉冲控制信号Hf可以由外部集成电路(Integrated Circuit，IC)产生。
在一些示例性实施例中，如图9所示，当多个像素电路阵列排布时，包括多条第一扫描信号线GL1、多条第二扫描信号线GL2、多条第三扫描信号线GL3、多条第四扫描信号线GL4、多条第一数据信号线DL1、多条第二数据信号线DL2、多条补偿电压控制线RL以及一条发光控制信号线E1、一条脉冲控制信号线E2、一条第一电压线LV1、一条第二电压线LV2。
可以理解的是，一行子像素对应的各像素电路的第一扫描信号端GataA、第二扫描信号端GH、第三扫描信号端GE、第四扫描信号端GB分别与多条第一扫描信号线GL1、多条第二扫描信号线GL2、多条第三扫描信号线GL3、 多条第四扫描信号线GL4耦接；一列子像素对应的各像素电路的模式控制信号端DT、数据信号端DI、阈值电压输出端Rdout分别与多条第一数据信号线DL1、多条第二数据信号线DL2、多条补偿电压控制线RL耦接；发光控制信号线E1、脉冲控制信号线E2、第一电压线LV1、第二电压线LV2为共用信号线，分别与全部像素电路对应的发光控制信号端EM_B、脉冲控制信号端Hf、第一电压端LVSS、第二电压端LVDD耦接。
图10为图8a所示的像素电路的工作时序图，下面通过像素电路的工作过程进一步说明本申请实施例的技术方案，如图9所示，其中，第一电压端LVSS持续提供低电平信号lvss，第二电压端LVDD持续提供高电平信号lvdd。像素电路在每次扫描周期内的工作过程包括：
第一阶段T1，如图11所示，第二扫描信号端GH输出的第二扫描信号GH为高电平信号，第三晶体管M3导通，将模式控制信号DT写入到第一节点N1，第一电容C1进行充电；
第二阶段T2，如图12所示，第三扫描信号端GE输出的第三扫描信号GE为高电平信号，第四晶体管M4导通，将模式控制信号DT写入到第二节点N2，第二电容C2进行充电；
第三阶段T3，第二扫描信号端GH输出的第二扫描信号GH为低电平信号，第三扫描信号端GE输出的第三扫描信号GE为低电平信号，第一扫描信号端GataA输出的第一扫描信号GA为高电平信号，第八晶体管M8开启，数据信号端DI提供的数据信号DI写入并存储到第四节点N4，即驱动晶体管Md的栅极。
第四阶段T4，即发光阶段，第一扫描信号端GataA输出的第一扫描信号GA变为低电平信号，第七晶体管M7和第八晶体管M8关闭，第五晶体管M5根据第三节点N3的电位，控制向发光元件提供所述驱动电流的时间长度。在一些实施例中，如图13所示，若T1阶段中模式控制信号DT为高电平信号DTH，T2阶段中模式控制信号DT为低电平信DTL，此时，第一电容C1为高电平，第二电容C2为低电平，第二晶体管M2关闭，第一晶体管M1导 通，脉冲控制端Hf输出的脉冲控制信号hf经过第一晶体管M1写入第三节点N3，即第五晶体管M5的控制极，则在发光阶段，发光元件实现高灰阶亮度；在另一些实施例中，如图14所示，T1阶段中模式控制信号DT为低电平信DTL，T2阶段中模式控制信号DT为高电平信号DTH，此时，第一电容C1为低电平，第二电容C2为高电平，第二晶体管M2导通，第一晶体管M1关闭，发光控制信号端EM_B输出的发光控制信号em_b经过第二晶体管M2写入第三节点N3，即第五晶体管M5的控制极，则在发光阶段，发光元件实现高灰阶亮度。
示例性地，本申请实施例中的脉冲控制信号hf为高频脉冲信号，例如，脉冲控制信号hf的频率可以在3000Hz～60000Hz之间取值，例如可以为3000Hz或者60000Hz；发光控制信号em_b的频率可以在60Hz～120Hz之间取值，例如可以为60Hz或者120Hz。
综合以上步骤，通过设置数据信号端DI提供的数据信号DI的幅值，使发光元件能够工作在较大幅值的电流通路中，保证发光元件出光亮度均一性高、发光效率高以及色坐标稳定，在实现高灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第二时长；而在实现低灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第一时长，这样高幅值的驱动电流配合较短的发光时间可以实现低灰阶亮度显示，从而可以提高显示装置在低灰阶下的显示效果。
在一些实施例中，本申请实施例提供的像素电路，在工作时，除了包括前述T1阶段、T2阶段、T3阶段和T4阶段以外，还可以包括阈值电压Vth读取阶段。例如，可以将阈值电压输出端Rdout与读取电路40连接，对驱动晶体管Md的阈值电压Vth进行采样，如图15所示；具体地，读取电路40的工作时序图如图16所示，读取电路40是在相邻两次扫描周期之间的Blanking(黑画面)时间内工作的，Blanking(黑画面)时间为发光控制信号端EM_B输出的发光控制信号em_b为低电平的时间段，可以理解的是，一个Blanking(黑画面)时间和一次扫描周期构成一帧，其中在Blanking(黑画面) 时间内，包括：
初始化阶段(Initial)，第一扫描信号端GA提供的第一扫描信号GA、第四扫描信号端GB提供的第四扫描信号GB均为高电平信号，第八晶体管M8和第九晶体管M9打开，开关Sw_ref闭合，节点N5与阈值电压输出端Rdout被外部电源端置为0V，实现电位初始化；
阈值电压输出阶段，第一扫描信号端GA提供的第一扫描信号GA、第四扫描信号端GB提供的第四扫描信号GB为高电平信号，而发光控制信号端EM_B提供的发光控制信号em_b、脉冲控制信号端提供的脉冲控制信号hf均为低电平信号，第八晶体管M8和第九晶体管M9打开，开关Sw_ref断开，第五晶体管M5和第六晶体管M6截止，对驱动晶体管Md的第二极(即第五节点N5)充电至(Vdata-Vth)，并通过第九晶体管M9将第五节点N5的电位传输至阈值电压输出端Rdout；
阈值电压读取采样阶段(Sampling)，Sw_samp闭合，将阈值电压输出端Rdout存储的电位(Vdata-Vth)传输到外部芯片，提取出Vth；从而，在Blanking(黑画面)时间之后的扫描周期中的第三阶段T3，可以将Vth补偿到数据信号端DI提供的数据信号DI中，从而使得驱动电流的幅值与驱动晶体管Md的阈值电压Vth无关，即避免驱动晶体管Md的阈值电压Vth影响提供给发光元件的驱动电流的幅值大小。
可以理解的是，在Blanking(黑画面)时间内，脉冲控制信号端Hf提供低电平信号，从而保证驱动晶体管Md的阈值电压Vth的准确读取。
在一些实施例中，像素电路还可以采用内部补偿的方式，消除驱动晶体管Md的阈值电压Vth对驱动电流幅值的影响。例如，可以在扫描周期中的第三阶段T3之前，将驱动晶体管Md充电至饱和区，在此不做限定。本申请实施例还提供了一种显示装置，该显示装置包括阵列排布的多个子像素，每个子像素包括前述任一实施例所述的像素电路。本公开实施例的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
基于相同的发明构思，本申请实施例还提供了一种像素电路的驱动方法，用于驱动如前所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，如图17所示，所述驱动方法包括步骤S1700至步骤S1701。
步骤S1700、电流控制电路接收数据信号和第一扫描信号，根据所述数据信号和所述第一扫描信号控制产生的驱动电流的幅值；
步骤S1701、时长控制电路接收模式控制信号、脉冲控制信号、发光控制信号和电流控制电路的驱动电流，并根据模式控制信号的幅值，控制向发光元件提供所述驱动电流的时间长度。
本申请实施例提供的像素电路及其驱动方法、显示装置，通过设置数据信号端DI提供的数据信号DI的幅值，使发光元件能够工作在较大幅值的电流通路中，保证发光元件出光亮度均一性高、发光效率高以及色坐标稳定，在实现高灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第二时长；而在实现低灰阶亮度的情况下，向发光元件提供驱动电流的时间长度即为第一时长，这样高幅值的驱动电流配合较短的发光时间可以实现低灰阶亮度显示，从而可以提高显示装置在低灰阶下的显示效果。
有以下几点需要说明：
本申请实施例附图只涉及本申请实施例涉及到的结构，其他结构可参考通常设计。
在不冲突的情况下，本申请的实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本申请所揭露的实施方式如上，但所述的内容仅为便于理解本申请而采用的实施方式，并非用以限定本申请。任何本申请所属领域内的技术人员，在不脱离本申请所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本申请的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种像素电路，其特征在于，包括：电流控制电路、时长控制电路和发光元件，其中：
    所述电流控制电路，用于接收数据信号和第一扫描信号，根据所述数据信号和所述第一扫描信号控制产生的驱动电流的幅值；
    所述时长控制电路，用于接收模式控制信号、脉冲控制信号、发光控制信号和所述电流控制电路的驱动电流，所述时长控制电路被配置为根据模式控制信号的幅值，控制向发光元件提供所述驱动电流的时间长度。
  2. 如权利要求1所述的像素电路，其特征在于，所述时长控制电路包括：时长选择子电路、第一时长控制子电路、第二时长控制子电路、发光控制电路，其中，
    所述时长选择子电路分别与第一电压端、所述模式控制信号端、第二扫描信号端、第三扫描信号端、第一节点和第二节点连接，用于在所述模式控制信号、所述第二扫描信号端输出的第二扫描信号和所述第三扫描信号端输出的第三扫描信号的控制下，将所述模式控制信号写入到所述第一节点和所述第二节点；
    所述第一时长控制子电路分别与所述第一节点、第三节点和脉冲控制信号端连接，用于在所述第一节点的信号的控制下，将所述脉冲控制信号端的脉冲控制信号写入到所述第三节点；
    所述第二时长控制子电路分别与所述第二节点、所述第三节点和发光控制信号端连接，用于在所述第二节点的信号的控制下，将所述发光控制信号端的发光控制信号写入到所述第三节点；
    所述发光控制电路分别与所述第三节点、所述第一电压端、所述电流控制电路连接，用于接收所述驱动电流，并在所述第三节点的信号、所述发光控制信号端输出的发光控制信号、所述第一扫描信号端输出的第一扫描信号的控制下，控制所述驱动电流流过所述发光元件的时长。
  3. 如权利要求2所述的像素电路，其特征在于，所述时长选择子电路包括第一时长选择子电路和第二时长选择子电路，其中，
    所述第一时长选择子电路分别与所述第一电压端、所述模式控制信号端、所述第二扫描信号端和所述第一节点连接，用于在所述模式控制信号和所述第二扫描信号的控制下，将所述模式控制信号写入到所述第一节点；
    所述第二时长选择子电路分别与所述第一电压端、所述模式控制信号端、所述第三扫描信号端和所述第二节点连接，用于在所述模式控制信号和所述第三扫描信号的控制下，将所述模式控制信号写入到所述第二节点。
  4. 如权利要求2所述的像素电路，其特征在于，所述发光控制电路分别与所述电流控制电路、所述第三节点和所述第一电压端连接，用于接收所述驱动电流，并在所述第三节点的信号的控制下，控制所述驱动电流流过所述发光元件的时长。
  5. 如权利要求2所述的像素电路，其特征在于，所述第一时长控制子电路包括第一晶体管，其中：
    所述第一晶体管的控制极与所述第一节点连接，所述第一晶体管的第一极与所述脉冲控制信号端连接，所述第一晶体管的第二极与所述第三节点连接。
  6. 如权利要求2或5所述的像素电路，其特征在于，所述第二时长控制子电路包括第二晶体管，其中：
    所述第二晶体管的控制极与所述第二节点连接，所述第二晶体管的第一极与所述发光控制信号端连接，所述第二晶体管的第二极与所述第三节点连接。
  7. 如权利要求3所述的像素电路，其特征在于，所述第一时长选择子电路包括第一电容和第三晶体管，其中：
    所述第三晶体管的控制极与所述第二扫描信号端连接，所述第三晶体管的第一极与所述模式控制信号端连接，所述第三晶体管的第二极与所述第一节点连接；所述第一电容的第一端与所述第一电压端连接，所述第一电容的 第二端与所述第一节点连接。
  8. 如权利要求3或7所述的像素电路，其特征在于，所述第二时长选择子电路包括第二电容和第四晶体管，其中：
    所述第四晶体管的控制极与所述第三扫描信号端连接，所述第四晶体管的第一极与所述模式控制信号端连接，所述第四晶体管的第二极与所述第二节点连接；所述第二电容的第一端与所述第一电压端连接，所述第二电容的第二端与所述第二节点连接。
  9. 如权利要求4所述的像素电路，其特征在于，所述发光控制电路包括第五晶体管，其中：
    所述第五晶体管的控制极与所述第三节点连接，所述第五晶体管的第一极与所述电流控制电路连接，所述第五晶体管的第二极与所述第一电压端连接。
  10. 如权利要求1所述的像素电路，其特征在于，所述电流控制电路包括：数据写入电路、存储电路和驱动电路；
    所述数据写入电路，用于在所述第一扫描信号的控制下，将所述数据信号端输出的数据信号写入到第四节点；
    所述存储电路，用于存储所述第四节点处的电能；
    所述驱动电路，用于在所述第四节点的信号的控制下，产生驱动电流。
  11. 如权利要求10所述的像素电路，其特征在于，所述数据写入电路包括第八晶体管，所述存储电路包括第三电容，所述驱动电路包括驱动晶体管，其中：
    所述第八晶体管的控制极与所述第一扫描信号端连接，所述第八晶体管的第一极与所述显示数据信号端连接，所述第八晶体管的第二极与所述第四节点连接；
    所述第三电容的第一端与所述第四节点连接，所述第三电容的第二端与第五节点连接；
    所述驱动晶体管的控制极与所述第四节点连接，所述驱动晶体管的第一 极与所述发光元件连接，所述驱动晶体管的第二极与所述第五节点连接。
  12. 如权利要求1所述的像素电路，其特征在于，还包括外部补偿电路，所述外部补偿电路用于对阈值电压进行补偿。
  13. 如权利要求12所述的像素电路，其特征在于，所述外部补偿电路包括第六晶体管、第七晶体管和第九晶体管，所述第六晶体管的控制极与所述发光控制信号端连接，所述第六晶体管的第一极与所述电流控制电路连接，所述第六晶体管的第二极与所述第七晶体管的第一极连接；所述第七晶体管的控制极与所述第一扫描信号端连接，所述第七晶体管的第二极与所述第一电压端连接；所述第九晶体管的控制极与第四扫描信号端连接，所述第九晶体管的第一极与所述第五节点连接，所述第九晶体管的第二极与所述电压输出端连接。
  14. 一种显示装置，其特征在于，包括如权利要求1至13任一所述的像素电路。
  15. 一种像素电路的驱动方法，其特征在于，用于驱动如权利要求1至13任一所述的像素电路，所述像素电路具有多个扫描周期，在一个扫描周期内，所述驱动方法包括：
    电流控制电路接收数据信号和第一扫描信号，根据所述数据信号和所述第一扫描信号控制产生的驱动电流的幅值；
    所述时长控制电路接收模式控制信号、脉冲控制信号、发光控制信号和电流控制电路的驱动电流，并根据模式控制信号的幅值，控制向发光元件提供所述驱动电流的时间长度。
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