WO2020199774A1 - 像素驱动电路及其驱动方法以及显示面板 - Google Patents

像素驱动电路及其驱动方法以及显示面板 Download PDF

Info

Publication number
WO2020199774A1
WO2020199774A1 PCT/CN2020/075797 CN2020075797W WO2020199774A1 WO 2020199774 A1 WO2020199774 A1 WO 2020199774A1 CN 2020075797 W CN2020075797 W CN 2020075797W WO 2020199774 A1 WO2020199774 A1 WO 2020199774A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
circuit
electrode
reset
Prior art date
Application number
PCT/CN2020/075797
Other languages
English (en)
French (fr)
Inventor
刘利宾
杨倩
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020199774A1 publication Critical patent/WO2020199774A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a pixel driving circuit, a driving method thereof, and a display panel.
  • Low temperature polycrystalline silicon (LTPS) process and oxide (Oxide) process are two processes commonly used to manufacture thin film transistor (TFT) array substrates.
  • the low temperature polycrystalline oxide (LTPO) process combines the LTPS and Oxide processes in order to achieve better display performance.
  • the embodiments of the present disclosure provide a pixel driving circuit and a driving method thereof, and a display panel.
  • a pixel driving circuit configured to drive a light-emitting element to emit light.
  • the pixel driving circuit includes: a driving sub-circuit configured to generate a current for causing the light-emitting element to emit light;
  • the light-emitting control sub-circuit is electrically connected to the driving sub-circuit and the first end of the light-emitting element, and is electrically connected to the first node and the second node of the driving sub-circuit, the light-emitting control sub-circuit Is configured to receive a light-emitting control signal, and under the control of the light-emitting control signal, provide the current for causing the light-emitting element to emit light to the first end of the light-emitting element; a drive control sub-circuit electrically connected to the The driving sub-circuit is configured to receive a data signal and a gate driving signal, and under the control of the gate driving signal, provide the data signal to the driving sub-circuit; the reset sub
  • the driving sub-circuit includes a driving transistor, a first transistor, and a storage capacitor.
  • the control electrode of the driving transistor is electrically connected to the third node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the second node; the control electrode of the first transistor is electrically connected to receive For the gate drive signal, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node; and the first end of the storage capacitor is electrically connected to receive the first voltage signal, and the second end is electrically connected Connect the third node.
  • the driving control sub-circuit includes a second transistor, wherein the control electrode of the second transistor is electrically connected to receive the gate driving signal, and the first electrode is electrically connected to receive the data signal, The second pole is electrically connected to the first node.
  • the first transistor and the second transistor are N-type transistors.
  • the light emission control sub-circuit includes a third transistor and a fourth transistor.
  • the control electrode of the third transistor is electrically connected to receive the light-emitting control signal, the first electrode is electrically connected to receive the first voltage signal, and the second electrode is electrically connected to the first node; control of the fourth transistor The electrode is electrically connected to receive the light emitting control signal, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first end of the light emitting element.
  • the third transistor and the fourth transistor are both P-type transistors or both are N-type transistors.
  • the reset sub-circuit includes a fifth transistor and a sixth transistor.
  • the control electrode and the first electrode of the fifth transistor are commonly electrically connected to receive the reset reference signal, and the second electrode is electrically connected to the third node.
  • the control electrode and the first electrode of the sixth transistor are commonly electrically connected to receive the reset reference signal, and the second electrode is electrically connected to the first end of the light-emitting element.
  • the fifth transistor and the sixth transistor are both P-type transistors or both are N-type transistors.
  • the first transistor and the second transistor are IGZO transistors
  • the fifth transistor and the sixth transistor are LTPS transistors.
  • a display panel including: a plurality of scan lines; a plurality of data lines arranged to cross the plurality of scan lines; and a plurality of pixel units arranged in a matrix form at each Where a data line crosses each scan line and is electrically connected to a corresponding data line and scan line, each pixel unit includes a light-emitting element and the pixel driving circuit according to any one of the above embodiments.
  • the data signal received by the pixel drive circuit is provided by the corresponding data line of the pixel unit, and the gate drive signal received by the pixel drive circuit is provided by the corresponding scan line of the pixel unit.
  • the display panel further includes a plurality of light-emitting control lines.
  • the plurality of light emission control lines are arranged in parallel with the plurality of scan lines or the plurality of data lines, and are respectively electrically connected to the same pixel unit as the plurality of scan lines or the plurality of data lines.
  • the light emission control signal received by the pixel drive circuit is provided by the corresponding light emission control line of the pixel unit.
  • the display panel further includes a plurality of inverters, which are respectively electrically connected to the plurality of scan lines in a one-to-one correspondence.
  • the input terminal of the inverter is electrically connected with the corresponding scan line
  • the output terminal of the inverter is electrically connected with the reset line of the pixel unit driven by the scan line located after the corresponding scan line in the scanning order, wherein, the reset reference signal received by the pixel driving circuit included in the pixel unit is provided by the reset line.
  • the inverter is configured to provide a reset reference signal having a reset level or a reset reference signal having a reference level to the output of the reset line under the control of the gate driving signal.
  • the inverter includes a first inverting transistor and a second inverting transistor.
  • the control electrode of the first inverting transistor is electrically connected to the scan line, the first electrode is electrically connected to receive the reset level, the second electrode is electrically connected to the reset line, and the second electrode is electrically connected to the scan line.
  • the control electrode is electrically connected to the scan line, the second electrode is electrically connected to receive the reference level, and the second electrode is electrically connected to the reset line.
  • the first inverting transistor is an N-type transistor
  • the second inverting transistor is a P-type transistor.
  • the reset level is a level required to turn on the driving transistor, and the reference level is equal to a level required to turn off the driving transistor.
  • a method for driving the pixel driving circuit includes: in a first period, providing a light emission control signal having a first level, providing a gate driving signal having a second level, and providing a reset reference signal having a reset level; and in a second period, providing The light emission control signal and the gate drive signal of the first level provide a reset reference signal with a reference level; in the third period, the light emission control signal and the gate drive signal with the second level are provided to provide a reference level The reset reference signal.
  • the reference level is equal to the first level.
  • Fig. 1 shows a schematic block diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 2 shows an example structure of the pixel driving circuit of FIG. 1.
  • FIG. 3A shows a signal timing diagram of the pixel driving circuit of FIG. 2.
  • 3B-3D show schematic diagrams of the principle of each stage of the pixel driving circuit of FIG. 2.
  • Fig. 4 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • Fig. 5 shows a schematic structural diagram of an inverter on a display panel according to an embodiment of the present disclosure.
  • Fig. 6 shows an example structure of the inverter of Fig. 5.
  • FIG. 7 shows a flowchart of a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
  • the term "electrically connected” may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components. In addition, these two components can be electrically connected or coupled in a wired or wireless manner.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged. In the embodiments of the present disclosure, the gate of the transistor is called a control electrode, one of the source and drain is called a first electrode, and the other of the source and drain is called a second electrode.
  • a pixel driving circuit implemented using LTPO technology in which some transistors are implemented by LTPS process, and the remaining transistors are implemented by oxide (for example, IGZO) process.
  • oxide for example, IGZO
  • some transistors including the driving transistor are exemplified as P-type thin film transistors realized by the LTPS process, and some other transistors are exemplified as N-type transistors realized by the IGZO process. It should be understood that this is just an example, and in other embodiments, the transistors of the present disclosure may be implemented by other processes, and may belong to different transistor types.
  • first level and second level are only used to distinguish the two levels from being different in amplitude.
  • the "first level” may be a level that turns off the related transistor
  • the “second level” may be a level that turns on the related transistor.
  • the driving transistor is exemplified as a P-type thin film transistor
  • the "first level” is exemplified as the high level VH
  • the “second level” is exemplified as the low level VL.
  • FIG. 1 shows a schematic block diagram of a pixel driving circuit 100 according to an embodiment of the present disclosure.
  • the pixel driving circuit 100 is configured to drive the light emitting element to emit light.
  • the light-emitting element 150 is shown with a dotted line in the following FIGS. 1 to 3D.
  • the light-emitting element 110 may be any light-emitting element driven by current, such as an OLED or AMOLED light-emitting element.
  • the light emitting element 110 has a first end and a second end.
  • the first terminal is the anode of the light-emitting element 110
  • the second terminal is the cathode of the light-emitting element 110
  • the second terminal is electrically connected to the fixed voltage terminal ELVSS.
  • the pixel driving circuit 100 may include a driving sub-circuit 110, a light emission control sub-circuit 120, a driving control sub-circuit 130 and a reset sub-circuit 140.
  • the driving sub-circuit 110 is electrically connected to the light emission control sub-circuit 120 and the reset sub-circuit 140. As shown in FIG. 1, the driving sub-circuit 110 and the light emission control sub-circuit 120 are electrically connected to the first node N1 and the second node N2, and the reset sub-circuit 140 is electrically connected to the third node N3.
  • the driver sub-circuit 110 is configured to generate a current for causing the light emitting element 150 to emit light.
  • the lighting control sub-circuit 120 includes a first lighting control sub-circuit and a second lighting control sub-circuit. As shown in FIG. 1, the first lighting control sub-circuit and the driving sub-circuit 110 are electrically connected to the first node N1, and the second lighting control sub-circuit and the driving sub-circuit 120 are electrically connected to the second node N2.
  • the second light-emitting control sub-circuit is also electrically connected to the first end of the light-emitting element 150.
  • the first light-emission control sub-circuit and the second light-emission control sub-circuit are configured to receive the light-emission control signal EM, and under the control of the light-emission control signal EM, provide current for causing the light-emitting element 150 to emit light to the first light-emitting element 150 One end.
  • the first light emission control sub-circuit receives the first voltage V1 from the first voltage signal line, and under the control of the light emission control signal EM, transmits the first voltage to the driving sub-circuit 110.
  • the first voltage may be the power supply voltage ELVDD.
  • ELVDD may be higher than the first level (ie, the high level VH).
  • the second light emission control sub-circuit provides the current generated by the driving sub-circuit 110 for causing the light-emitting element 150 to emit light to the first end of the light-emitting element 150.
  • the driving control sub-circuit 130 is electrically connected to the driving sub-circuit 110, and is electrically connected to the first node N1 with the driving sub-circuit 110.
  • the driving control sub-circuit 130 is configured to receive the data signal DATA and the gate driving signal GATE.
  • the driving control sub-circuit 130 is configured to provide the data signal DATA to the driving sub-circuit 110 under the control of the gate driving signal GATE.
  • the reset sub-circuit 140 is electrically connected to the driving sub-circuit 110 and the first end of the light emitting element 150, and is electrically connected to the driving sub-circuit 110 to the third node N3.
  • the reset sub-circuit 140 is configured to receive a reset reference signal line RESET.
  • the reset sub-circuit 140 is configured to use the reset reference signal RESET to reset the third node N3 and the first end of the light emitting element 150 under the control of the reset reference signal RESET.
  • FIG. 2 shows an example structure of the pixel driving circuit 100 of FIG. 1.
  • the driving sub-circuit 110 includes a driving transistor Md, a first transistor M1, and a storage capacitor Cst.
  • the control electrode of the driving transistor Md is electrically connected to the third node N3, the first electrode and the first light emission control sub-circuit of the light emission control sub-circuit 120 are electrically connected to the first node N1, and the second electrode is electrically connected to the second light emission of the light emission control sub-circuit 120
  • the control sub-circuit is electrically connected to the second node N2.
  • the control electrode of the first transistor M1 receives the gate drive signal GATE, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.
  • the first terminal of the storage capacitor Cst is electrically connected to the first voltage signal line to receive the first voltage signal V1, and the second terminal is electrically connected to the third node N3.
  • the first transistor M1 may be an IGZO transistor. In other exemplary embodiments, the first transistor M1 may be an N-type IGZO transistor.
  • the first emission control sub-circuit of the emission control sub-circuit 120 includes a third transistor M3, and the second emission control sub-circuit of the emission control sub-circuit 120 includes a fourth transistor M4.
  • control electrode of the third transistor M3 is electrically connected to receive the light emission control signal EM
  • the first electrode is electrically connected to the first voltage signal line to receive the first voltage signal V1
  • the second electrode is electrically connected to the first node N1.
  • the control electrode of the fourth transistor M4 is electrically connected to receive the light emission control signal EM, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the first end of the light emitting element 150,
  • the third transistor M3 and the fourth transistor M4 may both be P-type transistors or both may be N-type transistors.
  • the driving control sub-circuit 130 includes a second transistor M2.
  • the control electrode of the second transistor M2 is electrically connected to receive the gate drive signal GATE, the first electrode is electrically connected to receive the data signal DATA, and the second electrode is electrically connected to the first node N1.
  • the second transistor M2 may be an IGZO transistor. In other exemplary embodiments, the second transistor M2 may be an N-type IGZO transistor.
  • the reset sub-circuit 140 includes a fifth transistor M5 and a sixth transistor M6.
  • control electrode and the first electrode of the fifth transistor M5 are commonly electrically connected to receive the reset reference signal RESET, and the second electrode is electrically connected to the third node N3.
  • control electrode and the first electrode of the sixth transistor M6 are commonly electrically connected to receive the reset reference signal RESET, and the second electrode is electrically connected to the first end of the light emitting element 150.
  • the fifth transistor M5 and the sixth transistor M6 may both be P-type transistors or both may be N-type transistors. In other exemplary embodiments, the fifth transistor M5 and the sixth transistor M6 may both be P-type LTPS transistors or both may be N-type LTPS transistors.
  • FIG. 3A shows a signal timing diagram of the pixel driving circuit 100 of FIG. 2.
  • the light emission control signal EM having the first level ie, the high level VH
  • the reset reference signal having the second level ie, the low level VL
  • the third transistor M3 and the fourth transistor M4 are turned off; under the control of the gate drive signal GATE, the first transistor M1 and the second transistor M2 Turn off; under the control of the reset reference signal RESET, the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the schematic diagram of the principle of the pixel driving circuit 100 is shown in FIG. 3B. It should be noted that in FIG. 3B, the transistors that are turned off at this stage are marked with an oblique cross " ⁇ ".
  • the reset reference signal of low level When the fifth transistor M5 is turned on, the reset reference signal of low level is transmitted to the third node N3, and when the sixth transistor M6 is turned on, the reset reference signal of low level is transmitted to the first node of the light emitting element 150.
  • the reset reference signal of low level causes the control electrode of the driving transistor Md to become a low level, which will turn on the driving transistor Md.
  • the anode of the light-emitting element 150 also becomes a low level.
  • both the driving transistor Md and the anode of the light emitting element 150 are reset to a low level. Therefore, the first phase T1 is also called the "reset phase".
  • the light emission control signal EM and the gate drive signal GATE having the first level are provided, the reset reference signal RESET having the reference level is provided, and the first level is provided The data signal DATA.
  • the reference level may be a high level REF.
  • the high level REF is a high level VH that can ensure that the fifth transistor M5 is reliably turned off.
  • the high level REF is slightly larger than the sum of the maximum voltage value of the data signal DATA and the threshold voltage Vth of the driving transistor (here, the threshold voltage Vth of the N-type transistor is considered to be a positive value, and the P-type transistor The threshold voltage of the transistor is negative).
  • the third transistor M3 and the fourth transistor M4 are turned off; under the control of the gate drive signal GATE, the first transistor M1 and the second transistor M2 Turned on; under the control of the reset reference signal RESET, the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the schematic diagram of the principle of the pixel driving circuit 100 is shown in FIG. 3C. It should be noted that in FIG. 3C, the transistors that are turned off at this stage are marked with an oblique cross " ⁇ ".
  • the high-level data signal DATA is transmitted to the first node N1. Since the driving transistor Md is in the on state in the previous stage, the driving transistor Md is still in the on state at this time, so the high-level data signal DATA continues to be transmitted to the second node N2.
  • the first transistor M1 is turned on, the high-level data signal DATA continues to be transmitted to the third node N3, and the third node N3 at the low level is charged.
  • Vdata may have a first level (ie, a high level VH).
  • a reset reference signal RESET having a reference level REF is provided, and a light emission control signal EM and a gate driving signal GATE having a second level (ie, a low level VL) are provided.
  • the third transistor M3 and the fourth transistor M4 are turned on; under the control of the gate drive signal GATE, the first transistor M1 and the second transistor M2 Turn off; under the control of the reset reference signal RESET, the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the schematic diagram of the principle of the pixel driving circuit 100 is shown in FIG. 3D. It should be noted that the transistors that are turned off at this stage are marked by an oblique cross " ⁇ " in FIG. 3D.
  • the fourth transistor M4 When the fourth transistor M4 is turned on, the driving current Id generated by the driving transistor Md is applied to the anode of the light emitting element 150 and drives the light emitting element 150 to emit light. Therefore, the third stage T3 is also called the "light-emitting stage".
  • the driving current Id flowing through the light emitting element 150 can be expressed by the following formula:
  • K is the current constant associated with the driving transistor Md, which is related to the process parameters and geometric dimensions of the driving transistor Md. It can be seen from the above formula that the driving current Id used to drive the light-emitting element 150 to emit light is independent of the threshold voltage Vth of the driving transistor Md.
  • the pixel driving circuit realizes the driving of the light-emitting element on the basis of compensating the threshold voltage of the driving transistor Md. It should be noted that the pixel driving circuit of the present disclosure only receives the gate driving signal GATE, the light emission control signal EM, the reset reference signal RESET, and the data signal DATA. That is, in addition to the gate drive signal GATE and the data signal DATA, only two additional control signals are needed to drive the light-emitting element. Therefore, the pixel driving circuit according to the embodiment of the present disclosure can save wiring space, realize a tighter circuit layout, and is more conducive to the realization of high PPI.
  • the first electrode of the fifth transistor M5 receives the reference level with the high level REF.
  • the high level REF is a high level slightly larger than the sum of the maximum voltage value of the data signal DATA and the threshold voltage Vth of the driving transistor.
  • the voltage of the second electrode of the fifth transistor M5 (ie, the third node N3) is Vdata+Vth always lower than the reference level, and the fifth transistor M5 It is always in a reliable off state, and the third node N3 is not discharged, so that the gate leakage of the driving transistor Md can be suppressed.
  • FIG. 4 shows a schematic block diagram of a display panel 400 according to an embodiment of the present disclosure.
  • the display panel 400 may include a plurality of scan lines SL and a plurality of data lines DL, and the plurality of data lines DL and the plurality of scan signal lines SL are arranged vertically and horizontally.
  • the display panel 400 may further include a plurality of pixel units 410, which are arranged in a matrix at the intersection of each scan line SL and each data line DL, and are electrically connected to the corresponding scan line SL and the data line DL.
  • Each pixel unit of the plurality of pixel units 410 includes a light emitting element 150 and a pixel driving circuit according to an embodiment of the present disclosure, for example, according to the pixel driving circuit 100 shown in FIG. 1 or FIG. 2.
  • the data signal received by the pixel driving circuit 100 is provided by the corresponding data line DL of the pixel unit 410, and the gate driving signal received by the pixel driving circuit 100 is provided by the corresponding scan line SL of the pixel unit 410.
  • the display panel 400 may further include a plurality of light emitting control lines EL which are arranged in parallel with the plurality of scan lines SL or the plurality of data lines DL, and are arranged in parallel with the plurality of scan lines SL or The multiple data lines DL are electrically connected to the same pixel unit 410, respectively.
  • a plurality of light emitting control lines EL which are arranged in parallel with the plurality of scan lines SL or the plurality of data lines DL, and are arranged in parallel with the plurality of scan lines SL or The multiple data lines DL are electrically connected to the same pixel unit 410, respectively.
  • the light emission control signal received by the pixel driving circuit 100 is provided by the corresponding light emission control line EL of the pixel unit 410.
  • the reset reference signal received by the pixel driving circuit 100 is provided by the previous scan line SL of the corresponding scan line SL of the pixel unit 410 in the scan order.
  • the display panel 400 further includes a plurality of inverters.
  • the plurality of inverters are electrically connected to the plurality of scan lines SL in one-to-one correspondence.
  • FIG. 5 shows a schematic structural diagram of an inverter 500.
  • the input terminal of the inverter 500 is electrically connected to the (corresponding) scan line SL, and the output terminal of the inverter 500 is connected to the reset of the pixel unit 410 driven by the scan line located after the scan line in the scanning order.
  • the line RST is electrically connected.
  • the reset reference signal RESET received by the pixel driving circuit 100 in the pixel unit 410 is provided by the reset line RST.
  • the inverter 500 is also electrically connected to the reset level terminal VINIT and the reference level terminal VREF.
  • the inverter 500 is configured to provide the reset level from the reset level terminal VINIT or the reference level from the reference level terminal VREF to the reset line RST under the control of the gate drive signal GATE from the scan line SL.
  • a reset reference signal having a reset level or a reset reference signal having a reference level is provided through the reset line RST.
  • the reset level is the level at which the driving transistor Md is turned on (for example, the low level VL in the above-mentioned embodiment), and the reference level REF is slightly larger than the maximum voltage value of the data signal DATA and the driving transistor. The sum of the threshold voltage Vth.
  • FIG. 6 shows an example structure of the inverter 500.
  • the inverter 500 includes a first inverting transistor Mi1 and a second inverting transistor Mi2.
  • the control electrode of the first inverting transistor Mi1 is electrically connected to the scan line SL, the first electrode is electrically connected to the reset level terminal VINIT to receive the reset level, and the second electrode is electrically connected to the reset line RST.
  • the control electrode of the second inversion transistor Mi2 is electrically connected to the scan line SL, the first electrode is electrically connected to the reference level terminal VREF to receive the reference level, and the second electrode is electrically connected to the reset line RST.
  • the first inverting transistor Mi1 may be an N-type transistor
  • the second inverting transistor Mi2 may be a P-type transistor.
  • the reset reference signal required in the pixel drive circuit can be obtained on the basis of the gate drive signal from the scan line.
  • the phases of the gate drive signal and the reset reference signal can be referred to The timing diagram shown in Figure 3A.
  • FIG. 7 shows a flowchart of a driving method 700 of a pixel driving circuit according to an embodiment of the present disclosure.
  • the driving method 700 can be used to drive the pixel driving circuit 100 shown in FIG. 1 or FIG. 2.
  • step S710 in the first period, a light emission control signal with a first level is provided, a gate drive signal with a second level is provided, a reset reference signal with a reset level is provided, and Provide a data signal with a second level.
  • step S720 in the second period, the light emission control signal and the gate driving signal having the first level are provided, the reset reference signal having the reference level is provided, and the data signal having the first level is provided.
  • step S730 in the third period, the light emission control signal and the gate driving signal having the second level are provided, the reset reference signal having the reference level is provided, and the data signal having the second level is provided.
  • the first level is a level corresponding to the level at which the driving transistor is turned off
  • the second level is a level corresponding to the level at which the driving transistor is turned on.
  • the data signal having the first level refers to the level of a valid data signal that can be used for display.
  • the reference level may be equal to the first level.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开提供了一种像素驱动电路及其驱动方法和显示面板。像素驱动电路包括被配置为驱动发光元件发光，包括：驱动子电路，产生用于使发光元件发光的电流；发光控制子电路，与驱动子电路电连接于第一节点和第二节点，并且电连接到发光元件的第一端；驱动控制子电路，电连接到驱动子电路，向驱动子电路提供数据信号；复位子电路，与驱动子电路电连接于第三节点，并且电连接到发光元件的第一端，被配置为接收复位参考信号，并在复位参考信号的控制下，使用复位参考信号对第三节点和发光元件的第一端进行复位。

Description

像素驱动电路及其驱动方法以及显示面板
本申请要求于2019年3月29日提交的、申请号为201910247440.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及显示技术领域，具体地涉及一种像素驱动电路及其驱动方法以及显示面板。
背景技术
低温多晶硅(Low temperature Polycrystalline Sillicon，LTPS)工艺和氧化物(Oxide)工艺(例如，IGZO工艺)是常用来制造薄膜晶体管(TFT)阵列基板的两种工艺。低温多晶氧化物(Low temperature Polycrystalline Oxide，LTPO)工艺将LTPS和Oxide两种工艺融合，以期实现更为出色的显示性能。
发明内容
本公开实施例提出了一种像素驱动电路及其驱动方法以及显示面板。
根据本公开的一个方面，提出了一种像素驱动电路，被配置为驱动发光元件发光，所示像素驱动电路包括：驱动子电路，被配置为产生用于使发光元件发光的电流；发光控制子电路，所述发光控制子电路电连接到所述驱动子电路和所述发光元件的第一端，并且与所述驱动子电路电连接于第一节点和第二节点，所述发光控制子电路被配置为接收发光控制信号，并在所述发光控制信号的控制下，将所述用于使发光元件发光的电流提供到所述发光元件的第一端；驱动控制子电路，电连接所述驱动子电路，被配置为接收数据信号和栅极驱动信号，并在所述栅极驱动信号的控制下，将所述数据信号提供到所述驱动子电路；复位子电路，电连接到所述驱动子电路和所述发光元件的第一端，并且与所述驱动子电路电连接于第三节点，被配置为接收复位参考信号，并在所述复位参考信号的控制下，使用所述复位参考信号对所述第三节点和所述发光元件的第一端进行复位。
在一些实施例中，所述驱动子电路包括驱动晶体管、第一晶体管和存储电容。所述 驱动晶体管的控制极电连接所述第三节点，第一极电连接所述第一节点，第二极电连接所述第二节点；所述第一晶体管的控制极电连接为接收所述栅极驱动信号，第一极电连接所述第二节点，第二极电连接所述第三节点；以及所述存储电容的第一端电连接为接收第一电压信号，第二端电连接所述第三节点。
在一些实施例中，所述驱动控制子电路包括第二晶体管，其中，所述第二晶体管的控制极电连接为接收所述栅极驱动信号，第一极电连接为接收所述数据信号，第二极电连接所述第一节点。
在一些实施例中，所述第一晶体管和所述第二晶体管为N型晶体管。
在一些实施例中，所述发光控制子电路包括第三晶体管和第四晶体管。所述第三晶体管的控制极电连接为接收所述发光控制信号，第一极电连接为接收所述第一电压信号，第二极电连接所述第一节点；所述第四晶体管的控制极电连接为接收所述发光控制信号，第一极电连接所述第二节点，第二极电连接到所述发光元件的第一端。
在一些实施例中，所述第三晶体管和所述第四晶体管均为P型晶体管或均为N型晶体管。
在一些实施例中，所述复位子电路包括第五晶体管和第六晶体管。所述第五晶体管的控制极和第一极共同电连接为接收所述复位参考信号，第二极电连接所述第三节点。所述第六晶体管的控制极和第一极共同电连接为接收所述复位参考信号，第二极电连接到所述发光元件的第一端。
在一些实施例中，所述第五晶体管和所述第六晶体管均为P型晶体管或均为N型晶体管。
在一些实施例中，所述第一晶体管和所述第二晶体管是IGZO晶体管，所述第五晶体管和所述第六晶体管是LTPS晶体管。
根据本公开的另一方面，提供了一种显示面板，包括：多条扫描线；多条数据线，与所述多条扫描线交叉设置；以及多个像素单元，以矩阵的形式设置在每个数据线和每个扫描线交叉处，并与对应的数据线和扫描线电连接，每个像素单元包括发光元件和根据上述任一实施例的像素驱动电路。所述像素驱动电路所接收的数据信号由所述像素单元的对应数据线提供，所述像素驱动电路所接收的栅极驱动信号由所述像素单元的对应扫描线提供。
在一些实施例中，显示面板还包括多条发光控制线。所述多条发光控制线与所述多 条扫描线或所述多条数据线平行地布置，并与所述多条扫描线或所述多条数据线分别电连接到相同的像素单元。所述像素驱动电路所接收的发光控制信号由所述像素单元的对应发光控制线提供。
在一些实施例中，所述显示面板还包括多个反相器，分别与所述多个扫描线一一对应地电连接。所述反相器的输入端与对应的扫描线电连接，所述反相器的输出端与按照扫描顺序位于所述对应的扫描线之后的扫描线所驱动的像素单元的复位线电连接，其中，包括在所述像素单元中的像素驱动电路所接收的复位参考信号由所述复位线提供。所述反相器被配置为在所述栅极驱动信号的控制下向所述复位线的输出提供具有复位电平的复位参考信号或具有参考电平的复位参考信号。
在一些实施例中，所述反相器包括第一反相晶体管和第二反相晶体管。所述第一反相晶体管的控制极电连接到所述扫描线，第一极电连接为接收所述复位电平，第二极电连接到所述复位线，所述第二反相晶体管的控制极电连接到所述扫描线，第二极电连接为接收所述参考电平，第二极电连接到所述复位线。所述第一反相晶体管为N型晶体管，所述第二反相为P型晶体管。
在一些实施例中，所述复位电平是使驱动晶体管导通所需的电平，所述参考电平等于使所述驱动晶体管关断所需的电平。
根据本公开的又一方面，提供了一种对根据上述任一实施例的像素驱动电路进行驱动的方法。所述方法包括：在第一时段，提供具有第一电平的发光控制信号，提供具有第二电平的栅极驱动信号，提供具有复位电平的复位参考信号；在第二时段，提供具有第一电平的发光控制信号和栅极驱动信号，提供具有参考电平的复位参考信号；在第三时段，提供具有第二电平的发光控制信号和栅极驱动信号，提供具有参考电平的复位参考信号。
在一些实施例中，所述参考电平等于所述第一电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了根据本公开实施例的像素驱动电路的示意方框图。
图2示出了图1的像素驱动电路的一个示例结构。
图3A示出了图2的像素驱动电路的信号时序图。
图3B-图3D示出了图2的像素驱动电路的各阶段原理示意图。
图4示出了根据本公开实施例的显示面板的示意方框图。
图5示出了根据本公开实施例的显示面板上的反相器的示意结构图。
图6示出了图5的反相器的一个示例结构。
图7示出了根据本公开实施例的像素驱动电路的驱动方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“电连接”可以是指两个组件直接电连接，也可以是指两个组件之间经由一个或多个其他组件电连接。此外，这两个组件可以通过有线或无线方式电连接或耦接。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。根据在电路中的作用，本公开实施例使用的晶体管主要为开关晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将晶体管的栅极称为控制极，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。
在以下示例中，描述了采用LTPO技术实现的像素驱动电路，其中，部分晶体管通过LTPS工艺实现，其余晶体管通过氧化物(例如IGZO)工艺实现。在下文中，将包括驱动晶体管在内的一些晶体管例示为通过LTPS工艺实现的P型薄膜晶体管，并将其他一些晶体管例示为通过IGZO工艺实现的N型晶体管。应该理解的是，这只是作为示例，在其他实施例中，本公开的各晶体管可以通过其他的工艺来实现，并且可以属于不同的晶体管类型。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。在一些实施例中，“第一电平”可以是使相关晶体管关断的电平，“第二电平”可以是使相关晶体管导通的电平。下文中，由于驱动晶体管被示例为P型薄膜晶体管，因此“第一电平”被示例为高电平VH，“第二电平”被示例为低电平VL。
以下参考附图对本公开的实施例进行具体描述。
图1示出了根据本公开实施例的像素驱动电路100的示意方框图。像素驱动电路100被配置为驱动发光元件发光。为了更清楚地说明书像素驱动电路100与发光元件之间的连接关系，在以下的图1至图3D中将发光元件150以虚线示出。发光元件110可以是任何以电流驱动的发光元件，如OLED或AMOLED发光元件。发光元件110具有第一端和第二端。在一些实施例中，第一端为发光元件110的阳极，第二端为发光元件110的阴极，第二端电连接固定电压端ELVSS。
如图1所示，像素驱动电路100可以包括驱动子电路110、发光控制子电路120、驱动控制子电路130和复位子电路140。
驱动子电路110与发光控制子电路120和复位子电路140电连接。如图1所示，驱动子电路110与发光控制子电路120电连接于第一节点N1和第二节点N2，与复位子电路140电连接于第三节点N3。驱动子电路110被配置为产生用于使发光元件150发光的电流。
发光控制子电路120包括第一发光控制子电路和第二发光控制子电路。如图1所示，第一发光控制子电路与驱动子电路110电连接于第一节点N1，第二发光控制子电路与驱动子电路120电连接于第二节点N2。第二发光控制子电路还电连接到发光元件150的第一端。第一发光控制子电路和第二发光控制子电路被配置为接收发光控制信号EM，并且在发光控制信号EM的的控制下，将用于使发光元件150发光的电流提供到发光元件150的第一端。
如图1所示，第一发光控制子电路从第一电压信号线接收第一电压V1，并且在发光控制信号EM的控制下，将第一电压传递到驱动子电路110。在一些实施例中，第一电压可以是电源电压ELVDD。在一些实施例中，ELVDD可以高于第一电平(即高电平VH)。第二发光控制子电路在发光控制信号EM的控制下，将驱动子电路110产生的用于使发光元件150发光的电流提供到发光元件150的第一端。
驱动控制子电路130电连接到驱动子电路110，并且与驱动子电路110电连接于第一节点N1。驱动控制子电路130被配置为接收数据信号DATA和栅极驱动信号GATE。驱动控制子电路130被配置为在栅极驱动信号GATE的控制下，将数据信号DATA提供到驱动子电路110。
复位子电路140电连接到驱动子电路110和发光元件150的第一端，并且与驱动子电路110电连接于第三节点N3。复位子电路140被配置为接收复位参考信号线RESET。复位子电路140被配置为在复位参考信号RESET的控制下，使用复位参考信号RESET来对第三节点N3和发光元件150的第一端进行复位。
图2示出了图1的像素驱动电路100的一个示例结构。
如图2所示，驱动子电路110包括驱动晶体管Md、第一晶体管M1和存储电容Cst。
驱动晶体管Md的控制极电连接第三节点N3，第一极与发光控制子电路120的第一发光控制子电路电连接于第一节点N1，第二极与发光控制子电路120的第二发光控制子电路电连接于第二节点N2。
第一晶体管M1的控制极接收栅极驱动信号GATE，第一极电连接第二节点N2，第二极电连接第三节点N3。
存储电容Cst的第一端电连接第一电压信号线以接收第一电压信号V1，第二极电连接第三节点N3。
在一些示例性实施例中，第一晶体管M1可以为IGZO晶体管。在另一些示例性实施例中，第一晶体管M1可以为N型IGZO晶体管。
发光控制子电路120的第一发光控制子电路包括第三晶体管M3，发光控制子电路120的第二发光控制子电路包括第四晶体管M4。
根据实施例，第三晶体管M3的控制极电连接为接收发光控制信号EM，第一极电连接第一电压信号线以接收第一电压信号V1，第二极电连接第一节点N1。
第四晶体管M4的控制极电连接为接收发光控制信号EM，第一极电连接第二节点 N2，第二极电连接发光元件150的第一端，
在示例性实施例中，第三晶体管M3和第四晶体管M4可以均为P型晶体管或均为N型晶体管。
驱动控制子电路130包括第二晶体管M2。
第二晶体管M2的控制极电连接为接收栅极驱动信号GATE，第一极电连接为接收数据信号DATA，第二极电连接第一节点N1。
在一些示例性实施例中，第二晶体管M2可以为IGZO晶体管。在另一些示例性实施例中，第二晶体管M2可以为N型IGZO晶体管。
复位子电路140包括第五晶体管M5和第六晶体管M6。
第五晶体管M5的控制极和第一极共同电连接为接收复位参考信号RESET，第二极电连接到第三节点N3。
第六晶体管M6的控制极和第一极共同电连接为接收复位参考信号RESET，第二极电连接到发光元件150的第一端。
在一些示例性实施例中，第五晶体管M5和第六晶体管M6可以均为P型晶体管或均为N型晶体管。在另一些示例性实施例中，第五晶体管M5和第六晶体管M6可以均为P型LTPS晶体管或均为N型LTPS晶体管。
图3A示出了图2的像素驱动电路100的信号时序图。
如图3A所示，在第一阶段T1期间，提供具有第一电平(即高电平VH)的发光控制信号EM，并提供具有第二电平(即低电平VL)的复位参考信号RESET和栅极驱动信号GATE。
由此，在第一阶段T1期间，在发光控制信号EM的控制下，第三晶体管M3和第四晶体管M4关断；在栅极驱动信号GATE的控制下，第一晶体管M1和第二晶体管M2关断；在复位参考信号RESET的控制下，第五晶体管M5和第六晶体管M6导通。此时像素驱动电路100的原理示意图如图3B所示，应该指出的是，图3B中将本阶段关断的晶体管通过斜十字“×”标记。
在第五晶体管M5导通的情况下，低电平的复位参考信号传输到第三节点N3，在第六晶体管M6导通的情况下，低电平的复位参考信号传输到发光元件150的第一端。从而，低电平的复位参考信号使得驱动晶体管Md的控制极变为低电平，这将使得驱动晶体管Md导通。并且，发光元件150的阳极也变为低电平。从而驱动晶体管Md和发 光元件150的阳极均被低电平复位。因此，第一阶段T1也被称为“复位阶段”。
在第二阶段T2期间，提供具有第一电平(即高电平VH)的发光控制信号EM和栅极驱动信号GATE，提供具有参考电平的复位参考信号RESET，并且提供具有第一电平的数据信号DATA。在驱动晶体管为P型晶体管的实施例中，参考电平可以是高电平REF。在一些实施例中，高电平REF是能够确保第五晶体管M5可靠地关断的高电平VH。在一些实施例中，高电平REF是略大于数据信号DATA的最大电压值与驱动晶体管的阈值电压Vth之和的高电平(这里，认为N型晶体管的阈值电压Vth为正值，P型晶体管的阈值电压为负值)。
由此，在第二阶段T2期间，在发光控制信号EM的控制下，第三晶体管M3和第四晶体管M4关断；在栅极驱动信号GATE的控制下，第一晶体管M1和第二晶体管M2导通；在复位参考信号RESET的控制下，第五晶体管M5和第六晶体管M6关断。此时像素驱动电路100的原理示意图如图3C所示，应该指出的是，图3C中将本阶段关断的晶体管通过斜十字“×”标记。
在第二晶体管M2导通的情况下，高电平的数据信号DATA传输到第一节点N1。由于在上一阶段中驱动晶体管Md处于导通状态，此时驱动晶体管Md仍处于导通状态，从而高电平的数据信号DATA继续传输到第二节点N2。在第一晶体管M1导通的情况下，高电平的数据信号DATA继续传输到第三节点N3，并对处于低电平的第三节点N3进行充电。随着第三节点N3的电压不断上升，驱动晶体管Md的栅源电压Vgs从VL-Vdata逐渐增加，直到Vgs＝Vth为止，其中Vth为驱动晶体管Md的阈值电压，Vdata为数据信号DATA的电压。此时，驱动晶体管Md不再导通，同时停止对第三节点N3进行充电。此时，第三节点N3处(即Md的控制极)的电压为Vg＝Vgs+Vs＝Vdata+Vth。数据信号DATA的电压Vdata已经写入第三节点N3。因此，此第二阶段T2也可以称为“数据电压写入阶段”。在一些实施例中，Vdata可以具有第一电平(即高电平VH)。
在第三阶段T3期间，提供具有参考电平REF的复位参考信号RESET，并且提供具有第二电平(即低电平VL)的发光控制信号EM和栅极驱动信号GATE。
由此，在第三阶段T3期间，在发光控制信号EM的控制下，第三晶体管M3和第四晶体管M4导通；在栅极驱动信号GATE的控制下，第一晶体管M1和第二晶体管M2关断；在复位参考信号RESET的控制下，第五晶体管M5和第六晶体管M6关断。此时像素驱动电路100的原理示意图如图3D所示，应该指出的是，图3D中将本阶段 关断的晶体管通过斜十字“×”标记。
在第三晶体管M3导通的情况下，第一电压V1(即ELVDD)传输到第一节点N1，即驱动晶体管Md的源极电压Vs＝ELVDD。此时，由于第一晶体管M1和第五晶体管M5都关断，因此第三节点N3处于浮置状态，其电压保持为Vdata+Vth，即驱动晶体管Md的控制极电压Vg＝Vdata+Vth，从而，Vgs＝Vdata+Vth-ELVDD，其小于Vth，使得驱动晶体管Md导通。在第四晶体管M4导通的情况下，驱动晶体管Md产生的驱动电流Id施加到发光元件150的阳极，并驱动发光元件150发光。因此，第三阶段T3也被称为“发光阶段”。
具体地，流过发光元件150的驱动电流Id可以由下式表示：
Id＝K·(Vgs-Vth) 2
＝K·(Vdata+Vth-ELVDD-Vth) 2
＝K·(ELVDD-Vdata) 2
其中，K为与驱动晶体管Md相关联的电流常数，与驱动晶体管Md的工艺参数和几何尺寸有关。由以上公式可知，用于驱动发光元件150进行发光的驱动电流Id与驱动晶体管Md的阈值电压Vth无关。
在本公开的上述实施例中，像素驱动电路在对驱动晶体管Md的阈值电压进行了补偿的基础上实现了对发光元件的驱动。应该注意到，本公开的像素驱动电路中只接收栅极驱动信号GATE、发光控制信号EM、复位参考信号RESET和数据信号DATA。即除栅极驱动信号GATE和数据信号DATA以外，仅需要两个附加的控制信号就可以实现对发光元件的驱动。因此，根据本公开实施例的像素驱动电路能够节省布线空间，实现更为紧致的电路布局，更有利于高PPI的实现。
此外，根据上述实施例可知，在数据电压写入阶段T2和发光阶段T3期间，第五晶体管M5的第一极接收具有高电平REF的参考电平。在一些实施例中，高电平REF高电平REF是略大于数据信号DATA的最大电压值与驱动晶体管的阈值电压Vth之和的高电平。在一些实施例中，在数据电压写入阶段T2和发光阶段T3期间，第五晶体管M5的第二极(即第三节点N3)的电压为Vdata+Vth始终小于参考电平，第五晶体管M5始终处于可靠的关断状态，并不会对第三节点N3进行放电，从而能够抑制驱动晶体管Md的栅极漏电。
图4示出了根据本公开实施例的显示面板400的示意方框图。如图4所示，显示面 板400可以包括多条扫描线SL和多条数据线DL，多条数据线DL与多条扫描信号线SL纵横交叉设置。显示面板400还可以包括多个像素单元410，以矩阵的形式设置在每个扫描线SL和每个数据线DL的交叉处，并且与对应的扫描线SL和数据线DL电连接。多个像素单元410中的每个像素单元包括发光元件150和根据本公开实施例的像素驱动电路，例如根据图1或图2所示的像素驱动电路100。
在一些实施例中，像素驱动电路100所接收的数据信号由像素单元410的对应数据线DL提供，像素驱动电路100所接收的栅极驱动信号由像素单元410的对应扫描线SL提供。
在一些实施例中，显示面板400还可包括多条发光控制线EL，该多条发光控制线EL与多条扫描线SL或多条数据线DL平行地布置，并与多条扫描线SL或多条数据线DL分别电连接到相同的像素单元410。
在一些实施例中，像素驱动电路100所接收的发光控制信号由像素单元410的对应发光控制线EL提供。
在一些实施例中，像素驱动电路100所接收的复位参考信号由像素单元410的对应扫描线SL的按照扫描顺序的前一扫描线SL提供。
在一些实施例中，显示面板400还包括多个反相器。该多个反相器分别与多个扫描线SL一一对应地电连接。
图5示出了反相器500的示意结构图。
如图5所示，反相器500的输入端与(对应的)扫描线SL电连接，反相器500的输出端与按照扫描顺序位于扫描线之后的扫描线所驱动的像素单元410的复位线RST电连接。像素单元410中的像素驱动电路100所接收的复位参考信号RESET由复位线RST提供。
如图5所示，反相器500还电连接到复位电平端VINIT和参考电平端VREF。反相器500被配置为在来自扫描线SL的栅极驱动信号GATE的控制下将来自复位电平端VINIT的复位电平或来自参考电平端VREF的参考电平提供到复位线RST。由此，通过复位线RST提供具有复位电平的复位参考信号或具有参考电平的复位参考信号。
在一些实施例中，复位电平是使驱动晶体管Md导通的电平(例如，在上述实施例中的低电平VL)，参考电平REF略大于数据信号DATA的最大电压值与驱动晶体管的阈值电压Vth之和。
图6示出了反相器500的一个示例结构。
反相器500包括第一反相晶体管Mi1和第二反相晶体管Mi2。第一反相晶体管Mi1的控制极电连接到扫描线SL，第一极电连接到复位电平端VINIT以接收复位电平，第二极电连接到复位线RST。第二反相晶体管Mi2的控制极电连接到扫描线SL，第一极电连接到参考电平端VREF以接收参考电平，第二极电连接到复位线RST。根据实施例，第一反相晶体管Mi1可以为N型晶体管，第二反相晶体管Mi2可以为P型晶体管。
通过图6所示的反相器的示例电路，能够在来自扫描线的栅极驱动信号的基础上得到像素驱动电路中所需要的复位参考信号，栅极驱动信号和复位参考信号的相位可以参考图3A所示的时序图。
图7示出了根据本公开实施例的像素驱动电路的驱动方法700的流程图。该驱动方法700可以用于驱动根据图1或图2所示的像素驱动电路100。
如图7所示，在步骤S710中，在第一时段，提供具有第一电平的发光控制信号，提供具有第二电平的栅极驱动信号，提供具有复位电平的复位参考信号，以及提供具有第二电平的数据信号。
在步骤S720中，在第二时段，提供具有第一电平的发光控制信号和栅极驱动信号，提供具有参考电平的复位参考信号，以及提供具有第一电平的数据信号。
在步骤S730中，在第三时段，提供具有第二电平的发光控制信号和栅极驱动信号，提供具有参考电平的复位参考信号，以及提供具有第二电平的数据信号。
其中，第一电平是与使驱动晶体管关断的电平相对应的电平，第二电平是与使驱动晶体管导通的电平相对应的电平。具有第一电平的数据信号指代可以用于显示的有效的数据信号的电平。
在一些实施例中，参考电平可以等于第一电平。
上面的实施例已经结合图2对方法700的不同驱动过程阶段进行了描述，在此不再赘述。
以上的详细描述通过使用示意图、流程图和/或示例，已经阐述了众多实施例。在这种示意图、流程图和/或示例包含一个或多个功能和/或操作的情况下，本领域技术人员应理解，这种示意图、流程图或示例中的每一功能和/或操作可以通过各种结构、硬件、软件、固件或实质上它们的任意组合来单独和/或共同实现。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例 性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (16)

  1. 一种像素驱动电路，被配置为驱动发光元件发光，所示像素驱动电路包括：
    驱动子电路，被配置为产生用于使发光元件发光的电流；
    发光控制子电路，所述发光控制子电路电连接到所述驱动子电路和所述发光元件的第一端，并且与所述驱动子电路电连接于第一节点和第二节点，所述发光控制子电路被配置为接收发光控制信号，并在所述发光控制信号的控制下，将所述用于使发光元件发光的电流提供到所述发光元件的第一端；
    驱动控制子电路，电连接到所述驱动子电路，被配置为接收数据信号和栅极驱动信号，并在所述栅极驱动信号的控制下，将所述数据信号提供到所述驱动子电路；
    复位子电路，电连接到所述驱动子电路和所述发光元件的第一端，并且与所述驱动子电路电连接于第三节点，被配置为接收复位参考信号，并在所述复位参考信号的控制下，使用所述复位参考信号对所述第三节点和所述发光元件的第一端进行复位。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管、第一晶体管和存储电容，其中，
    所述驱动晶体管的控制极电连接所述第三节点，第一极电连接所述第一节点，第二极电连接所述第二节点；
    所述第一晶体管的控制极电连接为接收所述栅极驱动信号，第一极电连接所述第二节点，第二极电连接所述第三节点；以及
    所述存储电容的第一端电连接为接收第一电压信号，第二端电连接所述第三节点。
  3. 根据权利要求2所述的像素驱动电路，其中，所述驱动控制子电路包括第二晶体管，其中
    所述第二晶体管的控制极电连接为接收所述栅极驱动信号，第一极电连接为接收所述数据信号，第二极电连接所述第一节点。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一晶体管和所述第二晶体管为N型晶体管。
  5. 根据权利要求3所述的像素驱动电路，其中，所述发光控制子电路包括第三晶体管和第四晶体管，其中
    所述第三晶体管的控制极电连接为接收所述发光控制信号，第一极电连接为接收 所述第一电压信号，第二极电连接所述第一节点；
    所述第四晶体管的控制极电连接为接收所述发光控制信号，第一极电连接所述第二节点，第二极电连接到所述发光元件的第一端。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第三晶体管和所述第四晶体管均为P型晶体管或均为N型晶体管。
  7. 根据权利要求5所述的像素驱动电路，其中，所述复位子电路包括第五晶体管和第六晶体管，其中
    所述第五晶体管的控制极和第一极共同电连接为接收所述复位参考信号，第二极电连接所述第三节点，
    所述第六晶体管的控制极和第一极共同电连接为接收所述复位参考信号，第二极电连接到所述发光元件的第一端。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第五晶体管和所述第六晶体管均为P型晶体管或均为N型晶体管。
  9. 根据权利要求7所述的像素驱动电路，所述第一晶体管和所述第二晶体管是IGZO晶体管，所述第五晶体管和所述第六晶体管是LTPS晶体管。
  10. 一种显示面板，包括：
    多条扫描线；
    多条数据线，与所述多条扫描线交叉设置；以及
    多个像素单元，以矩阵的形式设置在每个数据线和每个扫描线交叉处，并与对应的数据线和扫描线电连接，每个像素单元包括发光元件和根据权利要求1-9中任一项所述的像素驱动电路，
    其中，所述像素驱动电路所接收的数据信号由所述像素单元的对应数据线提供，所述像素驱动电路所接收的栅极驱动信号由所述像素单元的对应扫描线提供。
  11. 根据权利要求10所述的显示面板，还包括多条发光控制线，所述多条发光控制线与所述多条扫描线或所述多条数据线平行地布置，并与所述多条扫描线或所述多条数据线分别电连接到相同的像素单元，
    其中，所述像素驱动电路所接收的发光控制信号由所述像素单元的对应发光控制线提供。
  12. 根据权利要求10所述的显示面板，其中，所述显示面板还包括多个反相器， 分别与所述多个扫描线一一对应地电连接，其中，
    所述反相器的输入端与对应的扫描线电连接，所述反相器的输出端与按照扫描顺序位于所述对应的扫描线之后的扫描线所驱动的像素单元的复位线电连接，其中，包括在所述像素单元中的像素驱动电路所接收的复位参考信号线由所述复位线提供，
    所述反相器被配置为在所述栅极驱动信号的控制下向所述复位线的输出提供具有复位电平的复位参考信号或具有参考电平的复位参考信号。
  13. 根据权利要求12所述的显示面板，其中，所述反相器包括第一反相晶体管和第二反相晶体管，其中，
    所述第一反相晶体管的控制极电连接到所述扫描线，第一极电连接为接收所述复位电平，第二极电连接到所述复位线，
    所述第二反相晶体管的控制极电连接到所述扫描线，第一极电连接为接收所述参考电平，第二极电连接到所述复位线，
    其中，所述第一反相晶体管为N型晶体管，所述第二反相晶体管为P型晶体管。
  14. 根据权利要求12所述的显示面板，其中，所述复位电平是使驱动晶体管导通所需的电平，所述参考电平等于使所述驱动晶体管关断所需的电平。
  15. 一种对根据权利要求1-9中的任一项所述的像素驱动电路进行驱动的方法，包括：
    在第一时段，提供具有第一电平的发光控制信号，提供具有第二电平的栅极驱动信号，提供具有复位电平的复位参考信号；
    在第二时段，提供具有第一电平的发光控制信号和栅极驱动信号，提供具有参考电平的复位参考信号；
    在第三时段，提供具有第二电平的发光控制信号和栅极驱动信号，提供具有参考电平的复位参考信号。
  16. 根据权利要求15所述的方法，其中，所述参考电平等于所述第一电平。
PCT/CN2020/075797 2019-03-29 2020-02-19 像素驱动电路及其驱动方法以及显示面板 WO2020199774A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910247440.XA CN109859686B (zh) 2019-03-29 2019-03-29 像素驱动电路及其驱动方法以及显示面板
CN201910247440.X 2019-03-29

Publications (1)

Publication Number Publication Date
WO2020199774A1 true WO2020199774A1 (zh) 2020-10-08

Family

ID=66902456

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/075797 WO2020199774A1 (zh) 2019-03-29 2020-02-19 像素驱动电路及其驱动方法以及显示面板

Country Status (2)

Country Link
CN (1) CN109859686B (zh)
WO (1) WO2020199774A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109859686B (zh) * 2019-03-29 2021-03-23 京东方科技集团股份有限公司 像素驱动电路及其驱动方法以及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2438363A1 (en) * 2003-08-28 2005-02-28 Ignis Innovation Inc. A pixel circuit for amoled displays
CN1822083A (zh) * 2005-01-21 2006-08-23 株式会社半导体能源研究所 半导体器件、显示设备和电子装置
CN1901008A (zh) * 2005-07-21 2007-01-24 精工爱普生株式会社 电子电路、电子装置及其驱动方法、电光学装置及电子机器
US20150294616A1 (en) * 2014-04-10 2015-10-15 Samsung Display Co., Ltd. Organic light-emitting diode display and method of driving the same
CN105427806A (zh) * 2016-01-06 2016-03-23 京东方科技集团股份有限公司 像素电路、显示基板及显示装置、驱动显示基板的方法
CN109859686A (zh) * 2019-03-29 2019-06-07 京东方科技集团股份有限公司 像素驱动电路及其驱动方法以及显示面板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154239B (zh) * 2017-06-30 2019-07-05 武汉天马微电子有限公司 一种像素电路、驱动方法、有机发光显示面板及显示装置
CN107993612A (zh) * 2017-12-21 2018-05-04 信利（惠州）智能显示有限公司 一种amoled像素驱动电路及像素驱动方法
CN108389549B (zh) * 2018-01-30 2019-09-24 上海天马微电子有限公司 像素电路及其驱动方法、显示面板及其驱动方法
CN109003586B (zh) * 2018-08-03 2020-03-17 武汉华星光电半导体显示技术有限公司 一种像素驱动电路及液晶显示面板
CN109119027B (zh) * 2018-09-10 2020-06-16 京东方科技集团股份有限公司 像素电路及其驱动方法以及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2438363A1 (en) * 2003-08-28 2005-02-28 Ignis Innovation Inc. A pixel circuit for amoled displays
CN1822083A (zh) * 2005-01-21 2006-08-23 株式会社半导体能源研究所 半导体器件、显示设备和电子装置
CN1901008A (zh) * 2005-07-21 2007-01-24 精工爱普生株式会社 电子电路、电子装置及其驱动方法、电光学装置及电子机器
US20150294616A1 (en) * 2014-04-10 2015-10-15 Samsung Display Co., Ltd. Organic light-emitting diode display and method of driving the same
CN105427806A (zh) * 2016-01-06 2016-03-23 京东方科技集团股份有限公司 像素电路、显示基板及显示装置、驱动显示基板的方法
CN109859686A (zh) * 2019-03-29 2019-06-07 京东方科技集团股份有限公司 像素驱动电路及其驱动方法以及显示面板

Also Published As

Publication number Publication date
CN109859686A (zh) 2019-06-07
CN109859686B (zh) 2021-03-23

Similar Documents

Publication Publication Date Title
CN110223636B (zh) 像素驱动电路及其驱动方法、显示装置
WO2023005621A1 (zh) 像素电路及其驱动方法、显示面板
US10700146B2 (en) Pixel and organic light-emitting display device having the same
TWI806283B (zh) 像素、級電路以及具有像素和級電路之有機發光顯示裝置
WO2020062802A1 (zh) 显示面板及像素电路的驱动方法
WO2018188390A1 (zh) 像素电路及其驱动方法、显示装置
CN112489599B (zh) Amoled像素驱动电路、驱动方法及显示面板
WO2016145693A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2016165529A1 (zh) 像素电路及其驱动方法、显示装置
WO2016095477A1 (zh) 像素驱动电路、像素驱动方法和显示装置
WO2023005694A1 (zh) 像素电路及其驱动方法、显示面板
WO2016119304A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
WO2016011711A1 (zh) 像素电路、像素电路的驱动方法和显示装置
WO2018228202A1 (zh) 像素电路、像素驱动方法和显示装置
WO2018161553A1 (zh) 显示装置、显示面板、像素驱动电路和驱动方法
CN110660360A (zh) 像素电路及其驱动方法、显示面板
WO2017117938A1 (zh) 像素驱动电路、像素驱动方法和显示装置
WO2015180352A1 (zh) 像素电路及其驱动方法、有机发光显示面板及显示装置
WO2020143234A1 (zh) 像素驱动电路、像素驱动方法和显示装置
WO2016161896A1 (zh) 像素驱动电路、显示装置和像素驱动方法
CN108777131B (zh) Amoled像素驱动电路及驱动方法
CN106504701B (zh) Amoled像素驱动电路及像素驱动方法
WO2015003434A1 (zh) 发光二极管像素单元电路、其驱动方法及显示面板
WO2017012075A1 (zh) 像素电路及其驱动方法、显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20781949

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20781949

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03.02.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 20781949

Country of ref document: EP

Kind code of ref document: A1