WO2021189313A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021189313A1
WO2021189313A1 PCT/CN2020/081168 CN2020081168W WO2021189313A1 WO 2021189313 A1 WO2021189313 A1 WO 2021189313A1 CN 2020081168 W CN2020081168 W CN 2020081168W WO 2021189313 A1 WO2021189313 A1 WO 2021189313A1
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WO
WIPO (PCT)
Prior art keywords
sub
base substrate
pixel
line
auxiliary
Prior art date
Application number
PCT/CN2020/081168
Other languages
English (en)
French (fr)
Inventor
李慧君
刘庭良
尚庭华
杨慧娟
杨路路
姜晓峰
屈忆
张鑫
张猛
王俊喜
王思雨
白露
代洁
张昊
王予
王梦奇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20926764.0A priority Critical patent/EP4109440A4/en
Priority to CN202080000377.0A priority patent/CN113785348B/zh
Priority to US17/755,304 priority patent/US20220367602A1/en
Priority to PCT/CN2020/081168 priority patent/WO2021189313A1/zh
Publication of WO2021189313A1 publication Critical patent/WO2021189313A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • other electroluminescent diodes have the advantages of self-luminescence, low energy consumption, etc., which are the most important in the application research field of electroluminescent display devices. One of the hot spots.
  • the gate conductive layer is located on the base substrate, and the gate conductive layer includes: a plurality of scan lines;
  • the first insulating layer is located on the gate conductive layer
  • the first conductive layer is located on a side of the first insulating layer away from the base substrate, and the first conductive layer includes a plurality of data lines; wherein, the plurality of data lines are arranged along a first direction;
  • An interlayer insulating layer located on the side of the first conductive layer away from the base substrate;
  • the auxiliary power line includes: a plurality of sub-auxiliary power lines and a plurality of auxiliary conduction lines; wherein the plurality of sub-auxiliary power lines are arranged along the first direction and extend along the second direction, and two adjacent sub-power lines are at least partially
  • the auxiliary power lines are electrically connected by at least one of the auxiliary conducting wires; the first direction is different from the second direction;
  • the orthographic projection of at least one of the plurality of auxiliary conductive lines on the base substrate and the orthographic projection of the scan line on the base substrate do not overlap.
  • the plurality of scan lines include a first scan line and a second scan line; wherein, the second scan line includes a scan line portion and a plurality of protrusions that are electrically connected to each other; The scan line portion extends in the first direction, and the protruding portion extends in the second direction;
  • the display panel further includes: a plurality of sub-pixels; at least one of the plurality of sub-pixels includes a pixel driving circuit; the pixel driving circuit includes a transistor;
  • the protrusion serves as the gate of the transistor, and the orthographic projection of each auxiliary conduction line on the base substrate and the orthographic projection of the protrusion on the base substrate do not overlap.
  • the pixel driving circuit includes: a driving transistor and a threshold compensation transistor; wherein, the threshold compensation transistor includes: a first sub-compensation transistor and a second sub-compensation transistor;
  • the gate of the first sub-compensation transistor is electrically connected to the second scan line
  • the first electrode of the first sub-compensation transistor is electrically connected to the gate of the drive transistor
  • the second pole is electrically connected to the first pole of the second sub-compensation transistor
  • the gate of the second sub-compensation transistor is electrically connected to the second scan line, and the second electrode of the second sub-compensation transistor is electrically connected to the second electrode of the driving transistor;
  • the protrusion serves as the gate of the first sub-compensation transistor
  • the part of the scan line part serves as the gate of the second sub-compensation transistor.
  • the display panel further includes: a plurality of repeating units; wherein, the repeating unit includes a plurality of sub-pixels; and the plurality of repeating units are arranged along the first direction to form A row of repeating units, and the row of repeating units is arranged along the second direction;
  • the auxiliary conduction line includes a first auxiliary conduction line; wherein a part of two adjacent sub-auxiliary power lines are electrically connected by at least one of the first auxiliary conduction lines;
  • One row of repeating units corresponds to one first scan line, one second scan line, and at least one first auxiliary conduction line;
  • the orthographic projection of the first auxiliary conduction line on the base substrate is located.
  • the protrusions of the first scan line and the second scan line are between the orthographic projection of the base substrate.
  • the display panel further includes:
  • a planarization layer located on the side of the second conductive layer away from the base substrate;
  • the first electrode layer is located on the side of the planarization layer away from the base substrate, and the first electrode layer includes a plurality of first electrodes spaced apart from each other; wherein, one sub-pixel is provided with one first electrode
  • the orthographic projection of the first auxiliary conducting line on the base substrate and the orthographic projection of the first electrode on the base substrate do not overlap.
  • the sub-pixels in the multiple repeating units include: a first-color sub-pixel, a second-color sub-pixel pair, and a third-color sub-pixel arranged along the first direction;
  • the second-color sub-pixel pair includes two second-color sub-pixels arranged along the second direction; and the repeating units in two adjacent repeating unit rows are arranged in a staggered manner.
  • each of the second color sub-pixel pairs corresponds to one of the first auxiliary conduction lines
  • the orthographic projection of the first auxiliary conductive line on the base substrate is located between the two first electrodes in the corresponding second color sub-pixel pair and the orthographic projection of the base substrate.
  • the pixel driving circuit further includes a data writing transistor; wherein, the data writing transistor in a column of sub-pixels is electrically connected to one of the data lines;
  • the orthographic projection of the first auxiliary conduction line corresponding to the second color sub-pixel pair on the base substrate and the first color sub-pixel The data lines electrically connected to the color sub-pixels have an overlapping area on the orthographic projection of the base substrate.
  • the data writing transistor is electrically connected to the data line through a first connection via
  • the orthographic projection of the first auxiliary conduction line corresponding to the second color sub-pixel pair on the base substrate and the first color sub-pixel has an overlapping area on the orthographic projection of the base substrate.
  • the pixel driving circuit further includes a first reset transistor;
  • the display panel further includes a plurality of first reset signal lines; wherein, the first reset transistor in each of the sub-pixels Electrically connected to the first reset signal line through a second connection via;
  • the second-color sub-pixel pair includes: a first second-color sub-pixel and a second second-color sub-pixel arranged in a second direction; the first auxiliary conduction line is on the front side of the base substrate.
  • the projection and the second connection via in the second second color sub-pixel have an overlapping area at the edge of the orthographic projection of the base substrate.
  • the first auxiliary conduction line extends in a linear shape along the first direction.
  • the auxiliary conduction line further includes a second auxiliary conduction line; wherein the remaining part passes through at least one of the second auxiliary power lines between two adjacent sub-auxiliary power lines.
  • the lead wire is electrically connected.
  • the The first electrode in the first color sub-pixel is arranged between the orthographic projection of the base substrate and the first electrode in the third color sub-pixel on the orthographic projection of the base substrate.
  • the The orthographic projection of the second auxiliary conduction line on the base substrate is relative to the orthographic projection of the first electrode in the first color sub-pixel on the base substrate, which is close to the first in the third color sub-pixel.
  • the orthographic projection of the electrode on the base substrate is relative to the orthographic projection of the electrode on the base substrate.
  • the first conductive layer further includes a main power line; wherein, the main power line and the data line are spaced apart;
  • the interlayer insulating layer has a first power via
  • the main power line and the auxiliary power line are electrically connected to each other through the first power supply via hole.
  • the orthographic projection of the main power line on the base substrate and the orthographic projection of the auxiliary power line on the base substrate have an overlapping area.
  • the sub-auxiliary power line and the auxiliary conduction line substantially form a grid structure.
  • the auxiliary power line is configured as a power line that transmits a driving voltage.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of the structure of some display panels provided by the embodiments of the present disclosure.
  • FIG. 2a is a schematic diagram of a circuit structure in some sub-pixels provided by an embodiment of the present disclosure
  • FIG. 2b is a timing diagram of some signals provided by the embodiments of the disclosure.
  • FIG. 3 is a schematic diagram of a layout structure in some sub-pixels provided by an embodiment of the disclosure.
  • 4a is a schematic diagram of the layout structure of the semiconductor layers in some sub-pixels provided by the embodiments of the present disclosure
  • 4b is a schematic diagram of the layout structure of the gate conductive layer in some sub-pixels provided by the embodiments of the present disclosure
  • 4c is a schematic diagram of the layout structure of capacitor electrode layers in some sub-pixels provided by the embodiments of the present disclosure.
  • 4d is a schematic diagram of the layout structure of the first conductive layer in some sub-pixels provided by the embodiments of the present disclosure
  • 4e is a schematic diagram of the layout structure of the second conductive layer in some sub-pixels provided by the embodiments of the present disclosure
  • Fig. 5 is a schematic cross-sectional structure view along the AA' direction in the schematic layout structure shown in Fig. 3;
  • FIG. 6 is a schematic diagram of a layout structure of multiple sub-pixels in a display panel provided by an embodiment of the disclosure
  • FIG. 7 is a schematic diagram of a layout structure of a semiconductor layer in a plurality of sub-pixels in a display panel provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a layout structure of a gate conductive layer in a plurality of sub-pixels in a display panel provided by an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of the layout structure of capacitor electrode layers in a plurality of sub-pixels in a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a layout structure of a first conductive layer in a plurality of sub-pixels in a display panel provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a layout structure of a second conductive layer in a plurality of sub-pixels in a display panel provided by an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a layout structure of a first electrode layer in a plurality of sub-pixels in a display panel provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a layout structure of a first electrode layer in a repeating unit in a display panel provided by an embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of the layout structure of still other multiple sub-pixels in the display panel provided by the embodiments of the present disclosure.
  • the display panel provided by an embodiment of the present disclosure may include: a base substrate 1000.
  • at least one sub-pixel spx of the plurality of sub-pixels spx may include: a pixel driving circuit 0121 and a light emitting device 0120.
  • the pixel driving circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the first electrode of the light-emitting device 0120.
  • a corresponding voltage is applied to the second electrode of the light-emitting device 0120 to drive the light-emitting device 0120 to emit light.
  • the pixel driving circuit 0121 may include: a driving control circuit 0122, a first light emission control circuit 0123, a second light emission control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129 .
  • the drive control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the driving control circuit 0122 is configured to provide the light emitting device 0120 with a driving current for driving the light emitting device 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the first light emission control circuit 0123 is configured to realize the connection between the drive control circuit 0122 and the first voltage terminal VDD being turned on or off.
  • the second light emitting control circuit 0124 is electrically connected to the second end of the driving control circuit 0122 and the first electrode of the light emitting device 0120. And the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting device 0120 to be turned on or off.
  • the data writing circuit 0126 is electrically connected to the first end of the drive control circuit 0122.
  • the second light emission control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scan line GA2.
  • the storage circuit 0127 is electrically connected to the control terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals.
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the drive control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation for the drive control circuit 0122.
  • the reset circuit 0129 is electrically connected to the control terminal of the drive control circuit 0122 and the first electrode of the light emitting device 0120. And the reset circuit 0129 is configured to reset the control terminal of the drive control circuit 0122 and the first electrode of the light emitting device 0120 under the control of the signal on the gate line GA1.
  • the light emitting device 0120 can be configured as an electroluminescent diode, such as at least one of OLED and QLED.
  • the optical device 0120 may include a first electrode, a light-emitting function layer, and a second electrode that are stacked.
  • the first electrode may be an anode
  • the second electrode may be a cathode.
  • the light-emitting functional layer may include a light-emitting layer.
  • the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • the light emitting device 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited here.
  • the drive control circuit 0122 includes a drive transistor T1
  • the control end of the drive control circuit 0122 includes the gate of the drive transistor T1
  • the first end of the drive control circuit 0122 includes the first end of the drive transistor T1.
  • the second terminal of the driving control circuit 0122 includes the second terminal of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2.
  • the storage circuit 0127 includes a storage capacitor CST.
  • the threshold compensation circuit 0128 includes a threshold compensation transistor T3.
  • the first light emission control circuit 0123 includes a first light emission control transistor T4.
  • the second light emission control circuit 0124 includes a second light emission control transistor T5.
  • the reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.
  • the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1
  • the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal
  • the data writing transistor The gate of T2 is configured to be electrically connected to the second scan line GA2 to receive a scan signal.
  • the first electrode of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor T1.
  • the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1
  • the gate of the threshold compensation transistor T3 is configured to be connected to the second electrode.
  • the scan line GA2 is electrically connected to receive the scan signal.
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset signal line VINIT1 to receive the first reset signal
  • the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1
  • the first reset The gate of the transistor T6 is configured to be electrically connected to the first scan line GA1 to receive a control signal.
  • the first electrode of the second reset transistor T7 is configured to be electrically connected to the second reset signal line VINIT2 to receive the second reset signal
  • the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device 0120
  • the gate of the reset transistor T7 is configured to be electrically connected to the first scan line GA1 to receive a control signal.
  • the first electrode of the first light-emission control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light-emission control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light-emission control transistor T4 is It is configured to be electrically connected to the light emission control line EM to receive the light emission control signal.
  • the first electrode of the second light emission control transistor T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the second light emission control transistor T5 is electrically connected to the first electrode of the light emitting device 0120
  • the gate of the second light emission control transistor T5 The pole is configured to be electrically connected with the emission control line EM to receive the emission control signal.
  • the second electrode of the light emitting device 0120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the above-mentioned transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • the threshold compensation transistor T3 may include: a first sub-compensation transistor T31 and a second sub-compensation transistor T32; wherein,
  • the gate of the first sub-compensation transistor T31 is electrically connected to the second scan line GA2, the first electrode of the first sub-compensation transistor T31 is electrically connected to the gate of the driving transistor T1, and the second electrode of the first sub-compensation transistor T31 is electrically connected to the second scan line GA2.
  • the first pole of the two sub-compensation transistor T32 is electrically connected;
  • the gate of the second sub-compensation transistor T32 is electrically connected to the second scan line GA2, and the second electrode of the second sub-compensation transistor T32 is electrically connected to the second electrode of the driving transistor T1.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the first reset signal line VINIT1 and the second reset signal line VINIT2 are the same signal line.
  • the signal timing diagram corresponding to the pixel driving circuit shown in FIG. 2a is shown in FIG. 2b.
  • the working process of the pixel driving circuit has three stages: T10 stage, T20 stage, and T30 stage.
  • ga1 represents the signal transmitted on the first scan line GA1
  • ga2 represents the signal transmitted on the second scan line GA2
  • em represents the signal transmitted on the light-emitting control line EM.
  • the signal ga1 controls the first reset transistor T6 and the second reset transistor T7 to conduct.
  • the turned-on first reset transistor T6 provides the signal transmitted on the first reset signal line VINIT1 to the gate of the driving transistor T1 to reset the gate of the driving transistor T1.
  • the turned-on second reset transistor T7 provides the signal transmitted on the first reset signal line VINIT1 to the first electrode of the light-emitting device 0120 to reset the first electrode of the light-emitting device 0120.
  • the signal ga2 controls the data writing transistor T2, the first sub-compensation transistor T31, and the second sub-compensation transistor T32 to be turned off.
  • the signal em controls both the first light-emission control transistor T4 and the second light-emission control transistor T5 to be turned off.
  • the signal ga2 controls the data writing transistor T2, the first sub-compensation transistor T31 and the second sub-compensation transistor T32 to be turned on, so that the data signal transmitted on the data line VD can charge the gate of the driving transistor T1 , So that the voltage of the gate of the driving transistor T1 becomes: Vdata+
  • Vth represents the threshold voltage of the driving transistor T1
  • Vdata represents the voltage of the data signal.
  • the signal ga1 controls both the first reset transistor T6 and the second reset transistor T7 to be turned off.
  • the signal em controls both the first light-emission control transistor T4 and the second light-emission control transistor T5 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on.
  • the turned-on first light-emitting control transistor T4 provides the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor T1, so that the voltage of the first pole of the driving transistor T1 is Vdd.
  • the driving transistor T1 generates a driving current according to its gate voltage Vdata+
  • the driving current is provided to the light-emitting device 0120 through the turned-on second light-emitting control transistor T5 to drive the light-emitting device 0120 to emit light.
  • the signal ga1 controls both the first reset transistor T6 and the second reset transistor T7 to be turned off.
  • the signal ga2 controls the data writing transistor T2, the first sub-compensation transistor T31, and the second sub-compensation transistor T32 to turn off.
  • the pixel driving circuit in the sub-pixel may not only have the structure shown in FIG. 2a, but also may have a structure including other numbers of transistors, which is not limited in the embodiment of the present disclosure. .
  • FIG. 3 is a schematic diagram of a layout structure of a pixel driving circuit provided by some embodiments of the present disclosure.
  • 4a to 4e are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the disclosure. Among them, the examples shown in FIGS. 3 to 4e take a pixel driving circuit of a sub-pixel spx as an example.
  • the main power supply line VDD1 is electrically connected to the first power supply terminal VDD to input a driving voltage (ie, the first voltage) to the first power supply terminal VDD.
  • a plurality of data lines VD may be arranged along the first direction F1.
  • the semiconductor layer 500 of the pixel driving circuit 0121 is shown.
  • the semiconductor layer 500 may be formed by patterning a semiconductor material.
  • the semiconductor layer 500 can be used to make the aforementioned driving transistor T1, data writing transistor T2, first sub-threshold compensation transistor T31, second sub-threshold compensation transistor T32, first light-emission control transistor T4, second light-emission control transistor T5, first Active layers of the reset transistor T6 and the second reset transistor T7, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • Figure 4a illustrates the channel region T1-A of the driving transistor T1, the channel region T2-A of the data writing transistor T2, the first channel region T31-A of the first sub-threshold compensation transistor T31, and the second channel region T31-A of the first sub-threshold compensation transistor T31.
  • the second channel region T32-A of the sub-threshold compensation transistor T32, the channel region T4-A of the first light-emission control transistor T4, the channel region T5-A of the second light-emission control transistor T5, and the channel of the first reset transistor T6 The track area T6-A, and the channel area T7-A of the second reset transistor T7.
  • the active layer of each transistor may be integrally provided.
  • the semiconductor layer 500 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • a first gate insulating layer 610 is formed on the aforementioned semiconductor layer 500 to protect the aforementioned semiconductor layer 500.
  • the gate conductive layer 300 of the pixel driving circuit 0121 is shown.
  • the gate conductive layer 300 is disposed on the side of the first gate insulating layer 610 away from the base substrate 1000 so as to be insulated from the semiconductor layer 500.
  • the gate conductive layer 300 may include: a plurality of scan lines, a second electrode CC2a of the storage capacitor CST, a light emission control line EM, and a driving transistor T1, a data writing transistor T2, a first sub-threshold compensation transistor T31, and a second sub-threshold compensation transistor T32, the gates of the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7.
  • the plurality of scan lines include, for example, a plurality of first gate lines GA1 and a plurality of second gate lines GA2.
  • the gate of the data writing transistor T2 may be the first portion where the second scan line GA2 overlaps the semiconductor layer 500 (for example, the groove between the second scan line GA2 and the data writing transistor T2).
  • the gate of the first light-emission control transistor T4 may be the first part where the light-emission control line EM overlaps the semiconductor layer 500
  • the gate of the second light-emission control transistor T5 may be the light-emission control Line EM overlaps the second part of the semiconductor layer 500
  • the gate of the first reset transistor T6 is the first part where the first scan line GA1 overlaps the semiconductor layer 500
  • the gate of the second reset transistor T7 is the first scan line GA1 and
  • the threshold compensation transistor T3 may be a thin film transistor with a double gate structure
  • the gate of the second sub-threshold compensation transistor T32 may be the second part where the second scan line GA2 overlaps the semiconductor
  • each dashed rectangular frame in FIG. 4a shows each part where the gate conductive layer 300 and the semiconductor layer 500 overlap in the sub-pixel spx.
  • the first scan line GA1, the second scan line GA2, and the emission control line EM are arranged along the second direction F2, and the orthographic projection of the second scan line GA2 on the base substrate 1000 It is located between the orthographic projection of the first scan line GA1 on the base substrate 1000 and the orthographic projection of the light emission control line EM on the base substrate 1000.
  • the orthographic projection of the second pole CC2a of the storage capacitor CST on the base substrate 1000 is located on the orthographic projection of the second scan line GA2 on the base substrate 1000
  • the emission control line EM is between the orthographic projections of the base substrate 1000.
  • the orthographic projection of the protrusion 320 protruding from the second scan line GA2 on the base substrate 1000 is on the side of the orthographic projection of the second scan line GA2 on the base substrate 1000 away from the orthographic projection of the light emission control line EM on the base substrate 1000.
  • the gate of the data writing transistor T2 in the second direction F2, the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the second reset transistor
  • the gates of T7 are all located on the first side of the gate of the driving transistor T1
  • the gates of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the first direction F1.
  • a second gate insulating layer 620 is formed on the aforementioned gate conductive layer 300 to protect the aforementioned gate conductive layer 300.
  • the capacitor electrode layer 400 of the pixel driving circuit 0121 is shown.
  • the capacitor electrode layer 400 is disposed on the side of the second gate insulating layer 620 away from the base substrate 1000.
  • the capacitor electrode layer 400 may include a first electrode CC1a of the storage capacitor CST, a first reset signal line VINIT1, and a voltage stabilizing part 410.
  • the orthographic projection of the first pole CC1a of the storage capacitor CST on the base substrate 1000 and the orthographic projection of the second pole CC2a of the storage capacitor CST on the base substrate 1000 at least partially overlap to form the storage capacitor CST.
  • the orthographic projection of the voltage stabilizing portion 410 on the base substrate 1000 and the orthographic projection of the source region of the active layer of the data writing transistor T2 on the base substrate 1000 have an overlapping area.
  • the orthographic projection of the voltage stabilizing portion 410 on the base substrate 1000 and the orthographic projection of the drain region of the active layer of the first reset transistor T6 on the base substrate 1000 have an overlapping area.
  • the orthographic projection of the voltage stabilizing portion 410 on the base substrate 1000 is adjacent to the first channel region T31-A of the first sub-threshold compensation transistor T31 and the second channel region T32- of the second sub-threshold compensation transistor T32.
  • the conductor area between A has an overlapping area in the orthographic projection of the base substrate 1000 to reduce the leakage current caused by the photoelectric effect.
  • an interlayer dielectric layer 630 is formed on the aforementioned capacitor electrode layer 400 to protect the aforementioned capacitor electrode layer 400.
  • the first conductive layer 100 of the pixel driving circuit 0121 is shown.
  • the first conductive layer 100 is disposed on the side of the interlayer dielectric layer 630 away from the base substrate 1000.
  • the first conductive layer 100 may include: a data line VD, a main power supply line VDD1, and bridge portions 341a, 342a, and 343a. Among them, the data line VD and the main power line VDD1 are arranged at intervals.
  • an interlayer insulating layer 640 is formed on the above-mentioned first conductive layer 100 to protect the above-mentioned first conductive layer 100.
  • the second conductive layer 200 of the pixel driving circuit 0121 is shown.
  • the second conductive layer 200 is disposed on the side of the interlayer insulating layer 640 away from the base substrate 1000.
  • the second conductive layer 200 may include an auxiliary power supply line VDD2 and a transfer part 351a.
  • the interlayer insulating layer 640 has a first power supply via, and the main power supply line VDD1 and the auxiliary power supply line VDD2 are electrically connected to each other through the first power supply via to achieve the effect of reducing resistance.
  • the orthographic projection of the main power line VDD on the base substrate 1000 and the orthographic projection of the auxiliary power line VDD2 on the base substrate 1000 have overlapping areas.
  • the auxiliary power line may be configured as a power line that transmits the driving voltage (ie, the first voltage).
  • Fig. 5 is a schematic cross-sectional view of the layout structure shown in Fig. 3 along the AA' direction.
  • a first gate insulating layer 610 is provided between the semiconductor layer 500 and the gate conductive layer 300
  • a second gate insulating layer 620 is provided between the gate conductive layer 300 and the capacitor electrode layer 400
  • the capacitor electrode layer 400 is between the first conductive layer 100
  • An interlayer dielectric layer 630 is provided therebetween
  • an interlayer insulation layer 640 is provided between the first conductive layer 100 and the second conductive layer 200.
  • a planarization layer 650 is provided on the side of the second conductive layer 200 away from the base substrate 1000
  • a first electrode layer 600 is provided on the side of the planarization layer 650 away from the base substrate 1000.
  • the first electrode layer 600 may include a plurality of first electrodes spaced apart from each other, and the first electrodes are electrically connected to the vias 351a through the planarization layer 650. It should be noted that FIG. 5 does not show the vias of the transfer portion 351 a and the planarization layer 650.
  • the sub-pixel spx may include a first connection via, a second connection via, a third connection via, and a fourth connection via; wherein, the first connection via penetrates the first gate The insulating layer 610, the second gate insulating layer 620, and the interlayer dielectric layer 630; the second connecting via hole penetrates the second gate insulating layer 620 and the interlayer dielectric layer 630; the third connecting via hole penetrates the interlayer dielectric layer 630; fourth The connection through hole penetrates the interlayer insulating layer 640.
  • the sub-pixel spx may include first connection through holes 381a, 382a, 384a, 387a, and 388a.
  • the sub-pixel spx may include a second connection via 385a.
  • the sub-pixel spx may include third connection vias 386a and 3832a.
  • the sub-pixel spx includes fourth connection through holes 385a and 3831a.
  • the data line VD is electrically connected to the source region T2-S of the data writing transistor T2 in the semiconductor layer 500 through at least one first connection via 381a.
  • the main power line VDD1 is electrically connected to the source region of the corresponding first light emitting control transistor T4 in the semiconductor layer 500 through at least one first connection via 382a.
  • One end of the bridge portion 341a is electrically connected to the drain region of the corresponding first sub-threshold compensation transistor T31 in the semiconductor layer 500 through at least one first connection via 384a.
  • the other end of the bridge portion 341a is electrically connected to the gate of the driving transistor T1 in the gate conductive layer 300 (ie, the second electrode CC2a of the storage capacitor CST) through at least one second connection via 385a.
  • One end of the bridge portion 342a is electrically connected to the first reset signal line VINIT1 through at least one third connection through hole 386a, and the other end of the bridge portion 342a is electrically connected to the first reset transistor T6 in the semiconductor layer 500 through at least one first connection through hole 387a.
  • the source region T6-S is electrically connected.
  • the bridge portion 343a is electrically connected to the drain region of the second light emission control transistor T5 in the semiconductor layer 500 through at least one first connection via 388a.
  • the main power line VDD1 is electrically connected to the first electrode CC1a of the storage capacitor CST in the capacitor electrode layer 400 through at least one third connection via 3832a.
  • the main power line VDD1 is also electrically connected to the auxiliary power line VDD2 in the second conductive layer 200 through at least one fourth connection via 3831a (ie, the first power via).
  • the adapter portion 351a is electrically connected to the bridge portion 343a through at least one fourth connection through hole 385a.
  • the first connection through holes 381a, 382a, 384a, 387a, and 388a in the sub-pixels may be provided with one or two or more respectively.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • one second connection through hole 385a in the sub-pixel may be provided, or two or more may be provided.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third connection through holes 386a and 3832a in the sub-pixels may be provided with one respectively, or two or more may be provided respectively.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the fourth connection through holes 385a and 3831a in the sub-pixels may be provided with one respectively, or two or more may be provided respectively.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the first scan line GA1, the second scan line GA2, and the first reset signal line VINIT1 are all located on the first side of the gate of the driving transistor T1.
  • the emission control line EM is located on the second side of the driving transistor T1.
  • the first scan line GA1, the second scan line GA2, and the emission control line EM may be located in the same layer (ie, the gate conductive layer 300).
  • the main power line VDD1 and the data line VD are located in the same layer (ie, the first conductive layer 100).
  • each sub-pixel spx is not limited to the examples shown in FIGS. 3 to 4e, and the positions of the above-mentioned transistors can be specifically set according to actual application requirements.
  • first direction F1 may be the row direction of the sub-pixels
  • second direction F2 may be the column direction of the sub-pixels
  • first direction F1 may also be the column direction of the sub-pixels
  • second direction F2 may be the row direction of the sub-pixels. In actual applications, it can be set according to actual application requirements, which is not limited here.
  • the scan line will have an area directly opposite to other conductive film layers, which will generate a coupling capacitance. Because the scan line transmits a signal that controls the turn-on or turn-off of the transistor. Due to the existence of the coupling capacitor, the loading of the signal transmitted on the scan line is large, which will cause the stability of the signal transmitted on the scan line to decrease, thereby affecting the display effect.
  • the first insulating layer may include: a second gate insulating layer 620 and an interlayer dielectric layer 630.
  • the auxiliary power line VDD2 may include: a plurality of sub-auxiliary power lines 110 and a plurality of auxiliary conduction lines 120; wherein, the plurality of sub-auxiliary power lines 110 are arranged along the first direction F1 and extend along the second direction F2, and are at least partially adjacent to each other.
  • the sub-auxiliary power lines 110 are electrically connected by at least one auxiliary conducting wire 120.
  • the orthographic projection of at least one of the plurality of auxiliary conductive lines 120 on the base substrate 1000 and the orthographic projection of the scan line on the base substrate 1000 do not overlap. This can avoid the direct area between the auxiliary conductive line 120 and the scan line, thereby avoiding the coupling capacitance between the auxiliary conductive line 120 and the scan line, thereby improving the stability of the signal transmitted on the scan line and improving the display effect .
  • the orthographic projection of at least one of the plurality of auxiliary conductive lines 120 on the base substrate 1000 and the orthographic projection of the first scan line GA1 on the base substrate 1000 do not overlap.
  • the orthographic projection of at least one of the plurality of auxiliary conductive lines 120 on the base substrate 1000 and the orthographic projection of the second scan line GA2 on the base substrate 1000 do not overlap.
  • the orthographic projection of each auxiliary conducting line 120 on the base substrate 1000 and the orthographic projection of the first scan line GA1 on the base substrate 1000 may not overlap.
  • the orthographic projection of each auxiliary conductive line 120 on the base substrate 1000 and the orthographic projection of the second scan line GA2 on the base substrate 1000 do not overlap.
  • the plurality of sub-auxiliary power lines 110 extend along the second direction F2, which means that these sub-auxiliary power lines 110 extend substantially along the second direction F2. In practical applications, these sub-auxiliary power lines 110 can be stretched in the second direction F2 in a zigzag manner.
  • the second scan line GA2 may include a scan line portion 310 and a plurality of protrusions 320 that are electrically connected to each other; wherein, the scan line portion 310 extends along the first direction F1 , The protrusion 320 extends along the second direction F2.
  • the protrusion 320 can be used as the gate of the transistor, and the orthographic projection of each auxiliary conductive line 120 on the base substrate 1000 and the orthographic projection of the protrusion 320 on the base substrate 1000 do not overlap. In this way, a direct facing area between the auxiliary conduction line 120 and the protrusion 320 can be avoided, and the coupling effect of the auxiliary conduction line 120 on the gate of the transistor can be further reduced.
  • the protrusion 320 may be used as the gate of the first sub-threshold compensation transistor T31, and the portion of the scan line portion 310 may be used as the gate of the second sub-compensation transistor T32.
  • the direct area between the auxiliary conduction line 120 and the protrusion 320 can be avoided, and the coupling effect of the auxiliary conduction line 120 on the gate of the first sub-threshold compensation transistor T31 can be further reduced.
  • the scan line portions 310 extend along the first direction F1, which means that these scan line portions 310 extend substantially along the first direction F1.
  • the scan line portions 310 can be extended to form a straight line, or the scan line portions 310 can also be bent and extended along the first direction F1.
  • the display panel further includes: a plurality of repeating units 001; wherein the repeating unit 001 includes a plurality of sub-pixels spx; and the plurality of repeating units 001 are arranged along the first direction F1 to form one
  • the repeating unit row 01 is arranged along the second direction F2.
  • the repeating units 001 in two adjacent repeating unit rows 01 are arranged in a staggered manner.
  • the repeating unit 001 in two adjacent repeating unit rows 01 differs by 1/2 the size of the repeating unit 001.
  • the size of one repeating unit 001 described above may be the distance between the centers of the same color sub-pixels in two adjacent repeating units 001 in the first direction F1.
  • the size of one repeating unit 001 mentioned above may be: the distance between the centers of the first electrodes of the first color sub-pixels 010 in two adjacent repeating units 001 in the second direction F2.
  • the repeating units in adjacent repeating unit rows are staggered from each other along the first direction, that is, adjacent repeating units in adjacent repeating unit rows have a certain offset along the first direction. Therefore, the sub-pixels of the same color in adjacent repeating unit rows are not aligned in the second direction.
  • the offset of the same color sub-pixels in adjacent rows of repeating units in the first direction may be half of the size of the repeating unit in the first direction.
  • the size of the repeating unit in the first direction may be the pitch of the repeating unit in the first direction.
  • the sub-pixels in the multiple repeating units include: first-color sub-pixels 110 and second-color sub-pixels arranged along the first direction F1
  • the second-color sub-pixel pair 020 may include: a first second-color sub-pixel 021 and a second second-color sub-pixel 022 arranged along the second direction F2.
  • the first color sub-pixel 010 is configured to emit light of the first color
  • the second color sub-pixels 021 and 022 are configured to emit light of the second color
  • the third color sub-pixel is configured to emit light of the third color.
  • the first color, the second color, and the third color can be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue.
  • the repeating unit 001 is an arrangement structure of red, green and blue sub-pixels.
  • the embodiments of the present disclosure include but are not limited to this.
  • the aforementioned first color, second color, and third color may also be other colors.
  • the auxiliary conduction line 120 may include a first auxiliary conduction line 121; wherein, two sub-auxiliary power lines 110 are partially adjacent to each other. They are electrically connected through at least one first auxiliary conducting wire 121.
  • part of two adjacent sub-auxiliary power lines 110 may be electrically connected through a first auxiliary conducting wire 121.
  • part of two adjacent sub-auxiliary power lines 110 may also be electrically connected by two first auxiliary conducting wires 121.
  • part of two adjacent sub-auxiliary power lines 110 are electrically connected by three or more first auxiliary conducting wires 121. This can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • one repeating unit row 01 can be made to correspond to one first scan line GA1, one second scan line GA2, and at least one first auxiliary conduction.
  • Line 121 Exemplarily, one repeating unit row 01 may correspond to one, two, three or more first auxiliary conducting wires 121, which can be designed and determined according to the requirements of the actual application environment, and is not limited herein.
  • the orthographic projection of an auxiliary conductive line 121 on the base substrate 1000 is located between the protrusion 320 of the first scan line GA1 and the second scan line GA2 on the orthographic projection of the base substrate 1000.
  • the first color sub-pixel 010 is provided with a first electrode 611
  • the first second color sub-pixel 021 is provided with a first electrode 621
  • the second second color sub-pixel 022 is provided with a first electrode 622.
  • the first electrode 631 is provided in the third color sub-pixel 030.
  • the orthographic projection of the first auxiliary conductive line 121 on the base substrate 1000 and the orthographic projection of the first electrode on the base substrate 1000 may not overlap.
  • each of the second color sub-pixel pairs corresponds to a first auxiliary conduction line 121.
  • each of the partial second color sub-pixel pairs may correspond to one first auxiliary conduction line 121. It is also possible to make each of all the second color sub-pixel pairs correspond to one first auxiliary conduction line 121. This can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • the orthographic projection of the first auxiliary conductive line 121 on the base substrate may be located in the corresponding second color sub-pixel pair
  • the two first electrodes are between the orthographic projection of the base substrate.
  • the orthographic projection of the first auxiliary conduction line 121 on the base substrate 1000 may be located in the first electrode 621 and the second second color sub-pixel 022 in the corresponding first second-color sub-pixel 021
  • the first electrode 622 is between the orthographic projections of the base substrate 1000.
  • the data writing transistors in a column of sub-pixels are electrically connected to a data line.
  • the data line VD electrically connected to the pixel 010 has an overlapping area on the orthographic projection of the base substrate 100.
  • the first auxiliary corresponding to the second color sub-pixel pair 020
  • the orthographic projection of the conductive line 121 on the base substrate 1000 and the orthographic projection of the first connection via in the first color sub-pixel 010 on the base substrate 1000 have an overlapping area.
  • the first connection via 381a serves as the first connection via.
  • the first reset transistor in each sub-pixel is electrically connected to the first reset signal line through the second connection via.
  • the edge of the orthographic projection of the first auxiliary conducting line 121 on the base substrate and the second connection via in the second second color sub-pixel on the orthographic projection of the base substrate has an overlapping area.
  • the first connection via 387a serves as the second connection via.
  • the first auxiliary conducting wire 121 extends in a linear shape along the first direction. This can reduce the resistance.
  • the embodiments of the present disclosure include but are not limited thereto, and the above-mentioned implementation of the first auxiliary conducting wire 121 may also have other shapes.
  • the auxiliary conduction line may also include a second auxiliary conduction line 122; wherein the remaining part of the auxiliary power line 110 passes through at least one second auxiliary conduction line 122. Electric connection.
  • the auxiliary conducting wires can be used for electrical connection between every two adjacent sub-auxiliary power lines 110 respectively.
  • the remaining part of the two adjacent sub-auxiliary power lines 110 may be electrically connected through a second auxiliary conductive line 122.
  • the remaining two adjacent sub-auxiliary power lines 110 may also be electrically connected by two, three or more second auxiliary conducting wires 122. This can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • a first electrode 611 in the first color sub-pixel 010 is projected on the base substrate 1000 and the first electrode 631 in the third color sub-pixel 030 is projected on the base substrate 1000.
  • the second auxiliary conduction line 122 is at The orthographic projection of the base substrate 1000 is relative to the orthographic projection of the first electrode 611 in the first color sub-pixel 010 on the base substrate 1000, which is close to the orthographic projection of the first electrode 631 in the third color sub-pixel 030 on the base substrate 100 .
  • the sub-auxiliary power line 110 and the auxiliary conductive line can roughly form a grid structure .
  • the long-term luminescence stability of general light-emitting devices is also an important specification or index of display panels.
  • the disclosure of this application has noticed that there are many factors that affect the long-term light-emitting stability of the light-emitting device.
  • the working state of the transistor in the pixel driving circuit is stable to the light-emitting brightness and long-term light-emitting. Sex has a certain degree of influence.
  • the display panel may include a base substrate 1000, a pixel driving circuit, and a first electrode layer 600; the first electrode layer 600 includes a plurality of first electrodes.
  • the first electrode layer 600 includes a plurality of first electrodes.
  • One pixel driving circuit and one first electrode are arranged in one-to-one correspondence, and each pixel driving circuit may include a threshold compensation transistor T3; the display panel may also include a first pixel driving circuit 2657 and a second pixel driving circuit 2658 which are arranged adjacently.
  • the channel region of the threshold value compensation transistor T3 in the pixel drive circuit 2657 and the channel region of the threshold value compensation transistor T3 in the second pixel drive circuit 2658 on the base substrate 1000 both correspond to the first pixel drive circuit 2657.
  • the orthographic projection of an electrode on the base substrate has an overlapping area. Therefore, the channel region of the threshold compensation transistor in the first pixel drive circuit and the channel region of the threshold compensation transistor in the second pixel drive circuit can be simultaneously shielded by the first electrode, thereby improving the stability of the threshold compensation transistor. Performance and lifespan, thereby improving the long-term luminous stability and lifespan of the display panel.
  • first and second in the above-mentioned first pixel drive circuit and the second pixel drive circuit are only used to distinguish the two pixel drive circuits in text. These two pixel drive circuits The specific structure is the same.
  • the channel region of the threshold compensation transistor T3 in the first pixel driving circuit 2657 and the channel region of the threshold compensation transistor T3 in the second pixel driving circuit 2658 are on the base substrate.
  • the orthographic projection of 1000 overlaps the orthographic projection of the first electrode corresponding to the first pixel driving circuit 2657 on the base substrate 1000, and the first electrode corresponding to the first pixel driving circuit 2657 can be used for the first pixel driving circuit 2657.
  • the channel region of the threshold compensation transistor T3 and the channel region of the threshold compensation transistor T3 in the second pixel driving circuit 2658 are partially shielded or completely shielded.
  • the display panel in the embodiment of the present disclosure can improve the stability and life of the threshold compensation transistor T3 in the first pixel driving circuit and the threshold compensation transistor T3 in the second pixel driving circuit 2658, thereby improving the display panel Long-term luminescence stability and lifetime.
  • the channel region of the threshold compensation transistor T3 in the first pixel drive circuit 2657 and the channel region of the threshold compensation transistor T3 in the second pixel drive circuit 2658 may both fall into the corresponding channel of the first pixel drive circuit 2657.
  • the orthographic projection of the first electrode on the base substrate 1000, the first electrode corresponding to the first pixel driving circuit 2657 can be used for the channel region of the threshold compensation transistor T3 in the first pixel driving circuit 2657 and the channel region of the second pixel driving circuit 2658.
  • the channel region of the threshold compensation transistor T3 is completely shielded, thereby further improving the stability and life of the threshold compensation transistor, thereby improving the long-term light-emitting stability and life of the display panel.
  • the threshold compensation transistor T3 may be a thin film transistor with a double gate structure, thereby improving the reliability of the threshold compensation transistor.
  • the active layer of the threshold compensation transistor T3 includes a first channel region T31-A and a second channel region T32-A which are arranged at intervals, and are located in the first channel region T31-A and the second channel region T32-
  • the common conductive area SE between A is also provided.
  • the common conductive region SE of the threshold compensation transistor T3 in the first pixel driving circuit 2657 and the common conductive region SE of the threshold compensation transistor T3 in the second pixel driving circuit 2658 are both aligned with the first projection on the base substrate 1000.
  • the first electrode corresponding to a pixel driving circuit 2657 has an overlapping area on the orthographic projection of the base substrate 1000. Therefore, the first electrode corresponding to the first pixel driving circuit 2657 can share the common conductive area SE of the threshold compensation transistor T3 in the first pixel driving circuit 2657 and the threshold compensation transistor T3 in the second pixel driving circuit 2658.
  • the conductive region SE is partially shielded or completely shielded, thereby further improving the stability and lifespan of the threshold compensation transistor, thereby improving the long-term light-emitting stability and lifespan of the display panel.
  • the first pixel driving circuit 2657 and the second pixel driving circuit 2658 are arranged along the first direction F1.
  • the first pixel driving circuit 2657 is electrically connected to the first electrode 631 in one repeating unit 001 correspondingly.
  • the second pixel driving circuit 2658 is electrically connected to the first electrode 621 in the other repeating unit 001 correspondingly.
  • first electrode 631 electrically connected to the first pixel driving circuit 2657 and the first electrode 621 electrically connected to the second pixel driving circuit 2658 are respectively located in different repeating unit rows 01, and the first pixel driving circuit 2657 is electrically connected to the first The electrode 631 is adjacent to the repeating unit row 01 where the first electrode 621 electrically connected to the second pixel driving circuit 2658 is located.
  • the pixel defining layer 660 includes a plurality of openings; the plurality of openings includes a first opening 1951, a second opening 19521, a third opening 19522, and A fourth opening 1953.
  • the first opening 1951 and the first electrode 611 are arranged corresponding to and expose the first electrode 611
  • the second opening 19521 is arranged corresponding to the first electrode 621 and exposes the first electrode 621
  • the third opening 19522 is arranged corresponding to the first electrode 622 and exposes the first electrode 611.
  • the first electrode 622 is exposed
  • the fourth opening 1953 is arranged corresponding to the first electrode 631 and exposes the first electrode 631.
  • the first electrode 611 includes a first body portion 6111 and a first connection portion 6112 that are electrically connected to each other, and the first opening 1951 lies on the orthographic projection of the base substrate 1000.
  • the first body portion 6111 is inserted into the orthographic projection of the base substrate 1000, and the first connection portion 6112 is electrically connected to the pixel driving circuit corresponding to the first electrode 611.
  • the first electrode 621 includes a second body portion 6211 and a second connection portion 6212 that are electrically connected to each other, and the second opening 19521 falls on the orthographic projection of the base substrate 1000.
  • the second main body portion 6211 is in the orthographic projection of the base substrate 1000, and the second connection portion 6212 is electrically connected to the pixel driving circuit corresponding to the first electrode 621.
  • the first electrode 622 includes a third body portion 6221 and a third connection portion 6222 that are electrically connected to each other, and the third opening 19522 falls on the orthographic projection of the base substrate 1000.
  • the third main body portion 6221 is in the orthographic projection of the base substrate 1000, and the third connection portion 6222 is electrically connected to the pixel driving circuit corresponding to the first electrode 622.
  • the first electrode 631 includes a fourth body portion 6311 and a fourth connection portion 6312, and the fourth opening 1953 is projected into the fourth body on the base substrate 1000.
  • the portion 6311 is in the orthographic projection of the base substrate 1000, and the fourth connection portion 6312 is electrically connected to the pixel driving circuit corresponding to the first electrode 631 (for example, the aforementioned first pixel driving circuit 2657).
  • the shape of the first body portion 6111 is substantially the same as the shape of the first opening 1951; the shape of the second body portion 6211 is substantially the same as the shape of the second opening 19521
  • the shape of the fourth opening 1953 is a hexagon
  • the shape of the fourth body portion 6311 is also a hexagon.
  • the shapes of the fourth opening and the fourth main body are not limited to hexagons, and may also be other shapes such as ellipse.
  • the first electrode 631 may further include a first supplement 6313.
  • the orthographic projections of the first channel region T31-A and the second channel region T32-A of the threshold compensation transistor T3 in the first pixel driving circuit 2657 corresponding to the first electrode 631 on the base substrate 1000 are respectively the same as those of the first supplementary part.
  • the orthographic projection of 6313 on the base substrate 1000 overlaps.
  • the first electrode can overlap or cover the two channel regions of the threshold compensation transistor in the corresponding pixel drive circuit, thereby increasing the threshold compensation transistor.
  • the stability and lifespan of the display panel can thereby improve the long-term luminous stability and lifespan of the display panel.
  • the first supplemental portion 6313 protrudes from the fourth body portion 6311 toward the first electrode 622, and the first supplementary portion 6313 is located at the fourth connecting portion 6312 close to the first electrode 622.
  • the main body portion 6311 protrudes from the fourth body portion 6311 toward the first electrode 622, and the first supplementary portion 6313 is located at the fourth connecting portion 6312 close to the first electrode 622.
  • the first supplementary portion 6313 is electrically connected to the fourth main body portion 6311 and the fourth connection portion 6312. Therefore, the display panel can make full use of the area on the display panel, and the first electrodes are closely arranged, so that the resolution of the display panel can be ensured.
  • the channel region of the threshold compensation transistor T3 in the pixel driving circuit corresponding to the first electrode 611 falls into the first body portion in the orthographic projection of the base substrate 1000.
  • 6111 is in the orthographic projection of the base substrate 1000.
  • the orthographic projection of the second channel region T32-A of the threshold compensation transistor T3 in the pixel driving circuit 265 corresponding to the first electrode 622 on the base substrate 1000 It falls into the orthographic projection of the third main body portion 6221 on the base substrate 1000.
  • the first electrode 631 may also include a second supplementary portion 6314; the first channel region T31-A of the threshold compensation transistor T3 in the second pixel driving circuit 2658 is located on the positive side of the base substrate 1000.
  • the projection overlaps with the orthographic projection of the second supplement 6314 on the base substrate 1000.
  • the second supplemental portion 6314 protrudes from the fourth body portion 6311 to the first electrode 611 adjacent in the first direction.
  • the orthographic projection of the second channel region T32-A of the threshold compensation transistor T3 in the second pixel driving circuit 2658 on the base substrate 1000 can fall into the fourth main body portion 6311 on the substrate 1000. In the orthographic projection of the base substrate 1000.
  • the common conductive area SE of the threshold compensation transistor T3 in the first pixel driving circuit 2657 overlaps the orthographic projection of the first supplement 6313 on the base substrate 1000, and the second pixel driving circuit
  • the orthographic projection of the common conductive region SE of the threshold compensation transistor T3 in the circuit 2658 on the base substrate 1000 and the orthographic projection of the fourth body portion 6311 of the first electrode 631 corresponding to the first pixel driving circuit 2657 on the base substrate 1000 intersect Stacked.
  • the first electrode 611 may further include a third supplementary portion 6113 protruding from the first body portion 6111 toward the first electrode 622, and the first electrode 611 corresponds to the driving thin film transistor in the pixel driving circuit
  • the orthographic projection of the gate of T1 and the drain region of the threshold compensation transistor T3 on the base substrate 1000 falls within the orthographic projection of the third supplement 6113 on the base substrate 1000. Therefore, the display panel can stably drive the potentials on the gate of the thin film transistor T1 and the drain of the threshold compensation transistor T3 through the third supplementary portion 6113, thereby further improving the long-term light-emitting stability and lifetime of the display panel.
  • the first electrode 622 may further include a fourth supplementary portion 6223, and the first channel region T31-A of the threshold compensation transistor T3 in the pixel driving circuit corresponding to the first electrode 622 is on the base substrate
  • the orthographic projection on 1000 falls within the orthographic projection of the fourth supplement 6223 on the base substrate 1000.
  • the third main body portion 6221 and the fourth supplementary portion 6223 of the first electrode 622 can be used for the first channel region T31-A and the first channel of the threshold compensation transistor T3 in the pixel driving circuit corresponding to the first electrode 622.
  • the area T32-A is partially shielded or completely shielded, thereby improving the stability and lifespan of the threshold compensation transistor, thereby improving the long-term light-emitting stability and lifespan of the display panel.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the implementation of the display device can be referred to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.

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Abstract

本公开公开了显示面板及显示装置，其中，显示面板，包括：衬底基板；多条扫描线；第一绝缘层，多条数据线，层间绝缘层，辅助电源线；辅助电源线包括：多个子辅助电源线和多个辅助导通线；其中，多个子辅助电源线沿第一方向排列且沿第二方向延伸，至少部分相邻的两个子辅助电源线之间通过至少一个辅助导通线电连接；多个辅助导通线中的至少一个在衬底基板的正投影与扫描线在衬底基板的正投影不交叠。

Description

显示面板及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板；
栅导电层，位于所述衬底基板上，且所述栅导电层包括：多条扫描线；
第一绝缘层，位于所述栅导电层上；
第一导电层，位于所述第一绝缘层背离所述衬底基板一侧，且所述第一导电层包括多条数据线；其中，所述多条数据线沿第一方向排列；
层间绝缘层，位于所述第一导电层背离所述衬底基板一侧；
第二导电层，位于所述层间绝缘层背离所述衬底基板一侧，且所述第二导电层包括辅助电源线；
所述辅助电源线包括：多个子辅助电源线和多个辅助导通线；其中，所述多个子辅助电源线沿所述第一方向排列且沿第二方向延伸，至少部分相邻的两个子辅助电源线之间通过至少一个所述辅助导通线电连接；所述第一方向与所述第二方向不同；
所述多个辅助导通线中的至少一个在所述衬底基板的正投影与所述扫描线在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述多条扫描线包括第一扫描线和第二扫 描线；其中，所述第二扫描线包括相互电连接的扫描线部和多个突出部；所述扫描线部沿所述第一方向延伸，所述突出部沿所述第二方向延伸；
所述显示面板还包括：多个子像素；所述多个子像素中的至少一个包括像素驱动电路；所述像素驱动电路包括晶体管；
所述突出部作为所述晶体管的栅极，且各所述辅助导通线在所述衬底基板的正投影与所述突出部在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述像素驱动电路包括：驱动晶体管和阈值补偿晶体管；其中，所述阈值补偿晶体管包括：第一子补偿晶体管和第二子补偿晶体管；
所述第一子补偿晶体管的栅极与所述第二扫描线电连接，所述第一子补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一子补偿晶体管的第二极与所述第二子补偿晶体管的第一极电连接；
所述第二子补偿晶体管的栅极与所述第二扫描线电连接，所述第二子补偿晶体管的第二极与所述驱动晶体管的第二极电连接；
所述突出部作为所述第一子补偿晶体管的栅极；
所述扫描线部中的部分作为所述第二子补偿晶体管的栅极。
可选地，在本公开实施例中，所述显示面板还包括：多个重复单元；其中，所述重复单元包括多个子像素；并且，所述多个重复单元沿所述第一方向排列形成一个重复单元行，且所述重复单元行沿所述第二方向排列；
所述辅助导通线包括第一辅助导通线；其中，部分相邻两个所述子辅助电源线之间通过至少一条所述第一辅助导通线电连接；
一个所述重复单元行对应一条所述第一扫描线、一条所述第二扫描线以及至少一个第一辅助导通线；
针对同一所述重复单元行对应的所述第一扫描线、所述第二扫描线以及所述第一辅助导通线，所述第一辅助导通线在所述衬底基板的正投影位于所述第一扫描线和所述第二扫描线的突出部在所述衬底基板的正投影之间。
可选地，在本公开实施例中，所述显示面板还包括：
平坦化层，位于所述第二导电层背离所述衬底基板一侧；
第一电极层，位于所述平坦化层背离所述衬底基板一侧，且所述第一电极层包括相互间隔设置的多个第一电极；其中，一个所述子像素设置一个所述第一电极；
所述第一辅助导通线在所述衬底基板的正投影与所述第一电极在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述多个重复单元中的子像素包括：沿所述第一方向排列的第一颜色子像素、第二颜色子像素对以及第三颜色子像素；其中，所述第二颜色子像素对包括沿所述第二方向排列的两个第二颜色子像素；并且，相邻两个所述重复单元行中的重复单元错位排列。
可选地，在本公开实施例中，至少部分所述第二颜色子像素对中的每一个对应一条所述第一辅助导通线；
所述第一辅助导通线在所述衬底基板的正投影位于对应的所述第二颜色子像素对中的两个第一电极在所述衬底基板的正投影之间。
可选地，在本公开实施例中，所述像素驱动电路还包括数据写入晶体管；其中，一列子像素中的数据写入晶体管与一条所述数据线电连接；
针对同一所述重复单元中第二颜色子像素对和第一颜色子像素，对应所述第二颜色子像素对的第一辅助导通线在所述衬底基板的正投影与所述第一颜色子像素电连接的数据线在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述数据写入晶体管通过第一连接过孔与所述数据线电连接；
针对同一所述重复单元中第二颜色子像素对和第一颜色子像素，对应所述第二颜色子像素对的第一辅助导通线在所述衬底基板的正投影与所述第一颜色子像素中的所述第一连接过孔在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述像素驱动电路还包括第一复位晶体管；所述显示面板还包括多条第一复位信号线；其中，各所述子像素中的第一复位晶体管通过第二连接过孔与所述第一复位信号线电连接；
所述第二颜色子像素对包括：沿第二方向排列的第一个第二颜色子像素和第二个第二颜色子像素；所述第一辅助导通线在所述衬底基板的正投影与所述第二个第二颜色子像素中的所述第二连接过孔在所述衬底基板的正投影的边缘具有交叠区域。
可选地，在本公开实施例中，所述第一辅助导通线沿所述第一方向延伸为直线形。
可选地，在本公开实施例中，所述辅助导通线还包括第二辅助导通线；其中，其余部分相邻两个所述子辅助电源线之间通过至少一条所述第二辅助导通线电连接。
可选地，在本公开实施例中，针对一个重复单元行中的第一颜色子像素和相邻重复单元行中且与所述第一颜色子像素最近邻的第三颜色子像素，所述第一颜色子像素中的第一电极在所述衬底基板的正投影与所述第三颜色子像素中的第一电极在所述衬底基板的正投影之间设置有一条所述第二辅助导通线在所述衬底基板的正投影。
可选地，在本公开实施例中，针对一个重复单元行中的第一颜色子像素和相邻重复单元行中且与所述第一颜色子像素最近邻的第三颜色子像素，所述第二辅助导通线在所述衬底基板的正投影相对所述第一颜色子像素中的第一电极在所述衬底基板的正投影，靠近所述第三颜色子像素中的第一电极在所述衬底基板的正投影。
可选地，在本公开实施例中，所述第一导电层还包括主电源线；其中，所述主电源线与所述数据线间隔设置；
所述层间绝缘层具有第一电源过孔；
所述主电源线通过所述第一电源过孔与所述辅助电源线彼此电连接。
可选地，在本公开实施例中，所述主电源线在所述衬底基板的正投影与所述辅助电源线在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述子辅助电源线与所述辅助导通线大致形成网格结构。
可选地，在本公开实施例中，所述辅助电源线被配置为传输驱动电压的电源线。
本公开实施例还提供的显示装置，包括上述显示面板。
附图说明
图1为本公开实施例提供的一些显示面板的结构示意图；
图2a为本公开实施例提供的一些子像素中的电路结构示意图；
图2b为本公开实施例提供的一些信号时序图；
图3为本公开实施例提供的一些子像素中的布局结构示意图；
图4a为本公开实施例提供的一些子像素中的半导体层的布局结构示意图；
图4b为本公开实施例提供的一些子像素中的栅导电层的布局结构示意图；
图4c为本公开实施例提供的一些子像素中的电容电极层的布局结构示意图；
图4d为本公开实施例提供的一些子像素中的第一导电层的布局结构示意图；
图4e为本公开实施例提供的一些子像素中的第二导电层的布局结构示意图；
图5为图3所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图6为本公开实施例提供的显示面板中多个子像素的布局结构示意图；
图7为本公开实施例提供的显示面板中多个子像素中半导体层的布局结构示意图；
图8为本公开实施例提供的显示面板中多个子像素中栅导电层的布局结构示意图；
图9为本公开实施例提供的显示面板中多个子像素中电容电极层的布局结构示意图；
图10为本公开实施例提供的显示面板中多个子像素中第一导电层的布局结构示意图；
图11为本公开实施例提供的显示面板中多个子像素中第二导电层的布局结构示意图；
图12为本公开实施例提供的显示面板中多个子像素中第一电极层的布局结构示意图；
图13为本公开实施例提供的显示面板中一个重复单元中的第一电极层的布局结构示意图；
图14为本公开实施例提供的显示面板中的又一些多个子像素的布局结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的显示面板，可以包括：衬底基板1000。 位于衬底基板1000的显示区A1中的多个子像素spx。示例性地，结合图1与图2a所示，多个子像素spx中的至少一个子像素spx可以包括：像素驱动电路0121和发光器件0120。其中，像素驱动电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号输入到发光器件0120的第一电极中。并且对发光器件0120的第二电极加载相应的电压，可以驱动发光器件0120发光。
结合图2a所示，像素驱动电路0121可以包括：驱动控制电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。
驱动控制电路0122可以包括控制端、第一端和第二端。且驱动控制电路0122被配置为发光器件0120提供驱动发光器件0120发光的驱动电流。例如，第一发光控制电路0123与驱动控制电路0122的第一端和第一电压端VDD连接。且第一发光控制电路0123被配置为实现驱动控制电路0122和第一电压端VDD之间的连接导通或断开。
第二发光控制电路0124与驱动控制电路0122的第二端和发光器件0120的第一电极电连接。且第二发光控制电路0124被配置为实现驱动控制电路0122和发光器件0120之间的连接导通或断开。
数据写入电路0126与驱动控制电路0122的第一端电连接。且第二发光控制电路0124被配置为在扫描线GA2上的信号的控制下将数据线VD上的信号写入存储电路0127。
存储电路0127与驱动控制电路0122的控制端和第一电压端VDD电连接。且存储电路0127被配置为存储数据信号。
阈值补偿电路0128与驱动控制电路0122的控制端和第二端电连接。且阈值补偿电路0128被配置为对驱动控制电路0122进行阈值补偿。
复位电路0129与驱动控制电路0122的控制端和发光器件0120的第一电极电连接。且复位电路0129被配置为在栅线GA1上的信号的控制下对驱动控制电路0122的控制端和发光器件0120的第一电极进行复位。
其中，发光器件0120可以设置为电致发光二极管，例如OLED和QLED中的至少一种。其中，光器件0120可以包括层叠设置的第一电极、发光功能层、第二电极。示例性地，第一电极可以为阳极、第二电极可以为阴极。发光功能层可以包括发光层。进一步地，发光功能层还可以包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光器件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2a所示，驱动控制电路0122包括：驱动晶体管T1，驱动控制电路0122的控制端包括驱动晶体管T1的栅极，驱动控制电路0122的第一端包括驱动晶体管T1的第一极，驱动控制电路0122的第二端包括驱动晶体管T1的第二极。
示例性地，结合图2a所示，数据写入电路0126包括数据写入晶体管T2。存储电路0127包括存储电容CST。阈值补偿电路0128包括阈值补偿晶体管T3。第一发光控制电路0123包括第一发光控制晶体管T4。第二发光控制电路0124包括第二发光控制晶体管T5。复位电路0129包括第一复位晶体管T6和第二复位晶体管T7。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线VD电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第二扫描线GA2电连接以接收扫描信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T1的栅极电连接。
阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描线GA2电连接以接收扫描信号。
第一复位晶体管T6的第一极被配置为与第一复位信号线VINIT1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极 电连接，第一复位晶体管T6的栅极被配置为与第一扫描线GA1电连接以接收控制信号。
第二复位晶体管T7的第一极被配置为与第二复位信号线VINIT2电连接以接收第二复位信号，第二复位晶体管T7的第二极与发光器件0120的第一电极电连接，第二复位晶体管T7的栅极被配置为与第一扫描线GA1电连接以接收控制信号。
第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光器件0120的第一电极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
发光器件0120的第二电极与第二电源端VSS电连接。其中，上述晶体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，如图2a所示，阈值补偿晶体管T3可以包括：第一子补偿晶体管T31和第二子补偿晶体管T32；其中，
第一子补偿晶体管T31的栅极与第二扫描线GA2电连接，第一子补偿晶体管T31的第一极与驱动晶体管T1的栅极电连接，第一子补偿晶体管T31的第二极与第二子补偿晶体管T32的第一极电连接；
第二子补偿晶体管T32的栅极与第二扫描线GA2电连接，第二子补偿晶体管T32的第二极与驱动晶体管T1的第二极电连接。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2a所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。第一复位信号线VINIT1和第二复位信号线VINIT2为同 一信号线。
图2a所示的像素驱动电路对应的信号时序图，如图2b所示。一帧显示时间中，像素驱动电路的工作过程具有三个阶段：T10阶段、T20阶段、T30阶段。其中，ga1代表第一扫描线GA1上传输的信号，ga2代表第二扫描线GA2上传输的信号，em代表发光控制线EM上传输的信号。
在T10阶段，信号ga1控制第一复位晶体管T6和第二复位晶体管T7导通。导通的第一复位晶体管T6将第一复位信号线VINIT1上传输的信号提供给驱动晶体管T1的栅极，以对驱动晶体管T1的栅极进行复位。导通的第二复位晶体管T7将第一复位信号线VINIT1上传输的信号提供给发光器件0120的第一电极，以对发光器件0120的第一电极进行复位。并且，此阶段中，信号ga2控制数据写入晶体管T2、第一子补偿晶体管T31和第二子补偿晶体管T32均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T20阶段，信号ga2控制数据写入晶体管T2、第一子补偿晶体管T31和第二子补偿晶体管T32均导通，从而可以使数据线VD上传输的数据信号对驱动晶体管T1的栅极进行充电，以使驱动晶体管T1的栅极的电压变为：Vdata+|Vth|。其中，Vth代表驱动晶体管T1的阈值电压，Vdata代表数据信号的电压。并且，此阶段中，信号ga1控制第一复位晶体管T6和第二复位晶体管T7均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T30阶段，信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均导通。导通的第一发光控制晶体管T4将第一电源端VDD的电压Vdd提供给驱动晶体管T1的第一极，以使驱动晶体管T1的第一极的电压为Vdd。驱动晶体管T1根据其栅极电压Vdata+|Vth|，以及第一极的电压Vdd，产生驱动电流。该驱动电流通过导通的第二发光控制晶体管T5提供给发光器件0120，驱动发光器件0120发光。并且，此阶段中，信号ga1控制第一复位晶体管T6和第二复位晶体管T7均截止。信号ga2控制数据写入晶体管T2、第一子补 偿晶体管T31和第二子补偿晶体管T32均截止。
需要说明的是，在本公开实施例中，子像素中的像素驱动电路除了可以为图2a所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
图3为本公开一些实施例提供的像素驱动电路的布局(Layout)结构示意图。图4a至图4e为本公开一些实施例提供的像素驱动电路的各层的示意图。其中，图3至图4e所示的示例以一个子像素spx的像素驱动电路为例。其中，图3至图4e还示出了电连接到像素驱动电路0121的第一扫描线GA1、第二扫描线GA2、第一复位信号线VINIT1(第一复位信号线VINIT1和第二复位信号线VINIT2为同一条信号线，则示出了第一复位信号线VINIT1)、发光控制线EM、数据线VD、主电源线VDD1、以及辅助电源线VDD2。其中，主电源线VDD1与第一电源端VDD电连接，以向第一电源端VDD输入驱动电压(即第一电压)。示例性地，可以使多条数据线VD沿第一方向F1排列。
示例性地，如图3、图4a以及图5所示，示出了该像素驱动电路0121的半导体层500。半导体层500可采用半导体材料图案化形成。半导体层500可用于制作上述的驱动晶体管T1、数据写入晶体管T2、第一子阈值补偿晶体管T31、第二子阈值补偿晶体管T32、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，图4a示意出了驱动晶体管T1的沟道区T1-A，数据写入晶体管T2的沟道区T2-A，第一子阈值补偿晶体管T31的第一沟道区T31-A，第二子阈值补偿晶体管T32的第二沟道区T32-A，第一发光控制晶体管T4的沟道区T4-A，第二发光控制晶体管T5的沟道区T5-A，第一复位晶体管T6的沟道区T6-A，和第二复位晶体管T7的沟道区T7-A。
并且，示例性地，可以使各晶体管的有源层一体设置。进一步地，半导体层500可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
示例性地，如图5所示，在上述的半导体层500上形成有第一栅绝缘层610，用于保护上述的半导体层500。如图3、图4b以及图5所示，示出了该像素驱动电路0121的栅导电层300。栅导电层300设置在第一栅绝缘层610背离衬底基板1000一侧，从而与半导体层500绝缘。栅导电层300可以包括：多条扫描线，存储电容CST的第二极CC2a、发光控制线EM以及驱动晶体管T1、数据写入晶体管T2、第一子阈值补偿晶体管T31、第二子阈值补偿晶体管T32、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。示例性地，多条扫描线例如包括多条第一栅线GA1和多条第二栅线GA2。
例如，如图3至图4b所示，数据写入晶体管T2的栅极可以为第二扫描线GA2与半导体层500交叠的第一部分(例如第二扫描线GA2与数据写入晶体管T2的沟道区T2-A交叠的第一部分)，第一发光控制晶体管T4的栅极可以为发光控制线EM与半导体层500交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制线EM与半导体层500交叠的第二部分，第一复位晶体管T6的栅极为第一扫描线GA1与半导体层500交叠的第一部分，第二复位晶体管T7的栅极为第一扫描线GA1与半导体层500交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，第二子阈值补偿晶体管T32的栅极可为第二扫描线GA2与半导体层500交叠的第二部分(例如第二扫描线GA2与第二子阈值补偿晶体管T32的第二沟道区T32-A交叠的第二部分)，第一子阈值补偿晶体管T31的栅极可为从第二扫描线GA2突出的突出部320与半导体层500交叠的部分。示例性地，驱动晶体管T1的栅极可以设置为存储电容CST的第二极CC2a。也可以说，驱动晶体管T1的栅极和存储电容CST的第二极CC2a为一体结构。
需要说明的是，图4a中的各虚线矩形框示出了子像素spx中栅导电层300与半导体层500交叠的各个部分。
示例性地，如图3与图4b所示，第一扫描线GA1、第二扫描线GA2以及发光控制线EM沿第二方向F2排布，第二扫描线GA2在衬底基板1000的 正投影位于第一扫描线GA1在衬底基板1000的正投影和发光控制线EM在衬底基板1000的正投影之间。
示例性地，如图3与图4b所示，在第二方向F2上，存储电容CST的第二极CC2a在衬底基板1000的正投影位于第二扫描线GA2在衬底基板1000的正投影和发光控制线EM在衬底基板1000的正投影之间。从第二扫描线GA2突出的突出部320在衬底基板1000的正投影位于第二扫描线GA2在衬底基板1000的正投影远离发光控制线EM在衬底基板1000的正投影的一侧。
示例性地，如图3与图4b所示，在第二方向F2上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。
例如，在一些实施例中，如图3与图4b所示，在第一方向F1上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。其中，驱动晶体管T1的栅极的第三侧和第四侧为在第一方向F1上驱动晶体管T1的栅极的彼此相对的两侧。
示例性地，如图5所示，在上述的栅导电层300上形成有第二栅绝缘层620，用于保护上述的栅导电层300。如图3、图4c以及图5所示，示出了该像素驱动电路0121的电容电极层400。电容电极层400设置在第二栅绝缘层620背离衬底基板1000一侧。电容电极层400可以包括存储电容CST的第一极CC1a、第一复位信号线VINIT1以及稳压部410。示例性地，存储电容CST的第一极CC1a在衬底基板1000的正投影与存储电容CST的第二极CC2a在衬底基板1000的正投影至少部分交叠以形成存储电容CST。稳压部410在衬底基板1000的正投影与数据写入晶体管T2的有源层的源极区域在衬底基板1000的正投影具有交叠区域。以及，稳压部410在衬底基板1000的正投影与 第一复位晶体管T6的有源层的漏极区域在衬底基板1000的正投影具有交叠区域。并且，稳压部410在衬底基板1000的正投影与相邻的第一子阈值补偿晶体管T31的第一沟道区T31-A和第二子阈值补偿晶体管T32的第二沟道区T32-A之间的导体区在衬底基板1000的正投影具有交叠区域，以减少光电效应引起的漏电流。
示例性地，如图5所示，在上述的电容电极层400上形成有层间介质层630，用于保护上述的电容电极层400。如图3、图4d以及图5所示，示出了该像素驱动电路0121的第一导电层100，第一导电层100设置在层间介质层630背离衬底基板1000一侧。第一导电层100可以包括：数据线VD、主电源线VDD1以及桥接部341a、342a以及343a。其中，数据线VD与主电源线VDD1间隔设置。
示例性地，如图5所示，在上述的第一导电层100上形成有层间绝缘层640，用于保护上述的第一导电层100。如图3、图4e以及图5所示，示出了该像素驱动电路0121的第二导电层200，第二导电层200设置在层间绝缘层640背离衬底基板1000一侧。第二导电层200可以包括辅助电源线VDD2和转接部351a。并且，层间绝缘层640具有第一电源过孔，主电源线VDD1通过第一电源过孔与辅助电源线VDD2彼此电连接，以实现降低电阻的效果。进一步地，主电源线VDD在衬底基板1000的正投影与辅助电源线VDD2在衬底基板1000的正投影具有交叠区域。示例性地，辅助电源线可以被配置为传输驱动电压(即第一电压)的电源线。
图5为图3所示的布局结构示意图沿AA’方向上的剖视结构示意图。半导体层500与栅导电层300之间设置有第一栅绝缘层610，栅导电层300与电容电极层400之间设置有第二栅绝缘层620，电容电极层400与第一导电层100之间设置有层间介质层630，第一导电层100与第二导电层200之间设置有层间绝缘层640。进一步地，在第二导电层200背离衬底基板1000一侧设置有平坦化层650，在平坦化层650背离衬底基板1000一侧设置有第一电极层600。在第一电极层600背离衬底基板1000一侧依次设置有像素限定层660、 发光功能层0122以及第二电极层0123。其中，第一电极层600可以包括相互间隔设置的多个第一电极，并且第一电极通过贯穿平坦化层650的过孔与转接部351a电连接。需要说明的是，图5未示出转接部351a和平坦化层650的过孔。
结合图3与图5所示，子像素spx中可以包括第一连接通孔、第二连接通孔、第三连接通孔以及第四连接通孔；其中，第一连接通孔贯穿第一栅绝缘层610、第二栅绝缘层620以及层间介质层630；第二连接通孔贯穿第二栅绝缘层620与层间介质层630；第三连接通孔贯穿层间介质层630；第四连接通孔贯穿层间绝缘层640。
示例性地，子像素spx中可以包括第一连接通孔381a、382a、384a、387a以及388a。子像素spx中可以包括第二连接通孔385a。子像素spx中可以包括第三连接通孔386a和3832a。子像素spx中包括第四连接通孔385a和3831a。其中，数据线VD通过至少一个第一连接通孔381a与半导体层500中的数据写入晶体管T2的源极区域T2-S电连接。主电源线VDD1通过至少一个第一连接通孔382a与半导体层500中对应的第一发光控制晶体管T4的源极区域电连接。桥接部341a的一端通过至少一个第一连接通孔384a与半导体层500中对应的第一子阈值补偿晶体管T31的漏极区域电连接。桥接部341a的另一端通过至少一个第二连接通孔385a与栅导电层300中的驱动晶体管T1的栅极(即存储电容CST的第二极CC2a)电连接。桥接部342a的一端通过至少一个第三连接通孔386a与第一复位信号线VINIT1电连接，桥接部342a的另一端通过至少一个第一连接通孔387a与半导体层500中的第一复位晶体管T6的源极区域T6-S电连接。桥接部343a通过至少一个第一连接通孔388a与半导体层500中的第二发光控制晶体管T5的漏极区域电连接。主电源线VDD1通过至少一个第三连接通孔3832a与电容电极层400中的存储电容CST的第一极CC1a电连接。主电源线VDD1还通过至少一个第四连接通孔3831a(即第一电源过孔)与第二导电层200中的辅助电源线VDD2电连接。转接部351a通过至少一个第四连接通孔385a与桥接部343a电连接。
示例性地，子像素中的第一连接通孔381a、382a、384a、387a以及388a可以分别设置一个，也可以分别设置两个或多个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，子像素中的第二连接通孔385a可以设置一个，也可以设置两个或多个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，子像素中的第三连接通孔386a和3832a可以分别设置一个，也可以分别设置两个或多个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，子像素中的第四连接通孔385a和3831a可以分别设置一个，也可以分别设置两个或多个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
例如，如图3至图4e所示，在第二方向F2上，第一扫描线GA1、第二扫描线GA2、第一复位信号线VINIT1均位于的驱动晶体管T1的栅极的第一侧，发光控制线EM位于驱动晶体管T1的第二侧。
示例性地，第一扫描线GA1、第二扫描线GA2、发光控制线EM可以位于同一层(即栅导电层300)。主电源线VDD1和数据线VD位于同一层(即第一导电层100)。
需要说明的是，每个子像素spx中的晶体管的位置排布关系不限于图3至图4e所示的示例，根据实际应用需求，可以具体设置上述晶体管的位置。
需要说明的是，第一方向F1可以为子像素的行方向，第二方向F2可以为子像素的列方向。或者，第一方向F1也可以为子像素的列方向，第二方向F2为子像素的行方向。在实际应用中，可以根据实际应用需求进行设置，在此不作限定。
在实际应用中，一般扫描线会与其他导电膜层存在正对面积，这样将会产生耦合电容。由于扫描线上一搬传输控制晶体管导通或截止的信号。由于耦合电容的存在，导致扫描线上传输的信号的负载(Loading)较大，则会导 致扫描线上传输的信号的稳定性降低，从而影响显示效果。
在具体实施时，在本公开实施例中，如图2a至图11所示，第一绝缘层可以包括：第二栅绝缘层620和层间介质层630。辅助电源线VDD2可以包括：多个子辅助电源线110和多个辅助导通线120；其中，多个子辅助电源线110沿第一方向F1排列且沿第二方向F2延伸，至少部分相邻的两个子辅助电源线110之间通过至少一个辅助导通线120电连接。并且，多个辅助导通线120中的至少一个在衬底基板1000的正投影与扫描线在衬底基板1000的正投影不交叠。这样可以避免辅助导通线120与扫描线之间存在正对面积，从而避免辅助导通线120与扫描线之间存在耦合电容，进而可以提高扫描线上传输的信号的稳定性，提高显示效果。
示例性地，如图6与图8所示，多个辅助导通线120中的至少一个在衬底基板1000的正投影与第一扫描线GA1在衬底基板1000的正投影不交叠。以及，多个辅助导通线120中的至少一个在衬底基板1000的正投影与第二扫描线GA2在衬底基板1000的正投影不交叠。进一步地，可以使每一个辅助导通线120在衬底基板1000的正投影与第一扫描线GA1在衬底基板1000的正投影不交叠。以及，每一个辅助导通线120在衬底基板1000的正投影与第二扫描线GA2在衬底基板1000的正投影不交叠。
需要说明的是，多个子辅助电源线110沿第二方向F2延伸，指的可以是这些子辅助电源线110大致沿着第二方向F2进行延伸的。在实际应用中，可以使这些子辅助电源线110曲折的沿第二方向F2进行延伸。
示例性地，如图3、图6至图8所示，第二扫描线GA2可以包括相互电连接的扫描线部310和多个突出部320；其中，扫描线部310沿第一方向F1延伸，突出部320沿第二方向F2延伸。并且，突出部320可以作为晶体管的栅极，且各辅助导通线120在衬底基板1000的正投影与突出部320在衬底基板1000的正投影不交叠。这样可以避免辅助导通线120与突出部320之间存在正对面积，进一步降低辅助导通线120对晶体管的栅极的耦合影响。
示例性地，如图3、图4b、图6所示，突出部320可以作为第一子阈值 补偿晶体管T31的栅极，扫描线部310中的部分作为第二子补偿晶体管T32的栅极。这样可以避免辅助导通线120与突出部320之间存在正对面积，进一步降低辅助导通线120对第一子阈值补偿晶体管T31的栅极的耦合影响。
需要说明的是，扫描线部310沿第一方向F1延伸，指的可以是这些扫描线部310是大致沿着第一方向F1进行延伸的。在实际应用中，可以使这些扫描线部310延伸成一条直线，或者也可以使这些扫描线部310曲折的沿第一方向F1延伸。
示例性地，如图6至图12所示，显示面板还包括：多个重复单元001；其中，重复单元001包括多个子像素spx；并且，多个重复单元001沿第一方向F1排列形成一个重复单元行01，且重复单元行01沿第二方向F2排列。示例性地，相邻两个重复单元行01中的重复单元001错位排列。示例性地，相邻两个重复单元行01中的重复单元001相差1/2个重复单元001的尺寸。需要说明的是，上述的一个重复单元001的尺寸可以为：第一方向F1上相邻两个重复单元001中的相同颜色子像素的中心之间的距离。例如上述的一个重复单元001的尺寸可以为：第二方向F2上相邻两个重复单元001中的第一颜色子像素010的第一电极的中心之间的距离。
或者，例如，相邻重复单元行中的重复单元沿第一方向是彼此错开的，也就是说，相邻的重复单元行中的相邻的重复单元沿第一方向有一定的偏移量。因此，相邻重复单元行中相同颜色的子像素在第二方向上并不是对齐的。在一些示例中，相邻重复单元行中的相同颜色子像素在第一方向上的偏移量可以为重复单元在第一方向上的尺寸的一半。例如，重复单元在第一方向上的尺寸可以为重复单元在第一方向上的节距。
在具体实施时，在本公开实施例中，如图6至图12所示，多个重复单元中的子像素包括：沿第一方向F1排列的第一颜色子像素110、第二颜色子像素对020以及第三颜色子像素030；其中，第二颜色子像素对020可以包括沿第二方向F2排列的两个第二颜色子像素。例如，第二颜色子像素对020可以包括：沿第二方向F2排列的第一个第二颜色子像素021和第二个第二颜色子 像素022。示例性地，第一颜色子像素010被配置为发第一颜色的光，第二颜色子像素021、022被配置为发第二颜色的光，第三颜色子像素被配置为发第三颜色的光。在一些示例中，第一颜色、第二颜色以及第三颜色可以从红色、绿色以及蓝色中进行选取。例如，第一颜色为红色、第二颜色为绿色、第三颜色为蓝色。由此，该重复单元001为红绿蓝子像素的排列结构。当然，本公开实施例包括但不限于此。上述的第一颜色、第二颜色和第三颜色还可为其他颜色。
在具体实施时，在本公开实施例中，如图3、图6以及图11所示，辅助导通线120可以包括第一辅助导通线121；其中，部分相邻两个子辅助电源线110之间通过至少一条第一辅助导通线121电连接。示例性地，部分相邻两个子辅助电源线110之间可以通过一条第一辅助导通线121电连接。或者，部分相邻两个子辅助电源线110之间也可以通过2条第一辅助导通线121电连接。或者，部分相邻两个子辅助电源线110之间通过三条，或更多条第一辅助导通线121电连接。这可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6以及图11所示，可以使一个重复单元行01对应一条第一扫描线GA1、一条第二扫描线GA2以及至少一个第一辅助导通线121。示例性地，可以使一个重复单元行01对应一个、两个、三个或更多个第一辅助导通线121，这可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6以及图11所示，针对同一重复单元行01对应的第一扫描线GA1、第二扫描线GA2以及第一辅助导通线121，第一辅助导通线121在衬底基板1000的正投影位于第一扫描线GA1和第二扫描线GA2的突出部320在衬底基板1000的正投影之间。
在具体实施时，在本公开实施例中，如图6以及图12、图13所示，第一电极层600可以包括相互间隔设置的多个第一电极；其中，一个子像素设置一个第一电极。例如，第一颜色子像素010中设置有第一电极611，第一个第 二颜色子像素021中设置有第一电极621，第二个第二颜色子像素022中设置有第一电极622，第三颜色子像素030中设置有第一电极631。并且，可以使第一辅助导通线121在衬底基板1000的正投影与第一电极在衬底基板1000的正投影不交叠。
在具体实施时，在本公开实施例中，如图6至图12所示，至少部分第二颜色子像素对中的每一个对应一条第一辅助导通线121。示例性地，可以使部分第二颜色子像素对中的每一个对应一条第一辅助导通线121。也可以使所有第二颜色子像素对中的每一个对应一条第一辅助导通线121。这可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图3、图6至图12所示，可以使第一辅助导通线121在衬底基板的正投影位于对应的第二颜色子像素对中的两个第一电极在衬底基板的正投影之间。示例性地，可以使第一辅助导通线121在衬底基板1000的正投影位于对应的第一个第二颜色子像素021中的第一电极621和第二个第二颜色子像素022中的第一电极622在衬底基板1000的正投影之间。
在具体实施时，结合图3与图6所示，一列子像素中的数据写入晶体管与一条数据线电连接。针对同一重复单元001中第二颜色子像素对020和第一颜色子像素010，对应第二颜色子像素对020的第一辅助导通线121在衬底基板1000的正投影与第一颜色子像素010电连接的数据线VD在衬底基板100的正投影具有交叠区域。进一步地，在具体实施时，结合图3与图6所示，针对同一重复单元001中第二颜色子像素对020和第一颜色子像素010，对应第二颜色子像素对020的第一辅助导通线121在衬底基板1000的正投影与第一颜色子像素010中的第一连接过孔在衬底基板1000的正投影具有交叠区域。其中，第一连接通孔381a作为该第一连接过孔。
在具体实施时，结合图3与图6所示，各子像素中的第一复位晶体管通过第二连接过孔与第一复位信号线电连接。第一辅助导通线121在衬底基板的正投影与第二个第二颜色子像素中的第二连接过孔在衬底基板的正投影的 边缘具有交叠区域。示例性地，第一连接通孔387a作为该第二连接过孔。
在具体实施时，结合图3与图6所示，第一辅助导通线121沿第一方向延伸为直线形。这样可以降低电阻。当然，本公开实施例包括但不限于此，上述第一辅助导通线121的实施方式还可以为其他形状。
在具体实施时，结合图6所示，辅助导通线还可以包括第二辅助导通线122；其中，其余部分相邻两个子辅助电源线110之间通过至少一条第二辅助导通线122电连接。这样可以使每相邻两次子辅助电源线110之间分别可以采用辅助导通线进行电连接。示例性地，其余部分相邻两个子辅助电源线110之间可以通过一条第二辅助导通线122电连接。其余部分相邻两个子辅助电源线110之间也可以通过两条、三条或更多条第二辅助导通线122电连接。这可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，结合图3至图12所示，针对一个重复单元行01中的第一颜色子像素010和相邻重复单元行中且与第一颜色子像素010最近邻的第三颜色子像素030，第一颜色子像素010中的第一电极611在衬底基板1000的正投影与第三颜色子像素030中的第一电极631在衬底基板1000的正投影之间设置有一条第二辅助导通线122在衬底基板1000的正投影。进一步地，针对一个重复单元行01中的第一颜色子像素010和相邻重复单元行中且与第一颜色子像素010最近邻的第三颜色子像素030，第二辅助导通线122在衬底基板1000的正投影相对第一颜色子像素010中的第一电极611在衬底基板1000的正投影，靠近第三颜色子像素030中的第一电极631在衬底基板100的正投影。
在具体实施时，结合图3至图12所示，通过设置第一辅助导通线121和第二辅助导通线122，从而可以使子辅助电源线110与辅助导通线大致形成网格结构。
另一方面，一般发光器件的长期发光稳定性也是显示面板的一个重要的规格或指标。在研究中，本申请的公开人注意到：影响发光器件的长期发光稳定性的因素有很多，除了发光材料本身的寿命之外，像素驱动电路中的晶 体管的工作状态对发光亮度和长期发光稳定性都有一定程度的影响。
对此，本公开实施例提供了一些显示面板。结合图6至图13所示，显示面板可以包括衬底基板1000、像素驱动电路和第一电极层600；第一电极层600包括多个第一电极。一个像素驱动电路与一个第一电极一一对应设置，各像素驱动电路可以包括阈值补偿晶体管T3；显示面板还可以包括相邻设置的第一像素驱动电路2657和第二像素驱动电路2658，第一像素驱动电路2657中的阈值补偿晶体管T3的沟道区和第二像素驱动电路2658中的阈值补偿晶体管T3的沟道区在衬底基板1000的正投影均与第一像素驱动电路2657对应的第一电极在衬底基板的正投影具有交叠区域。由此，可以通过第一电极对第一像素驱动电路中的阈值补偿晶体管的沟道区和第二像素驱动电路中的阈值补偿晶体管的沟道区同时进行遮挡，从而可提高阈值补偿晶体管的稳定性和寿命，从而可提高该显示面板的长期发光稳定性和寿命。
需要说明的是，上述的第一像素驱动电路和第二像素驱动电路中的“第一”和“第二”仅用于在文字上将两个像素驱动电路进行区分，这两个像素驱动电路的具体结构相同。
在具体实施时，在本公开实施例中，由于第一像素驱动电路2657中的阈值补偿晶体管T3的沟道区和第二像素驱动电路2658中的阈值补偿晶体管T3的沟道区在衬底基板1000的正投影均与第一像素驱动电路2657对应的第一电极在衬底基板1000的正投影交叠，第一像素驱动电路2657对应的第一电极则可对第一像素驱动电路2657中的阈值补偿晶体管T3的沟道区和第二像素驱动电路2658中的阈值补偿晶体管T3的沟道区进行部分遮挡或完全遮挡。由此，本公开实施例中的显示面板，可提高第一像素驱动电路中的阈值补偿晶体管T3和第二像素驱动电路2658中的阈值补偿晶体管T3的稳定性和寿命，从而可提高该显示面板的长期发光稳定性和寿命。
在一些示例中，第一像素驱动电路2657中的阈值补偿晶体管T3的沟道区和第二像素驱动电路2658中的阈值补偿晶体管T3的沟道区可以均落入第一像素驱动电路2657对应的第一电极在衬底基板1000的正投影，第一像素 驱动电路2657对应的第一电极则可对第一像素驱动电路2657中的阈值补偿晶体管T3的沟道区和第二像素驱动电路2658中的阈值补偿晶体管T3的沟道区进行完全遮挡，从而进一步提高阈值补偿晶体管的稳定性和寿命，进而可提高该显示面板的长期发光稳定性和寿命。
在一些示例中，如图2a、图3、图4a以及图6所示，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，从而可提高阈值补偿晶体管的可靠性。其中，阈值补偿晶体管T3的有源层包括间隔设置的第一沟道区T31-A和第二沟道区T32-A，以及位于第一沟道区T31-A和第二沟道区T32-A之间的共用导体化区SE。并且，第一像素驱动电路2657中的阈值补偿晶体管T3的共用导体化区SE和第二像素驱动电路2658中的阈值补偿晶体管T3的共用导体化区SE在衬底基板1000的正投影均与第一像素驱动电路2657对应的第一电极在衬底基板1000的正投影具有交叠区域。由此，第一像素驱动电路2657对应的第一电极则可对第一像素驱动电路2657中的阈值补偿晶体管T3的共用导体化区SE和第二像素驱动电路2658中的阈值补偿晶体管T3的共用导体化区SE进行部分遮挡或完全遮挡，从而进一步提高阈值补偿晶体管的稳定性和寿命，进而可提高该显示面板的长期发光稳定性和寿命。
示例性地，如图6、图12和图13所示，第一像素驱动电路2657和第二像素驱动电路2658沿第一方向F1设置。其中，第一像素驱动电路2657与一个重复单元001中的第一电极631对应电连接。第二像素驱动电路2658与另一个重复单元001中的第一电极621对应电连接。并且，第一像素驱动电路2657电连接的第一电极631和第二像素驱动电路2658电连接的第一电极621分别位于不同的重复单元行01，且第一像素驱动电路2657电连接的第一电极631和第二像素驱动电路2658电连接的第一电极621所在的重复单元行01相邻。
示例性地，如图5、图6、图12和图13所示，像素限定层660包括多个开口；多个开口包括一个第一开口1951、一个第二开口19521、一个第三开口19522和一个第四开口1953。其中，第一开口1951与第一电极611对应设 置并暴露第一电极611，第二开口19521与第一电极621对应设置并暴露第一电极621，第三开口19522与第一电极622对应设置并暴露第一电极622，第四开口1953与第一电极631对应设置并暴露第一电极631。
示例性地，如图6、图12和图13所示，第一电极611包括相互电连接的第一主体部6111和第一连接部6112，第一开口1951在衬底基板1000的正投影落入第一主体部6111在衬底基板1000的正投影内，且第一连接部6112与第一电极611对应的像素驱动电路电连接。
示例性地，如图6、图12和图13所示，第一电极621包括相互电连接的第二主体部6211和第二连接部6212，第二开口19521在衬底基板1000的正投影落入第二主体部6211在衬底基板1000的正投影内，且第二连接部6212与第一电极621对应的像素驱动电路电连接。
示例性地，如图6、图12和图13所示，第一电极622包括相互电连接的第三主体部6221和第三连接部6222，第三开口19522在衬底基板1000的正投影落入第三主体部6221在衬底基板1000的正投影内，且第三连接部6222与第一电极622对应的像素驱动电路电连接。
示例性地，如图6、图12和图13所示，第一电极631包括第四主体部6311和第四连接部6312，第四开口1953在衬底基板1000的正投影落入第四主体部6311在衬底基板1000的正投影内，第四连接部6312与第一电极631对应的像素驱动电路(例如，上述的第一像素驱动电路2657电连接。
在一些示例中，如图6、图12和图13所示，第一主体部6111的形状与第一开口1951的形状大致相同；第二主体部6211的形状与第二开口19521的形状大致相同；第三主体部6221的形状与第三开口19522的形状大致相同；第四主体部6311的形状与第四开口1953的形状大致相同。例如，当第四开口1953的形状为六边形时，第四主体部6311的形状也为六边形。当然，第四开口和第四主体部的形状也不限于六边形，例如还可为椭圆形等其他形状。
在一些示例中，如图4a、图6、图12和图13所示，第一电极631还可以包括第一增补部6313。第一电极631对应的第一像素驱动电路2657中的阈 值补偿晶体管T3的第一沟道区T31-A和第二沟道区T32-A在衬底基板1000的正投影分别与第一增补部6313在衬底基板1000的正投影交叠。在该显示面板中，通过在第一电极增加第一增补部，使得第一电极可以与对应的像素驱动电路中的阈值补偿晶体管的两个沟道区交叠或覆盖，从而可提高阈值补偿晶体管的稳定性和寿命，从而可提高该显示面板的长期发光稳定性和寿命。
在一些示例中，如图6、图12和图13所示，第一增补部6313从第四主体部6311向第一电极622凸出，且第一增补部6313位于第四连接部6312靠近第四主体部6311的一侧。
在一些示例中，如图6、图12和图13所示，第一增补部6313与第四主体部6311和第四连接部6312均电连接。由此，该显示面板可充分利用显示面板上的面积，将第一电极紧密地排列，从而可保证显示面板的分辨率。
在一些示例中，如图6、图12和图13所示，第一电极611对应的像素驱动电路中的阈值补偿晶体管T3的沟道区在衬底基板1000的正投影落入第一主体部6111在衬底基板1000的正投影内。
在一些示例中，如图6、图12和图13所示，第一电极622对应的像素驱动电路265中的阈值补偿晶体管T3的第二沟道区T32-A在衬底基板1000的正投影落入第三主体部6221在衬底基板1000的正投影。
进一步地，如图14所示，第一电极631还可以包括第二增补部6314；第二像素驱动电路2658中的阈值补偿晶体管T3的第一沟道区T31-A在衬底基板1000的正投影与第二增补部6314在衬底基板1000的正投影交叠。通过在第一电极增加第二增补部，使得第一电极可以部分甚至完全覆盖第二像素驱动电路2658中的阈值补偿晶体管T3的第一沟道区T31-A，从而可提高阈值补偿晶体管的稳定性和寿命，从而可提高该显示面板的长期发光稳定性和寿命。
在一些示例中，如图14所示，第二增补部6314从第四主体部6311向在第一方向上相邻的第一电极611凸出。
需要说明的是，如图14所示，第二像素驱动电路2658中的阈值补偿晶 体管T3的第二沟道区T32-A在衬底基板1000的正投影可落入第四主体部6311在衬底基板1000的正投影内。
在一些示例中，如图14所示，第一像素驱动电路2657中的阈值补偿晶体管T3的共用导体化区SE与第一增补部6313在衬底基板1000的正投影交叠，第二像素驱动电路2658中的阈值补偿晶体管T3的共用导体化区SE在衬底基板1000的正投影与第一像素驱动电路2657对应的第一电极631的第四主体部6311在衬底基板1000的正投影交叠。
进一步地，如图14所示，第一电极611还可以包括第三增补部6113，从第一主体部6111向第一电极622凸出，第一电极611对应的像素驱动电路中的驱动薄膜晶体管T1的栅极和阈值补偿晶体管T3的漏极区域在衬底基板1000的正投影落入第三增补部6113在衬底基板1000的正投影内。由此，该显示面板可通过第三增补部6113来稳定驱动薄膜晶体管T1的栅极和阈值补偿晶体管T3的漏极上的电位，从而进一步提高该显示面板的长期发光稳定性和寿命。
进一步地，如图14所示，第一电极622还可以包括第四增补部6223，第一电极622对应的像素驱动电路中的阈值补偿晶体管T3的第一沟道区T31-A在衬底基板1000上正投影落入第四增补部6223在衬底基板1000的正投影内。由此，第一电极622的第三主体部6221和第四增补部6223可对第一电极622对应的像素驱动电路中的阈值补偿晶体管T3的第一沟道区T31-A和第一沟道区T32-A进行部分遮挡或完全遮挡，从而提高阈值补偿晶体管的稳定性和寿命，从而可提高该显示面板的长期发光稳定性和寿命。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种显示面板，其中，包括：
    衬底基板；
    栅导电层，位于所述衬底基板上，且所述栅导电层包括：多条扫描线；
    第一绝缘层，位于所述栅导电层上；
    第一导电层，位于所述第一绝缘层背离所述衬底基板一侧，且所述第一导电层包括多条数据线；其中，所述多条数据线沿第一方向排列；
    层间绝缘层，位于所述第一导电层背离所述衬底基板一侧；
    第二导电层，位于所述层间绝缘层背离所述衬底基板一侧，且所述第二导电层包括辅助电源线；
    所述辅助电源线包括：多个子辅助电源线和多个辅助导通线；其中，所述多个子辅助电源线沿所述第一方向排列且沿第二方向延伸，至少部分相邻的两个子辅助电源线之间通过至少一个所述辅助导通线电连接；所述第一方向与所述第二方向不同；
    所述多个辅助导通线中的至少一个在所述衬底基板的正投影与所述扫描线在所述衬底基板的正投影不交叠。
  2. 如权利要求1所述的显示面板，其中，所述多条扫描线包括第一扫描线和第二扫描线；其中，所述第二扫描线包括相互电连接的扫描线部和多个突出部；所述扫描线部沿所述第一方向延伸，所述突出部沿所述第二方向延伸；
    所述显示面板还包括：多个子像素；所述多个子像素中的至少一个包括像素驱动电路；所述像素驱动电路包括晶体管；
    所述突出部作为所述晶体管的栅极，且各所述辅助导通线在所述衬底基板的正投影与所述突出部在所述衬底基板的正投影不交叠。
  3. 如权利要求2所述的显示面板，其中，所述像素驱动电路包括：驱动晶体管和阈值补偿晶体管；其中，所述阈值补偿晶体管包括：第一子补偿晶 体管和第二子补偿晶体管；
    所述第一子补偿晶体管的栅极与所述第二扫描线电连接，所述第一子补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一子补偿晶体管的第二极与所述第二子补偿晶体管的第一极电连接；
    所述第二子补偿晶体管的栅极与所述第二扫描线电连接，所述第二子补偿晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述突出部作为所述第一子补偿晶体管的栅极；
    所述扫描线部中的部分作为所述第二子补偿晶体管的栅极。
  4. 如权利要求3所述的显示面板，其中，所述显示面板还包括：多个重复单元；其中，所述重复单元包括多个子像素；并且，所述多个重复单元沿所述第一方向排列形成一个重复单元行，且所述重复单元行沿所述第二方向排列；
    所述辅助导通线包括第一辅助导通线；其中，部分相邻两个所述子辅助电源线之间通过至少一条所述第一辅助导通线电连接；
    一个所述重复单元行对应一条所述第一扫描线、一条所述第二扫描线以及至少一个第一辅助导通线；
    针对同一所述重复单元行对应的所述第一扫描线、所述第二扫描线以及所述第一辅助导通线，所述第一辅助导通线在所述衬底基板的正投影位于所述第一扫描线和所述第二扫描线的突出部在所述衬底基板的正投影之间。
  5. 如权利要求4所述的显示面板，其中，所述显示面板还包括：
    平坦化层，位于所述第二导电层背离所述衬底基板一侧；
    第一电极层，位于所述平坦化层背离所述衬底基板一侧，且所述第一电极层包括相互间隔设置的多个第一电极；其中，一个所述子像素设置一个所述第一电极；
    所述第一辅助导通线在所述衬底基板的正投影与所述第一电极在所述衬底基板的正投影不交叠。
  6. 如权利要求4或5所述的显示面板，其中，所述多个重复单元中的子 像素包括：沿所述第一方向排列的第一颜色子像素、第二颜色子像素对以及第三颜色子像素；其中，所述第二颜色子像素对包括沿所述第二方向排列的两个第二颜色子像素；并且，相邻两个所述重复单元行中的重复单元错位排列。
  7. 如权利要求6所述的显示面板，其中，至少部分所述第二颜色子像素对中的每一个对应一条所述第一辅助导通线；
    所述第一辅助导通线在所述衬底基板的正投影位于对应的所述第二颜色子像素对中的两个第一电极在所述衬底基板的正投影之间。
  8. 如权利要求7所述的显示面板，其中，所述像素驱动电路还包括数据写入晶体管；其中，一列子像素中的数据写入晶体管与一条所述数据线电连接；
    针对同一所述重复单元中第二颜色子像素对和第一颜色子像素，对应所述第二颜色子像素对的第一辅助导通线在所述衬底基板的正投影与所述第一颜色子像素电连接的数据线在所述衬底基板的正投影具有交叠区域。
  9. 如权利要求8所述的显示面板，其中，所述数据写入晶体管通过第一连接过孔与所述数据线电连接；
    针对同一所述重复单元中第二颜色子像素对和第一颜色子像素，对应所述第二颜色子像素对的第一辅助导通线在所述衬底基板的正投影与所述第一颜色子像素中的所述第一连接过孔在所述衬底基板的正投影具有交叠区域。
  10. 如权利要求9所述的显示面板，其中，所述像素驱动电路还包括第一复位晶体管；所述显示面板还包括多条第一复位信号线；其中，各所述子像素中的第一复位晶体管通过第二连接过孔与所述第一复位信号线电连接；
    所述第二颜色子像素对包括：沿第二方向排列的第一个第二颜色子像素和第二个第二颜色子像素；所述第一辅助导通线在所述衬底基板的正投影与所述第二个第二颜色子像素中的所述第二连接过孔在所述衬底基板的正投影的边缘具有交叠区域。
  11. 如权利要求4-10任一项所述的显示面板，其中，所述第一辅助导通 线沿所述第一方向延伸为直线形。
  12. 如权利要求4-11任一项所述的显示面板，其中，所述辅助导通线还包括第二辅助导通线；其中，其余部分相邻两个所述子辅助电源线之间通过至少一条所述第二辅助导通线电连接。
  13. 如权利要求12所述的显示面板，其中，针对一个重复单元行中的第一颜色子像素和相邻重复单元行中且与所述第一颜色子像素最近邻的第三颜色子像素，所述第一颜色子像素中的第一电极在所述衬底基板的正投影与所述第三颜色子像素中的第一电极在所述衬底基板的正投影之间设置有一条所述第二辅助导通线在所述衬底基板的正投影。
  14. 如权利要求13所述的显示面板，其中，针对一个重复单元行中的第一颜色子像素和相邻重复单元行中且与所述第一颜色子像素最近邻的第三颜色子像素，所述第二辅助导通线在所述衬底基板的正投影相对所述第一颜色子像素中的第一电极在所述衬底基板的正投影，靠近所述第三颜色子像素中的第一电极在所述衬底基板的正投影。
  15. 如权利要求1-11任一项所述的显示面板，其中，所述第一导电层还包括主电源线；其中，所述主电源线与所述数据线间隔设置；
    所述层间绝缘层具有第一电源过孔；
    所述主电源线通过所述第一电源过孔与所述辅助电源线彼此电连接。
  16. 如权利要求15所述的显示面板，其中，所述主电源线在所述衬底基板的正投影与所述辅助电源线在所述衬底基板的正投影具有交叠区域。
  17. 如权利要求1-16任一项所述的显示面板，其中，所述子辅助电源线与所述辅助导通线大致形成网格结构。
  18. 如权利要求1-17任一项所述的显示面板，其中，所述辅助电源线被配置为传输驱动电压的电源线。
  19. 一种显示装置，其中，包括如权利要求1-18任一项所述的显示面板。
PCT/CN2020/081168 2020-03-25 2020-03-25 显示面板及显示装置 WO2021189313A1 (zh)

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