WO2024045830A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2024045830A1
WO2024045830A1 PCT/CN2023/103163 CN2023103163W WO2024045830A1 WO 2024045830 A1 WO2024045830 A1 WO 2024045830A1 CN 2023103163 W CN2023103163 W CN 2023103163W WO 2024045830 A1 WO2024045830 A1 WO 2024045830A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
light
control
drain
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PCT/CN2023/103163
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English (en)
French (fr)
Inventor
张筱霞
戴超
阳志林
Original Assignee
武汉华星光电半导体显示技术有限公司
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Publication of WO2024045830A1 publication Critical patent/WO2024045830A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • the present application relates to the field of display technology, and specifically to a pixel circuit and a display panel.
  • the pixel circuit may need to switch from high-frequency driving to low-frequency driving, that is, the frequency of one or more signals is reduced from high frequency such as 120Hz or 60Hz to low frequency such as 10Hz or 1Hz.
  • high-frequency driving that is, the frequency of one or more signals is reduced from high frequency such as 120Hz or 60Hz to low frequency such as 10Hz or 1Hz.
  • the data signal will not be rewritten, that is, the gate potential of the driving transistor remains unchanged, but the potential of the source and/or drain of the driving transistor will change periodically, which will easily lead to brightness changes when switching to low-frequency driving. Flickering occurs.
  • the present application provides a pixel circuit and a display panel to alleviate the technical problem that the potential of the source and/or drain of the driving transistor changes periodically when switching to low-frequency driving.
  • the present application provides a pixel circuit.
  • the pixel circuit includes a driving transistor, a writing transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a first initialization transistor.
  • the writing transistor is in the source or drain of the transistor.
  • One of the writing transistors is electrically connected to the driving transistor, the other of the source or drain of the writing transistor is electrically connected to the data line, the gate of the writing transistor is connected to the first control line; the source of the first light emitting control transistor Or one of the drain electrodes is electrically connected to one of the source electrode or the drain electrode of the driving transistor, and the other one of the source electrode or the drain electrode of the first light-emitting control transistor is electrically connected to the positive power line, and the first light-emitting control transistor
  • the gate of the second light-emitting control transistor is electrically connected to the first light-emitting control line; one of the source or drain of the second light-emitting control transistor is electrically connected to the other of the source or drain of the driving transistor, and the second light-emitting control transistor is electrically connected to the gate.
  • the other one of the source electrode or the drain electrode is electrically connected to the negative power line
  • the gate electrode of the second light-emitting control transistor is electrically connected to the first light-emitting control line or the second light-emitting control line
  • the source electrode or the drain electrode of the first initialization transistor One of the source electrodes or the drain electrodes of the first initialization transistor is electrically connected to the source electrode or the drain electrode of the first initialization transistor.
  • the other one of the source electrodes or drain electrodes of the first initialization transistor is electrically connected to the first initialization line.
  • the control line is electrically connected and used to initialize the potential of the source or drain of the driving transistor at least once before and after the charging phase of one frame.
  • the driving transistor when the first initialization transistor is in the on state, the driving transistor is in the on state, and the writing transistor, the first light emitting control transistor and the second light emitting control transistor are all in the off state.
  • the pixel circuit further includes a coupling capacitor and a storage capacitor.
  • One end of the coupling capacitor is electrically connected to one of the gate of the driving transistor and the source or drain of the writing transistor.
  • the other end of the coupling capacitor is electrically connected to The other one of the source or the drain of the second light emitting control transistor is electrically connected;
  • one end of the storage capacitor is electrically connected to the other end of the coupling capacitor, and the other end of the storage capacitor is electrically connected to the positive power line.
  • the gate of the second light-emitting control transistor is electrically connected to the first light-emitting control line; during the charging phase, the conduction time of the write transistor is related to the first light-emitting control transistor and/or the second light-emitting control transistor.
  • the conduction times of the transistors overlap at least partially.
  • the first control line is used to transmit the first control signal
  • the second control line is used to transmit the second control signal.
  • the first control signal and the second control signal both have sequentially distributed patterns in one frame.
  • the waveform of the first control signal is the same as the waveform of the second control signal, and the phase of the second control signal lags behind the phase of the first control signal; in one frame, the A pulse is temporally positioned between the first pulse of the first control signal and the second pulse of the first control signal, and the second pulse of the first control signal is temporally positioned between the first pulse of the second control signal and the second pulse of the second control signal. between the second pulse of the signal.
  • the data line is used to transmit a data signal; the duration of the first pulse is less than the duration of the second pulse; and during the duration of the first pulse, the potential of the data signal is less than the pulse amplitude of the data signal.
  • the pixel circuit further includes a storage capacitor and a first transistor.
  • One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is connected to the source or drain of the second light-emitting control transistor.
  • the other one is electrically connected; one of the source electrode or the drain electrode of the first transistor is electrically connected to one of the source electrode or the drain electrode of the driving transistor, and the other one of the source electrode or the drain electrode of the first transistor is electrically connected to the driving electrode.
  • the gate of the transistor is electrically connected, and the gate of the first transistor is electrically connected to the third control line; wherein, one of the source or drain of the writing transistor and the other of the source or drain of the driving transistor Electrically connected; when the first initialization transistor is in the on state, the driving transistor is in the on state, and the writing transistor, the first light emitting control transistor, the second light emitting control transistor are in the on state. and the first transistor are both in the off state.
  • the first initialization transistor when the first initialization transistor is in the off state, the first transistor and the first light emitting control transistor are both in the on state, and the writing transistor and the second light emitting control transistor are in the off state.
  • the pixel circuit further includes a light-emitting device and a second initialization transistor.
  • the anode of the light-emitting device is electrically connected to the other one of the source or drain of the second light-emitting control transistor.
  • the cathode of the light-emitting device is connected to the negative power supply.
  • one of the source or drain of the second initialization transistor is connected to the anode of the light-emitting device, the other of the source or drain of the second initialization transistor is electrically connected to the second initialization line, and the second initialization transistor
  • the gate is electrically connected to the fourth control line or the third control line; wherein, the second initialization transistor is in a conductive state multiple times in the non-light-emitting phase of one frame.
  • the present application provides a display panel, which includes the pixel circuit in at least one embodiment, wherein the channel type of the driving transistor and the channel type of the writing transistor, and the channel type of the first light-emitting control transistor are The channel type, the channel type of the second light emission control transistor and the channel type of the first initialization transistor are all the same.
  • the pixel circuit and display panel provided by this application can initialize the potential of the source or drain of the driving transistor at least once before and after the charging stage of a frame, so that the potential of one of the source or drain of the driving transistor can be adjusted before and after charging.
  • the potential is reset, and then the potential of the other of the source or drain of the driving transistor can be reset through the linkage of the driving transistor itself. This can stabilize the potential of the source or drain of the driving transistor, even if the pixel circuit switches the driving frequency. Maintaining the three-terminal voltage of the driving transistor improves the flicker phenomenon caused by periodic changes in the potential of the source and/or drain of the driving transistor.
  • Figure 1 is a first structural schematic diagram of a pixel circuit in the related art.
  • FIG. 2 is a timing diagram of the pixel circuit shown in FIG. 1 .
  • FIG. 3 is a second structural schematic diagram of a pixel circuit in the related art.
  • FIG. 4 is a timing diagram of the pixel circuit shown in FIG. 3 .
  • FIG. 5 is a first structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a working state of the pixel circuit shown in FIG. 5 .
  • FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 5 .
  • FIG. 8 is a second structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a working state of the pixel circuit shown in FIG. 8 .
  • FIG. 10 is a timing diagram of the pixel circuit shown in FIG. 8 .
  • Figure 1 is a schematic structural diagram of the first pixel circuit in the related art. The working process of the pixel circuit is shown in Figure 2, including the following four stages:
  • the first stage the reset signal Reset and the scan signal Scan(n) are set high, the transistor T4 and the transistor T3 are turned on, and the low potential Vref of the initialization signal Vint and the data signal Data are written to the node N2 and the node N1 respectively. Due to the coupling capacitance The existence of C1 causes a fixed pressure difference between node N1 and node N2.
  • VN1 is the potential of node N1.
  • VN2 is the potential of node N2.
  • VD1 is the anode potential of the light-emitting device D1.
  • Vth is the threshold voltage of drive transistor T1.
  • VSS is the potential of the negative power signal transmitted in the negative power line.
  • the third stage the reset signal Reset is set low, the potential of the scan signal Scan(n) remains unchanged, the light-emitting control signal EM is set low, the potential of the data signal Data jumps from the low potential Vref to the high potential, and the voltage of the node N1 subsequently changes from low to high.
  • the potential Vref jumps to the high potential of the data signal Data.
  • C1 is the capacitance of coupling capacitor C1.
  • Cst is the capacitance of the storage capacitor Cst.
  • CD1 is the equivalent capacitance of the light-emitting device D1.
  • ⁇ VN1 is the potential change amount of node N1.
  • ⁇ VN2 is the potential change amount of node N2.
  • the fourth stage the reset signal Reset is set low, the electrical position of the scan signal Scan(n) is low, and the light is emitted.
  • the control signal EM is set high, and the positive power signal VDD transmitted in the positive power line flows to the negative power signal VSS. After the transistor T2 is turned on, the node N2 charges the capacitor of the light-emitting device until it is saturated and starts to emit light.
  • the frequency of the scanning signal Scan(n) also needs to be reduced from high frequency such as 120Hz or 60Hz to low frequency such as 10Hz or 1Hz.
  • the data signal Data will not be rewritten, that is, the gate potential of the driving transistor T1 remains unchanged, but the potential of the source and/or drain of the driving transistor T1 will change periodically, so Flickering is prone to occur.
  • FIG 3 is a second structural schematic diagram of a pixel circuit in the related art. The working process of the pixel circuit is shown in Figure 4, including the following four stages:
  • the first stage the light-emitting control signal EM2 and the scanning signal Nscan1 are both set high, and the transistors T4 and T6 are turned on, which can write the positive power supply signal VDD and the initialization signal Vi_1 to the two plates of the storage capacitor Cst respectively, ensuring that the storage capacitor Cst There is a fixed potential difference between the two ends.
  • the second stage the scanning signal Nscan2 is set high and the scanning signal Nscan1 is set low. At this time, the data signal Data will be written to node A through the transistor T2 and the driving transistor T1. However, because the scanning signal Nscan1 is set low, the transistor T3 cannot be turned on, that is, It says that the data signal Data cannot be written to node Q point.
  • the third stage The scanning signal Nscan1 and the scanning signal Nscan2 are both set high, and the data signal Data is written to node Q.
  • the fourth stage the light-emitting control signal EM1 and the light-emitting control signal EM2 are both set high, and the light-emitting device D1 emits normal light.
  • the frequency of the scanning signal Nscan1 also needs to be reduced from high frequency such as 120Hz or 60Hz to low frequency such as 10Hz or 1Hz.
  • the data signal Data will not be rewritten, that is, the gate potential of the driving transistor T1 remains unchanged, but the potential of the source and/or drain of the driving transistor T1 will change periodically, which is prone to flickering. Phenomenon.
  • the pixel circuit includes at least one of a driving transistor T1, a writing transistor T2, a first light emission control transistor T4, a second light emission control transistor T5 and a first initialization transistor T7.
  • a driving transistor T1 a writing transistor T2
  • a first light emission control transistor T4 a second light emission control transistor T5
  • a first initialization transistor T7 One of the source or drain of the writing transistor T2 is electrically connected to the driving transistor T1.
  • the other one of the source or the drain of the transistor T2 is electrically connected to the data line, and the gate of the writing transistor T2 is connected to the first control line.
  • One of the source electrode or the drain electrode of the first light emitting control transistor T4 is electrically connected to one of the source electrode or the drain electrode of the driving transistor T1.
  • the other one of the source electrode or the drain electrode of the first light emitting control transistor T4 is connected to the positive electrode.
  • the power supply line is electrically connected, and the gate of the first light-emitting control transistor T4 is electrically connected to the first light-emitting control line.
  • One of the source electrode or the drain electrode of the second light emission control transistor T5 is electrically connected to the other of the source electrode or the drain electrode of the driving transistor T1, and the other one of the source electrode or the drain electrode of the second light emission control transistor T5 is electrically connected to The negative power supply line is electrically connected, and the gate of the second light-emitting control transistor T5 is electrically connected to the first light-emitting control line or the second light-emitting control line.
  • One of the source electrode or the drain electrode of the first initialization transistor T7 is electrically connected to the source electrode or the drain electrode of the driving transistor T1, and the other one of the source electrode or the drain electrode of the first initialization transistor T7 is electrically connected to the first initialization line. connection, the gate of the first initialization transistor T7 is electrically connected to the second control line, and is used to initialize the potential of the source or drain of the driving transistor T1 at least once before and after the charging phase of one frame.
  • the pixel circuit provided in this embodiment can initialize the potential of the source or drain of the driving transistor T1 at least once before and after the charging stage of a frame, so that the source or drain of the driving transistor T1 can be reset before and after charging.
  • the potential of one of the drains is reset, and then the potential of the source or drain of the driving transistor T1 can be reset through the linkage of the driving transistor T1 itself. This can stabilize the potential of the source or drain of the driving transistor T1.
  • Even if the pixel circuit switches the driving frequency the three-terminal voltage of the driving transistor T1 can be maintained, thereby improving the flicker phenomenon caused by periodic changes in the potential of the source and/or drain of the driving transistor T1.
  • the gate electrode of the first light emission control transistor T4 and the gate electrode of the second light emission control transistor T5 share the same first light emission control line, thereby reducing the number of signal lines required for the pixel circuit. This is beneficial to improving the aperture ratio of the display panel.
  • the writing transistor T2 the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are all in the off state, which can prevent other signals from changing the potential of the source and/or drain of the driving transistor T1 during this stage.
  • the first initialization transistor T7 and the driving transistor T1 are in the on state, they can respectively adjust the potential of the source or drain of the driving transistor T1 before and after charging. Resetting is performed, and then the potential of the other source or drain of the driving transistor T1 can be reset through the linkage of the driving transistor T1 itself, so that the potential of the source or the drain of the driving transistor T1 can be stabilized.
  • the pixel circuit also includes a coupling capacitor C1 and a storage capacitor Cst.
  • One end of the coupling capacitor C1 is connected to the gate of the driving transistor T1 and the source or drain of the writing transistor T2.
  • One of the electrodes is electrically connected, and the other end of the coupling capacitor C1 is electrically connected to the other of the source electrode or the drain electrode of the second light-emitting control transistor T5.
  • One end of the storage capacitor Cst is electrically connected to the other end of the coupling capacitor C1, and the other end of the storage capacitor Cst is electrically connected to the positive power line.
  • one of the source or drain of the writing transistor T2 is directly electrically connected to the gate of the driving transistor T1, which can reduce the transmission path of the data signal Data to the gate of the driving transistor T1 and reduce the data transmission cost.
  • the transmission voltage drop loss of signal Data is directly electrically connected to the gate of the driving transistor T1, which can reduce the transmission path of the data signal Data to the gate of the driving transistor T1 and reduce the data transmission cost.
  • the gate of the second light-emitting control transistor T5 is electrically connected to the first light-emitting control line.
  • the conduction time of the write transistor T2 at least partially overlaps with the conduction time of the first light emission control transistor T4 and/or the second light emission control transistor T5.
  • the conduction of the first light-emitting control transistor T4 and/or the second light-emitting control transistor T5 can be triggered by the positive power supply signal VDD. Take the threshold voltage of drive transistor T1.
  • the first control line is used to transmit a first control signal
  • the second control line is used to transmit a second control signal.
  • Both the first control signal and the second control signal have sequentially distributed patterns in one frame.
  • First pulse, second pulse The waveform of the first control signal is the same as the waveform of the second control signal, and the phase of the second control signal lags behind the phase of the first control signal.
  • the first pulse of the second control signal is located between the first pulse of the first control signal and the second pulse of the first control signal in time
  • the second pulse of the first control signal is located in time between the first pulse of the first control signal and the second pulse of the first control signal. between the first pulse of the two control signals and the second pulse of the second control signal.
  • the first pulse of the first control signal is used to reset the gate potential of the driving transistor T1 using the low potential of the data signal Data
  • the second pulse of the first control signal is used to write the low potential of the data signal Data.
  • the high potential to the gate potential of the driving transistor T1 charges the pixel circuit.
  • the first pulse of the second control signal is used to change the source potential of the driving transistor T1 before charging in one frame or
  • the second pulse of the second control signal is used to initialize the source potential or the drain potential of the driving transistor T1 after charging in one frame.
  • the data line is used to transmit the data signal Data.
  • the duration of the first pulse is less than the duration of the second pulse.
  • the potential of the data signal Data is smaller than the pulse amplitude of the data signal Data.
  • the first pulse of the first control signal and the first pulse of the second control signal are both used to reset the corresponding node potential, and the duration of the second pulse of the first control signal determines the charging time. Therefore, the duration of the second pulse needs to be appropriately configured to meet the charging time requirements. The duration of the first pulse has almost no impact on the reset effect. Therefore, a shorter time can be configured for the first pulse to reduce power consumption.
  • the pixel circuit further includes a storage capacitor Cst and a first transistor T3.
  • One end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the other end of the storage capacitor Cst is electrically connected to the other one of the source or the drain of the second light emission control transistor T5.
  • One of the source electrode or the drain electrode of the first transistor T3 is electrically connected to one of the source electrode or the drain electrode of the driving transistor T1.
  • the other one of the source electrode or the drain electrode of the first transistor T3 is connected to the gate of the driving transistor T1.
  • the gate electrode of the first transistor T3 is electrically connected to the third control line.
  • one of the source electrode or the drain electrode of the writing transistor T2 is electrically connected to the other one of the source electrode or the drain electrode of the driving transistor T1.
  • the driving transistor T1 is in the on state
  • the writing transistor T2 the first light emitting control transistor T4, the second light emitting control transistor T5 and the first transistor T3 are all in the off state.
  • the first transistor T3 can reset the anode potential of the light-emitting device D1 to accurately control the accuracy of the luminous intensity in each frame.
  • the writing transistor T2, the first light-emitting control transistor T4, the second light-emitting control transistor T5 and the first transistor T3 are all in the off state, which can prevent other signals from changing the potential of the source and/or drain of the driving transistor T1 during this stage.
  • the first initialization transistor T7 and the driving transistor T1 are in a conductive state, the potential of the source or the drain of the driving transistor T1 can be reset respectively before and after charging, and then the driving transistor T1 can be reset through the linkage effect of the driving transistor T1 itself.
  • the potential of the other one of the source or drain of the driving transistor T1 can be stabilized.
  • the first transistor The transistor T3 and the first light-emitting control transistor T4 are both in a conductive state, and the writing transistor T2 and the second light-emitting control transistor T5 are both in a cut-off state.
  • the first transistor T3 can not only be used to transmit the data signal Data to the gate of the driving transistor T1 to realize charging of the pixel circuit, but can also be used to transmit the positive power signal VDD to the driving transistor.
  • the gate of T1 resets the gate potential of the drive transistor T1.
  • the pixel circuit further includes a light-emitting device D1 and a second initialization transistor T6.
  • the anode of the light-emitting device D1 is electrically connected to the other one of the source or the drain of the second light-emitting control transistor T5, and the cathode of the light-emitting device D1 is connected to the negative power line.
  • One of the source electrode or the drain electrode of the second initialization transistor T6 is connected to the anode of the light emitting device D1, and the other one of the source electrode or the drain electrode of the second initialization transistor T6 is electrically connected to the second initialization line.
  • the second initialization transistor T6 The gate of T6 is electrically connected to the fourth control line or the third control line. Among them, the second initialization transistor T6 is in the conducting state multiple times in the non-light-emitting phase of one frame.
  • the gate of the second initialization transistor T6 when the gate of the second initialization transistor T6 is electrically connected to the third control line, it can share the same third control line with the gate of the first transistor T3, which can reduce the number of signal lines required by the pixel circuit. , which is beneficial to improving the aperture ratio of the display panel.
  • Each turn-on of the second initialization transistor T6 in the non-light-emitting phase of a frame can reset the source potential and/or the drain potential of the driving transistor T1.
  • the light-emitting device D1 can be an organic light-emitting diode, a mini-light-emitting diode, a micro-light-emitting diode or a quantum dot light-emitting diode.
  • the channel type of the driving transistor T1, the channel type of the writing transistor T2, the channel type of the first emission control transistor T4, the channel type of the second emission control transistor T5, the first initialization transistor At least one of the channel type of T7, the channel type of the first transistor T3, and the channel type of the first initialization transistor T7 may be an N-channel type or a P-channel type, specifically, it may also be an N-channel type metal oxide Thin film transistor or P-channel low-temperature polysilicon thin film transistor.
  • the positive power supply line is used to transmit the positive power supply signal VDD
  • the negative power supply line is used to transmit the negative power supply signal VSS.
  • the potential of the positive power supply signal VDD is higher than the potential of the negative power supply signal VSS.
  • the data line is used to transmit the data signal Data.
  • the first lighting control line is used to transmit a first lighting control signal, and the first lighting control signal may be a lighting control signal EM or a lighting control signal EM2.
  • the second lighting control line For transmitting the second light-emitting control signal, the second light-emitting control signal may be the light-emitting control signal EM1.
  • the first control line is used to transmit a first control signal, and the first control signal may be a scan signal Scan(n) or a scan signal Nscan2.
  • the second control line is used to transmit a second control signal, and the second control signal may be a scan signal Scan(n+1) or a scan signal Nscan1(n+1).
  • the third control line is used to transmit a third control signal, and the third control signal may be the scan signal Nscan1(n).
  • the fourth control line is used to transmit a fourth control signal, and the fourth control signal may be the scanning signal Scan(n-2).
  • the first initialization line is used to transmit a first initialization signal, and the first initialization signal may be the voltage signal Vi_2.
  • the second initialization line is used to transmit a second initialization signal, and the second initialization signal may be the voltage signal Vi_1.
  • Figure 7 is a timing diagram of the pixel circuit shown in Figure 5.
  • the working process of the pixel circuit shown in Figure 5 in one frame includes the following stages:
  • the first stage S1 When the scan signal Scan(n-2) and the scan signal Scan(n) are at high potential, the write transistor T2 and the second initialization transistor T6 are turned on, and the low potential of the data signal Data and the second initialization signal are respectively Reset node Q and node C.
  • Second stage S2 The scan signal Scan(n+1) is at a high potential, the first initialization transistor T7 is turned on, at this time, the driving transistor T1 is also in an open state, and the first initialization signal resets one of the node A or the node B. , and then by driving the transistor T1 to its own open state, the other one of node A or node B can be linked to reset.
  • the third stage S3 The scan signal Scan(n) is at a high potential, the writing transistor T2 is turned on, and the high potential of the data signal Data is charged to the gate of the driving transistor T1; in this stage, the light-emitting control signal EM is activated at least part of the time. At a high potential, at this time, both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on, and the threshold voltage of the driving transistor T1 can be captured through the positive power supply signal VDD.
  • the fourth stage S4 The scan signal Scan(n+1) is at a high potential, the first initialization transistor T7 is turned on, at this time, the driving transistor T1 is also in an open state, and the first initialization signal resets one of the node A or the node B. , and then by driving the transistor T1 to its own open state, the other one of node A or node B can be linked to reset.
  • the fifth stage S5 the light-emitting control signal EM is at a high potential, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are both turned on, and the light-emitting device D1 starts to emit light.
  • the second light emission control transistor T5, the first initialization transistor T7 and the second initialization transistor The channel aspect ratio W/L of the body tube T6 is the same, which can ensure the consistency of the conduction degree of the three. Setting the channel aspect ratio W/L of the three to a range of 0.5 to 1 can ensure the adequacy of conduction among the three.
  • W is the channel width and L is the channel length.
  • the gate control signal of the second initialization transistor T6 in the pixel circuit shown in FIGS. 5 and 6 becomes the scan signal Scan(n-2), and
  • the scan signal Scan(n-2), the scan signal Scan(n+1) and the scan signal Scan(n) all have a first pulse and a second pulse that appear successively.
  • the pulse width of the first pulse may be 1/2H
  • the pulse width of the second pulse may be 1H
  • the interval between the first pulse and the second pulse of the same scanning signal is 1H.
  • the high-level time of the scan signal Scan(n) is all within the low-level period of the light-emitting control signal EM, with the exception of the first pulse of the light-emitting control signal EM.
  • the pulse width of each pulse may be 1/2H, which is consistent with the rising edge of the second pulse of the scanning signal Scan(n), and at the falling edge of the second pulse of the scanning signal Scan(n+1), the luminescence control signal EM
  • H 1/(display frequency*number of pixel rows).
  • Figure 10 is a timing diagram of the pixel circuit shown in Figure 8.
  • the working process of the pixel circuit shown in Figure 8 in one frame includes the following stages:
  • the first stage S1 the scanning signal Nscan1(n) and the emission control signal EM2 are at high potential, the first emission control transistor T4, the first transistor T3 and the second initialization transistor T6 are turned on, and the positive power supply signal VDD is applied to the node A and the node Q. Reset, the second initialization signal resets node C.
  • Second stage S2 The scan signal Nscan(n+1) is at a high potential, the first initialization transistor T7 is turned on, at this time, the driving transistor T1 is also in an open state, and the first initialization signal resets one of node A or node B. , and then by driving the transistor T1 to its own open state, the other one of node A or node B can be linked to reset.
  • the third stage S3 the second pulse of the scanning signal Nscan(n) and the second pulse of the scanning signal Nscan2 are at high potential, the first transistor T3 and the writing transistor T2 are turned on, and the high potential of the data signal Data is charged to the driving transistor T1 gate.
  • the fourth stage S4 The scan signal Nscan(n+1) is at a high potential, the first initialization transistor T7 is turned on, at this time, the driving transistor T1 is also in an open state, and the first initialization signal is applied to node A or One of the nodes B is reset, and then by driving the transistor T1 to its own open state, the node A or the other node B can be reset.
  • the fifth stage S5 the light-emitting control signal EM1 and the light-emitting control signal EM2 are both at high potential, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are both turned on, and the light-emitting device D1 starts to emit light.
  • the channel aspect ratio W/L of the first initialization transistor T7 and the second initialization transistor T6 is the same, which can ensure the consistency of the conduction degree of the two. Setting the channel aspect ratio W/L of both to a range of 0.5 to 1 can ensure the adequacy of conduction between the two.
  • W is the channel width and L is the channel length.
  • the scanning signal Nscan1(n+1) has a first pulse and a second pulse that appear sequentially when the light-emitting control signal EM1 and the light-emitting control signal EM2 are in a low-potential state, which are in phase with the scanning signal Nscan1(n).
  • the first pulse of the scanning signal Nscan1(n+1) lags behind the first pulse 1H of the scanning signal Nscan1(n).
  • the pulse of the scan signal Nscan2 in one frame is located between the first pulse of the scan signal Nscan1(n+1) and the second pulse of the scan signal Nscan1(n+1). This ensures that the charging of node A and/or before and after charging is achieved. Node B performs a reset respectively.
  • this embodiment provides a display panel, which includes the pixel circuit in at least one of the above embodiments.
  • the display panel provided in this embodiment can initialize the potential of the source or drain of the driving transistor T1 at least once before and after the charging phase of a frame, so that the source or drain of the driving transistor T1 can be reset before and after charging.
  • the potential of one of the drains is reset, and then the potential of the source or the other drain of the driving transistor T1 can be reset through the linkage of the driving transistor T1 itself. This can stabilize the potential of the source or drain of the driving transistor T1.
  • Even if the pixel circuit switches the driving frequency the three-terminal voltage of the driving transistor T1 can be maintained, thereby improving the flicker phenomenon caused by periodic changes in the potential of the source and/or drain of the driving transistor T1.

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Abstract

一种像素电路及显示面板，属于显示技术领域，像素电路包括驱动晶体管（T1）、写入晶体管（T2）、第一发光控制晶体管（T4）、第二发光控制晶体管（T5）以及第一初始化晶体管（T7），通过在一帧的充电阶段前后分别初始化至少一次驱动晶体管（T1）的源极或者漏极的电位，可以稳定驱动晶体管（T1）的源极或者漏极的电位。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
背景技术
像素电路在工作过程中有可能需要从高频驱动切换至低频驱动，即某一个或者多个信号的频率从120Hz或者60Hz等高频降低到10Hz或者1Hz等低频，然而进行这种频率切换后，数据信号不会被重新写入即驱动晶体管的栅极电位保持不变，而驱动晶体管的源极和/或漏极的电位会发生周期性变化，这样在切换至低频驱动时容易导致亮度变化，出现闪烁现象。
技术问题
本申请提供一种像素电路及显示面板，以缓解切换至低频驱动时驱动晶体管的源极和/或漏极的电位会发生周期性变化的技术问题。
技术解决方案
第一方面，本申请提供一种像素电路，该像素电路包括驱动晶体管、写入晶体管、第一发光控制晶体管、第二发光控制晶体管以及第一初始化晶体管，写入晶体管的源极或者漏极中的一个与驱动晶体管电性连接，写入晶体管的源极或者漏极中的另一个与数据线电性连接，写入晶体管的栅极与第一控制线连接；第一发光控制晶体管的源极或者漏极中的一个与驱动晶体管的源极或者漏极中的一个电性连接，第一发光控制晶体管的源极或者漏极中的另一个与正电源线电性连接，第一发光控制晶体管的栅极与第一发光控制线电性连接；第二发光控制晶体管的源极或者漏极中的一个与驱动晶体管的源极或者漏极中的另一个电性连接，第二发光控制晶体管的源极或者漏极中的另一个与负电源线电性连接，第二发光控制晶体管的栅极与第一发光控制线或者第二发光控制线电性连接；第一初始化晶体管的源极或者漏极中的一个与驱动晶体管的源极或者漏极电性连接，第一初始化晶体管的源极或者漏极中的另一个与第一初始化线电性连接，第一初始化晶体管的栅极与第二控制线电性连接，用于在一帧的充电阶段前后分别初始化至少一次驱动晶体管的源极或者漏极的电位。
在其中一些实施方式中，第一初始化晶体管处于导通状态时，驱动晶体管处于导通状态，且写入晶体管、第一发光控制晶体管以及第二发光控制晶体管均处于截止状态。
在其中一些实施方式中，像素电路还包括耦合电容和存储电容，耦合电容的一端与驱动晶体管的栅极、写入晶体管的源极或者漏极中的一个电性连接，耦合电容的另一端与第二发光控制晶体管的源极或者漏极中的另一个电性连接；存储电容的一端与耦合电容的另一端电性连接，存储电容的另一端与正电源线电性连接。
在其中一些实施方式中，第二发光控制晶体管的栅极与第一发光控制线电性连接；在充电阶段中，写入晶体管的导通时间与第一发光控制晶体管和/或第二发光控制晶体管的导通时间至少部分重叠。
在其中一些实施方式中，第一控制线用于传输第一控制信号，第二控制线用于传输第二控制信号，第一控制信号、第二控制信号在一帧中均具有先后依次分布的第一脉冲、第二脉冲；第一控制信号的波形与第二控制信号的波形相同，且第二控制信号的相位滞后于第一控制信号的相位；在一帧中，第二控制信号的第一脉冲在时间上位于第一控制信号的第一脉冲与第一控制信号的第二脉冲之间，第一控制信号的第二脉冲在时间上位于第二控制信号的第一脉冲与第二控制信号的第二脉冲之间。
在其中一些实施方式中，数据线用于传输数据信号；第一脉冲的持续时间小于第二脉冲的持续时间；在第一脉冲的持续时间中，数据信号的电位小于数据信号的脉冲幅度。
在其中一些实施方式中，像素电路还包括存储电容和第一晶体管，存储电容的一端与驱动晶体管的栅极电性连接，存储电容的另一端与第二发光控制晶体管的源极或者漏极中的另一个电性连接；第一晶体管的源极或者漏极中的一个与驱动晶体管的源极或者漏极中的一个电性连接，第一晶体管的源极或者漏极中的另一个与驱动晶体管的栅极电性连接，第一晶体管的栅极与第三控制线电性连接；其中，写入晶体管的源极或者漏极中的一个与驱动晶体管的源极或者漏极中的另一个电性连接；第一初始化晶体管处于导通状态时，驱动晶体管处于导通状态，且写入晶体管、第一发光控制晶体管、第二发光控制晶体管以 及第一晶体管均处于截止状态。
在其中一些实施方式中，第一初始化晶体管处于截止状态时，第一晶体管、第一发光控制晶体管均处于导通状态，且写入晶体管、第二发光控制晶体管均处于截止状态。
在其中一些实施方式中，像素电路还包括发光器件和第二初始化晶体管，发光器件的阳极与第二发光控制晶体管的源极或者漏极中的另一个电性连接，发光器件的阴极与负电源线连接；第二初始化晶体管的源极或者漏极中的一个与发光器件的阳极连接，第二初始化晶体管的源极或者漏极中的另一个与第二初始化线电性连接，第二初始化晶体管的栅极与第四控制线或者第三控制线电性连接；其中，第二初始化晶体管在一帧的非发光阶段中多次处于导通状态。
第二方面，本申请提供一种显示面板，该显示面板包括上述至少一实施方式中的像素电路，其中，驱动晶体管的沟道类型与写入晶体管的沟道类型、第一发光控制晶体管的沟道类型、第二发光控制晶体管的沟道类型以及第一初始化晶体管的沟道类型均相同。
有益效果
本申请提供的像素电路及显示面板，通过在一帧的充电阶段前后分别初始化至少一次驱动晶体管的源极或者漏极的电位，可以在充电前后分别对驱动晶体管的源极或者漏极中一个的电位进行复位，进而通过驱动晶体管自身的联动作用可以复位驱动晶体管的源极或者漏极中另一个的电位，如此可以稳定驱动晶体管的源极或者漏极的电位，即使像素电路切换驱动频率也可以保持驱动晶体管的三端电压，改善了驱动晶体管的源极和/或漏极的电位发生周期性变化导致的闪烁现象。
附图说明
图1为相关技术中像素电路的第一种结构示意图。
图2为图1所示像素电路的时序示意图。
图3为相关技术中像素电路的第二种结构示意图。
图4为图3所示像素电路的时序示意图。
图5为本申请实施例提供的像素电路的第一种结构示意图。
图6为图5所示像素电路的一种工作状态示意图。
图7为图5所示像素电路的时序示意图。
图8为本申请实施例提供的像素电路的第二种结构示意图。
图9为图8所示像素电路的一种工作状态示意图。
图10为图8所示像素电路的时序示意图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
图1为相关技术中像素电路的第一种结构示意图，该像素电路的工作过程如图2所示，包括以下四个阶段：
第一阶段：复位信号Reset和扫描信号Scan(n)置高，晶体管T4、晶体管T3打开，初始化信号Vint、数据信号Data的低电位Vref分别写入到节点N2、节点N1，其中，由于耦合电容C1的存在，使得节点N1与节点N2之间存在固定的压差。
第二阶段：复位信号Reset置低，扫描信号Scan(n)的电位不变，发光控制信号EM置高，节点N1的电压不变，节点N2逐渐充电到Vref-Vth(节点N2会持续充电到截止状态，Vgs＝VN1-VN2＝Vth)，此时VD1＝Vref-Vth-VSS，需要VD1小于启亮电压。其中，VN1为节点N1的电位。VN2为节点N2的电位。VD1为发光器件D1的阳极电位。Vth为驱动晶体管T1的阈值电压。VSS为负电源线中传输的电源负信号的电位。
第三阶段：复位信号Reset置低，扫描信号Scan(n)的电位不变，发光控制信号EM置低，数据信号Data的电位由低电位Vref跳变至高电位，节点N1的电压随之从低电位Vref跳变到数据信号Data的高电位，由于耦合电容C1的作用，节点N2的电压也会被耦合拉高，满足ΔVN2×(C1+Cst+CD1)＝ΔVN1×C1。其中，C1为耦合电容C1的电容。Cst为存储电容Cst的电容。CD1为发光器件D1的等效电容。ΔVN1为节点N1的电位变化量。ΔVN2为节点N2的电位变化量。
第四阶段：复位信号Reset置低，扫描信号Scan(n)的电位置低，发光 控制信号EM置高，正电源线中传输的电源正信号VDD流向电源负信号VSS。晶体管T2打开后，节点N2给发光器件的电容充电到饱和即开始发光。
图1、图2所示像素电路在工作过程中从高频显示切换至低频显示时，扫描信号Scan(n)的频率也需要随之从120Hz或者60Hz等高频降低到10Hz或者1Hz等低频，然而进行这种频率切换后，数据信号Data不会被重新写入即驱动晶体管T1的栅极电位保持不变，而驱动晶体管T1的源极和/或漏极的电位会发生周期性变化，这样容易出现闪烁现象。
图3为相关技术中像素电路的第二种结构示意图，该像素电路的工作过程如图4所示，包括以下四个阶段：
第一阶段：发光控制信号EM2、扫描信号Nscan1均置高，晶体管T4、晶体管T6打开，能够将电源正信号VDD和初始化信号Vi_1分别写到存储电容Cst的两个极板，保证存储电容Cst的两端有一个固定的电位差。
第二阶段：扫描信号Nscan2置高，扫描信号Nscan1置低，此时数据信号Data会经过晶体管T2、驱动晶体管T1写入到节点A，但是由于扫描信号Nscan1置低，晶体管T3无法打开，也就是说数据信号Data无法写入到节点Q点。
第三阶段：扫描信号Nscan1、扫描信号Nscan2均置高，数据信号Data写入到节点Q。
第四阶段：发光控制信号EM1、发光控制信号EM2均置高，发光器件D1进行正常的发光。
图3、图4所示像素电路在工作过程中从高频显示切换至低频显示时，扫描信号Nscan1的频率也需要随之从120Hz或者60Hz等高频降低到10Hz或者1Hz等低频，然而进行这种频率切换后，数据信号Data不会被重新写入即驱动晶体管T1的栅极电位保持不变，而驱动晶体管T1的源极和/或漏极的电位会发生周期性变化，这样容易出现闪烁现象。
有鉴于上述提及的切换至低频驱动时驱动晶体管T1的源极和/或漏极的电位会发生周期性变化的技术问题，本实施例提供了一种像素电路，请参阅图5至图10，该像素电路包括驱动晶体管T1、写入晶体管T2、第一发光控制晶体管T4、第二发光控制晶体管T5以及第一初始化晶体管T7中的至少一个。写入晶体管T2的源极或者漏极中的一个与驱动晶体管T1电性连接，写入晶 体管T2的源极或者漏极中的另一个与数据线电性连接，写入晶体管T2的栅极与第一控制线连接。第一发光控制晶体管T4的源极或者漏极中的一个与驱动晶体管T1的源极或者漏极中的一个电性连接，第一发光控制晶体管T4的源极或者漏极中的另一个与正电源线电性连接，第一发光控制晶体管T4的栅极与第一发光控制线电性连接。第二发光控制晶体管T5的源极或者漏极中的一个与驱动晶体管T1的源极或者漏极中的另一个电性连接，第二发光控制晶体管T5的源极或者漏极中的另一个与负电源线电性连接，第二发光控制晶体管T5的栅极与第一发光控制线或者第二发光控制线电性连接。第一初始化晶体管T7的源极或者漏极中的一个与驱动晶体管T1的源极或者漏极电性连接，第一初始化晶体管T7的源极或者漏极中的另一个与第一初始化线电性连接，第一初始化晶体管T7的栅极与第二控制线电性连接，用于在一帧的充电阶段前后分别初始化至少一次驱动晶体管T1的源极或者漏极的电位。
可以理解的是，本实施例提供的像素电路，通过在一帧的充电阶段前后分别初始化至少一次驱动晶体管T1的源极或者漏极的电位，可以在充电前后分别对驱动晶体管T1的源极或者漏极中一个的电位进行复位，进而通过驱动晶体管T1自身的联动作用可以复位驱动晶体管T1的源极或者漏极中另一个的电位，如此可以稳定驱动晶体管T1的源极或者漏极的电位，即使像素电路切换驱动频率也可以保持驱动晶体管T1的三端电压，改善了驱动晶体管T1的源极和/或漏极的电位发生周期性变化导致的闪烁现象。
又，如图5、图6所示，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极通过共用同一第一发光控制线，可以减少像素电路所需的信号线数量，进而有利于提高显示面板的开口率。
在其中一个实施例中，如图5至图10所示，第一初始化晶体管T7处于导通状态时，驱动晶体管T1处于导通状态，且写入晶体管T2、第一发光控制晶体管T4以及第二发光控制晶体管T5均处于截止状态。
需要进行说明的时，写入晶体管T2、第一发光控制晶体管T4以及第二发光控制晶体管T5均处于截止状态可以在该阶段中阻止其他信号改变驱动晶体管T1的源极和/或漏极的电位，而第一初始化晶体管T7、驱动晶体管T1处于导通状态可以在充电前后分别对驱动晶体管T1的源极或者漏极中一个的电位 进行复位，进而通过驱动晶体管T1自身的联动作用可以复位驱动晶体管T1的源极或者漏极中另一个的电位，如此可以稳定驱动晶体管T1的源极或者漏极的电位。
在其中一个实施例中，如图5、图6所示，像素电路还包括耦合电容C1和存储电容Cst，耦合电容C1的一端与驱动晶体管T1的栅极、写入晶体管T2的源极或者漏极中的一个电性连接，耦合电容C1的另一端与第二发光控制晶体管T5的源极或者漏极中的另一个电性连接。存储电容Cst的一端与耦合电容C1的另一端电性连接，存储电容Cst的另一端与正电源线电性连接。
需要进行说明的是，写入晶体管T2的源极或者漏极中的一个与驱动晶体管T1的栅极直接电性连接，可以减少数据信号Data至驱动晶体管T1的栅极的传输路径，降低了数据信号Data的传输压降损耗。
在其中一个实施例中，如图5至图7所示，第二发光控制晶体管T5的栅极与第一发光控制线电性连接。在充电阶段中，写入晶体管T2的导通时间与第一发光控制晶体管T4和/或第二发光控制晶体管T5的导通时间至少部分重叠。
需要进行说明的是，在充电阶段即为数据信号Data的脉冲写入像素电路的时间段中，第一发光控制晶体管T4和/或第二发光控制晶体管T5的导通可以通过电源正信号VDD抓取驱动晶体管T1的阈值电压。
在其中一个实施例中，第一控制线用于传输第一控制信号，第二控制线用于传输第二控制信号，第一控制信号、第二控制信号在一帧中均具有先后依次分布的第一脉冲、第二脉冲。第一控制信号的波形与第二控制信号的波形相同，且第二控制信号的相位滞后于第一控制信号的相位。在一帧中，第二控制信号的第一脉冲在时间上位于第一控制信号的第一脉冲与第一控制信号的第二脉冲之间，第一控制信号的第二脉冲在时间上位于第二控制信号的第一脉冲与第二控制信号的第二脉冲之间。
需要进行说明的是，第一控制信号的第一脉冲用于利用数据信号Data的低电位对驱动晶体管T1的栅极电位进行复位，第一控制信号的第二脉冲用于写入数据信号Data的高电位至驱动晶体管T1的栅极电位即为像素电路充电。第二控制信号的第一脉冲用于在一帧中充电前对驱动晶体管T1的源极电位或 者漏极电位进行初始化，第二控制信号的第二脉冲用于在一帧中充电后对驱动晶体管T1的源极电位或者漏极电位进行初始化。
在其中一个实施例中，数据线用于传输数据信号Data。第一脉冲的持续时间小于第二脉冲的持续时间。在第一脉冲的持续时间中，数据信号Data的电位小于数据信号Data的脉冲幅度。
需要进行说明的是，第一控制信号的第一脉冲、第二控制信号的第一脉冲均是为了实现对应节点电位的复位，而第一控制信号的第二脉冲的持续时间决定了充电时间，因此，第二脉冲的持续时间需要合适配置以满足充电时间的要求。而第一脉冲的持续时间多少对复位效果的影响几乎没有，因此，可以为第一脉冲配置较短的时间，以降低功耗。
在其中一个实施例中，如图8至图10所示，像素电路还包括存储电容Cst和第一晶体管T3。存储电容Cst的一端与驱动晶体管T1的栅极电性连接，存储电容Cst的另一端与第二发光控制晶体管T5的源极或者漏极中的另一个电性连接。第一晶体管T3的源极或者漏极中的一个与驱动晶体管T1的源极或者漏极中的一个电性连接，第一晶体管T3的源极或者漏极中的另一个与驱动晶体管T1的栅极电性连接，第一晶体管T3的栅极与第三控制线电性连接。其中，写入晶体管T2的源极或者漏极中的一个与驱动晶体管T1的源极或者漏极中的另一个电性连接。第一初始化晶体管T7处于导通状态时，驱动晶体管T1处于导通状态，且写入晶体管T2、第一发光控制晶体管T4、第二发光控制晶体管T5以及第一晶体管T3均处于截止状态。
需要进行说明的是，第一晶体管T3可以对发光器件D1的阳极电位进行复位，以精确控制每帧中发光强度的精度。写入晶体管T2、第一发光控制晶体管T4、第二发光控制晶体管T5以及第一晶体管T3均处于截止状态可以在该阶段中阻止其他信号改变驱动晶体管T1的源极和/或漏极的电位，而第一初始化晶体管T7、驱动晶体管T1处于导通状态可以在充电前后分别对驱动晶体管T1的源极或者漏极中一个的电位进行复位，进而通过驱动晶体管T1自身的联动作用可以复位驱动晶体管T1的源极或者漏极中另一个的电位，如此可以稳定驱动晶体管T1的源极或者漏极的电位。
在其中一个实施例中，第一初始化晶体管T7处于截止状态时，第一晶体 管T3、第一发光控制晶体管T4均处于导通状态，且写入晶体管T2、第二发光控制晶体管T5均处于截止状态。
需要进行说明的是，在本实施例中，第一晶体管T3不仅可以用于传输数据信号Data至驱动晶体管T1的栅极以实现像素电路的充电，还可以用于传输电源正信号VDD至驱动晶体管T1的栅极以复位驱动晶体管T1的栅极电位。
在其中一个实施例中，如图5至图10所示，像素电路还包括发光器件D1和第二初始化晶体管T6。发光器件D1的阳极与第二发光控制晶体管T5的源极或者漏极中的另一个电性连接，发光器件D1的阴极与负电源线连接。第二初始化晶体管T6的源极或者漏极中的一个与发光器件D1的阳极连接，第二初始化晶体管T6的源极或者漏极中的另一个与第二初始化线电性连接，第二初始化晶体管T6的栅极与第四控制线或者第三控制线电性连接。其中，第二初始化晶体管T6在一帧的非发光阶段中多次处于导通状态。
需要进行说明的是，第二初始化晶体管T6的栅极与第三控制线电性连接时，可以与第一晶体管T3的栅极共用同一第三控制线，可以减少像素电路所需的信号线数量，进而有利于提高显示面板的开口率。第二初始化晶体管T6在一帧的非发光阶段中的每次导通均可以复位驱动晶体管T1的源极电位和/或漏极电位。
其中，发光器件D1可以为有机发光二极管、迷你发光二极管、微发光二极管或者量子点发光二极管。
在其中一个实施例中，驱动晶体管T1的沟道类型、写入晶体管T2的沟道类型、第一发光控制晶体管T4的沟道类型、第二发光控制晶体管T5的沟道类型、第一初始化晶体管T7的沟道类型、第一晶体管T3的沟道类型以及第一初始化晶体管T7的沟道类型中的至少一个可以为N沟道型或者P沟道型，具体还可以为N沟道型金属氧化物薄膜晶体管或者P沟道型低温多晶硅薄膜晶体管。
其中，正电源线用于传输电源正信号VDD，负电源线用于传输电源负信号VSS，电源正信号VDD的电位高于电源负信号VSS的电位。数据线用于传输数据信号Data。第一发光控制线用于传输第一发光控制信号，第一发光控制信号可以为发光控制信号EM或者发光控制信号EM2。第二发光控制线用 于传输第二发光控制信号，第二发光控制信号可以为发光控制信号EM1。第一控制线用于传输第一控制信号，第一控制信号可以为扫描信号Scan(n)或者扫描信号Nscan2。第二控制线用于传输第二控制信号，第二控制信号可以为扫描信号Scan(n+1)或者扫描信号Nscan1(n+1)。第三控制线用于传输第三控制信号，第三控制信号可以为扫描信号Nscan1(n)。第四控制线用于传输第四控制信号，第四控制信号可以为扫描信号Scan(n-2)。第一初始化线用于传输第一初始化信号，第一初始化信号可以为电压信号Vi_2。第二初始化线用于传输第二初始化信号，第二初始化信号可以为电压信号Vi_1。
其中，图7为图5所示像素电路的时序示意图，图5所示像素电路在一帧中的工作过程包括以下阶段：
第一阶段S1：扫描信号Scan(n-2)、扫描信号Scan(n)处于高电位时，写入晶体管T2、第二初始化晶体管T6打开，数据信号Data的低电位、第二初始化信号依次分别对节点Q、节点C进行复位。
第二阶段S2：扫描信号Scan(n+1)处于高电位，第一初始化晶体管T7打开，此时，驱动晶体管T1也处于打开状态，第一初始化信号对节点A或者节点B中的一个进行复位，然后通过驱动晶体管T1的自身打开状态，可以联动节点A或者节点B中的另一个进行复位。
第三阶段S3：扫描信号Scan(n)处于高电位，写入晶体管T2打开，数据信号Data的高电位充电至驱动晶体管T1的栅极；在此阶段中，发光控制信号EM在至少部分时间中处于高电位，此时第一发光控制晶体管T4、第二发光控制晶体管T5均打开，可以通过电源正信号VDD来抓取驱动晶体管T1的阈值电压。
第四阶段S4：扫描信号Scan(n+1)处于高电位，第一初始化晶体管T7打开，此时，驱动晶体管T1也处于打开状态，第一初始化信号对节点A或者节点B中的一个进行复位，然后通过驱动晶体管T1的自身打开状态，可以联动节点A或者节点B中的另一个进行复位。
第五阶段S5：发光控制信号EM处于高电位，第一发光控制晶体管T4、第二发光控制晶体管T5均打开，发光器件D1开始进行发光。
其中，第二发光控制晶体管T5、第一初始化晶体管T7以及第二初始化晶 体管T6的沟道长宽比W/L均相同，可以保证三者的导通程度的一致性。而设置三者的沟道长宽比W/L的范围均为0.5～1，能够保证三者的导通的充分性。其中，W为沟道宽度，L为沟道长度。
需要进行说明的是，相较于图1所示的像素电路，图5、图6所述的像素电路中第二初始化晶体管T6的栅极控制信号变为了扫描信号Scan(n-2)，而扫描信号Scan(n-2)、扫描信号Scan(n+1)以及扫描信号Scan(n)均具有先后出现的第一脉冲、第二脉冲。其中，第一脉冲的脉冲宽度可以为1/2H，第二脉冲的脉冲宽度可以为1H，同一扫描信号的第一脉冲与第二脉冲之间的间隔为1H。时序上，扫描信号Scan(n)的高电平时间全部位于发光控制信号EM的低电平时间段内，只有发光控制信号EM的第一个脉冲(pulse)例外，发光控制信号EM的第一个脉冲的脉冲宽度可以为1/2H，与扫描信号Scan(n)的第二脉冲的上升沿一致，且在扫描信号Scan(n+1)的第二脉冲的下降沿时刻，发光控制信号EM的电位由低电位跳变为高电位。其中，H＝1/(显示频率*像素行数)。
可以理解的是，如此可以保证像素电路的工作时序的可靠性而不会出现时序混乱。
其中，图10为图8所示像素电路的时序示意图，图8所示像素电路在一帧中的工作过程包括以下阶段：
第一阶段S1：扫描信号Nscan1(n)、发光控制信号EM2处于高电位，第一发光控制晶体管T4、第一晶体管T3以及第二初始化晶体管T6打开，电源正信号VDD对节点A、节点Q进行复位，第二初始化信号对节点C进行复位。
第二阶段S2：扫描信号Nscan(n+1)处于高电位，第一初始化晶体管T7打开，此时，驱动晶体管T1也处于打开状态，第一初始化信号对节点A或者节点B中的一个进行复位，然后通过驱动晶体管T1的自身打开状态，可以联动节点A或者节点B中的另一个进行复位。
第三阶段S3：扫描信号Nscan(n)的第二脉冲、扫描信号Nscan2的第二脉冲处于高电位，第一晶体管T3、写入晶体管T2打开，数据信号Data的高电位充电至驱动晶体管T1的栅极。
第四阶段S4：扫描信号Nscan(n+1)处于高电位，第一初始化晶体管T7打开，此时，驱动晶体管T1也处于打开状态，第一初始化信号对节点A或者 节点B中的一个进行复位，然后通过驱动晶体管T1的自身打开状态，可以联动节点A或者节点B中的另一个进行复位。
第五阶段S5：发光控制信号EM1、发光控制信号EM2均处于高电位，第一发光控制晶体管T4、第二发光控制晶体管T5均打开，发光器件D1开始进行发光。
其中，第一初始化晶体管T7、第二初始化晶体管T6的沟道长宽比W/L相同，可以保证两者导通程度的一致性。而设置两者的沟道长宽比W/L的范围均为0.5～1，能够保证两者导通的充分性。其中，W为沟道宽度，L为沟道长度。
需要进行说明的是，扫描信号Nscan1(n+1)在发光控制信号EM1、发光控制信号EM2处于低电位状态下具有先后依次出现的第一脉冲、第二脉冲，与扫描信号Nscan1(n)相比，扫描信号Nscan1(n+1)的第一脉冲滞后于扫描信号Nscan1(n)的第一脉冲1H。扫描信号Nscan2在一帧中的脉冲位于扫描信号Nscan1(n+1)的第一脉冲与扫描信号Nscan1(n+1)的第二脉冲之间，如此可以确保实现充电前后对节点A和/或节点B分别进行一次复位。
在其中一个实施例中，本实施例提供一种显示面板，该显示面板包括上述至少一实施例中的像素电路。
可以理解的是，本实施例提供的显示面板，通过在一帧的充电阶段前后分别初始化至少一次驱动晶体管T1的源极或者漏极的电位，可以在充电前后分别对驱动晶体管T1的源极或者漏极中一个的电位进行复位，进而通过驱动晶体管T1自身的联动作用可以复位驱动晶体管T1的源极或者漏极中另一个的电位，如此可以稳定驱动晶体管T1的源极或者漏极的电位，即使像素电路切换驱动频率也可以保持驱动晶体管T1的三端电压，改善了驱动晶体管T1的源极和/或漏极的电位发生周期性变化导致的闪烁现象。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，其中，包括：
    驱动晶体管；
    写入晶体管，所述写入晶体管的源极或者漏极中的一个与所述驱动晶体管电性连接，所述写入晶体管的源极或者漏极中的另一个与数据线电性连接，所述写入晶体管的栅极与第一控制线连接；
    第一发光控制晶体管，所述第一发光控制晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极中的一个电性连接，所述第一发光控制晶体管的源极或者漏极中的另一个与正电源线电性连接，所述第一发光控制晶体管的栅极与第一发光控制线电性连接；
    第二发光控制晶体管，所述第二发光控制晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极中的另一个电性连接，所述第二发光控制晶体管的源极或者漏极中的另一个与负电源线电性连接，所述第二发光控制晶体管的栅极与所述第一发光控制线或者第二发光控制线电性连接；以及
    第一初始化晶体管，所述第一初始化晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极电性连接，所述第一初始化晶体管的源极或者漏极中的另一个与第一初始化线电性连接，所述第一初始化晶体管的栅极与第二控制线电性连接，用于在一帧的充电阶段前后分别初始化至少一次所述驱动晶体管的源极或者漏极的电位。
  2. 根据权利要求1所述的像素电路，其中，所述第一初始化晶体管处于导通状态时，所述驱动晶体管处于导通状态，且所述写入晶体管、所述第一发光控制晶体管以及所述第二发光控制晶体管均处于截止状态。
  3. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    耦合电容，所述耦合电容的一端与所述驱动晶体管的栅极、所述写入晶体管的源极或者漏极中的一个电性连接，所述耦合电容的另一端与所述第二发光控制晶体管的源极或者漏极中的另一个电性连接；和
    存储电容，所述存储电容的一端与所述耦合电容的另一端电性连接，所述存储电容的另一端与所述正电源线电性连接。
  4. 根据权利要求3所述的像素电路，其中，所述第二发光控制晶体管的 栅极与所述第一发光控制线电性连接；
    在所述充电阶段中，所述写入晶体管的导通时间与所述第一发光控制晶体管和/或所述第二发光控制晶体管的导通时间至少部分重叠。
  5. 根据权利要求4所述的像素电路，其中，所述第一控制线用于传输第一控制信号，所述第二控制线用于传输第二控制信号，所述第一控制信号、所述第二控制信号在一帧中均具有先后依次分布的第一脉冲、第二脉冲；
    所述第一控制信号的波形与所述第二控制信号的波形相同，且所述第二控制信号的相位滞后于所述第一控制信号的相位；
    在一帧中，所述第二控制信号的第一脉冲在时间上位于所述第一控制信号的第一脉冲与所述第一控制信号的第二脉冲之间，所述第一控制信号的第二脉冲在时间上位于所述第二控制信号的第一脉冲与所述第二控制信号的第二脉冲之间。
  6. 根据权利要求5所述的像素电路，其中，所述数据线用于传输数据信号；所述第一脉冲的持续时间小于所述第二脉冲的持续时间；
    在所述第一脉冲的持续时间中，所述数据信号的电位小于所述数据信号的脉冲幅度。
  7. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    存储电容，所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端与所述第二发光控制晶体管的源极或者漏极中的另一个电性连接；和
    第一晶体管，所述第一晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极中的一个电性连接，所述第一晶体管的源极或者漏极中的另一个与所述驱动晶体管的栅极电性连接，所述第一晶体管的栅极与第三控制线电性连接；
    其中，所述写入晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极中的另一个电性连接；所述第一初始化晶体管处于导通状态时，所述驱动晶体管处于导通状态，且所述写入晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管以及所述第一晶体管均处于截止状态。
  8. 根据权利要求7所述的像素电路，其中，所述第一初始化晶体管处于 截止状态时，所述第一晶体管、所述第一发光控制晶体管均处于导通状态，且所述写入晶体管、所述第二发光控制晶体管均处于截止状态。
  9. 根据权利要求3所述的像素电路，其中，所述像素电路还包括：
    发光器件，所述发光器件的阳极与所述第二发光控制晶体管的源极或者漏极中的另一个电性连接，所述发光器件的阴极与所述负电源线连接；和
    第二初始化晶体管，所述第二初始化晶体管的源极或者漏极中的一个与所述发光器件的阳极连接，所述第二初始化晶体管的源极或者漏极中的另一个与第二初始化线电性连接，所述第二初始化晶体管的栅极与第四控制线或者所述第三控制线电性连接；
    其中，所述第二初始化晶体管在一帧的非发光阶段中多次处于导通状态。
  10. 一种显示面板，其中，包括如权利要求1所述的像素电路，其中，所述驱动晶体管的沟道类型与所述写入晶体管的沟道类型、所述第一发光控制晶体管的沟道类型、所述第二发光控制晶体管的沟道类型以及所述第一初始化晶体管的沟道类型均相同。
  11. 根据权利要求10所述的显示面板，其中，所述第一初始化晶体管处于导通状态时，所述驱动晶体管处于导通状态，且所述写入晶体管、所述第一发光控制晶体管以及所述第二发光控制晶体管均处于截止状态。
  12. 根据权利要求10所述的显示面板，其中，所述像素电路还包括：
    耦合电容，所述耦合电容的一端与所述驱动晶体管的栅极、所述写入晶体管的源极或者漏极中的一个电性连接，所述耦合电容的另一端与所述第二发光控制晶体管的源极或者漏极中的另一个电性连接；和
    存储电容，所述存储电容的一端与所述耦合电容的另一端电性连接，所述存储电容的另一端与所述正电源线电性连接。
  13. 根据权利要求12所述的显示面板，其中，所述第二发光控制晶体管的栅极与所述第一发光控制线电性连接；
    在所述充电阶段中，所述写入晶体管的导通时间与所述第一发光控制晶体管和/或所述第二发光控制晶体管的导通时间至少部分重叠。
  14. 根据权利要求13所述的显示面板，其中，所述第一控制线用于传输第一控制信号，所述第二控制线用于传输第二控制信号，所述第一控制信号、 所述第二控制信号在一帧中均具有先后依次分布的第一脉冲、第二脉冲；
    所述第一控制信号的波形与所述第二控制信号的波形相同，且所述第二控制信号的相位滞后于所述第一控制信号的相位；
    在一帧中，所述第二控制信号的第一脉冲在时间上位于所述第一控制信号的第一脉冲与所述第一控制信号的第二脉冲之间，所述第一控制信号的第二脉冲在时间上位于所述第二控制信号的第一脉冲与所述第二控制信号的第二脉冲之间。
  15. 根据权利要求14所述的显示面板，其中，所述数据线用于传输数据信号；所述第一脉冲的持续时间小于所述第二脉冲的持续时间；
    在所述第一脉冲的持续时间中，所述数据信号的电位小于所述数据信号的脉冲幅度。
  16. 根据权利要求10所述的显示面板，其中，所述像素电路还包括：
    存储电容，所述存储电容的一端与所述驱动晶体管的栅极电性连接，所述存储电容的另一端与所述第二发光控制晶体管的源极或者漏极中的另一个电性连接；和
    第一晶体管，所述第一晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极中的一个电性连接，所述第一晶体管的源极或者漏极中的另一个与所述驱动晶体管的栅极电性连接，所述第一晶体管的栅极与第三控制线电性连接；
    其中，所述写入晶体管的源极或者漏极中的一个与所述驱动晶体管的源极或者漏极中的另一个电性连接；所述第一初始化晶体管处于导通状态时，所述驱动晶体管处于导通状态，且所述写入晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管以及所述第一晶体管均处于截止状态。
  17. 根据权利要求16所述的显示面板，其中，所述第一初始化晶体管处于截止状态时，所述第一晶体管、所述第一发光控制晶体管均处于导通状态，且所述写入晶体管、所述第二发光控制晶体管均处于截止状态。
  18. 根据权利要求12所述的显示面板，其中，所述像素电路还包括：
    发光器件，所述发光器件的阳极与所述第二发光控制晶体管的源极或者漏极中的另一个电性连接，所述发光器件的阴极与所述负电源线连接；和
    第二初始化晶体管，所述第二初始化晶体管的源极或者漏极中的一个与所述发光器件的阳极连接，所述第二初始化晶体管的源极或者漏极中的另一个与第二初始化线电性连接，所述第二初始化晶体管的栅极与第四控制线或者所述第三控制线电性连接；
    其中，所述第二初始化晶体管在一帧的非发光阶段中多次处于导通状态。
  19. 根据权利要求10所述的显示面板，其中，所述驱动晶体管、所述写入晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、以及所述第一初始化晶体管中的至少一个为N沟道型金属氧化物薄膜晶体管。
  20. 根据权利要求18所述的显示面板，其中，所述第二发光控制晶体管、所述第一初始化晶体管以及所述第二初始化晶体管的沟道长宽比的范围均为0.5～1。
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