WO2020079971A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020079971A1
WO2020079971A1 PCT/JP2019/034331 JP2019034331W WO2020079971A1 WO 2020079971 A1 WO2020079971 A1 WO 2020079971A1 JP 2019034331 W JP2019034331 W JP 2019034331W WO 2020079971 A1 WO2020079971 A1 WO 2020079971A1
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WIPO (PCT)
Prior art keywords
heat sink
terminal
layer
semiconductor chip
semiconductor device
Prior art date
Application number
PCT/JP2019/034331
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English (en)
French (fr)
Inventor
瞭一 海津
匠 野村
哲人 山岸
祐樹 稲葉
善次 坂本
Original Assignee
株式会社デンソー
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Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to DE112019005155.5T priority Critical patent/DE112019005155B4/de
Priority to CN201980063390.8A priority patent/CN112753101B/zh
Publication of WO2020079971A1 publication Critical patent/WO2020079971A1/ja
Priority to US17/228,033 priority patent/US11710709B2/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/26Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264Bi as the principal constituent
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
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    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/30Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
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Definitions

  • the present disclosure relates to semiconductor devices.
  • Patent Document 1 proposes a semiconductor device having a double-sided heat dissipation structure.
  • This semiconductor device includes a semiconductor chip, a pair of heat sinks (lead frames), and terminals (heat sink blocks).
  • the semiconductor chip is formed by forming elements such as IGBT and MOSFET on a silicon substrate, and has main electrodes on one surface and the back surface, respectively.
  • the pair of heat sinks has a first heat sink arranged on one surface side and a second heat sink arranged on the back surface side.
  • the terminal is interposed between the second heat sink and the semiconductor chip and electrically relays.
  • the semiconductor chip and the first heat sink, the semiconductor chip and the terminal, and the terminal and the second heat sink are connected to each other via a joining member.
  • SiC has been attracting attention because it has characteristics such as a larger dielectric breakdown electric field and bandgap than Si, a high thermal conductivity, and a high electron saturation speed.
  • Young's modulus of SiC is about three times as large as that of Si. For this reason, in the above-mentioned double-sided heat dissipation structure in which the semiconductor chip is sandwiched by the heat sinks from above and below, if SiC is used for the semiconductor chip, a crack may occur in the bonding member or the semiconductor chip.
  • An object of the present disclosure is to provide a suitable semiconductor device even when SiC is used for a semiconductor chip.
  • an element is formed on a SiC substrate, and a semiconductor chip in which a main electrode is formed on each of one surface and a back surface opposite to the one surface in the plate thickness direction, and a semiconductor chip in the plate thickness direction.
  • a pair of heat sinks arranged so as to sandwich the semiconductor chip, the first heat sink arranged on one surface side, the second heat sink arranged on the back surface side, and the second heat sink and the semiconductor chip interposed therebetween.
  • a terminal that electrically relays the main electrode on the back surface side and the second heat sink, between the main electrode on the one surface side and the first heat sink, between the main electrode on the back surface side and the terminal, and the terminal and the second heat sink.
  • the terminal is formed by laminating a plurality of types of metal layers in the plate thickness direction, and the coefficient of linear expansion in at least the direction orthogonal to the plate thickness direction is larger than that of the semiconductor chip and smaller than that of the second heat sink as a whole of the terminal.
  • the plurality of types of metal layers are symmetrically arranged in the plate thickness direction.
  • a plurality of types of metal layers are stacked to form a terminal, and the linear expansion coefficient at least in the direction orthogonal to the plate thickness direction is the same as that of the semiconductor chip and the second heat sink. It is a value between. Therefore, it is possible to reduce the thermal stress that acts on each joining member and the semiconductor chip. Furthermore, the metal layers are symmetrically arranged in the Z direction. As a result, the warp of the terminal can be suppressed, and the local stress can be suppressed from acting on each bonding member and the semiconductor chip. Therefore, the present disclosure is suitable for a configuration using SiC for a semiconductor chip in a semiconductor device having a double-sided heat dissipation structure.
  • a semiconductor device includes a semiconductor chip in which an element is formed on a SiC substrate, and a main electrode is formed on each of one surface and a back surface opposite to the one surface in the plate thickness direction, and a plate thickness.
  • a pair of heat sinks arranged so as to sandwich the semiconductor chip in the direction, the first heat sink arranged on one surface side, the second heat sink arranged on the back surface side, and the second heat sink and the semiconductor chip.
  • a terminal that electrically relays between the main electrode on the back surface side and the second heat sink, between the main electrode on the one surface side and the first heat sink, between the main electrode on the back surface side, the terminal and the second heat sink.
  • a joining member disposed on each of the heat sink and the heat sink.
  • the terminal is a clad material of three or more layers in which a Cu layer and an alloy layer containing Cu and Cr are sequentially stacked in the plate thickness direction, and the Cu layer and the alloy layer are symmetrically arranged in the plate thickness direction. .
  • a clad material including a Cu layer and an alloy layer containing Cu and Cr is used as a terminal in a semiconductor device.
  • this alloy layer expansion of the Cu layer in the direction orthogonal to the plate thickness direction is restricted, and the linear expansion coefficient in the orthogonal direction can be reduced for the entire terminal. Therefore, it is possible to reduce the thermal stress that acts on each joining member and the semiconductor chip.
  • the Cu layer and the alloy layer are symmetrically arranged in the plate thickness direction. As a result, the warp of the terminal can be suppressed, and the local stress can be suppressed from acting on each bonding member and the semiconductor chip. Therefore, the present disclosure is suitable for a configuration using SiC for a semiconductor chip in a semiconductor device having a double-sided heat dissipation structure.
  • FIG. 1 is a diagram showing a configuration of a power conversion device to which the semiconductor device of the first embodiment is applied.
  • FIG. 2 is a perspective view showing a semiconductor device.
  • FIG. 3 is a sectional view taken along the line III-III in FIG.
  • FIG. 4 is a perspective view showing a lead frame including the first heat sink.
  • FIG. 5 is a perspective view showing a state in which semiconductor chips are arranged.
  • FIG. 6 is a perspective view showing a state in which the terminals are arranged.
  • FIG. 7 is a perspective view showing the second heat sink.
  • FIG. 8 is a perspective view showing a state in which the second heat sink is arranged.
  • FIG. 9 is a sectional view showing the detailed structure of the terminal.
  • FIG. 10 is a cross-sectional view showing a first modification and corresponds to FIG. 9.
  • FIG. 11 is a cross-sectional view showing a second modified example and corresponds to FIG. 9.
  • FIG. 12 is a cross-sectional view showing a third modified example and corresponds to FIG. 9.
  • FIG. 13 is a cross-sectional view showing the periphery of the terminal in the semiconductor device of the second embodiment.
  • FIG. 14 is a cross-sectional view showing the semiconductor device of the third embodiment and corresponds to the line XIV-XIV in FIG.
  • FIG. 15 is a sectional view showing a fourth modified example.
  • FIG. 16 is a diagram showing a simulation result of solder distortion in the Pb-free solder applied to the semiconductor device of the fourth embodiment.
  • the plate thickness direction of the semiconductor chips is defined as the Z direction
  • the direction perpendicular to the Z direction and the direction in which the semiconductor chips are arranged is referred to as the X direction.
  • the direction orthogonal to both the Z direction and the X direction is referred to as the Y direction.
  • the shape when viewed in the XY plane is the planar shape. It can be said that the XY plane view is a projection view in the Z direction.
  • H at the end of the reference sign indicates that the element is on the upper arm side of the upper and lower arms
  • L at the end indicates that it is the element on the lower arm side.
  • H and L are added at the end in order to clarify the upper arm and the lower arm, and the other part has the same reference numeral for the upper arm and the lower arm.
  • the power conversion device 1 shown in FIG. 1 is mounted in, for example, an electric vehicle or a hybrid vehicle.
  • the power conversion device 1 is configured to convert a DC voltage supplied from a DC power supply 2 mounted on a vehicle into a three-phase AC and output the three-phase AC motor 3 to the three-phase AC motor 3.
  • the motor 3 functions as a traveling drive source of the vehicle.
  • the power conversion device 1 can also convert the electric power generated by the motor 3 into a direct current and charge the direct current power supply 2 or the like. In this way, the power conversion device 1 is capable of bidirectional power conversion.
  • the power conversion device 1 includes a smoothing capacitor 4 and an inverter 5 that is a power converter.
  • the positive electrode side terminal of the smoothing capacitor 4 is connected to the positive electrode which is the high potential side electrode of the DC power supply 2, and the negative electrode side terminal is connected to the negative potential which is the low potential side electrode of the DC power supply 2.
  • the inverter 5 converts the input DC power into a three-phase AC having a predetermined frequency and outputs it to the motor 3.
  • the inverter 5 converts the AC power generated by the motor 3 into DC power.
  • the inverter 5 has six arms.
  • the upper and lower arms of each phase are formed by connecting two arms in series between the positive electrode side terminal and the negative electrode side terminal of the smoothing capacitor 4.
  • the upper and lower arms of each phase are configured by the semiconductor device 10 described later.
  • the inverter 5 is composed of three semiconductor devices 10.
  • each arm has a MOSFET 6.
  • the MOSFET 6 an n-channel type is adopted.
  • the MOSFET 6 has a drain electrode and a source electrode as a main electrode through which a main current flows.
  • the drain electrode of the MOSFET 6 on the upper arm side is connected to the positive terminal of the smoothing capacitor 4.
  • the source electrode of the MOSFET 6 on the lower arm side is connected to the negative terminal of the smoothing capacitor 4.
  • the source electrode of the MOSFET 6 on the upper arm side and the drain electrode of the MOSFET 6 on the lower arm side are connected to each other.
  • the power conversion device 1 includes a boost converter that boosts a DC voltage supplied from the DC power supply 2, a drive circuit of an element forming the inverter 5 or the boost converter, and a drive circuit.
  • a control circuit or the like for outputting a drive command may be provided.
  • the semiconductor device 10 includes a semiconductor chip 12, a sealing resin body 14, a first heat sink 16, a terminal 20, a second heat sink 24, a joint portion 28, a power supply terminal 32, an output terminal 34, and And a signal terminal 36.
  • FIG. 4 only the lead frame 40 including the first heat sink 16 in the semiconductor device 10 is shown.
  • FIG. 5 shows a state in which the semiconductor chip 12 is connected to FIG.
  • FIG. 6 shows a state in which the terminal 20 is connected to FIG.
  • FIG. 8 shows a state in which the second heat sink 24 is connected to FIG.
  • the semiconductor chip 12 has an element formed on a SiC substrate.
  • the semiconductor chip 12 on which the upper arm side element is formed is also referred to as a semiconductor chip 12H
  • the semiconductor chip 12 on which the lower arm side element is formed is also referred to as a semiconductor chip 12L.
  • the two semiconductor chips 12H and 12L are arranged so that the plate thickness direction is the same direction (Z direction).
  • the elements formed on the semiconductor chip 12 have a vertical structure so that a current flows in the Z direction.
  • an n-channel MOSFET is formed as an element as described above.
  • the drain electrode 12d is formed on one surface of the semiconductor chip 12, and the source electrode 12s is formed on the back surface opposite to the one surface.
  • the drain electrode 12d corresponds to the main electrode on the one surface side
  • the source electrode 12s corresponds to the main electrode on the back surface side.
  • the semiconductor chips 12H and 12L have substantially the same planar shape as each other, more specifically, a substantially rectangular planar shape, and have substantially the same size and thickness as each other.
  • the thickness of the semiconductor chip 12 is, for example, about 100 ⁇ m.
  • the semiconductor chips 12H and 12L have the same configuration as each other.
  • the semiconductor chips 12H and 12L are arranged so that the drain electrode 12d is on the same side in the Z direction and the source electrode 12s is on the same side in the Z direction.
  • the semiconductor chips 12H and 12L are located at substantially the same height in the Z direction and are arranged side by side in the X direction.
  • a pad 12p which is a signal electrode is formed on the back surface of the semiconductor chip 12, that is, the source electrode formation surface.
  • the pad 12p is formed on the back surface at a position different from that of the source electrode 12s.
  • the pad 12p is formed at the end portion on the side opposite to the formation region of the source electrode 12s in the Y direction.
  • the semiconductor chip 12 has five pads 12p. Specifically, as the five pads 12p, one for the gate electrode, one for detecting the potential of the source electrode 12s, one for current sensing, one for the anode potential of the temperature sensor (temperature sensitive diode) for detecting the temperature of the semiconductor chip 12, and one for the cathode potential are also used.
  • the five pads 12p are collectively formed on one end side in the Y direction of the semiconductor chip 12 having a substantially rectangular plane shape, and are formed side by side in the X direction.
  • the sealing resin body 14 seals the semiconductor chip 12.
  • the sealing resin body 14 is made of, for example, an epoxy resin.
  • the sealing resin body 14 is molded by, for example, a transfer molding method. As shown in FIGS. 2 and 3, the sealing resin body 14 has one surface 14a and a back surface 14b opposite to the one surface 14a in the Z direction.
  • One surface 14a is a surface on the side of the drain electrode 12d
  • the back surface 14b is a surface on the side of the source electrode 12s.
  • the one surface 14a and the back surface 14b are flat surfaces, for example.
  • the sealing resin body 14 has a substantially rectangular shape in a plane.
  • the first heat sink 16 is arranged on one surface side of the semiconductor chip 12, that is, on the drain electrode 12d side.
  • the first heat sink 16 has a function of radiating the heat of the corresponding semiconductor chip 12 to the outside of the semiconductor device 10 and a function of a wiring of the main electrode. Therefore, in order to secure thermal conductivity and electric conductivity, the metal material such as Cu or Al is used.
  • the first heat sink 16 is made of Cu and has a thickness of about 2 mm. Further, the first heat sink 16 has a first heat sink 16H corresponding to the semiconductor chip 12H and a first heat sink 16L corresponding to the semiconductor chip 12L, as shown in FIGS.
  • the first heat sink 16 is provided so as to include the corresponding semiconductor chip 12 in the projection view from the Z direction.
  • the first heat sink 16 is connected to the corresponding drain electrode 12d of the semiconductor chip 12 via the solder 18.
  • Most of each of the first heat sinks 16 is covered with the sealing resin body 14.
  • the solder 18 is connected to the mounting surface 16 a of the surface of the first heat sink 16.
  • the heat dissipation surface 16b opposite to the mounting surface 16a is exposed from the sealing resin body 14.
  • the heat dissipation surface 16b is substantially flush with the one surface 14a.
  • the drain electrode 12d of the semiconductor chip 12H is connected to the mounting surface 16a of the first heat sink 16H via the solder 18. Further, the drain electrode 12d of the semiconductor chip 12L is connected to the mounting surface 16a of the first heat sink 16L via the solder 18.
  • the first heat sinks 16H and 16L are arranged side by side in the X direction and at substantially the same position in the Z direction.
  • the heat radiation surfaces 16b of the first heat sinks 16H and 16L are exposed from the one surface 14a of the sealing resin body 14 and are arranged in the X direction.
  • the terminal 20 is interposed between the semiconductor chip 12 and the second heat sink 24, and electrically relays the semiconductor chip 12 and the second heat sink 24. Since the terminal 20 is located in the middle of the heat conduction and electric conduction paths between the semiconductor chip 12 and the second heat sink 24, it is formed of at least a metal material in order to secure the thermal conductivity and the electric conductivity.
  • the terminal 20 is arranged to face the source electrode 12s and is connected to the source electrode 12s via the solder 22.
  • the terminal 20 is provided for each semiconductor chip 12. That is, the semiconductor device 10 includes two terminals 20. One of the terminals 20 is interposed between the semiconductor chip 12H and the second heat sink 24H, and another one of the terminals 20 is interposed between the semiconductor chip 12L and the second heat sink 24L. Details of the terminal 20 will be described later.
  • the second heat sink 24 also has the function of radiating the heat of the corresponding semiconductor chip 12 to the outside of the semiconductor device 10 and the function of the wiring of the main electrode.
  • the second heat sink 24 is arranged on the source electrode 12s side of the semiconductor chip 12.
  • the second heat sink 24 is arranged so as to sandwich the semiconductor chip 12 with the first heat sink 16.
  • the first heat sink 16 and the second heat sink 24 correspond to a pair of heat sinks.
  • the first heat sink 16 and the second heat sink 24 are also referred to as heat sinks 16 and 24.
  • the second heat sink 24 is also formed by using a metal material such as Cu or Al.
  • the second heat sink 24 is made of Cu and has a thickness of about 2 mm.
  • the second heat sink 24 has a second heat sink 24H corresponding to the semiconductor chip 12H and a second heat sink 24L corresponding to the semiconductor chip 12L, as shown in FIGS. 3, 7, and 8.
  • the second heat sink 24 is provided so as to include the corresponding semiconductor chip 12 in the projection view from the Z direction.
  • the second heat sink 24 is electrically connected to the source electrode 12s of the corresponding semiconductor chip 12.
  • the second heat sink 24 is electrically connected to the corresponding source electrode 12s via the solder 22, the terminal 20, and the solder 26.
  • Most of each of the second heat sinks 24 is covered with the sealing resin body 14.
  • the solder 26 is connected to the mounting surface 24 a of the surface of the second heat sink 24, and the heat dissipation surface 24 b opposite to the mounting surface 24 a is exposed from the sealing resin body 14.
  • the heat dissipation surface 24b is substantially flush with the back surface 14b.
  • the solders 18, 22, 26 correspond to joining members.
  • the terminal 20 corresponding to the semiconductor chip 12H is connected to the mounting surface 24a of the second heat sink 24H via the solder 26.
  • the terminal 20 corresponding to the semiconductor chip 12L is connected to the mounting surface 24a of the second heat sink 24L via the solder 26.
  • the second heat sinks 24H and 24L are arranged side by side in the X direction and at substantially the same position in the Z direction.
  • the heat radiation surfaces 24b of the second heat sinks 24H and 24L are exposed from the back surface 14b of the sealing resin body 14 and are lined up in the X direction.
  • the joint portion 28 has a first joint portion 28a, a second joint portion 28b, and a third joint portion 28c.
  • the first joint portion 28a and the third joint portion 28c electrically connect the second heat sink 24H on the upper arm side and the first heat sink 16L on the lower arm side.
  • the second joint portion 28b electrically connects the second heat sink 24L on the lower arm side and the negative electrode terminal 32n.
  • the first joint portion 28a is provided integrally with the second heat sink 24H by processing the same metal plate.
  • the second joint portion 28b is provided integrally with the second heat sink 24L by processing the same metal plate. Then, the second heat sink 24H including the first joint portion 28a and the second heat sink 24L including the second joint portion 28b are used as a common member, and in the semiconductor device 10, these arrangements are performed with the Z axis as the rotation axis. It has a rotational symmetry.
  • the first joint portion 28a is provided thinner than the second heat sink 24H so as to be covered with the sealing resin body 14.
  • the first joint portion 28a is connected to the second heat sink 24H so as to be substantially flush with the mounting surface 24a of the second heat sink 24H.
  • the first joint portion 28a extends in the X direction from the side surface 24c of the second heat sink 24H on the second heat sink 24L side.
  • a third joint portion 28c is connected via a solder 30 to a surface of the first joint portion 28a that is continuous with the mounting surface 24a of the second heat sink 24H.
  • the second joint portion 28b has the same structure as the first joint portion 28a.
  • a negative terminal 32n is connected via a solder 30 to a surface of the second joint portion 28b which is continuous with the mounting surface 24a of the second heat sink 24L.
  • Grooves for absorbing the overflowed solder 30 are formed on the surfaces of the first joint portion 28a and the second joint portion 28b which are continuous with the mounting surface 24a. The groove is formed in an annular shape.
  • the third joint portion 28c is also provided integrally with the first heat sink 16L by processing the same metal plate.
  • the third joint portion 28c is provided thinner than the first heat sink 16L so as to be covered with the sealing resin body 14.
  • the third joint portion 28c is substantially flush with the mounting surface 16a of the first heat sink 16L.
  • the third joint portion 28c extends from the side surface 16c of the first heat sink 16L on the first heat sink 16H side toward the second heat sink 24H.
  • the third joint portion 28c extends in the X direction when seen in a plan view from the Z direction.
  • the third joint portion 28c has two bent portions.
  • the tip end portion of the third joint portion 28c overlaps with the first joint portion 28a in the projection view from the Z direction.
  • the third joint portion 28c and the first joint portion 28a are connected via the solder 30.
  • the third joint portion 28c is provided so as to be laterally aligned with the second joint portion 28b in the Y direction.
  • first joint portion 28a may be a member separate from the second heat sink 24H and may be connected to the second heat sink 24H to be connected to the second heat sink 24H.
  • the second joint portion 28b may be a member separate from the second heat sink 24L, and may be connected to the second heat sink 24L to be connected to the second heat sink 24L.
  • the third joint portion 28c may be a member separate from the first heat sink 16L, and may be connected to the first heat sink 16L to be connected to the first heat sink 16L. It is also possible to electrically connect the upper arm and the lower arm by only one of the first joint portion 28a and the third joint portion 28c.
  • the power supply terminal 32 has a positive electrode terminal 32p and a negative electrode terminal 32n.
  • the positive electrode terminal 32p is electrically connected to the positive electrode side terminal of the smoothing capacitor 4.
  • the positive electrode terminal 32p is a main terminal through which a main current flows.
  • the positive electrode terminal 32p is also called a high potential power supply terminal or P terminal. As shown in FIG. 4, the positive electrode terminal 32p is connected to the first heat sink 16H, and is extended in the Y direction from the side surface of the first heat sink 16H opposite to the surface on the signal terminal 36 side. .
  • the positive electrode terminal 32p is provided integrally with the first heat sink 16H by processing the same metal plate.
  • the positive electrode terminal 32p is connected to one end of the first heat sink 16H in the Y direction.
  • the positive electrode terminal 32p is extended in the Y direction and, as shown in FIG. 2, projects outward from the side surface 14c of the sealing resin body 14.
  • the negative electrode terminal 32n is electrically connected to the negative electrode side terminal of the smoothing capacitor 4.
  • the negative electrode terminal 32n is a main terminal through which a main current flows.
  • the negative electrode terminal 32n is also referred to as a low potential power supply terminal or N terminal.
  • the negative electrode terminal 32n is arranged such that a part thereof overlaps with the second joint portion 28b in a projection view from the Z direction.
  • the negative electrode terminal 32n is arranged at a position closer to the semiconductor chip 12 than the second joint portion 28b in the Z direction.
  • the negative electrode terminal 32n and the second joint portion 28b are also connected via the solder 30.
  • the negative electrode terminal 32n extends in the Y direction and protrudes to the outside from the same side surface 14c as the positive electrode terminal 32p.
  • the output terminal 34 is electrically connected to the connection point of the upper and lower arms.
  • the output terminal 34 is electrically connected to the coil (stator winding) of the corresponding phase of the motor 3.
  • the output terminal 34 is also called an AC terminal or an O terminal.
  • the output terminal 34 is connected to the first heat sink 16L, and from the side surface of the first heat sink 16L opposite to the surface on the signal terminal 36 side, the output terminal 34 is in the Y direction and the positive terminal. It is extended to the same side as 32p.
  • the output terminal 34 is provided integrally with the first heat sink 16L by processing the same metal plate.
  • the output terminal 34 is connected to one end of the first heat sink 16L in the Y direction.
  • the output terminal 34 extends in the Y direction and projects to the outside of the sealing resin body 14 from the same side surface 14c as the positive electrode terminal 32p and the negative electrode terminal 32n.
  • the protruding portions of the positive electrode terminal 32p, the negative electrode terminal 32n, and the output terminal 34 from the sealing resin body 14 are arranged at substantially the same positions in the Z direction. Further, in the X direction, the positive electrode terminal 32p, the negative electrode terminal 32n, and the output terminal 34 are arranged side by side in this order. In this way, the negative electrode terminal 32n is arranged next to the positive electrode terminal 32p.
  • the power supply terminal 32 and the output terminal 34 are also called main terminals because a main current flows through them.
  • a bus bar (not shown) is connected to the power supply terminal 32 and the output terminal 34.
  • the bus bar is connected to the corresponding power supply terminal 32 and output terminal 34 by, for example, laser welding.
  • the extension length of the protruding portion from the sealing resin body 14 is different between the three power supply terminals 32 and the output terminals 34, and the output terminal 34 is the longest.
  • the negative electrode terminal 32n is made the shortest.
  • the width of the protruding portion is widest at the positive electrode terminal 32p and narrowest at the output terminal 34.
  • the positive electrode terminal 32p may be a member separate from the first heat sink 16H, and may be connected to the first heat sink 16H to be connected to the first heat sink 16H.
  • the negative electrode terminal 32n may be made of the same metal plate as the second joint portion 28b and, by extension, the second heat sink 24L.
  • the output terminal 34 may be a member separate from the first heat sink 16L, and may be connected to the first heat sink 16L to be connected to the first heat sink 16L.
  • the signal terminal 36 is electrically connected to the corresponding pad 12p of the semiconductor chip 12 via the bonding wire 38, as shown in FIG.
  • the signal terminal 36 extends in the Y direction and, as shown in FIG. 2, projects outward from a side surface 14d of the sealing resin body 14 opposite to the side surface 14c.
  • the first heat sink 16, the third joint portion 28c, the power supply terminal 32, the output terminal 34, and the signal terminal 36 are configured as a lead frame 40 that is the same metal plate.
  • the connecting portion between the first heat sink 16 and the second joint portion 28b in the negative electrode terminal 32n is a thick portion, and the other portions are thin portions that are thinner than the thick portion. Has been done.
  • the sealing resin body 14 allows the semiconductor chip 12, a part of each of the first heat sinks 16, a part of each of the terminals 20 and the second heat sinks 24, and one of each of the power supply terminals 32. , A part of the output terminal 34, and a part of the signal terminal 36 are integrally sealed.
  • the sealing resin body 14 seals the two semiconductor chips 12 forming the upper and lower arms for one phase. Therefore, the semiconductor device 10 is also referred to as a 2-in-1 package.
  • the heat radiation surface 16b of each of the first heat sinks 16H and 16L is located in the same plane and is substantially flush with the one surface 14a of the sealing resin body 14.
  • the heat radiation surface 24b of each of the second heat sinks 24H and 24L is located in the same plane and is substantially flush with the back surface 14b of the sealing resin body 14.
  • the semiconductor device 10 has a double-sided heat dissipation structure in which both the heat dissipation surfaces 16b and 24b are exposed from the sealing resin body 14.
  • FIGS. 2, 4 to 6, and 8. 2 show the lead frame 40 in a product state.
  • the lead frame 40 has an unillustrated outer frame and tie bar until the unnecessary portion is removed in the manufacturing process described below.
  • each element that constitutes the semiconductor device 10 is prepared.
  • the lead frame 40 shown in FIG. 4 is prepared.
  • the semiconductor chip 12, the terminal 20, and the second heat sink 24 are prepared.
  • the corresponding semiconductor chips 12H and 12L are arranged on the mounting surface 16a of the first heat sinks 16H and 16L in the lead frame 40 via the solder 18. At that time, the semiconductor chips 12H and 12L are arranged so that the drain electrode 12d faces the mounting surface 16a.
  • the terminals 20 in which the solders 22 and 26 are previously arranged as the solders on both surfaces are arranged so that the solders 22 are on the semiconductor chip 12 side.
  • the solder 26 is arranged in such an amount that the height variation in the semiconductor device 10 can be absorbed.
  • the solder 30 is arranged on the third joint portion 28c and the negative electrode terminal 32n.
  • the second heat sink 24 is placed on a pedestal not shown so that the mounting surface 24a faces upward. Then, the connection body is arranged on the second heat sink 24 so that the terminal 20 faces the second heat sink 24, and the solder second reflow is performed. In the 2nd reflow, a load is applied from the first heat sink 16 side so that the height of the semiconductor device 10 becomes a predetermined height.
  • FIG. 8 shows a state after the second reflow.
  • the sealing resin body 14 is molded by the transfer molding method.
  • the sealing resin body 14 is molded so that the first heat sink 16 and the second heat sink 24 are completely covered.
  • a polyamide resin is applied to the surface portions of the first heat sink 16, the semiconductor chip 12, the terminal 20 and the like which are in contact with the sealing resin body 14, and the surface of the sealing resin body 14 is The adhesion can be improved.
  • the molded sealing resin body 14 is cut together with a part of the first heat sink 16 to expose the heat radiation surface 16b of the first heat sink 16.
  • the heat dissipation surface 16b becomes substantially flush with the one surface 14a.
  • the heat radiation surface 24b of the second heat sink 24 is exposed.
  • the heat dissipation surface 24b becomes substantially flush with the back surface 14b.
  • the sealing resin body 14 may be molded in a state where the heat radiating surfaces 16b and 24b are pressed against the cavity wall surface of the molding die and brought into close contact with each other. In this case, the heat dissipation surfaces 16b and 24b are exposed from the sealing resin body 14 when the sealing resin body 14 is molded. Therefore, cutting after molding is unnecessary.
  • the terminal 20 is formed by laminating a plurality of types of metal layers. Metal layers adjacent to each other in the stacking direction are joined.
  • the different types may be different in constituent metals or different in linear expansion coefficient.
  • the plurality of kinds of metal layers have different linear expansion coefficients in at least one direction of the Z direction and the direction orthogonal to the Z direction, and the respective linear expansion coefficients are within the range of the semiconductor chip 12 or more and the second heat sink 24 or less. Should be said. It becomes easy to adjust the linear expansion coefficient of the entire terminal 20 between the semiconductor chip 12 and the second heat sink 24.
  • the direction orthogonal to the Z direction is the direction along the XY plane, that is, the X direction and the Y direction.
  • the coefficient of linear expansion of SiC is about 4 ⁇ 10 ⁇ 6 / K, and that of Cu is about 17 ⁇ 10 ⁇ 6 / K.
  • a clad material including a metal layer made of the first metal and an alloy layer containing the first metal is adopted as the terminal 20, a clad material including a metal layer made of the first metal and an alloy layer containing the first metal is adopted. Specifically, as shown in FIG. 9, a clad material including a Cu layer 20a and an alloy layer 20b containing Cu is adopted. Since the clad material is bonded by molecular diffusion without using a bonding material, it is possible to improve the connection reliability between layers as compared with the conventional laminated type. In this embodiment, since all layers contain the same metal (Cu), the connection reliability can be improved. Furthermore, as compared with the configuration in which all terminals are alloy layers, it is possible to suppress a decrease in heat dissipation.
  • the Cu layer 20a has excellent heat dissipation and thermal conductivity, but has a larger coefficient of linear expansion than that of SiC.
  • the linear expansion coefficient of the Cu layer 20a is the same as that of the second heat sink 24.
  • the alloy layer 20b contains Cu and a metal material having a smaller linear expansion coefficient than Cu.
  • the alloy layer 20b has a linear expansion coefficient smaller than that of Cu at least in the direction orthogonal to the Z direction.
  • the alloy layer 20b contains Cr. When Cr is used, the linear expansion coefficient can be reduced, and the terminal 20 can be inexpensive and lightweight.
  • the alloy layer 20b containing Cr is formed by rolling, for example, Cr impregnated with Cu.
  • rolling the coefficient of linear expansion in the rolling direction and the coefficient of linear expansion orthogonal to the rolling direction behave differently. This is because, when the thermal expansion of Cu is restricted by Cr that is flat in the rolling direction, the way the stress works differs in the direction orthogonal to the rolling direction.
  • the rolling reduction is the reduction rate of the plate thickness of the material to be rolled.
  • the coefficient of linear expansion continues to decrease as the rolling reduction increases.
  • the rolling reduction becomes almost constant at about 70%.
  • the linear expansion coefficient continues to decrease with an increase in the rolling reduction, but the reduction width with respect to the rolling reduction is smaller than that in the rolling direction.
  • the linear expansion coefficient continues to decrease even when rolled to a rolling reduction of 98%, and approaches the linear expansion coefficient in the rolling direction.
  • the terminal 20 is composed of a clad material that uses a rolled Cr—Cu material that has been rolled down to 70% or more.
  • the X direction and the Y direction are rolling directions, so that the same linear expansion coefficient is obtained in the direction orthogonal to the Z direction, that is, in the X direction and the Y direction. .
  • the coefficient of linear expansion in the Z direction is larger than those in the X and Y directions, and is smaller than Cu in the present embodiment.
  • the thermal expansion of the Cu layer 20a is constrained by the alloy layer 20b, and the effect of suppressing the linear expansion coefficient is higher than when the Cu and Cr—Cu alloy are simply compounded with each other.
  • the linear expansion coefficient in the direction orthogonal to the Z direction is a value between the semiconductor chip 12 and the second heat sink 24, for example, about 12 to 13 ⁇ 10 ⁇ 6 / K in the entire terminal 20. Has been done. Therefore, the thermal stress that acts on the solder 22 that connects the semiconductor chip 12 and the terminal 20 can be reduced.
  • the thermal stress acting on the solders 18 and 22 can be reduced without impairing the heat dissipation of the semiconductor device 10.
  • the alloy layer 20b is thinner than the Cu layer 20a, the heat dissipation effect can be enhanced while using the alloy layer 20b.
  • the Cu layer 20a and the alloy layer 20b are symmetrically arranged in the Z direction. Specifically, as shown in FIG. 9, the terminals 20 are arranged in line symmetry with respect to the center line CL in the Z direction.
  • the Cu layers 20a and the alloy layers 20b are alternately arranged so that the number of layers becomes 5, which is an odd number.
  • the Cu layers 20a have almost the same thickness, and the alloy layers 20b have the same thickness.
  • the terminal 20 Since the symmetry in the Z direction is high as described above, it is possible to prevent the terminal 20 from warping based on the difference in linear expansion coefficient between the metal layers forming the terminal 20. That is, the stress acting on the solders 18, 22, and 26 can be reduced.
  • the terminal 20 has a rectangular shape in plan view, and the Cu layer 20a and the alloy layer 20b have substantially the same shape when viewed in the Z direction. Therefore, the terminal 20 has a high symmetry even in the direction orthogonal to the Z direction, and thus the warp can be suppressed.
  • the Cu layer 20a, the alloy layer 20b, the Cu layer 20a, the alloy layer 20b, and the Cu layer 20a are laminated in this order.
  • the Cu layer 20a having higher wettability than the alloy layer 20b is arranged on the surface layer.
  • an alloy layer 20b having a lower wettability than the Cu layer 20a appears on the side surface of the terminal 20. As a result, it is possible to suppress the creeping of the solder to the side surface of the terminal 20 while ensuring the bondability with the solders 22 and 26.
  • SiC silicon carbide
  • SiC has characteristics such as a larger dielectric breakdown electric field and bandgap, a higher thermal conductivity, and a higher electron saturation speed than Si.
  • the Young's modulus is about three times as large as that of Si.
  • the terminal 20 is configured by laminating a plurality of types of metal layers.
  • the coefficient of linear expansion in the direction orthogonal to the Z direction is a value between the semiconductor chip 12 and the second heat sink 24 for the entire terminal 20. Therefore, the thermal stress acting on the solders 18, 22, 26 and the semiconductor chip 12 can be reduced.
  • the metal layers are symmetrically arranged in the Z direction.
  • the warp of the terminal 20 can be suppressed, and the local stress on the solders 18, 22, 26 and the semiconductor chip 12 can be suppressed.
  • the semiconductor device 10 of the present embodiment is suitable for the configuration using SiC for the semiconductor chip 12.
  • a clad material in which a Cu layer 20a and an alloy layer 20b containing Cu are sequentially laminated is used as the terminal 20.
  • the reliability of connection between layers can be improved as compared with the conventional laminated type terminal using a bonding material.
  • the connection reliability between the layers can be improved.
  • the alloy layer 20b contains Cr, the linear expansion coefficient can be made small and the structure can be made inexpensive and lightweight.
  • the surface layer of the terminal 20 is the Cu layer 20a.
  • the connection reliability with the solders 22 and 26 can be improved.
  • the alloy layer 20b having low wettability appears on the side surface, the creeping up of the solders 22 and 26 can be suppressed.
  • the configuration of the terminal 20 is not limited to the above example.
  • the arrangement of the Cu layer 20a and the alloy layer 20b containing Cr is not limited to the above example.
  • the number of layers is not limited to five. It may be three layers or more. In the case of odd layers, it becomes possible to have symmetry in the Z direction. Alternatively, the number of layers may be even.
  • two clad materials of the Cu layer 20a, the alloy layer 20b, and the Cu layer 20a are laminated to form a six-layer structure of the Cu layer 20a, the alloy layer 20b, the Cu layer 20a, the Cu layer 20a, the alloy layer 20b, and the Cu layer 20a. Good. Also in this case, it becomes possible to provide symmetry in the Z direction.
  • the alloy layer 20b is the surface layer
  • the alloy layer 20b, the Cu layer 20a, the alloy layer 20b, the Cu layer 20a, and the alloy layer 20b are stacked in this order.
  • the heat transfer from the small alloy layer 20b to the large Cu layer 20a has a smaller barrier to heat conduction than the heat transfer from the Cu layer 20a having a large linear expansion coefficient to the small alloy layer 20b.
  • the alloy layer 20b since the alloy layer 20b has a larger number of layers than the Cu layer 20a while adopting the five-layer structure, the heat dissipation property can be improved as compared with the configuration shown in FIG.
  • the surface Cu layer 20c may be thinner than the inner Cu layer 20a and alloy layer 20b.
  • the Cu layer 20c may be about 30 ⁇ m
  • the Cu layer 20a may be about 1 mm
  • the alloy layer 20b may be about 500 ⁇ m.
  • the linear expansion coefficient and heat dissipation are adjusted by the Cu layer 20a and the alloy layer 20b, and the Cu layer 20c is provided to improve the bondability.
  • a metal material having a small linear expansion coefficient such as Mo may be used.
  • a material having excellent heat conduction such as Al may be used.
  • a clad material of a Cu layer 20a, an alloy layer 20b containing Cr, and an alloy layer 20d containing Mo may be used as the terminal 20.
  • the Cu layer 20a, the alloy layer 20b, the Cu layer 20a, the alloy layer 20d, and the Cu layer 20a are stacked in this order.
  • the warp of the terminal 20 can be suppressed by making the linear expansion coefficients of the alloy layers 20b and 20d close to each other, preferably substantially the same. That is, by making the linear expansion coefficient have symmetry in the Z direction, the warpage of the terminal 20 can be suppressed.
  • the source electrode 12s has an upper layer formed on the base layer for the purpose of improving the bonding strength between the base layer containing Al as a main component such as AlSi and the solder 22 and the wettability of the solder 22.
  • the upper ground layer is formed using a material containing Ni as a main component such as NiP.
  • Ni is a metal material that is harder than Al.
  • SiC having a large Young's modulus is adopted as the semiconductor chip 12.
  • the surface of the terminal 20 facing the semiconductor chip 12 has a portion having good wettability with the solder 22, and a portion having lower wettability than the good portion.
  • a part of the Cu layer 20c on the semiconductor chip 12 side of the thin Cu layer 20c on the surface layer is removed by etching, and the Cu layer 20c is arranged only in the central region of the facing surface. In the outer peripheral region surrounding the Cu layer 20c, the alloy layer 20b immediately below the Cu layer 20c is exposed.
  • the solder 22 Since the wettability of the alloy layer 20b is lower than that of the Cu layers 20a and 20c, even if the solder 22 wets and spreads on the alloy layer 20b arranged in the outer peripheral region of the facing surface of the terminal 20, the solder 22 includes the fillet so as to include the outer peripheral region. Is not formed. Therefore, the angle formed by the source electrode 12s and the solder 22, that is, the fillet angle can be made acute. As a result, in the underlayer, the stress concentrated on the portion immediately below the end surface of the upper ground layer can be reduced. Further, since the clad material is prepared and only a part of the surface layer is removed, the structure can be simplified.
  • the broken line shown in FIG. 13 is a reference line showing a fillet when the Cu layer 20c is arranged on the entire surface of the facing surface.
  • the configuration of the terminal 20 is not limited to the above example.
  • a portion where the terminal 20 faces the semiconductor chip 12 is partially provided with poor wetting, and the fillet angle is controlled.
  • a film having good wettability may be locally provided by sputtering or the like.
  • the alloy layer 20b instead of the alloy layer 20b, the alloy layer 20d containing Mo may be exposed to form a poorly wetted portion.
  • the alloy layers 20b and 20d may be partially exposed to form a poorly wetted portion.
  • a clad material may be used for at least one of the heat sinks 16 and 24.
  • a clad material is used for each of the first heat sink 16 and the second heat sink 24.
  • the terminal 20 has the same configuration as that of the first embodiment (see FIG. 9).
  • FIG. 14 is a sectional view taken along line XIV-XIV shown in FIG.
  • the second heat sink 24H uses a clad material including the first joint portion 28a (not shown).
  • the second heat sink 24H including the first joint portion 28a is formed by alternately stacking the Cu layers 24d and the alloy layers 24e containing Cu and Cr, and has three Cu layers 24d and two alloy layers 24e. ing. In this way, the second heat sink 24H is configured similarly to the terminal 20. The same applies to the second heat sink 24L.
  • the positive electrode terminal 32p and the signal terminal 36, the negative electrode terminal 32n (not shown), the output terminal 34, the third joint portion 28c, and a part of the first heat sink 16 are formed of a base material 41 made of Cu.
  • the thin portion of the lead frame 40 is composed of the base material 41.
  • the thick portion of the lead frame 40 includes the clad material 42.
  • the clad material 42 is formed by alternately stacking Cu layers 16d and alloy layers 16e containing Cu and Cr.
  • the base material 41 and the clad material 42 form the first heat sink 16 shown in FIG.
  • the first heat sink 16 has a laminated structure of a Cu layer 16d of three layers and an alloy layer 16e of two layers by the base material 41 and the clad material 42.
  • the second heat sink 24 is also made of the clad material.
  • the second heat sink 24 it is possible to reduce the linear expansion coefficient in the direction orthogonal to the Z direction, that is, in the X direction and the Y direction, while suppressing the decrease in heat dissipation.
  • the difference in the coefficient of linear expansion from the terminal 20 can be reduced or substantially matched. Therefore, the thermal stress acting on the solder 26 between the second heat sink 24 and the terminal 20 can be reduced.
  • the Cu layer 24d constitutes the surface on the mounting surface 24a side, the connectivity with the solders 26 and 30 can be improved.
  • the first heat sink 16 is also made of a clad material.
  • the first heat sink 16 it is possible to reduce the linear expansion coefficient in the direction orthogonal to the Z direction while suppressing the decrease in heat dissipation. Therefore, the thermal stress acting on the solder 18 between the first heat sink 16 and the semiconductor chip 12 can be reduced.
  • both the heat sinks 16 and 24 include the clad material, and the linear expansion coefficient of the entire first heat sink 16 and the linear expansion coefficient of the entire second heat sink 24 are substantially the same in the direction orthogonal to the Z direction. Has a value. Therefore, the warp of the semiconductor device 10 can be suppressed. Further, since the base material 41 made of Cu is used, the connectivity with the solder 18, the bonding wire 38, the bus bar, etc. can be improved.
  • the application of the clad material to the heat sinks 16 and 24 is not limited to the above example. Only the first heat sink 16 may include the clad material. Alternatively, only the second heat sink 24 may include the clad material. However, as described above, it is preferable that both the heat sinks 16 and 24 include the clad material.
  • the configuration of the clad material may be different from the example shown in FIG.
  • the configuration may be different from that of the terminal 20.
  • the lead frame 40 including the first heat sink 16 may be composed of only the clad material, like the second heat sink 24H.
  • the positive electrode terminal 32p and the signal terminal 36 also have a laminated structure of the Cu layer 16d and the alloy layer 16e.
  • the surface layer is the Cu layer 16d, the connectivity with the solder 18, the bonding wire 38, the bus bar, etc. can be improved.
  • the second heat sink 24 may have the same configuration as the lead frame 40 (first heat sink 16) described above. That is, the first joint portion 28a may be made of a base material made of Cu, and the second heat sink 24 may be made of a base material and a clad material. Since the base material constitutes the surface on the mounting surface 16a side, the connectivity with the solders 26 and 30 can be improved.
  • the alloy layer 24e may form the heat dissipation surface 24b. Further, the alloy layer 16e may form the heat dissipation surface 16b. For example, by providing a cutting line in the middle of the alloy layer 24e, the alloy layer 24e forms the heat dissipation surface 24b. Further, by providing a cutting line in the middle of the alloy layer 16e, the alloy layer 16e forms the heat dissipation surface 16b. Since Cr has a better machinability than Mo or Cu, if a cutting line is provided in the alloy layers 16e and 24e containing Cr, the machinability when exposing the heat dissipation surfaces 16b and 24b can be improved.
  • the second heat sink 24 may be configured such that the alloy layer 24e forms the mounting surface 24a.
  • the heat dissipation can be improved by having a structure in which the alloy layer 24e is larger than the Cu layer 24d.
  • An alloy layer containing Cu and Mo may be adopted instead of the alloy layers 16e and 24e containing Cr. This also makes it possible to reduce the coefficient of linear expansion of the heat sinks 16 and 24.
  • the heat sinks 16 and 24 may be made of only the clad material, and the positive electrode terminal 32p, the first joint portion 28a, and the like that are continuous with the heat sinks 16 and 24 may be made of a thin plate made of Cu.
  • the thin plate and the clad material may be connected by diffusion bonding, laser welding, caulking or the like.
  • a clad material may be used for the second heat sink 24 in a configuration in which the clad material is not used for the terminal 20, for example, in a configuration in which the terminal 20 is made of Cu. Also in this case, the machinability can be improved by using the alloy layer 24e as the heat dissipation surface 24b.
  • the clad material may be used for the first heat sink 16. It is possible to reduce the difference in the coefficient of linear expansion from the semiconductor chip 12 and reduce the thermal stress that acts on the solder 18 between the semiconductor chip 12 and the first heat sink 16. Further, when the alloy layer 16e is used as the heat dissipation surface 16b, the machinability can be improved.
  • the lead-free solder specified below is used as at least one of the solders 18, 22, and 26. This lead-free solder can be combined with any of the preceding embodiments and modifications.
  • the lead-free solder contains Ag of 3.2 to 3.8% by mass, Cu of 0.6 to 0.8% by mass, Ni of 0.01 to 0.2% by mass, and further contains Sb and Bi. .
  • Addition of Ag has the effect of improving solder wettability and strengthening precipitation dispersion.
  • the liquidus temperature rises.
  • the content of Ag is set to 3.2 to 3.8 mass% in order to sufficiently obtain the effects of improving wettability and precipitation dispersion and suppressing the liquidus temperature to 270 ° C. or less in consideration of variations. ing.
  • the addition of Cu has the effects of preventing Cu from being eaten by the Cu land and precipitating Cu 6 Sn 5 which is a fine intermetallic compound in the solder matrix to strengthen the matrix. If added excessively, an intermetallic compound will be precipitated at the bonding interface, and crack propagation will be accelerated. Therefore, the Cu content is set to 0.6 to 0.8 mass%.
  • Ni has the effect of strengthening the bonding interface by refining the intermetallic compound that precipitates at the bonding interface.
  • the liquidus temperature rises.
  • the Ni content is set to 0.01 to 0.2 mass% in order to suppress the liquidus temperature to 270 ° C. or lower while sufficiently obtaining the effect of strengthening the bonding interface.
  • Sb has the effects of solid solution precipitation strengthening and precipitation dispersion strengthening, and the substitution of Sb for Sn causes lattice distortion, and has the effect of strengthening the Sn matrix.
  • Bi having an atomic radius larger than that of Sb exerts an effect of Sb or more in strengthening the Sn matrix.
  • Sb and Bi are excessively contained, wettability and workability into foil are deteriorated.
  • Creep resistance increases due to the effect of strengthening the Sn matrix with the addition of Sb and Bi. That is, creep can be suppressed low.
  • the solidus temperature is 200 ° C. or higher in order to maintain solder connection reliability in a molding process after soldering.
  • the amounts of Sb and Bi added are adjusted in consideration of the above effects.
  • Lead-free solder satisfying the above requirements not only extends the service life of the solder joints, but also reduces unnecessary stress concentration on a part of the semiconductor chip due to creep, while responding to the high temperature of the operating environment. become. Therefore, it is suitable for the semiconductor chip 12 made of a SiC substrate that can operate at high temperature and has a large Young's modulus.
  • the lead-free solder described above may be used for the solder 26. Even if the thermal stress acting on the solder 22 is increased by using the terminal 20 shown in the previous embodiment, high connection reliability can be maintained.
  • solder 18 may be used for the solder 18. Even when thermal stress based on the difference in linear expansion coefficient between the semiconductor chip 12 and the first heat sink 16 acts, high connection reliability can be maintained.
  • the semiconductor chip 12 has a large Young's modulus, when the power cycle test is performed, the solders 18 and 22 around the semiconductor chip 12 creep, and there is a concern that solder cracks and the like may occur as the number of cycles increases. On the other hand, by using the lead-free solder described above, the creep of the solders 18, 22 can be suppressed.
  • lead-free solder Since the above-mentioned lead-free solder has characteristics such as excellent creep resistance, it is effective for extending the life of the entire semiconductor device 10 regardless of the configuration of the terminal 20 and the heat sinks 16 and 24. Therefore, lead-free solder may be used for at least one of the solders 18, 22, and 26 in a configuration in which a clad material is not used for each component.
  • FIG. 16 shows the result of simulation of solder distortion.
  • FIG. 16 shows the result of a configuration in which the terminal 20 and the heat sinks 16 and 24 do not use a clad material.
  • Below the element is the solder 18 immediately below the semiconductor chip 12, above the element is the solder 22 immediately above the semiconductor chip 12, and above TML is the solder 26 on the terminal 20.
  • Comparative Example 1 shows the result of the configuration using the conventional solder in the semiconductor chip using the Si substrate.
  • Comparative example 2 (ratio 2 in the figure) shows the result of a configuration in which the Si substrate of comparative example 1 is replaced with a SiC substrate.
  • the example (actual in the figure) shows the result of the configuration in which the solder is replaced with the above-mentioned lead-free solder as compared with the comparative example 2.
  • the solder strain of the solders 18 and 22 around the semiconductor chip 12 increases.
  • the solder strain of both the solders 18 and 22 can be reduced.
  • the PB-free solder is suitable even in the configuration in which the terminal 20 and the heat sinks 16 and 24 do not use the clad material.
  • the present disclosure is not limited to the illustrated embodiments.
  • the present disclosure encompasses the illustrated embodiments and variations based on them based on those skilled in the art.
  • the present disclosure is not limited to the combination of elements shown in the embodiments.
  • the disclosure can be implemented in various combinations.
  • the disclosed technical scope is not limited to the description of the embodiments. It is to be understood that some technical scopes disclosed are shown by the description of the claims, and further include meanings equivalent to the description of the claims and all modifications within the scope.
  • the example of the 2 in 1 package structure including the semiconductor chip 12H on the upper arm side and the semiconductor chip 12L on the lower arm side is shown as the semiconductor device 10, but the invention is not limited to this.
  • the present invention can also be applied to a 1-in-1 package structure including one semiconductor chip forming one arm and a 6-in-1 package structure including six semiconductor chips forming upper and lower arms for three phases.
  • heat radiation surfaces 16b and 24b of the heat sinks 16 and 24 are exposed from the sealing resin body 14 has been shown, but the invention is not limited to this. At least one of the heat radiation surfaces 16b and 24b may be covered with the sealing resin body 14.
  • the example of the MOSFET 6 is shown as an element formed on the semiconductor chip 12, but the element is not limited to this. Any vertical element applied to the power conversion device may be used. For example, it can be applied to an IGBT and an SBD. In the case of the IGBT, the IGBT and the FWD may be configured by one chip or may be separate chips.
  • the present invention is not limited to this. It can also be applied to a structure without coating.
  • the adhesion may be increased by roughening the surface by laser processing. In this case, for example, the surface may be roughened by irradiating laser light in the step of preparing each member.
  • SiC substrate An example of a SiC substrate has been shown as a semiconductor substrate forming the semiconductor chip 12. However, it can be applied to a semiconductor substrate having a Young's modulus larger than Si, other than SiC.
  • a film that enhances wettability with solder may be formed by plating, sputtering, or the like.
  • You may provide a Ni-based thin film, for example, a NiP plating film.
  • the wettability of the solder may be partially reduced by irradiating laser light. Irradiation with laser light forms an oxide film containing Ni as a main component and having fine irregularities on the surface. This oxide film can reduce the wettability.

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Abstract

半導体装置は、SiC基板に素子が形成され、一面及び裏面のそれぞれに主電極が形成された半導体チップ(12)と、一面側に配置された第1ヒートシンク(16)、及び、裏面側に配置された第2ヒートシンク(24)と、第2ヒートシンクと半導体チップとの間に介在し、裏面側の主電極と第2ヒートシンクとを電気的に中継するターミナル(20)と、一面側の主電極と第1ヒートシンクとの間、裏面側の主電極とターミナルとの間、ターミナルと第2ヒートシンクとの間、のそれぞれに配置された接合部材(18,22,26)と、を備える。ターミナルは、複数種類の金属層(20a,20b,20c,20d)が、板厚方向に積層されてなり、少なくとも板厚方向に直交する方向の線膨張係数が、半導体チップよりも大きく、第2ヒートシンクよりも小さい範囲内とされ、ターミナルにおいて、複数種類の金属層は、板厚方向において対称配置されている。

Description

半導体装置 関連出願の相互参照
  本出願は、2018年10月15日に出願された日本国特許出願2018-194377号に基づくものであり、ここにその記載内容を参照により援用する。
 本開示は、半導体装置に関する。
 特許文献1には、両面放熱構造の半導体装置が提案されている。この半導体装置は、半導体チップ、一対のヒートシンク(リードフレーム)、及びターミナル(ヒートシンクブロック)を備えている。半導体チップは、シリコン基板にIGBTやMOSFETなどの素子が形成されてなり、一面及び裏面のそれぞれに主電極を有している。一対のヒートシンクは、一面側に配置された第1ヒートシンクと、裏面側に配置された第2ヒートシンクを有している。ターミナルは、第2ヒートシンクと半導体チップの間に介在し、電気的に中継している。半導体チップと第1ヒートシンク、半導体チップとターミナル、ターミナルと第2ヒートシンクは、それぞれ接合部材を介して接続されている。
JP 2013-98228 A
 近年、Siに較べて絶縁破壊電界やバンドギャップが大きい、熱伝導率が高い、電子飽和速度が速いといった特性を備える点で、SiCが注目されている。しかしながら、SiCのヤング率はSiの約3倍と大きい。このため、半導体チップが上下からヒートシンクによって挟まれた上記の両面放熱構造において、半導体チップにSiCを用いると、接合部材や半導体チップにクラックなどが生じるおそれがある。
 本開示の目的は、半導体チップにSiCを用いた場合でも好適な半導体装置を提供することである。
 本開示の一態様によれば、半導体装置は、SiC基板に素子が形成され、一面及び該一面と板厚方向において反対の裏面のそれぞれに主電極が形成された半導体チップと、板厚方向において半導体チップを挟むように配置された一対のヒートシンクであって、一面側に配置された第1ヒートシンク、及び、裏面側に配置された第2ヒートシンクと、第2ヒートシンクと半導体チップとの間に介在し、裏面側の主電極と第2ヒートシンクとを電気的に中継するターミナルと、一面側の主電極と第1ヒートシンクとの間、裏面側の主電極とターミナルとの間、ターミナルと第2ヒートシンクとの間、のそれぞれに配置された接合部材と、を備える。ターミナルは、複数種類の金属層が、板厚方向に積層されてなり、少なくとも板厚方向に直交する方向の線膨張係数が、ターミナルの全体として、半導体チップよりも大きく、第2ヒートシンクよりも小さい範囲内とされ、ターミナルにおいて、複数種類の金属層は、板厚方向において対称配置されている。
 本開示の一態様によれば、半導体装置において、複数種類の金属層が積層されてターミナルが構成されており、少なくとも板厚方向に直交する方向における線膨張係数は、半導体チップと第2ヒートシンクとの間の値となっている。したがって、各接合部材や半導体チップに作用する熱応力を低減することができる。さらに、金属層は、Z方向において対称配置されている。これにより、ターミナルの反りを抑制し、各接合部材や半導体チップに局所的な応力が作用するのを抑制することができる。したがって、本開示は、両面放熱構造の半導体装置において、半導体チップにSiCを用いた構成に好適である。
 本開示の他の一態様によれば、半導体装置は、SiC基板に素子が形成され、一面及び該一面と板厚方向において反対の裏面のそれぞれに主電極が形成された半導体チップと、板厚方向において半導体チップを挟むように配置された一対のヒートシンクであって、一面側に配置された第1ヒートシンク、及び、裏面側に配置された第2ヒートシンクと、第2ヒートシンクと半導体チップとの間に介在し、裏面側の主電極と第2ヒートシンクとを電気的に中継するターミナルと、一面側の主電極と第1ヒートシンクの間、裏面側の主電極とターミナルとの間、ターミナルと第2ヒートシンクとの間、のそれぞれに配置された接合部材と、を備える。ターミナルは、Cu層と、CuとCrを含む合金層とが、板厚方向に順に積層された3層以上のクラッド材であり、Cu層及び合金層は、板厚方向において対称配置されている。
 本開示の他の一態様によれば、半導体装置において、ターミナルとして、Cu層と、CuとCrを含む合金層とのクラッド材を用いている。この合金層を含むことで、Cu層の板厚方向に直交する方向への膨張が拘束され、ターミナル全体として上記直交する方向の線膨張係数を小さくすることができる。したがって、各接合部材や半導体チップに作用する熱応力を低減することができる。さらに、Cu層及び合金層は、板厚方向において対称配置されている。これにより、ターミナルの反りを抑制し、各接合部材や半導体チップに局所的な応力が作用するのを抑制することができる。したがって、本開示は、両面放熱構造の半導体装置において、半導体チップにSiCを用いた構成に好適である。
 本開示についての上記および他の目的、特徴や利点は、添付図面を参照した下記詳細な説明から、より明確になる。添付図面において、
図1は、第1実施形態の半導体装置が適用される電力変換装置の構成を示す図である。 図2は、半導体装置を示す斜視図である。 図3は、図2のIII-III線に沿う断面図である。 図4は、第1ヒートシンクを含むリードフレームを示す斜視図である。 図5は、半導体チップを配置した状態を示す斜視図である。 図6は、ターミナルを配置した状態を示す斜視図である。 図7は、第2ヒートシンクを示す斜視図である。 図8は、第2ヒートシンクを配置した状態を示す斜視図である。 図9は、ターミナルの詳細構造を示す断面図である。 図10は、第1変形例を示す断面図であり、図9に対応している。 図11は、第2変形例を示す断面図であり、図9に対応している。 図12は、第3変形例を示す断面図であり、図9に対応している。 図13は、第2実施形態の半導体装置において、ターミナル周辺を示す断面図である。 図14は、第3実施形態の半導体装置を示す断面図であり、図2のXIV-XIV線に対応している。 図15は、第4変形例を示す断面図である。 図16は、第4実施形態の半導体装置に適用されるPbフリーはんだについて、はんだ歪のシミュレーション結果を示す図である。
 図面を参照しながら、複数の実施形態及び変形例を説明する。複数の実施形態及び変形例において、機能的に及び/又は構造的に対応する部分には同一の参照符号を付与する。以下において、半導体チップの板厚方向をZ方向、Z方向に直交し、半導体チップの並び方向をX方向と示す。また、Z方向及びX方向の両方向に直交する方向をY方向と示す。特に断わりのない限り、XY面視したときの形状(XY平面に沿う形状)を平面形状とする。XY面視は、Z方向の投影視とも言える。
 (第1実施形態)
 以下において、符号末尾のHは、上下アームのうち、上アーム側の要素であることを示し、末尾のLは、下アーム側の要素であることを示す。要素の一部には、上アーム及び下アームを明確にするために末尾にH,Lを付与し、別の一部については、上アームと下アームとで共通符号としている。
 (電力変換装置の構成)
 図1に示す電力変換装置1は、たとえば電気自動車やハイブリッド自動車に搭載される。電力変換装置1は、車両に搭載された直流電源2から供給される直流電圧を、三相交流に変換して、三相交流方式のモータ3に出力するように構成されている。モータ3は、車両の走行駆動源として機能する。電力変換装置1は、モータ3により発電された電力を、直流に変換して直流電源2などに充電することもできる。このように、電力変換装置1は、双方向の電力変換が可能となっている。
 電力変換装置1は、平滑コンデンサ4と、電力変換器であるインバータ5を備えている。平滑コンデンサ4の正極側端子は、直流電源2の高電位側の電極である正極に接続され、負極側端子は、直流電源2の低電位側の電極である負極に接続されている。インバータ5は、入力された直流電力を所定周波数の三相交流に変換し、モータ3に出力する。インバータ5は、モータ3により発電された交流電力を、直流電力に変換する。
 インバータ5は、6つのアームを備えて構成されている。各相の上下アームは、平滑コンデンサ4の正極側端子と負極側端子との間で、2つのアームが直列に接続されてなる。各相の上下アームは、後述する半導体装置10によって構成されている。インバータ5は、3つの半導体装置10によって構成されている。
 本実施形態では、各アームがMOSFET6を有している。また、MOSFET6として、nチャネル型を採用している。MOSFET6は、主電流が流れる主電極として、ドレイン電極及びソース電極を有している。上アーム側のMOSFET6のドレイン電極は、平滑コンデンサ4の正極側端子に接続されている。下アーム側のMOSFET6のソース電極は、平滑コンデンサ4の負極側端子に接続されている。上アーム側のMOSFET6のソース電極と、下アーム側のMOSFET6のドレイン電極が相互に接続されている。
 電力変換装置1は、上記した平滑コンデンサ4及びインバータ5に加えて、直流電源2から供給される直流電圧を昇圧する昇圧コンバータ、インバータ5や昇圧コンバータを構成する素子の駆動回路、駆動回路に対して駆動指令を出力する制御回路などを備えてもよい。
 (半導体装置の構成)
 図2~図8に示すように、半導体装置10は、半導体チップ12、封止樹脂体14、第1ヒートシンク16、ターミナル20、第2ヒートシンク24、継手部28、電源端子32、出力端子34、及び信号端子36を備えている。図4では、半導体装置10のうち、第1ヒートシンク16を含むリードフレーム40のみを示している。図5では、図4に対し、半導体チップ12が接続された状態を示している。図6では、図5に対し、ターミナル20が接続された状態を示している。図8では、図6に対し、第2ヒートシンク24が接続された状態を示している。
 半導体チップ12は、SiC基板に素子が形成されてなる。以下において、上アーム側の素子が形成された半導体チップ12を半導体チップ12H、下アーム側の素子が形成された半導体チップ12を半導体チップ12Lとも示す。2つの半導体チップ12H,12Lは、板厚方向を同じ方向(Z方向)にして配置されている。
 半導体チップ12に形成された素子は、Z方向に電流が流れるように縦型構造をなしている。本実施形態では、素子として、上記したようにnチャネル型のMOSFETが形成されている。図3に示すように、半導体チップ12の板厚方向、すなわちZ方向において、半導体チップ12の一面にドレイン電極12dがそれぞれ形成され、一面と反対の裏面にソース電極12sがそれぞれ形成されている。ドレイン電極12dが一面側の主電極に相当し、ソース電極12sが裏面側の主電極に相当する。
 半導体チップ12H,12Lは、互いにほぼ同じ平面形状、詳しくは平面略矩形状をなすとともに、互いにほぼ同じ大きさ、厚みを有している。半導体チップ12の厚みは、たとえば100μm程度とされている。半導体チップ12H,12Lは、互いに同じ構成となっている。半導体チップ12H,12Lは、ドレイン電極12dがZ方向において同じ側となり、ソース電極12sがZ方向における同じ側となるように配置されている。半導体チップ12H,12Lは、Z方向においてほぼ同じ高さに位置するとともに、X方向に横並びで配置されている。
 図5及び図6に示すように、半導体チップ12の裏面、すなわちソース電極形成面には、信号用の電極であるパッド12pが形成されている。パッド12pは、裏面においてソース電極12sとは別の位置に形成されている。パッド12pは、Y方向において、ソース電極12sの形成領域とは反対側の端部に形成されている。
 本実施形態では、半導体チップ12が、5つのパッド12pをそれぞれ有している。詳しくは、5つのパッド12pとして、ゲート電極用、ソース電極12sの電位検出用、電流センス用、半導体チップ12の温度を検出する温度センサ(感温ダイオード)のアノード電位用、同じくカソード電位用を有している。5つのパッド12pは、平面略矩形状の半導体チップ12において、Y方向の一端側にまとめて形成されるとともに、X方向に並んで形成されている。
 封止樹脂体14は、半導体チップ12を封止している。封止樹脂体14は、たとえばエポキシ系樹脂からなる。封止樹脂体14は、たとえばトランスファモールド法により成形されている。図2及び図3に示すように、封止樹脂体14は、Z方向において、一面14aと、一面14aと反対の裏面14bを有している。一面14aはドレイン電極12d側の面であり、裏面14bはソース電極12s側の面である。一面14a及び裏面14bは、たとえば平坦面となっている。本実施形態では、封止樹脂体14が、平面略矩形状をなしている。
 第1ヒートシンク16は、半導体チップ12の一面側、すなわちドレイン電極12d側に配置されている。第1ヒートシンク16は、対応する半導体チップ12の熱を半導体装置10の外部に放熱する機能とともに、主電極の配線としての機能も果たす。このため、熱伝導性及び電気伝導性を確保すべく、CuやAlなどの金属材料を用いて形成されている。本実施形態では、第1ヒートシンク16がCuを用いて形成されており、その厚みが2mm程度とされている。また、第1ヒートシンク16は、図3~図5に示すように、半導体チップ12Hに対応する第1ヒートシンク16Hと、半導体チップ12Lに対応する第1ヒートシンク16Lを有している。
 第1ヒートシンク16は、Z方向からの投影視において、対応する半導体チップ12を内包するように設けられている。第1ヒートシンク16は、対応する半導体チップ12のドレイン電極12dと、はんだ18を介して接続されている。第1ヒートシンク16のそれぞれの大部分は封止樹脂体14によって覆われている。第1ヒートシンク16の表面のうち、実装面16aにはんだ18が接続されている。実装面16aとは反対の放熱面16bは、封止樹脂体14から露出されている。放熱面16bは、一面14aと略面一となっている。
 詳しくは、第1ヒートシンク16Hの実装面16aに、半導体チップ12Hのドレイン電極12dが、はんだ18を介して接続されている。また、第1ヒートシンク16Lの実装面16aに、半導体チップ12Lのドレイン電極12dが、はんだ18を介して接続されている。第1ヒートシンク16H,16Lは、X方向に並んで配置されるとともに、Z方向においてほぼ同じ位置に配置されている。第1ヒートシンク16H,16Lの放熱面16bは、封止樹脂体14の一面14aから露出されるとともに、互いにX方向に並んでいる。
 ターミナル20は、半導体チップ12と第2ヒートシンク24との間に介在し、半導体チップ12と第2ヒートシンク24を電気的に中継する。ターミナル20は、半導体チップ12と第2ヒートシンク24との熱伝導、電気伝導経路の途中に位置するため、熱伝導性及び電気伝導性を確保すべく、少なくとも金属材料を用いて形成されている。ターミナル20は、ソース電極12sに対向配置され、はんだ22を介してソース電極12sと接続されている。ターミナル20は、半導体チップ12ごとに設けられている。すなわち、半導体装置10が、2つのターミナル20を備えている。ターミナル20のひとつは、半導体チップ12Hと第2ヒートシンク24Hとの間に介在し、ターミナル20の別のひとつは、半導体チップ12Lと第2ヒートシンク24Lとの間に介在している。ターミナル20の詳細については、後述する。
 第2ヒートシンク24も、第1ヒートシンク16同様、対応する半導体チップ12の熱を半導体装置10の外部に放熱する機能とともに、主電極の配線としての機能を果たす。第2ヒートシンク24は、半導体チップ12のソース電極12s側に配置されている。第2ヒートシンク24は、第1ヒートシンク16との間に半導体チップ12を挟むように配置されている。第1ヒートシンク16及び第2ヒートシンク24が、一対のヒートシンクに相当する。以下において、第1ヒートシンク16及び第2ヒートシンク24を、ヒートシンク16,24とも称する。
 第2ヒートシンク24も、CuやAlなどの金属材料を用いて形成されている。本実施形態では、第2ヒートシンク24がCuを用いて形成されており、その厚みが2mm程度とされている。また、第2ヒートシンク24は、図3、図7、及び図8に示すように、半導体チップ12Hに対応する第2ヒートシンク24Hと、半導体チップ12Lに対応する第2ヒートシンク24Lを有している。
 第2ヒートシンク24は、Z方向からの投影視において、対応する半導体チップ12を内包するように設けられている。第2ヒートシンク24は、対応する半導体チップ12のソース電極12sと電気的に接続されている。第2ヒートシンク24は、対応するソース電極12sと、はんだ22、ターミナル20、及びはんだ26を介して、電気的に接続されている。第2ヒートシンク24のそれぞれの大部分は封止樹脂体14によって覆われている。第2ヒートシンク24の表面のうち、実装面24aにはんだ26が接続されており、実装面24aとは反対の放熱面24bが封止樹脂体14から露出されている。放熱面24bは、裏面14bと略面一となっている。はんだ18,22,26が、接合部材に相当する。
 詳しくは、第2ヒートシンク24Hの実装面24aに、半導体チップ12Hに対応するターミナル20が、はんだ26を介して接続されている。第2ヒートシンク24Lの実装面24aに、半導体チップ12Lに対応するターミナル20が、はんだ26を介して接続されている。第2ヒートシンク24H,24Lは、X方向に並んで配置されるとともに、Z方向においてほぼ同じ位置に配置されている。そして、第2ヒートシンク24H,24Lの放熱面24bが、封止樹脂体14の裏面14bから露出されるとともに、互いにX方向に並んでいる。
 継手部28は、第1継手部28a、第2継手部28b、及び第3継手部28cを有している。第1継手部28a及び第3継手部28cは、上アーム側の第2ヒートシンク24Hと、下アーム側の第1ヒートシンク16Lとを電気的に接続している。第2継手部28bは、下アーム側の第2ヒートシンク24Lと負極端子32nとを電気的に接続している。
 本実施形態では、第1継手部28aが、同一の金属板を加工することで第2ヒートシンク24Hと一体的に設けられている。第2継手部28bは、同一の金属板を加工することで第2ヒートシンク24Lと一体的に設けられている。そして、第1継手部28aを含む第2ヒートシンク24Hと、第2継手部28bを含む第2ヒートシンク24Lとを共通部材としており、半導体装置10においてこれらの配置は、Z軸を回転軸とする2回対称となっている。
 第1継手部28aは、封止樹脂体14に被覆されるように、第2ヒートシンク24Hよりも薄く設けられている。第1継手部28aは、第2ヒートシンク24Hの実装面24aと略面一となるように、第2ヒートシンク24Hに連なっている。第1継手部28aは、第2ヒートシンク24Hにおける第2ヒートシンク24L側の側面24cからX方向に延びている。第1継手部28aにおいて、第2ヒートシンク24Hの実装面24aに連なる面には、はんだ30を介して第3継手部28cが接続されている。
 第2継手部28bも、第1継手部28a同様の構成となっている。第2継手部28bにおいて、第2ヒートシンク24Lの実装面24aに連なる面には、はんだ30を介して負極端子32nが接続されている。なお、第1継手部28a及び第2継手部28bそれぞれの実装面24aに連なる面には、溢れたはんだ30を吸収するための溝が形成されている。溝は、環状に形成されている。
 第3継手部28cも、同一の金属板を加工することで第1ヒートシンク16Lと一体的に設けられている。第3継手部28cは、封止樹脂体14に被覆されるように、第1ヒートシンク16Lよりも薄く設けられている。第3継手部28cは、第1ヒートシンク16Lの実装面16aに略面一で連なっている。第3継手部28cは、第1ヒートシンク16Lにおける第1ヒートシンク16H側の側面16cから、第2ヒートシンク24Hに向けて延設されている。
 第3継手部28cは、Z方向からの平面視において、X方向に延設されている。本実施形態では、図3に示すように、第3継手部28cが屈曲部を2箇所有している。第3継手部28cの先端部分は、Z方向からの投影視において、第1継手部28aと重なっている。そして、第3継手部28cと第1継手部28aとが、はんだ30を介して接続されている。第3継手部28cは、Y方向において、第2継手部28bと横並びとなるように設けられている。
 なお、第1継手部28aを、第2ヒートシンク24Hとは別部材とし、第2ヒートシンク24Hに接続することで第2ヒートシンク24Hに連なる構成としてもよい。第2継手部28bを、第2ヒートシンク24Lとは別部材とし、第2ヒートシンク24Lに接続することで第2ヒートシンク24Lに連なる構成としてもよい。また、第3継手部28cを、第1ヒートシンク16Lとは別部材とし、第1ヒートシンク16Lに接続することで第1ヒートシンク16Lに連なる構成としてもよい。第1継手部28a及び第3継手部28cの一方のみにより、上アームと下アームとを電気的に接続することもできる。
 電源端子32は、正極端子32pと、負極端子32nを有している。正極端子32pは、平滑コンデンサ4の正極側端子と電気的に接続される。正極端子32pは、主電流が流れる主端子である。正極端子32pは、高電位電源端子、P端子とも称される。図4に示すように、正極端子32pは、第1ヒートシンク16Hに連なっており、第1ヒートシンク16Hの側面のうち、信号端子36側の面とは反対の面からY方向に延設されている。
 本実施形態では、正極端子32pが、同一の金属板を加工することで第1ヒートシンク16Hと一体的に設けられている。正極端子32pは、第1ヒートシンク16HにおけるY方向の一端に連なっている。正極端子32pは、Y方向に延設され、図2に示すように、封止樹脂体14の側面14cから外部に突出している。
 負極端子32nは、平滑コンデンサ4の負極側端子と電気的に接続される。負極端子32nは、主電流が流れる主端子である。負極端子32nは、低電位電源端子、N端子とも称される。負極端子32nは、その一部が、Z方向からの投影視において第2継手部28bと重なるように配置されている。負極端子32nは、Z方向において、第2継手部28bよりも半導体チップ12に近い位置に配置されている。負極端子32nと第2継手部28bも、はんだ30を介して接続されている。負極端子32nは、Y方向に延設されて、正極端子32pと同じ側面14cから外部に突出している。
 出力端子34は、上下アームの接続点と電気的に接続される。出力端子34は、モータ3の対応する相のコイル(固定子巻線)と電気的に接続される。出力端子34は、交流端子、O端子とも称される。図4に示すように、出力端子34は、第1ヒートシンク16Lに連なっており、第1ヒートシンク16Lの側面のうち、信号端子36側の面とは反対の面から、Y方向であって正極端子32pと同じ側に延設されている。
 本実施形態では、出力端子34が、同一の金属板を加工することで、第1ヒートシンク16Lと一体的に設けられている。出力端子34は、第1ヒートシンク16LにおけるY方向の一端に連なっている。出力端子34は、Y方向に延設されて、正極端子32p及び負極端子32nと同じ側面14cから、封止樹脂体14の外に突出している。
 正極端子32p、負極端子32n、及び出力端子34それぞれの封止樹脂体14からの突出部分は、Z方向において互いにほぼ同じ位置に配置されている。また、X方向において、正極端子32p、負極端子32n、及び出力端子34の順に並んで配置されている。このように、正極端子32pの隣りに、負極端子32nが配置されている。
 電源端子32及び出力端子34は、主電流が流れるため主端子とも称される。電源端子32及び出力端子34には、図示しないバスバーが接続される。バスバーは、たとえばレーザ溶接により、対応する電源端子32、出力端子34と接続される。本実施形態では、バスバーなどとの接続性を考慮し、封止樹脂体14からの突出部分の延設長さが3本の電源端子32及び出力端子34で互いに異なり、出力端子34が最も長くされ、負極端子32nが最も短くされている。また、突出部分の幅は、正極端子32pが最も広く、出力端子34が最も狭くされている。
 なお、正極端子32pを、第1ヒートシンク16Hとは別部材とし、第1ヒートシンク16Hに接続することで第1ヒートシンク16Hに連なる構成としてもよい。負極端子32nを、第2継手部28b、ひいては第2ヒートシンク24Lと同一の金属板から構成してもよい。出力端子34を、第1ヒートシンク16Lとは別部材とし、第1ヒートシンク16Lに接続することで第1ヒートシンク16Lに連なる構成としてもよい。
 信号端子36は、図6に示すように、対応する半導体チップ12のパッド12pに、ボンディングワイヤ38を介して電気的に接続されている。信号端子36は、Y方向に延設されており、図2に示すように、封止樹脂体14において側面14cとは反対の側面14dから外部に突出している。
 図4に示すように、本実施形態では、第1ヒートシンク16、第3継手部28c、電源端子32、出力端子34、及び信号端子36が、同一の金属板であるリードフレーム40として構成されている。リードフレーム40において、第1ヒートシンク16、及び、負極端子32nにおける第2継手部28bとの接続部分が厚肉部とされており、それ以外の部分は厚肉部よりも厚みの薄い薄肉部とされている。
 以上のように構成される半導体装置10では、封止樹脂体14により、半導体チップ12、第1ヒートシンク16それぞれの一部、ターミナル20、第2ヒートシンク24それぞれの一部、電源端子32それぞれの一部、出力端子34の一部、及び信号端子36の一部が一体的に封止されている。半導体装置10では、封止樹脂体14によって、一相分の上下アームを構成する2つの半導体チップ12が封止されている。このため、半導体装置10は、2in1パッケージとも称される。
 第1ヒートシンク16H,16Lそれぞれの放熱面16bは、同一面内に位置するとともに、封止樹脂体14の一面14aと略面一となっている。同じく、第2ヒートシンク24H,24Lそれぞれの放熱面24bは、同一面内に位置するとともに、封止樹脂体14の裏面14bと略面一となっている。このように、半導体装置10は、放熱面16b,24bがともに封止樹脂体14から露出された両面放熱構造をなしている。
 (半導体装置の製造方法)
 図2、図4~図6、及び図8に基づき、上記した半導体装置10の製造方法の一例について説明する。なお、図2、図4~図6、及び図8は、製品状態のリードフレーム40を示している。リードフレーム40は、以下に示す製造工程において、不要部分の除去がなされるまで、図示しない外枠やタイバーを有している。
 先ず、半導体装置10を構成する各要素を準備する。たとえば図4に示すリードフレーム40を準備する。また、半導体チップ12、ターミナル20、第2ヒートシンク24をそれぞれ準備する。
 次いで、図5に示すように、リードフレーム40における第1ヒートシンク16H,16Lの実装面16a上に、はんだ18を介して、対応する半導体チップ12H,12Lを配置する。その際、ドレイン電極12dが実装面16aと対向するように、半導体チップ12H,12Lを配置する。
 次に、たとえば予め両面にはんだ22,26が迎えはんだとして配置されたターミナル20を、はんだ22が半導体チップ12側となるように配置する。はんだ26については、半導体装置10における高さばらつきを吸収可能な量、配置しておく。また、第3継手部28c及び負極端子32n上にはんだ30を配置しておく。
 そして、この積層状態で、はんだの1stリフローを実施する。これにより、はんだ18を介して、半導体チップ12のドレイン電極12dと対応する第1ヒートシンク16とが接続される。また、はんだ22を介して、半導体チップ12のソース電極12sと対応するターミナル20とが接続される。すなわち、図6に示すように、リードフレーム40、半導体チップ12、及びターミナル20が一体化された接続体を得ることができる。リフロー後、半導体チップ12のパッド12pと信号端子36を、ボンディングワイヤ38により接続する。
 次いで、実装面24aが上になるようにして第2ヒートシンク24を図示しない台座上に配置する。そして、ターミナル20が第2ヒートシンク24に対向するように、接続体を第2ヒートシンク24上に配置し、はんだの2ndリフローを実施する。2ndリフローでは、第1ヒートシンク16側から荷重を加えることで、半導体装置10の高さが所定高さとなるようにする。図8は、2ndリフロー後の状態を示している。
 次いで、トランスファモールド法により封止樹脂体14の成形を行う。本実施形態では、第1ヒートシンク16及び第2ヒートシンク24が完全に被覆されるように、封止樹脂体14を成形する。なお、成形の前に、第1ヒートシンク16、半導体チップ12、及びターミナル20などの封止樹脂体14と接触する表面部分に、たとえばポリアミド樹脂を塗布しておくと、封止樹脂体14との密着力を向上することができる。
 次いで、成形した封止樹脂体14を第1ヒートシンク16の一部ごと切削することにより、第1ヒートシンク16の放熱面16bを露出させる。これにより、放熱面16bは一面14aと略面一となる。同じく、封止樹脂体14を第2ヒートシンク24の一部ごと切削することにより、第2ヒートシンク24の放熱面24bを露出させる。これにより、放熱面24bは裏面14bと略面一となる。
 なお、放熱面16b,24bを成形金型のキャビティ壁面に押し当て、密着させた状態で、封止樹脂体14を成形してもよい。この場合、封止樹脂体14を成形した時点で、放熱面16b,24bが封止樹脂体14から露出される。このため、成形後の切削が不要となる。
 次いで、外枠やタイバーなど、リードフレーム40の不要部分を除去する。これにより、図2に示す半導体装置10を得ることができる。
 (ターミナル詳細)
 ターミナル20は、複数種類の金属層を積層してなる。積層方向において隣り合う金属層は接合されている。ここで、異なる種類とは、構成する金属が互いに異なってもよいし、線膨張係数が互いに異なってもよい。たとえば線膨張係数が同じでも、構成する金属が異なれば、異なる種類である。複数種類の金属層は、Z方向及びZ方向に直交する方向の少なくとも1方向において線膨張係数が互いに異なり、且つ、それぞれの線膨張係数が、半導体チップ12以上、第2ヒートシンク24以下の範囲内とされるとよい。ターミナル20全体の線膨張係数を、半導体チップ12と第2ヒートシンク24との間に調整しやすくなる。なお、Z方向に直交する方向とは、XY面に沿う方向、すなわちX方向及びY方向である。なお、SiCの線膨張係数は4×10-6/K程度、Cuは17×10-6/K程度である。
 本実施形態では、ターミナル20として、第1の金属からなる金属層と、第1の金属を含む合金層を備えたクラッド材を採用している。詳しくは、図9に示すように、Cu層20aと、Cuを含む合金層20bを備えたクラッド材を採用している。クラッド材は、接合材を用いない分子拡散による接合であるため、従来の積層型に較べて層間の接続信頼性を向上することができる。本実施形態では、すべての層が同一の金属(Cu)を含むため、接続信頼性を向上することができる。さらには、ターミナルすべてを合金層とする構成に較べて、放熱性の低下を抑制することができる。
 Cu層20aは、放熱性、熱伝導性に優れるものの、線膨張係数がSiCに較べて大きい。Cu層20aの線膨張係数は、第2ヒートシンク24と同じである。合金層20bは、Cuとともに、Cuよりも線膨張係数が小さい金属材料を含んでいる。合金層20bは、少なくともZ方向に直交する方向の線膨張係数がCuよりも小さい。本実施形態では、合金層20bがCrを含んでいる。Crを用いると、線膨張係数を小さくできるとともに、ターミナル20を安価で軽量に構成することもできる。
 Crを含む合金層20bは、たとえばCrにCuを含浸させたものを圧延することで構成されている。圧延において、圧下率に対する圧延方向及び圧延方向に直交する方向の線膨張係数はそれぞれ異なる振舞いをする。これは、圧延方向に扁平なCrにCuの熱膨張が拘束される際、圧延方向と直交方向で応力の働き方が異なるためである。なお、圧下率とは、被圧延材の板厚減少率である。
 圧延方向については圧下率の増加とともに線膨張係数が減少し続け、たとえば50質量%のCr-Cu圧延材では、圧下率70%程度でほぼ一定となる。直交方向も同様に圧下率の増加とともに線膨張係数が減少し続けるが、圧下率に対する減少幅は圧延方向よりも小さい。そしてたとえば50質量%のCr-Cu圧延材では、圧下率98%まで圧延しても線膨張係数は減少し続け、圧延方向の線膨張係数に近づいていく。
 本実施形態では、接合部への熱応力の発生に大きく寄与する圧延方向の線膨張係数が圧下率に対してほぼ一定となるCr-Cu圧延材、たとえば50質量%のCr-Cu圧延材では70%以上まで圧下したCr-Cu圧延材を用いたクラッド材によって、ターミナル20を構成している。なお、合金層20b(Cr-Cu圧延材)では、X方向及びY方向が圧延方向であり、これにより、Z方向に直交する方向、すなわちX方向及びY方向で同じ線膨張係数となっている。Z方向の線膨張係数は、X方向及びY方向よりも大きく、本実施形態ではCuよりも小さくなっている。
 ターミナル20は、合金層20bによってCu層20aの熱膨張が拘束され、単純にCuとCr-Cu合金を粉末同士で複合するよりも、線膨張係数の抑制効果が高い。このような積層構造により、Z方向に直交する方向の線膨張係数は、ターミナル20全体として、半導体チップ12と第2ヒートシンク24との間の値、たとえば12~13×10-6/K程度とされている。したがって、半導体チップ12とターミナル20を接続するはんだ22に作用する熱応力を小さくすることができる。
 また、線膨張係数を小さく保ちながら、Cu層20aによって高い熱拡散効果を得ることができる。したがって、半導体装置10の放熱性を損なうことなく、はんだ18,22に作用する熱応力を小さくすることができる。特に、合金層20bのほうがCu層20aよりも薄いため、合金層20bを用いつつ放熱効果を高めることができる。
 さらに、Cu層20aと合金層20bとが、Z方向において対称配置されている。具体的には、図9に示すように、ターミナル20におけるZ方向の中心線CLに対し、線対称配置とされている。層数を奇数である5となるように、Cu層20aと合金層20bとが交互に配置されている。Cu層20a同士は互いに厚みがほぼ等しく、合金層20b同士は互いに厚みがほぼ等しくされている。
 このようにZ方向の対称性が高いため、ターミナル20を構成する金属層の線膨張係数差に基づいて、ターミナル20に反りが生じるのを抑制することができる。すなわち、はんだ18,22,26に作用する応力を低減することができる。なお、ターミナル20は平面矩形状とされ、Z方向の投影視において、Cu層20aと合金層20bとの形状が略一致している。このため、ターミナル20は、Z方向に直交する方向においても対称性が高く、これによっても反りを抑制することができる。
 また、Cu層20a、合金層20b、Cu層20a、合金層20b、Cu層20aの順に積層されている。このように、合金層20bよりも濡れ性の高いCu層20aが表層に配置されている。また、ターミナル20の側面には、Cu層20aよりも濡れ性の低い合金層20bが現れる。これにより、はんだ22,26との接合性を確保しつつ、ターミナル20の側面へのはんだの這い上がりを抑制することができる。
 (半導体装置の効果)
 本実施形態では、両面放熱構造の半導体装置10において、半導体チップ12にSiC(シリコンカーバイド)を採用している。SiCは、Siに較べて絶縁破壊電界やバンドギャップが大きい、熱伝導率が高い、電子飽和速度が速いといった特性を備えている。しかしながら、ヤング率はSiの約3倍と大きい。
 これに対し、本実施形態では、複数種類の金属層が積層されてターミナル20が構成されている。そして、Z方向に直交する方向における線膨張係数が、ターミナル20全体として、半導体チップ12と第2ヒートシンク24との間の値となっている。したがって、はんだ18,22,26や半導体チップ12に作用する熱応力を低減することができる。
 さらに、金属層は、Z方向において対称配置されている。これにより、ターミナル20の反りを抑制し、はんだ18,22,26や半導体チップ12に局所的な応力が作用するのを抑制することができる。以上から、本実施形態の半導体装置10は、半導体チップ12にSiCを用いた構成に好適である。
 本実施形態では、ターミナル20として、Cu層20aと、Cuを含む合金層20bが順に積層されたクラッド材を用いている。これによれば、接合材を用いた従来の積層型のターミナルに較べて、層間の接続信頼性を向上することができる。また、すべての層がCuを含むため、層間の接続信頼性を向上することができる。さらには、放熱性の低下を抑制することができる。これにより、半導体装置10の使用時において温度上昇を抑制し、熱応力を低減することができる。また、半導体装置10を構成する部材の熱劣化を抑制することができる。特に、合金層20bがCrを含むため、線膨張係数を小さくしつつ、安価で軽量に構成することができる。
 本実施形態では、ターミナル20の表層がCu層20aとされている。これにより、はんだ22,26との接続信頼性を向上することができる。また、側面には、濡れ性の低い合金層20bが現れるため、はんだ22,26の這い上がりを抑制することができる。
 ターミナル20の構成は、上記例に限定されない。Cu層20aとCrを含む合金層20bとの配置は上記例に限定されない。たとえば層数は5層に限定されない。3層以上であればよい。奇数層の場合、Z方向において対称性をもたせることが可能となる。また、偶数層としてもよい。たとえば、Cu層20a、合金層20b、Cu層20aのクラッド材を2つ積層し、Cu層20a、合金層20b、Cu層20a、Cu層20a、合金層20b、Cu層20aの6層構造としてもよい。この場合も、Z方向において対称性をもたせることが可能となる。
 たとえば図10に示す第1変形例のように、合金層20bが表層となる構成を採用してもよい。図10では、合金層20b、Cu層20a、合金層20b、Cu層20a、合金層20bの順に積層されている。線膨張係数が大きいCu層20aから小さい合金層20bへの伝熱よりも、小さい合金層20bから大きいCu層20aへの伝熱のほうが、熱伝導の障壁が小さい。図10では、5層構造を採用しつつ、Cu層20aより合金層20bのほうが層数が多いため、図9に示す構成より放熱性を向上することができる。
 図11に示す第2変形例のように、表層のCu層20cの厚みを、内層のCu層20aや合金層20bより薄くしてもよい。たとえば、Cu層20cを30μm程度、Cu層20aを1mm程度、合金層20bのそれぞれを500μm程度としてもよい。Cu層20a及び合金層20bにより線膨張係数や放熱性が調整され、Cu層20cは接合性向上のために設けられている。
 Crに代えて、Moなどの線膨張係数が小さい金属材料を用いてもよい。また、Cuに代えて、Alなどの熱伝導に優れた材料を用いてもよい。たとえば図12に示す第3変形例のように、ターミナル20として、Cu層20a、Crを含む合金層20b、及びMoを含む合金層20d(Mo-Cu合金)のクラッド材を用いてもよい。図12では、Cu層20a、合金層20b、Cu層20a、合金層20d、Cu層20aの順に積層されている。Z方向において対称配置されていないが、合金層20b,20d同士の線膨張係数を近づける、好ましくはほぼ一致させることで、ターミナル20の反りを抑制することができる。すなわち、Z方向において線膨張係数に対称性をもたせることで、ターミナル20の反りを抑制することができる。
 (第2実施形態)
 本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
 ソース電極12sは、AlSiなどのAlを主成分とする下地層と、はんだ22との接合強度向上、はんだ22の濡れ性向上などを目的として、下地層上に形成された上地層を有している。上地層は、NiPなどのNiを主成分とする材料を用いて形成されている。Niは、Alよりも硬い金属材料である。この構造では、はんだ接合された状態で、パワーサイクル等の応力により、下地層において、上地層の端面の直下部分に応力が集中する。特に本実施形態では、半導体チップ12として、ヤング率の大きいSiCを採用している。
 これに対し、本実施形態では、ターミナル20における半導体チップ12との対向面が、はんだ22に対する濡れ性が良好な部分と、良好な部分よりも濡れ性が低い部分を有している。図13に示す例では、表層の薄いCu層20cのうち、半導体チップ12側のCu層20cの一部分がエッチングによって除去され、対向面の中央領域のみに配置されている。Cu層20cを取り囲む外周領域は、Cu層20cの直下の合金層20bが露出している。
 合金層20bの濡れ性はCu層20a,20cよりも低いため、はんだ22は、ターミナル20の対向面の外周領域に配置された合金層20b上を濡れ拡がっても、外周領域を含むようにフィレットが形成されない。したがって、ソース電極12sとはんだ22とのなす角、すなわちフィレット角を鋭角にすることができる。これにより、下地層において、上地層の端面の直下部分に集中する応力を低減することができる。また、クラッド材を用意し、表層の一部を除去するだけであるので、構成を簡素化することができる。なお、図13に示す破線は、対向面の全面にCu層20cを配置した場合のフィレットを示す参考線である。
 ターミナル20の構成は、上記例に限定されない。図13に示す例では、Cu層20cをエッチングすることで、ターミナル20における半導体チップ12との対向面において、部分的に濡れの悪い部分を設け、フィレット角を制御する例を示した。しかしながら、スパッタなどにより、濡れ性の良い膜を局所的に設けてもよい。また、合金層20bに代えて、Moを含む合金層20dを露出させ、濡れの悪い部分としてもよい。また、ターミナル20における第2ヒートシンク24との対向面において、合金層20b,20dを一部露出させ、濡れの悪い部分としてもよい。
 (第3実施形態)
 本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
 ヒートシンク16,24の少なくとも1つに、クラッド材を用いてもよい。図14に示す例では、第1ヒートシンク16及び第2ヒートシンク24のそれぞれに、クラッド材を用いている。ターミナル20は、第1実施形態(図9参照)と同じ構成となっている。図14は、図2に示すXIV-XIV線に沿う断面図である。
 第2ヒートシンク24Hは、図示しない第1継手部28aを含めて、クラッド材を採用している。第1継手部28aを含む第2ヒートシンク24Hは、Cu層24dと、CuとCrを含む合金層24eとを交互に積層してなり、Cu層24dを3層、合金層24eを2層有している。このように、第2ヒートシンク24Hは、ターミナル20と同様に構成されている。なお、第2ヒートシンク24Lについても同様である。
 リードフレーム40において、正極端子32p及び信号端子36と、図示しない負極端子32n、出力端子34、及び第3継手部28cと、第1ヒートシンク16の一部分は、Cuよりなる基材41によって構成されている。すなわち、リードフレーム40の薄肉部は、基材41によって構成されている。リードフレーム40の厚肉部は、クラッド材42を含んで構成されている。
 クラッド材42は、Cu層16dと、CuとCrを含む合金層16eとを交互に積層してなる。そして、基材41とクラッド材42により、図14に示す第1ヒートシンク16が形成されている。第1ヒートシンク16は、基材41とクラッド材42により、3層のCu層16dと2層の合金層16eとの積層構造をなしている。
 このように、本実施形態では、第2ヒートシンク24もクラッド材を用いて構成されている。これにより、第2ヒートシンク24において、放熱性の低下を抑制しつつ、Z方向に直交する方向、すなわちX方向及びY方向の線膨張係数を小さくすることができる。換言すれば、ターミナル20との線膨張係数差の差を小さくする、若しくは、略一致させることができる。したがって、第2ヒートシンク24とターミナル20との間のはんだ26に作用する熱応力を低減することができる。また、Cu層24dが実装面24a側の面を構成するため、はんだ26,30との接続性を向上することができる。
 本実施形態では、第1ヒートシンク16もクラッド材を用いて構成されている。これにより、第1ヒートシンク16において、放熱性の低下を抑制しつつ、Z方向に直交する方向の線膨張係数を小さくすることができる。したがって、第1ヒートシンク16と半導体チップ12との間のはんだ18に作用する熱応力を低減することができる。
 特に、本実施形態では、ヒートシンク16,24がともにクラッド材を含み、Z方向に直交する方向において、第1ヒートシンク16全体の線膨張係数と、第2ヒートシンク24全体の線膨張係数が互いにほぼ同じ値を有している。したがって、半導体装置10の反りを抑制することができる。また、Cuからなる基材41を用いるため、はんだ18、ボンディングワイヤ38、バスバーなどとの接続性を向上することができる。
 なお、ヒートシンク16,24へのクラッド材の適用は上記例に限定されない。第1ヒートシンク16のみがクラッド材を含む構成としてもよい。また、第2ヒートシンク24のみがクラッド材を含む構成としてもよい。しかしながら、上記したように、ヒートシンク16,24がともにクラッド材を含む構成とするとよい。
 図14に示す例とはクラッド材の構成を異ならせてもよい。ターミナル20とは異なる構成としてもよい。
 たとえば第1ヒートシンク16を含むリードフレーム40を、第2ヒートシンク24H同様、クラッド材のみによって構成してもよい。この場合、正極端子32pや信号端子36も、Cu層16dと合金層16eとの積層構造となる。表層をCu層16dとした場合、はんだ18、ボンディングワイヤ38、バスバーなどとの接続性を向上することができる。
 第2ヒートシンク24を、上記したリードフレーム40(第1ヒートシンク16)同様の構成としてもよい。すなわち、第1継手部28aをCuからなる基材にて構成し、第2ヒートシンク24を、基材とクラッド材にて構成してもよい。基材が実装面16a側の面を構成するため、はんだ26,30との接続性を向上することができる。
 図15に示す第4変形例のように、合金層24eが放熱面24bをなす構成としてもよい。また、合金層16eが放熱面16bをなす構成としてもよい。たとえば合金層24eの途中に切削ラインを設けることで、合金層24eが放熱面24bをなす。また、合金層16eの途中に切削ラインを設けることで、合金層16eが放熱面16bをなす。Crは、MoやCuに較べて切削性に優れるため、Crを含む合金層16e,24eに切削ラインを設けると、放熱面16b,24bを露出させる際の切削性を向上することができる。
 図示を省略するが、合金層24eが実装面24aをなすように、第2ヒートシンク24を構成してもよい。たとえば図10に示したターミナル20同様、Cu層24dより合金層24eが多い構成とすることで、放熱性を向上することができる。図示を省略するが、第1ヒートシンク16についても同様である。すなわち、合金層16eが、第1ヒートシンク16の実装面16aをなすように、クラッド材42を含むリードフレーム40を構成してもよい。
 Crを含む合金層16e,24eに代えて、CuとMoを含む合金層を採用してもよい。これによっても、ヒートシンク16,24の線膨張係数を小さくすることができる。
 ヒートシンク16,24をクラッド材のみによって構成し、正極端子32pや第1継手部28aなど、ヒートシンク16,24に連なる部分をCuからなる薄板にて構成してもよい。この場合、拡散接合、レーザ溶接、かしめなどによって、薄板とクラッド材を接続すればよい。
 ターミナル20にクラッド材を用いない構成、たとえばターミナル20がCuからなる構成において、第2ヒートシンク24にクラッド材を用いてもよい。この場合にも、合金層24eを放熱面24bとすることで、切削性を向上することができる。
 ターミナル20及び第2ヒートシンク24にクラッド材を用いない構成において、第1ヒートシンク16にクラッド材を用いてもよい。半導体チップ12との線膨張係数の差を低減し、半導体チップ12と第1ヒートシンク16との間のはんだ18に作用する熱応力を低減することができる。また、合金層16eを放熱面16bとすると、切削性を向上することができる。
 (第4実施形態)
 本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置10と共通する部分についての説明は省略する。
 本実施形態では、はんだ18,22,26の少なくとも1つとして、以下に規定する鉛フリーはんだを用いている。この鉛フリーはんだは、先行実施形態及び変形例のいずれとも組み合わせが可能である。
 鉛フリーはんだは、Agを3.2~3.8質量%、Cuを0.6~0.8質量%、Niを0.01~0.2質量%含み、さらにSbとBiを含んでいる。
 Agの添加には、はんだの濡れ性向上や析出分散強化の効果がある。その反面、液相線温度が上昇する。半導体チップ12(SiC)の耐熱性を考慮すると、はんだ付け時に温度を300℃以下に抑えることが好ましい。したがって、濡れ性向上、析出分散の効果を十分に得つつ、ばらつきも考慮して液相線温度を270℃以下に抑えるために、Agの含有量は3.2~3.8質量%とされている。
 Cuの添加には、Cuランドに対するCuの食われ防止、はんだマトリックス中に微細な金属間化合物であるCuSnを析出させてマトリックスを強化する効果がある。過剰に添加すると、接合界面に金属間化合物が析出し、クラック進展を加速してしまう。このため、Cu含有量は0.6~0.8質量%とされている。
 Niの添加には、接合界面に析出する金属間化合物を微細化することで、接合界面を強化する効果がある。その反面、液相線温度が上昇する。接合界面強化効果を十分に得つつ、液相線温度を上記した270℃以下に抑えるため、Niの含有量は0.01~0.2質量%とされている。
 Sbの添加には、固溶析出強化や析出分散強化の効果があり、Snに対してSbが置換されることで格子歪を起こし、Snマトリックス強化の効果がある。Sbよりも原子半径の大きいBiは、Snマトリックス強化においてSb以上の効果を発揮する。反面、SbやBiを過剰に含むと、濡れ性や箔への加工性が低下する。
 SbやBiの添加にともなうSnマトリックス強化の効果によって、クリープ耐性が増加する。すなわち、クリープを低く抑えることができる。
 また、半導体装置10を製造する際、はんだ付け後のモールド工程などで、はんだの接続信頼性を維持するため、固相線温度が200℃以上であることが好ましい。SbとBiの添加量は、上記した効果を考慮して調整されている。
 以上を満たす鉛フリーはんだは、使用環境の高温化に対応しながら、はんだによる接合部を高寿命化するだけでなく、クリープによる半導体チップの一部への不要な応力集中を低減することが可能になる。したがって、高温動作が可能であり、ヤング率が大きいSiC基板からなる半導体チップ12に好適である。
 特に上記した鉛フリーはんだを、はんだ26に用いるとよい。先行実施形態に示したターミナル20を用いることではんだ22に作用する熱応力が増加しても、高い接続信頼性を維持することができる。
 また、上記した鉛フリーはんだを、はんだ18に用いるとよい。半導体チップ12と第1ヒートシンク16との線膨張係数差に基づく熱応力が作用しても、高い接続信頼性を維持することができる。
 また、半導体チップ12のヤング率が大きいため、パワーサイクル試験を実施すると、半導体チップ12周辺のはんだ18,22がクリープし、サイクル数の増加にともなってはんだクラック等が懸念される。これに対し、上記した鉛フリーはんだを用いることで、はんだ18,22のクリープを抑制することができる。
 上記した鉛フリーはんだは、耐クリープ性に優れるなどの特性をもつため、ターミナル20、ヒートシンク16,24の構成に関わらず、半導体装置10全体の高寿命化に効果的である。したがって各部品にクラッド材を用いない構成において、鉛フリーはんだをはんだ18,22,26の少なくとも1つに使用してもよい。
 図16は、はんだ歪のシミュレーション結果を示している。図16は、ターミナル20、ヒートシンク16,24にクラッド材を用いない構成の結果を示している。素子下とは、半導体チップ12の直下のはんだ18、素子上とは、半導体チップ12の直上のはんだ22、TML上とは、ターミナル20上のはんだ26を示している。比較例1(図中、比1)は、Si基板を用いた半導体チップにおいて、従来構成のはんだを用いた構成の結果を示している。比較例2(図中、比2)は、比較例1のSi基板をSiC基板に置き換えた構成の結果を示している。実施例(図中、実)は、比較例2に対し、はんだを上記した鉛フリーはんだに置き換えた構成の結果を示している。
 図16に示すように、Siを、Siよりもヤング率の大きいSiCに置き換えると、半導体チップ12周辺のはんだ18,22のはんだ歪が増加する。そして、上記したPbフリーはんだを用いると、はんだ18,22のいずれもはんだ歪を小さくすることができる。このように、ターミナル20、ヒートシンク16,24にクラッド材を用いない構成においても、PBフリーはんだは好適である。
 本開示は、例示された実施形態に制限されない。本開示は、例示された実施形態と、それらに基づく当業者による変形態様を包含する。たとえば、本開示は、実施形態において示された要素の組み合わせに限定されない。開示は、多様な組み合わせによって実施可能である。開示される技術的範囲は、実施形態の記載に限定されない。開示されるいくつかの技術的範囲は、請求の範囲の記載によって示され、さらに請求の範囲の記載と均等の意味及び範囲内でのすべての変更を含むものと解されるべきである。
 半導体装置10として、上アーム側の半導体チップ12Hと下アーム側の半導体チップ12Lを備える2in1パッケージ構造の例を示したが、これに限定されない。1つのアームを構成する1つの半導体チップを備える1in1パッケージ構造や、三相分の上下アームを構成する6つの半導体チップを備える6in1パッケージ構造にも適用できる。
 ヒートシンク16,24の放熱面16b,24bが封止樹脂体14から露出される例を示したが、これに限定されない。放熱面16b,24bの少なくとも一方が封止樹脂体14によって覆われた構成としてもよい。
 半導体チップ12に形成される素子としてMOSFET6の例を示したが、これに限定されない。電力変換装置に適用される縦型素子であればよい。たとえば、IGBTやSBDにも適用できる。IGBTの場合、IGBTとFWDを1チップで構成してもよいし、別チップとしてもよい。
 封止樹脂体14との密着力向上のためにポリアミド樹脂を塗布する例を示したが、これに限定されない。塗布をしない構成にも適用できる。また、ポリアミド樹脂に代えて、レーザ加工による粗面化で密着力を高めてもよい。この場合、たとえば各部材を準備する工程においてレーザ光を照射し、粗面化すればよい。
 半導体チップ12を構成する半導体基板として、SiC基板の例を示した。しかしながら、SiC以外の、Siよりヤング率の大きい半導体基板にも適用することができる。
 第1ヒートシンク16の実装面16a、ターミナル20におけるはんだ接合面、第2ヒートシンク24の実装面24aに、めっきやスパッタなどによって、はんだとの濡れ性を高める膜を形成してもよい。Ni系の薄膜、たとえばNiPめっき膜を設けてもよい。また、ターミナル20の全面にNi系の薄膜を設けた後、レーザ光を照射することではんだの濡れ性を部分的に低下させてもよい。レーザ光の照射により、Niを主成分とし、表面が微細凹凸をなす酸化膜が形成される。この酸化膜により、濡れ性を低下させることができる。
  

 

Claims (9)

  1.  SiC基板に素子が形成され、一面及び前記一面と板厚方向において反対の裏面のそれぞれに主電極が形成された半導体チップ(12)と、
     前記板厚方向において前記半導体チップを挟むように配置された一対のヒートシンクであって、前記一面側に配置された第1ヒートシンク(16)、及び、前記裏面側に配置された第2ヒートシンク(24)と、
     前記第2ヒートシンクと前記半導体チップとの間に介在し、前記裏面側の主電極と前記第2ヒートシンクとを電気的に中継するターミナル(20)と、
     前記一面側の主電極と前記第1ヒートシンクとの間、前記裏面側の主電極と前記ターミナルとの間、前記ターミナルと前記第2ヒートシンクとの間、のそれぞれに配置された接合部材(18,22,26)と、
    を備え、
     前記ターミナルは、複数種類の金属層(20a,20b,20c,20d)が、前記板厚方向に積層されてなり、
     少なくとも前記板厚方向に直交する方向の線膨張係数が、前記ターミナルの全体として、前記半導体チップよりも大きく、前記第2ヒートシンクよりも小さい範囲内とされ、
     前記ターミナルにおいて、前記複数種類の金属層は、前記板厚方向において対称配置されている半導体装置。
  2.  前記ターミナルは、前記金属層として、Cu層と、Cuを含む合金層と、を有し、前記Cu層と前記合金層とが順に積層された3層以上のクラッド材である請求項1に記載の半導体装置。
  3.  前記板厚方向において、前記ターミナルの表層が、前記Cu層とされている請求項2に記載の半導体装置。
  4.  前記板厚方向において、前記ターミナルの表層が、前記合金層とされている請求項2に記載の半導体装置。
  5.  前記合金層は、Crを含む請求項2~4いずれか1項に記載の半導体装置。
  6.  SiC基板に素子が形成され、一面及び該一面と板厚方向において反対の裏面のそれぞれに主電極が形成された半導体チップ(12)と、
     前記板厚方向において前記半導体チップを挟むように配置された一対のヒートシンクであって、前記一面側に配置された第1ヒートシンク(16)、及び、前記裏面側に配置された第2ヒートシンク(24)と、
     前記第2ヒートシンクと前記半導体チップとの間に介在し、前記裏面側の主電極と前記第2ヒートシンクとを電気的に中継するターミナル(20)と、
     前記一面側の主電極と前記第1ヒートシンクの間、前記裏面側の主電極と前記ターミナルとの間、前記ターミナルと前記第2ヒートシンクとの間、のそれぞれに配置された接合部材(18,22,26)と、
    を備え、
     前記ターミナルは、Cu層(20a,20c)と、CuとCrを含む合金層(20b)とが、前記板厚方向に順に積層された3層以上のクラッド材であり、前記Cu層及び前記合金層は、前記板厚方向において対称配置されている半導体装置。
  7.  前記第1ヒートシンク及び前記第2ヒートシンクの少なくとも1つが、Cu層(16d,24d)と、Cuを含む合金層(16e,24e)と、を有し、前記Cu層と前記合金層とが順に積層された3層以上のクラッド材を含む請求項6に記載の半導体装置。
  8.  前記半導体チップ、前記ターミナル、前記接合部材、前記第1ヒートシンク、及び前記第2ヒートシンクを一体的に封止する封止樹脂体(14)をさらに備え、
     前記ヒートシンクの合金層は、Crを含むとともに、前記封止樹脂体の表面に対して面一で露出している請求項7に記載の半導体装置。
  9.  前記接合部材の少なくとも1つに、Agを3.2~3.8質量%、Cuを0.6~0.8質量%、Niを0.01~0.2質量%含むとともに、SbとBiを含む鉛フリーはんだを用いている請求項1~8いずれか1項に記載の半導体装置。

     
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