CN112753101A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112753101A
CN112753101A CN201980063390.8A CN201980063390A CN112753101A CN 112753101 A CN112753101 A CN 112753101A CN 201980063390 A CN201980063390 A CN 201980063390A CN 112753101 A CN112753101 A CN 112753101A
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semiconductor chip
fin
heat sink
layer
semiconductor device
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CN201980063390.8A
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CN112753101B (zh
Inventor
海津瞭一
野村匠
山岸哲人
稻叶祐树
坂本善次
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Denso Corp
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Denso Corp
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Abstract

半导体装置具备：半导体芯片(12)，在SiC基板中形成有元件，在一面及背面分别形成有主电极；配置在一面侧的第1散热片(16)及配置在背面侧的第2散热片(24)；接线部(20)，介于第2散热片与半导体芯片之间，将背面侧的主电极和第2散热片电中继；以及接合部件(18、22、26)，分别配置在一面侧的主电极与第1散热片之间、背面侧的主电极与接线部之间、接线部与第2散热片之间。接线部在板厚方向上层叠有多种金属层(20a、20b、20c、20d)，至少与板厚方向正交的方向的线膨胀系数被设为比半导体芯片大且比第2散热片小的范围内；在接线部中，多种金属层在板厚方向上对称配置。

Description

半导体装置
关联申请的相互参照
本申请基于2018年10月15日提出的日本专利申请第2018－194377号，这里通过参照而引用其记载内容。
技术领域
本发明涉及半导体装置。
背景技术
在专利文献1中，提出了两面散热构造的半导体装置。该半导体装置具备半导体芯片、一对散热片(引线框)、以及接线部(散热片块)。半导体芯片在硅基板上形成有IGBT及MOSFET等元件，在一面及背面分别具有主电极。一对散热片具有配置在一面侧的第1散热片和配置在背面侧的第2散热片。接线部介于第2散热片与半导体芯片之间，进行电中继。半导体芯片与第1散热片、半导体芯片与接线部、接线部与第2散热片分别经由接合部件而被连接。
现有技术文献
专利文献
专利文献1：JP 2013－98228 A
发明内容
近年来，与Si相比，SiC具有绝缘击穿电场及带隙大、热传导率高、电子饱和速度快这样的特征从而受到关注。但是，SiC的杨氏模量为Si的约3倍，是较大的。因此，在半导体芯片从上下被散热片夹着的上述两面散热构造中，若对半导体芯片采用SiC，则有可能在接合部件或半导体芯片中产生裂纹等。
本发明的目的在于，提供在对半导体芯片采用SiC的情况下也适合的半导体装置。
根据本发明的一技术方案，半导体装置具备：半导体芯片，在SiC基板中形成有元件，在一面及在板厚方向上与该一面相反的背面分别形成有主电极；第1散热片及第2散热片，是在板厚方向上夹着半导体芯片而配置的一对散热片，第1散热片配置在一面侧，第2散热片配置在背面侧；接线部，介于第2散热片与半导体芯片之间，将背面侧的主电极和第2散热片进行电中继；以及接合部件，分别配置在一面侧的主电极与第1散热片之间、背面侧的主电极与接线部之间、接线部与第2散热片之间。接线部在板厚方向上层叠有多种金属层，作为接线部的整体，至少与板厚方向正交的方向的线膨胀系数被设为比半导体芯片大且比第2散热片小的范围内；在接线部中，多种金属层在板厚方向上对称配置。
根据本发明的一技术方案，在半导体装置中，将多种金属层层叠而构成接线部，至少与板厚方向正交的方向上的线膨胀系数为半导体芯片与第2散热片之间的值。因而，能够减小作用于各接合部件及半导体芯片的热应力。进而，金属层在Z方向上对称配置。由此，能够抑制接线部的翘曲，抑制局部应力作用于各接合部件及半导体芯片。因而，在两面散热构造的半导体装置中，本发明适合于对半导体芯片采用了SiC的结构。
根据本发明的另一技术方案，半导体装置具备：半导体芯片，在SiC基板中形成有元件，在一面及在板厚方向上与该一面相反的背面分别形成有主电极；第1散热片及第2散热片，是在板厚方向上夹着半导体芯片而配置的一对散热片，第1散热片配置在一面侧，第2散热片配置在背面侧；接线部，介于第2散热片与半导体芯片之间，将背面侧的主电极和第2散热片进行电中继；以及接合部件，分别配置在一面侧的主电极与第1散热片之间、背面侧的主电极与接线部之间、接线部与第2散热片之间。接线部是在板厚方向上依次层叠有Cu层和含有Cu及Cr的合金层的3层以上的包层体，Cu层及合金层在板厚方向上对称配置。
根据本发明的另一技术方案，在半导体装置中，作为接线部而使用Cu层与含有Cu及Cr的合金层的包层体。通过包括该合金层，Cu层的向与板厚方向正交的方向的膨胀被约束，作为接线部整体，能够减小上述正交的方向的线膨胀系数。因而，能够减小作用于各接合部件及半导体芯片的热应力。进而，Cu层及合金层在板厚方向上对称配置。由此，能够抑制接线部的翘曲，抑制局部应力作用于各接合部件及半导体芯片。因而，在两面散热构造的半导体装置中，本发明适合于对半导体芯片采用了SiC的结构。
附图说明
关于本发明的上述目的及其他目的、特征及优点，一边参照附图一边通过下述详细的记述会更加明确。
图1是表示应用了第1实施方式的半导体装置的电力变换装置的结构的图。
图2是表示半导体装置的立体图。
图3是沿着图2的III－III线的剖视图。
图4是表示包含第1散热片的引线框的立体图。
图5是表示配置了半导体芯片的状态的立体图。
图6是表示配置了接线部的状态的立体图。
图7是表示第2散热片的立体图。
图8是表示配置了第2散热片的状态的立体图。
图9是表示接线部的详细构造的剖视图。
图10是表示第1变形例的剖视图，对应于图9。
图11是表示第2变形例的剖视图，对应于图9。
图12是表示第3变形例的剖视图，对应于图9。
图13是针对第2实施方式的半导体装置而表示接线部周边的剖视图。
图14是表示第3实施方式的半导体装置的剖视图，对应于图2的XIV－XIV线。
图15是表示第4变形例的剖视图。
图16是针对应用于第4实施方式的半导体装置的无铅钎焊部而表示钎焊部应变的模拟结果的图。
具体实施方式
一边参照附图一边说明多个实施方式及变形例。在多个实施方式及变形例中，对于在功能上及/或构造上对应的部分赋予相同的标号。以下，将半导体芯片的板厚方向表示为Z方向，将与Z方向正交且半导体芯片的排列方向表示为X方向。此外，将与Z方向及X方向这两个方向正交的方向表示为Y方向。只要没有特别声明，就将进行XY面观察时的形状(沿着XY平面的形状)设为平面形状。XY面观察也可以说是Z方向的投影观察。
(第1实施方式)
以下，标号末尾的H表示是上下臂中的上臂侧的要素，末尾的L表示是下臂侧的要素。对于要素的一部分，为了使上臂及下臂明确而对末尾赋予H、L，对于其他的一部分，在上臂和下臂中采用共通标号。
(电力变换装置的结构)
图1所示的电力变换装置1例如搭载于电动汽车或混合动力汽车。电力变换装置1构成为，将从搭载于车辆的直流电源2供给的直流电压变换为三相交流，并向三相交流式的马达3输出。马达3作为车辆的行驶驱动源发挥功能。电力变换装置1也能够将由马达3发出的电力变换为直流并向直流电源2等充电。这样，电力变换装置1能够进行双向的电力变换。
电力变换装置1具备平滑电容器4和作为电力变换器的逆变器5。平滑电容器4的正极侧端子与直流电源2的高电位侧的电极即正极连接，负极侧端子与直流电源2的低电位侧的电极即负极连接。逆变器5将被输入的直流电力变换为规定频率的三相交流，并向马达3输出。逆变器5将由马达3发出的交流电力变换为直流电力。
逆变器5具备6个臂。各相的上下臂通过在平滑电容器4的正极侧端子与负极侧端子之间串联连接2个臂而成。各相的上下臂包括后述的半导体装置10。逆变器5包括3个半导体装置10。
在本实施方式中，各臂具有MOSFET6。此外，作为MOSFET6而采用n沟道型。MOSFET6中，作为主电流流过的主电极而具有漏极电极及源极电极。上臂侧的MOSFET6的漏极电极与平滑电容器4的正极侧端子连接。下臂侧的MOSFET6的源极电极与平滑电容器4的负极侧端子连接。上臂侧的MOSFET6的源极电极和下臂侧的MOSFET6的漏极电极相互连接。
电力变换装置1也可以除了上述平滑电容器4及逆变器5以外还具备将从直流电源2供给的直流电压升压的升压变换器、构成逆变器5及升压变换器的元件的驱动电路、对驱动电路输出驱动指令的控制电路等。
(半导体装置的结构)
如图2～图8所示，半导体装置10具备半导体芯片12、封固树脂体14、第1散热片16、接线部(terminal)20、第2散热片24、接合部28、电源端子32、输出端子34及信号端子36。在图4中，仅表示了半导体装置10中的包括第1散热片16的引线框(lead frame)40。在图5中，表示了对图4连接了半导体芯片12的状态。在图6中，表示了对图5连接了接线部20的状态。在图8中，表示了对图6连接了第2散热片24的状态。
半导体芯片12在SiC基板上形成元件而成。以下，也将形成有上臂侧的元件的半导体芯片12表示为半导体芯片12H，将形成有下臂侧的元件的半导体芯片12表示为半导体芯片12L。2个半导体芯片12H、12L使板厚方向为同一方向(Z方向)而配置。
形成于半导体芯片12的元件成为在Z方向上流过电流的纵型构造。在本实施方式中，作为元件，如上述那样形成有n沟道型的MOSFET。如图3所示，在半导体芯片12的板厚方向即Z方向上，在半导体芯片12的一面分别形成有漏极电极12d，在与一面相反的背面分别形成有源极电极12s。漏极电极12d相当于一面侧的主电极，源极电极12s相当于背面侧的主电极。
半导体芯片12H、12L为相互大致相同的平面形状，详细地讲平面形状大致为矩形，并且具有相互大致相同的大小、厚度。半导体芯片12的厚度例如为100μm左右。半导体芯片12H、12L为相互相同的结构。半导体芯片12H、12L配置成，漏极电极12d在Z方向上成为相同侧，源极电极12s在Z方向上成为相同侧。半导体芯片12H、12L在Z方向上位于大致相同的高度，并且在X方向上横向排列配置。
如图5及图6所示，在半导体芯片12的背面即源极电极形成面，形成有作为信号用的电极的焊盘12p。焊盘12p在背面形成在源极电极12s以外的位置。焊盘12p在Y方向上形成在与源极电极12s的形成区域相反侧的端部。
在本实施方式中，半导体芯片12分别具有5个焊盘12p。详细地讲，作为5个焊盘12p，具有栅极电极用、源极电极12s的电位检测用、电流感测用、检测半导体芯片12的温度的温度传感器(感温二极管)的阳极电位用、该温度传感器的阴极电位用的焊盘。5个焊盘12p在平面形状大致矩形的半导体芯片12中集中形成在Y方向的一端侧，并且在X方向上排列而形成。
封固树脂体14将半导体芯片12封固。封固树脂体14例如由环氧类树脂构成。封固树脂体14例如通过传递模塑法而成形。如图2及图3所示，封固树脂体14在Z方向上具有一面14a及与一面14a相反的背面14b。一面14a是漏极电极12d侧的面，背面14b是源极电极12s侧的面。一面14a及背面14b例如为平坦面。在本实施方式中，封固树脂体14的平面形状大致为矩形。
第1散热片16配置在半导体芯片12的一面侧、即漏极电极12d侧。第1散热片16起到将对应的半导体芯片12的热向半导体装置10的外部散热的功能，并且还起到作为主电极的布线的功能。因此，为了确保导热性及导电性而用Cu或Al等金属材料形成。在本实施方式中，第1散热片16用Cu形成，其厚度为2mm左右。此外，第1散热片16如图3～图5所示，具有对应于半导体芯片12H的第1散热片16H和对应于半导体芯片12L的第1散热片16L。
在来自Z方向的投影观察下，第1散热片16以将对应的半导体芯片12包含在内部的方式设置。第1散热片16经由钎焊部(solder)18而与对应的半导体芯片12的漏极电极12d连接。第1散热片16各自的大部分被封固树脂体14覆盖。在第1散热片16的表面中的安装面16a，连接着钎焊部18。与安装面16a相反的散热面16b从封固树脂体14露出。散热面16b与一面14a大致共面。
详细地讲，在第1散热片16H的安装面16a，经由钎焊部18连接着半导体芯片12H的漏极电极12d。此外，在第1散热片16L的安装面16a，经由钎焊部18连接着半导体芯片12L的漏极电极12d。第1散热片16H、16L在X方向上排列配置，并且在Z方向上配置在大致相同的位置。第1散热片16H、16L的散热面16b从封固树脂体14的一面14a露出，并且相互在X方向上排列。
接线部20介于半导体芯片12与第2散热片24之间，将半导体芯片12和第2散热片24电中继。接线部20由于位于半导体芯片12与第2散热片24的热传导、电传导路径的中途，所以为了确保导热性及导电性而至少使用金属材料形成。接线部20与源极电极12s对置配置，经由钎焊部22而与源极电极12s连接。接线部20按每个半导体芯片12而设置。即，半导体装置10具备2个接线部20。接线部20的一个介于半导体芯片12H与第2散热片24H之间，接线部20的另一个介于半导体芯片12L与第2散热片24L之间。关于接线部20的详细情况在后面叙述。
第2散热片24也与第1散热片16同样，起到将对应的半导体芯片12的热向半导体装置10的外部散热的功能，并且起到作为主电极的布线的功能。第2散热片24配置在半导体芯片12的源极电极12s侧。第2散热片24配置成，在与第1散热片16之间夹着半导体芯片12。第1散热片16及第2散热片24相当于一对散热片。以下，将第1散热片16及第2散热片24也称作散热片16、24。
第2散热片24也使用Cu或Al等金属材料形成。在本实施方式中，第2散热片24使用Cu形成，其厚度为2mm左右。此外，第2散热片24如图3、图7及图8所示，具有对应于半导体芯片12H的第2散热片24H和对应于半导体芯片12L的第2散热片24L。
在来自Z方向的投影观察中，第2散热片24以将对应的半导体芯片12包含在内部的方式设置。第2散热片24与对应的半导体芯片12的源极电极12s电连接。第2散热片24经由钎焊部22、接线部20及钎焊部26而与对应的源极电极12s电连接。第2散热片24各自的大部分被封固树脂体14覆盖。在第2散热片24的表面中，在安装面24a连接着钎焊部26，与安装面24a相反的散热面24b从封固树脂体14露出。散热面24b与背面14b大致共面。钎焊部18、22、26相当于接合部件。
详细地讲，在第2散热片24H的安装面24a，经由钎焊部26连接着对应于半导体芯片12H的接线部20。在第2散热片24L的安装面24a，经由钎焊部26连接着对应于半导体芯片12L的接线部20。第2散热片24H、24L在X方向上排列配置，并且在Z方向上配置在大致相同的位置。并且，第2散热片24H、24L的散热面24b从封固树脂体14的背面14b露出，并且相互在X方向上排列。
接合部28具有第1接合部28a、第2接合部28b及第3接合部28c。第1接合部28a及第3接合部28c将上臂侧的第2散热片24H与下臂侧的第1散热片16L电连接。第2接合部28b将下臂侧的第2散热片24L与负极端子32n电连接。
在本实施方式中，通过将相同的金属板进行加工，从而将第1接合部28a与第2散热片24H一体地设置。通过将相同的金属板进行加工，从而将第2接合部28b与第2散热片24L一体地设置。并且，将包括第1接合部28a的第2散热片24H和包括第2接合部28b的第2散热片24L做成了共通部件，在半导体装置10中它们的配置成为以Z轴为旋转轴的2次对称。
第1接合部28a以被封固树脂体14覆盖的方式被设计得比第2散热片24H薄。第1接合部28a以与第2散热片24H的安装面24a大致共面的方式而与第2散热片24H相连。第1接合部28a从第2散热片24H的第2散热片24L侧的侧面24c沿X方向延伸。关于第1接合部28a，在与第2散热片24H的安装面24a相连的面，经由钎焊部30连接着第3接合部28c。
第2接合部28b也成为与第1接合部28a同样的结构。关于第2接合部28b，在与第2散热片24L的安装面24a相连的面，经由钎焊部30连接着负极端子32n。另外，在第1接合部28a及第2接合部28b各自的与安装面24a相连的面，形成有用来将溢出的钎焊部30吸收的槽。槽形成为环状。
第3接合部28c也通过将相同的金属板进行加工从而与第1散热片16L一体地设置。第3接合部28c以被封固树脂体14覆盖的方式而被设计得比第1散热片16L薄。第3接合部28c与第1散热片16L的安装面16a大致共面地相连。第3接合部28c从第1散热片16L的第1散热片16H侧的侧面16c朝向第2散热片24H延伸设置。
第3接合部28c在来自Z方向的平面观察中在X方向上延伸设置。在本实施方式中，如图3所示，第3接合部28c具有两处弯曲部。第3接合部28c的前端部分在来自Z方向的投影观察中与第1接合部28a重叠。并且，第3接合部28c与第1接合部28a经由钎焊部30连接。第3接合部28c以在Y方向上与第2接合部28b横向排列的方式设置。
另外，也可以使第1接合部28a为独立于第2散热片24H的部件，做成通过与第2散热片24H连接而与第2散热片24H相连的结构。也可以使第2接合部28b为独立于第2散热片24L的部件，做成通过与第2散热片24L连接而与第2散热片24L相连的结构。此外，也可以使第3接合部28c为独立于第1散热片16L的部件，做成通过与第1散热片16L连接而与第1散热片16L相连的结构。还能够仅通过第1接合部28a及第3接合部28c的一方将上臂与下臂电连接。
电源端子32具有正极端子32p和负极端子32n。正极端子32p与平滑电容器4的正极侧端子电连接。正极端子32p是流动主电流的主端子。正极端子32p也被称作高电位电源端子、P端子。如图4所示，正极端子32p与第1散热片16H相连，从第1散热片16H的侧面中的与信号端子36侧的面相反的面沿Y方向延伸设置。
在本实施方式中，通过将相同的金属板进行加工从而将正极端子32p与第1散热片16H一体地设置。正极端子32p与第1散热片16H的Y方向的一端相连。正极端子32p在Y方向上延伸设置，如图2所示，从封固树脂体14的侧面14c向外部突出。
负极端子32n与平滑电容器4的负极侧端子电连接。负极端子32n是流通主电流的主端子。负极端子32n也被称作低电位电源端子、N端子。负极端子32n以其一部分在来自Z方向的投影观察中与第2接合部28b重叠的方式配置。负极端子32n在Z方向上配置在比第2接合部28b更靠近半导体芯片12的位置。负极端子32n和第2接合部28b也经由钎焊部30连接。负极端子32n在Y方向上延伸设置，从与正极端子32p相同的侧面14c向外部突出。
输出端子34与上下臂的连接点电连接。输出端子34与马达3的对应的相的线圈(定子绕线)电连接。输出端子34也被称作交流端子、O端子。如图4所示，输出端子34与第1散热片16L相连，从第1散热片16L的侧面中的与信号端子36侧的面相反的面向Y方向上的与正极端子32p相同的一侧延伸设置。
在本实施方式中，通过将相同的金属板进行加工从而将输出端子34与第1散热片16L一体地设置。输出端子34与第1散热片16L的Y方向的一端相连。输出端子34在Y方向上延伸设置，从与正极端子32p及负极端子32n相同的侧面14c向封固树脂体14之外突出。
正极端子32p、负极端子32n及输出端子34各自的从封固树脂体14突出的突出部分在Z方向上配置在大致相同的位置。此外，在X方向上，正极端子32p、负极端子32n及输出端子34依次排列配置。这样，负极端子32n配置在正极端子32p的旁边。
电源端子32及输出端子34因为流通主电流所以也被称作主端子。在电源端子32及输出端子34上，连接着未图示的母线(bus bar)。母线例如通过激光焊接而与对应的电源端子32、输出端子34连接。在本实施方式中，考虑与母线等的连接性，从封固树脂体14突出的突出部分的延伸长度在3根电源端子32及输出端子34中相互不同，输出端子34最长，负极端子32n最短。此外，关于突出部分的宽度，正极端子32p最宽，输出端子34最窄。
另外，也可以将正极端子32p做成独立于第1散热片16H的部件，并做成通过与第1散热片16H连接而与第1散热片16H相连的结构。也可以将负极端子32n用与第2接合部28b以及第2散热片24L相同的金属板构成。也可以将输出端子34做成独立于第1散热片16L的部件，并做成通过与第1散热片16L连接而与第1散热片16L相连的结构。
信号端子36如图6所示，经由键合线38而与对应的半导体芯片12的焊盘12p电连接。信号端子36在Y方向上延伸设置，如图2所示，在封固树脂体14中从与侧面14c相反的侧面14d向外部突出。
如图4所示，在本实施方式中，第1散热片16、第3接合部28c、电源端子32、输出端子34及信号端子36构成为作为同一金属板的引线框40。在引线框40中，第1散热片16以及负极端子32n的与第2接合部28b的连接部分被做成厚壁部，其以外的部分被做成厚度比厚壁部薄的薄壁部。
在如以上那样构成的半导体装置10中，通过封固树脂体14，将半导体芯片12、第1散热片16各自的一部分、接线部20、第2散热片24各自的一部分、电源端子32各自的一部分、输出端子34的一部分、以及信号端子36的一部分一体地封固。在半导体装置10中，通过封固树脂体14，将构成一相的上下臂的2个半导体芯片12封固。因此，半导体装置10也被称作2in1封装。
第1散热片16H、16L各自的散热面16b位于同一面内，并且与封固树脂体14的一面14a大致共面。同样，第2散热片24H、24L各自的散热面24b位于同一面内，并且与封固树脂体14的背面14b大致共面。这样，半导体装置10成为散热面16b、24b都从封固树脂体14露出的两面散热构造。
(半导体装置的制造方法)
基于图2、图4～图6及图8，对上述的半导体装置10的制造方法的一例进行说明。另外，图2、图4～图6及图8示出了制品状态的引线框40。在以下所示的制造工序中，直到进行不需要部分的去除为止，引线框40具有未图示的外框及连接杆(tie bar)。
首先，准备构成半导体装置10的各要素。例如准备图4所示的引线框40。此外，分别准备半导体芯片12、接线部20、第2散热片24。
接着，如图5所示，在引线框40的第1散热片16H、16L的安装面16a上，经由钎焊部18而配置对应的半导体芯片12H、12L。此时，以漏极电极12d与安装面16a对置的方式配置半导体芯片12H、12L。
接着，例如配置预先在两面上作为预备钎焊部而配置有钎焊部22、26的接线部20，以使钎焊部22成为半导体芯片12侧。关于钎焊部26，配置能够将半导体装置10中的高度偏差吸收的量。此外，在第3接合部28c及负极端子32n上配置钎焊部30。
并且，在该层叠状态下，实施钎焊的第1次回流焊(reflow)。由此，经由钎焊部18将半导体芯片12的漏极电极12d与对应的第1散热片16连接。此外，经由钎焊部22将半导体芯片12的源极电极12s与对应的接线部20连接。即，如图6所示，能够得到引线框40、半导体芯片12及接线部20被一体化了的连接体。在回流焊后，将半导体芯片12的焊盘12p和信号端子36通过键合线38连接。
接着，使安装面24a朝上而将第2散热片24配置到未图示的台座上。并且，使接线部20与第2散热片24对置而将连接体配置到第2散热片24上，实施钎焊的第2次回流焊。在第2次回流焊中，通过从第1散热片16侧施加载荷，使得半导体装置10的高度成为规定高度。图8表示第2次回流焊后的状态。
接着，通过传递模塑法进行封固树脂体14的成形。在本实施方式中，将封固树脂体14成形，以使第1散热片16及第2散热片24完全被覆盖。另外，在成形之前，若向第1散热片16、半导体芯片12及接线部20等的与封固树脂体14接触的表面部分涂布例如聚酰胺树脂，则能够提高与封固树脂体14的密接力。
接着，通过将成形出的封固树脂体14连同第1散热片16的一部分一起切削，使第1散热片16的散热面16b露出。由此，散热面16b与一面14a大致共面。同样，通过将封固树脂体14连同第2散热片24的一部分一起切削，使第2散热片24的散热面24b露出。由此，散热面24b与背面14b大致共面。
另外，也可以将散热面16b、24b抵接于成形金属模的腔室壁面，在使其密接的状态下将封固树脂体14成形。在此情况下，在将封固树脂体14进行了成形的时点，散热面16b、24b从封固树脂体14露出。因此，不再需要成形后的切削。
接着，将外框及连接杆等引线框40的不需要部分除去。由此，能够得到图2所示的半导体装置10。
(接线部详细)
接线部20将多个种类的金属层层叠而成。在层叠方向上，相邻的金属层被接合。这里，所谓不同种类，可以是构成的金属相互不同，也可以是线膨胀系数相互不同。例如即使线膨胀系数相同，只要构成的金属不同，就是不同的种类。多个种类的金属层可以是，在Z方向及与Z方向正交的方向的至少1个方向上线膨胀系数相互不同，并且各自的线膨胀系数在半导体芯片12以上且第2散热片24以下的范围内。容易将接线部20整体的线膨胀系数在半导体芯片12与第2散热片24之间调整。另外，所谓与Z方向正交的方向，是沿着XY面的方向即X方向及Y方向。另外，SiC的线膨胀系数是4×10－6/K左右，Cu是17×10－6/K左右。
在本实施方式中，作为接线部20而采用具备由第1金属构成的金属层和含有第1金属的合金层的包层(clad)体。详细地讲，如图9所示，采用具备Cu层20a和含有Cu的合金层20b的包层体。由于包层体是不使用接合材料的基于分子扩散的接合，所以与以往的层叠型相比能够提高层间的连接可靠性。在本实施方式中，由于全部的层含有同一金属(Cu)，所以能够提高连接可靠性。进而，与使接线部全部为合金层的结构相比，能够抑制散热性的下降。
Cu层20a虽然散热性、导热性良好，但线膨胀系数比SiC大。Cu层20a的线膨胀系数与第2散热片24相同。合金层20b含有Cu以及线膨胀系数比Cu小的金属材料。合金层20b至少与Z方向正交的方向的线膨胀系数比Cu小。在本实施方式中，合金层20b含有Cr。使用Cr能够使线膨胀系数较小，并且能够将接线部20便宜且轻量地构成。
含有Cr的合金层20b例如通过轧制使Cu含浸于Cr而得到的材料而构成。在轧制中，与压下率对应的轧制方向及与轧制方向正交的方向的线膨胀系数分别有不同的表现。这是因为，当Cu的热膨胀被在轧制方向上扁平的Cr约束时，在轧制方向和正交方向上应力的作用方式不同。另外，所谓压下率，是被轧制材料的板厚减少率。
关于轧制方向，随着压下率的增加而线膨胀系数持续减小，例如在50质量％的Cr－Cu轧制材料下，压下率70％左右时变得大致固定。正交方向也同样地，随着压下率的增加而线膨胀系数持续减小，但相对于压下率的减少幅度比轧制方向小。并且，例如在50质量％的Cr－Cu轧制材料下，即使轧制到压下率98％，线膨胀系数也持续减小，接近于轧制方向的线膨胀系数。
在本实施方式中，在较大地贡献于向接合部的热应力的发生的轧制方向的线膨胀系数相对于压下率变得大致固定的Cr－Cu轧制材料、例如50质量％的Cr－Cu轧制材料中，通过采用了压下到70％以上的Cr－Cu轧制材料的包层体而构成了接线部20。另外，在合金层20b(Cr－Cu轧制材料)中，X方向及Y方向是轧制方向，由此，在与Z方向正交的方向即X方向及Y方向上成为相同的线膨胀系数。Z方向的线膨胀系数比X方向及Y方向大，在本实施方式中比Cu小。
接线部20的Cu层20a的热膨胀被合金层20b约束，与单纯地将Cu与Cr－Cu合金以粉末彼此复合相比，线膨胀系数的抑制效果较高。通过这样的层叠构造，作为接线部20整体，与Z方向正交的方向的线膨胀系数被设为半导体芯片12与第2散热片24之间的值、例如12～13×10－6/K左右。因而，能够减小作用于将半导体芯片12与接线部20连接的钎焊部22的热应力。
此外，能够在将线膨胀系数保持得较小的同时，通过Cu层20a得到较高的热扩散效果。因而，能够不损害半导体装置10的散热性地使作用于钎焊部18、22的热应力较小。特别是，由于合金层20b比Cu层20a薄，所以能够在使用合金层20b的同时提高散热效果。
进而，Cu层20a和合金层20b在Z方向上对称配置。具体而言，如图9所示，相对于接线部20的Z方向的中心线CL为线对称配置。将Cu层20a和合金层20b交替地配置，以使层数成为奇数5。Cu层20a彼此厚度相互大致相等，合金层20b彼此厚度相互大致相等。
这样，由于Z方向的对称性高，所以能够基于构成接线部20的金属层的线膨胀系数差来抑制接线部20发生翘曲。即，能够降低作用于钎焊部18、22、26的应力。另外，接线部20的平面形状为矩形，在Z方向的投影观察中，Cu层20a和合金层20b的形状大致一致。因此，接线部20在与Z方向正交的方向上也对称性高，由此也能够抑制翘曲。
此外，以Cu层20a、合金层20b、Cu层20a、合金层20b、Cu层20a的顺序层叠。这样，浸润性比合金层20b高的Cu层20a被配置在表层。此外，在接线部20的侧面出现浸润性比Cu层20a低的合金层20b。由此，能够在确保与钎焊部22、26的接合性的同时，抑制钎焊部向接线部20的侧面的爬升。
(半导体装置的效果)
在本实施方式中，在两面散热构造的半导体装置10中，半导体芯片12采用了SiC(碳化硅)。SiC与Si相比具备绝缘击穿电场及带隙大、热传导率高、电子饱和速度快的特性。但是，杨氏模量为Si的约3倍，是较大的。
相对于此，在本实施方式中，将多种金属层层叠而构成接线部20。并且，作为接线部20整体，与Z方向正交的方向上的线膨胀系数为半导体芯片12与第2散热片24之间的值。因而，能够减小作用于钎焊部18、22、26及半导体芯片12的热应力。
进而，金属层在Z方向上对称配置。由此，能够抑制接线部20的翘曲，抑制局部应力作用于钎焊部18、22、26及半导体芯片12。根据以上，本实施方式的半导体装置10适合于对半导体芯片12采用SiC的结构。
在本实施方式中，作为接线部20而使用依次层叠有Cu层20a和含有Cu的合金层20b的包层体。由此，与使用接合材料的以往的层叠型的接线部相比，能够提高层间的连接可靠性。此外，由于全部的层含有Cu，所以能够提高层间的连接可靠性。进而，能够抑制散热性的下降。由此，在半导体装置10的使用时能够抑制温度上升、降低热应力。此外，能够抑制构成半导体装置10的部件的热劣化。特别是，由于合金层20b含有Cr，所以能够在减小线膨胀系数的同时便宜且轻量地构成。
在本实施方式中，接线部20的表层为Cu层20a。由此，能够提高与钎焊部22、26的连接可靠性。此外，由于在侧面出现浸润性低的合金层20b，所以能够抑制钎焊部22、26的爬升。
接线部20的结构不限于上述例子。Cu层20a和含有Cr的合金层20b的配置不限于上述例子。例如层数不限于5层。3层以上就可以。在奇数层的情况下，能够在Z方向上具有对称性。此外，也可以设为偶数层。例如，也可以将Cu层20a、合金层20b、Cu层20a的包层体层叠两个，做成Cu层20a、合金层20b、Cu层20a、Cu层20a、合金层20b、Cu层20a的6层构造。在此情况下，也能够在Z方向上具有对称性。
例如也可以如图10所示的第1变形例那样，采用合金层20b为表层的结构。在图10中，以合金层20b、Cu层20a、合金层20b、Cu层20a、合金层20b的顺序层叠。与从线膨胀系数大的Cu层20a向线膨胀系数小的合金层20b传热相比，从线膨胀系数小的合金层20b向线膨胀系数大的Cu层20a传热时传热的障碍小。在图10中，采用5层构造，并且合金层20b比Cu层20a层数多，所以与图9所示的结构相比能够提高散热性。
也可以如图11所示的第2变形例那样，使表层的Cu层20c的厚度比内层的Cu层20a及合金层20b薄。例如，可以将Cu层20c设为30μm左右，将Cu层20a设为1mm左右，将合金层20b分别设为500μm左右。通过Cu层20a及合金层20b调整线膨胀系数及散热性，为了接合性提高而设置Cu层20c。
也可以代替Cr而使用Mo等线膨胀系数小的金属材料。此外，也可以代替Cu而使用Al等热传导良好的材料。例如也可以如图12所示的第3变形例那样，作为接线部20而使用Cu层20a、含有Cr的合金层20b以及含有Mo的合金层20d(Mo－Cu合金)的包层体。在图12中，以Cu层20a、合金层20b、Cu层20a、合金层20d、Cu层20a的顺序层叠。在Z方向上没有对称配置，但通过使合金层20b、20d彼此的线膨胀系数接近、优选的是大致一致，能够抑制接线部20的翘曲。即，通过在Z方向上使线膨胀系数具有对称性，能够抑制接线部20的翘曲。
(第2实施方式)
本实施方式能够参照在先实施方式。因此，关于与在先实施方式中表示的半导体装置10共通的部分的说明省略。
源极电极12s以AlSi等以Al为主成分的基底层与钎焊部22的接合强度提高、钎焊部22的浸润性提高等为目的而具有形成在基底层上的上基底层。上基底层使用NiP等以Ni为主成分的材料形成。Ni是比Al硬的金属材料。在该构造中，在被焊接了的状态下，通过动力循环等的应力，在基底层中，应力集中在上基底层的端面的紧下方部分。特别是，在本实施方式中，作为半导体芯片12而采用了杨氏模量大的SiC。
对此，在本实施方式中，接线部20的与半导体芯片12的对置面具有对于钎焊部22的浸润性良好的部分、和浸润性比良好的部分低的部分。在图13所示的例子中，在表层较薄的Cu层20c中，半导体芯片12侧的Cu层20c的一部分通过蚀刻而被除去，仅配置在对置面的中央区域。将Cu层20c包围的外周区域中，Cu层20c的紧下方的合金层20b露出。
由于合金层20b的浸润性比Cu层20a、20c低，所以即使钎焊部22在配置于接线部20的对置面的外周区域中的合金层20b上浸润扩散，也不会以包含外周区域的方式形成焊脚(fillet)。因而，能够使源极电极12s与钎焊部22所成的角即焊脚角度成为锐角。由此，在基底层中，能够减小集中于上基底层的端面的紧下方部分的应力。此外，由于只是准备包层体并将表层的一部分除去，所以能够使结构简化。另外，图13所示的虚线是表示向对置面的整面配置了Cu层20c的情况下的焊脚的参考线。
接线部20的结构并不限定于上述例子。在图13所示的例子中，表示了以下例子：通过将Cu层20c蚀刻，在接线部20的与半导体芯片12的对置面中，部分性地设置浸润差的部分而控制焊脚角度。但是，也可以通过溅射等而局部地设置浸润性好的膜。此外，也可以代替合金层20b而使含有Mo的合金层20d露出，作为浸润差的部分。此外，也可以在接线部20的与第2散热片24的对置面中使合金层20b、20d一部分露出而作为浸润差的部分。
(第3实施方式)
本实施方式能够参照在先实施方式。因此，关于与在先实施方式中表示的半导体装置10共通的部分的说明省略。
可以对于散热片16、24的至少1个使用包层体。在图14所示的例子中，对第1散热片16及第2散热片24分别使用包层体。接线部20为与第1实施方式(参照图9)相同的结构。图14是沿着图2所示的XIV－XIV线的剖视图。
第2散热片24H，包含未图示的第1接合部28a在内而采用包层体。包含第1接合部28a的第2散热片24H是交替地层叠Cu层24d和含有Cu及Cr的合金层24e而成的，具有3层Cu层24d和2层合金层24e。这样，第2散热片24H与接线部20同样地构成。另外，关于第2散热片24L也是同样的。
在引线框40中，正极端子32p及信号端子36、未图示的负极端子32n、输出端子34及第3接合部28c与第1散热片16的一部分通过由Cu形成的基材41构成。即，引线框40的薄壁部由基材41构成。引线框40的厚壁部包括包层体42而构成。
包层体42是将Cu层16d和含有Cu及Cr的合金层16e交替地层叠而成的。并且，由基材41和包层体42形成图14所示的第1散热片16。第1散热片16通过基材41和包层体42而成为3层的Cu层16d和2层的合金层16e的层叠构造。
这样，在本实施方式中，第2散热片24也使用包层体而构成。由此，在第2散热片24中，能够抑制散热性的下降、并且减小与Z方向正交的方向即X方向及Y方向的线膨胀系数。换言之，能够减小与接线部20的线膨胀系数差的差或使其大致一致。因而，能够降低作用于第2散热片24与接线部20之间的钎焊部26的热应力。此外，由于Cu层24d构成安装面24a侧的面，所以能够提高与钎焊部26、30的连接性。
在本实施方式中，第1散热片16也使用包层体而构成。由此，在第1散热片16中，能够抑制散热性的下降、并且使与Z方向正交的方向的线膨胀系数变小。因而，能够降低作用于第1散热片16与半导体芯片12之间的钎焊部18的热应力。
特别是，在本实施方式中，散热片16、24都包含包层体，在与Z方向正交的方向上，第1散热片16整体的线膨胀系数和第2散热片24整体的线膨胀系数具有大致相同的值。因而，能够抑制半导体装置10的翘曲。此外，由于使用由Cu构成的基材41，所以能够提高与钎焊部18、键合线38、母线等的连接性。
另外，包层体向散热片16、24的应用并不限定于上述例子。也可以做成仅第1散热片16包含包层体的结构。此外，也可以做成仅第2散热片24包含包层体的结构。但是，优选的是做成如上述那样散热片16、24都包含包层体的结构。
也可以使包层体的结构与图14所示的例子不同。也可以做成与接线部20不同的结构。
例如也可以将包括第1散热片16的引线框40与第2散热片24H同样地仅由包层体构成。在此情况下，正极端子32p及信号端子36也成为Cu层16d与合金层16e的层叠构造。在使表层为Cu层16d的情况下，能够提高与钎焊部18、键合线38、母线等的连接性。
也可以将第2散热片24做成与上述引线框40(第1散热片16)同样的结构。即，也可以将第1接合部28a用由Cu形成的基材构成，将第2散热片24用基材和包层体构成。由于基材构成安装面16a侧的面，所以能够提高与钎焊部26、30的连接性。
也可以如图15所示的第4变形例那样，做成使合金层24e形成散热面24b的结构。此外，也可以做成使合金层16e形成散热面16b的结构。例如通过在合金层24e的中途设置切削线，合金层24e形成散热面24b。此外，通过在合金层16e的中途设置切削线，合金层16e形成散热面16b。由于Cr与Mo及Cu相比切削性好，所以如果在含有Cr的合金层16e、24e中设置切削线，则能够提高使散热面16b、24b露出时的切削性。
虽然省略了图示，但也可以是，以使合金层24e形成安装面24a的方式构成第2散热片24。例如与图10所示的接线部20同样，通过做成合金层24e比Cu层24d多的结构，能够提高散热性。虽然省略了图示，但关于第1散热片16也是同样的。即，也可以是，以使合金层16e形成第1散热片16的安装面16a的方式构成包括包层体42的引线框40。
也可以代替含有Cr的合金层16e、24e而采用含有Cu和Mo的合金层。由此也能够使散热片16、24的线膨胀系数变小。
也可以是，将散热片16、24仅用包层体构成，将正极端子32p、第1接合部28a等与散热片16、24相连的部分用由Cu形成的薄板构成。在此情况下，通过扩散接合、激光焊接、敛缝等将薄板与包层体连接就可以。
在接线部20不使用包层体的结构、例如接线部20由Cu形成的结构中，也可以对第2散热片24使用包层体。在此情况下也能够通过使合金层24e成为散热面24b来提高切削性。
在接线部20及第2散热片24不使用包层体的结构中，也可以对第1散热片16使用包层体。能够降低与半导体芯片12的线膨胀系数的差，降低作用于半导体芯片12与第1散热片16之间的钎焊部18的热应力。此外，若将合金层16e作为散热面16b，则能够提高切削性。
(第4实施方式)
本实施方式能够参照在先实施方式。因此，关于与在先实施方式中表示的半导体装置10共通的部分的说明省略。
在本实施方式中，作为钎焊部18、22、26的至少1个，使用以下规定的无铅钎焊部。该无铅钎焊部与在先实施方式及变形例的哪个都能组合。
无铅钎焊部含有3.2～3.8质量％的Ag、0.6～0.8质量％的Cu、0.01～0.2质量％的Ni，还含有Sb和Bi。
Ag的添加具有钎焊部的浸润性提高及析出分散强化的效果。另一方面，液相线温度上升。若考虑半导体芯片12(SiC)的耐热性，则优选的是在焊接时将温度抑制在300℃以下。因而，为了在充分得到浸润性提高、析出分散的效果的同时还考虑离差而将液相线温度抑制为270℃以下，将Ag的含量设为3.2～3.8质量％。
Cu的添加具有防止Cu对于Cu焊接区(land)的侵蚀、使作为微细的金属间化合物的Cu6Sn5析出到钎焊基体中而将基体强化的效果。若过量地添加，则金属间化合物析出到接合界面，加速裂纹发展。因此，将Cu含量设为0.6～0.8质量％。
Ni的添加具有通过使向接合界面析出的金属间化合物微细化来强化接合界面的效果。另一方面，液相线温度上升。为了充分得到接合界面强化效果并且将液相线温度抑制为上述的270℃以下，将Ni的含量设为0.01～0.2质量％。
Sb的添加具有固溶析出强化及析出分散强化的效果，通过将Sb对于Sn置换而引起晶格畸变，具有Sn基体强化的效果。与Sb相比原子半径大的Bi在Sn基体强化中发挥Sb以上的效果。另一方面，若过量地包含Sb或Bi，则浸润性及对于箔的加工性下降。
通过伴随着Sb、Bi的添加的Sn基体强化的效果，蠕变耐性增加。即，能够将蠕变抑制得较低。
此外，当制造半导体装置10时，为了在焊接后的模铸工序等中维持钎焊部的连接可靠性，固相线温度优选的是200℃以上。Sb和Bi的添加量考虑上述的效果来调整。
满足以上的无铅钎焊部在应对使用环境的高温化的同时，不仅使基于钎焊部的接合部高寿命化，还能够减少由蠕变造成的向半导体芯片的一部分的不需要的应力集中。因而，能够进行高温动作，对于由杨氏模量大的SiC基板构成的半导体芯片12是适合的。
特别是，优选对钎焊部26使用上述的无铅钎焊部。即使通过使用在先实施方式中表示的接线部20而作用于钎焊部22的热应力增加，也能够维持较高的连接可靠性。
此外，优选的是对钎焊部18使用上述的无铅钎焊部。即使基于半导体芯片12与第1散热片16的线膨胀系数差的热应力起作用，也能够维持较高的连接可靠性。
此外，由于半导体芯片12的杨氏模量较大，所以如果实施动力循环试验，则半导体芯片12周边的钎焊部18、22蠕变，担心伴随着循环数的增加而发生钎焊部裂纹等。对此，通过使用上述的无铅钎焊部，能够抑制钎焊部18、22的蠕变。
上述的无铅钎焊部由于具有良好的耐蠕变性等特性，所以不论接线部20、散热片16、24的结构如何，对于半导体装置10整体的高寿命化都是有效的。因而，在不对各零件使用包层体的结构中，可以对钎焊部18、22、26的至少1个使用无铅钎焊部。
图16表示钎焊部应变的模拟结果。图16表示不对接线部20、散热片16、24使用包层体的结构的结果。所谓元件下，表示半导体芯片12的紧下方的钎焊部18，所谓元件上，表示半导体芯片12的紧上方的钎焊部22，所谓TML上，表示接线部20上的钎焊部26。比较例1(图中的比1)表示在使用Si基板的半导体芯片中使用以往结构的钎焊部的结构的结果。比较例2(图中的比2)表示将比较例1的Si基板替换为SiC基板的结构的结果。实施例(图中的实)表示相对于比较例2将钎焊部替换为上述的无铅钎焊部的结构的结果。
如图16所示，如果将Si替换为杨氏模量比Si大的SiC，则半导体芯片12周边的钎焊部18、22的钎焊部应变增加。并且，如果使用上述的无铅钎焊部，则钎焊部18、22都能够减小钎焊部应变。这样，在不对接线部20、散热片16、24使用包层体的结构中无铅钎焊部也是优选的。
本发明并不限制于例示的实施方式。本发明包含例示的实施方式和基于它们的由本领域技术人员做出的变形形态。例如，本发明并不限定于在实施方式中表示的要素的组合。本发明能够以多种多样的组合来实施。公开的技术范围并不限定于实施方式的记载。应理解为公开的若干技术范围由权利要求的记载表示，还包含与权利要求的记载等价的意义及范围内的全部变更。
作为半导体装置10，表示了具备上臂侧的半导体芯片12H和下臂侧的半导体芯片12L的2in1封装构造的例子，但并不限定于此。对于具备构成1个臂的1个半导体芯片的1in1封装构造、或具备构成三相的上下臂的6个半导体芯片的6in1封装构造也能够应用。
表示了散热片16、24的散热面16b、24b从封固树脂体14露出的例子，但并不限定于此。也可以做成散热面16b、24b的至少一方被封固树脂体14覆盖的结构。
作为形成于半导体芯片12的元件而表示了MOSFET6的例子，但并不限定于此。只要是应用于电力变换装置的纵型元件就可以。例如，对于IGBT或SBD也能够应用。在IGBT的情况下，既可以将IGBT和FWD用1个芯片构成，也可以做成不同的芯片。
表示了为了提高与封固树脂体14的密接力而涂布聚酰胺树脂的例子，但并不限定于此。对于不进行涂布的结构也能够应用。此外，也可以代替聚酰胺树脂而通过基于激光加工的粗糙化来提高密接力。在此情况下，例如在准备各部件的工序中照射激光而进行粗糙化就可以。
作为构成半导体芯片12的半导体基板而表示了SiC基板的例子。但是，对于SiC以外的杨氏模量比Si大的半导体基板也能够应用。
也可以是，在第1散热片16的安装面16a、接线部20的钎焊部接合面、第2散热片24的安装面24a，通过镀覆、溅射等，形成提高与钎焊部的浸润性的膜。可以设置Ni类的薄膜、例如NiP镀膜。此外，也可以在接线部20的整面设置了Ni类的薄膜后，通过照射激光而使钎焊部的浸润性部分地下降。通过激光的照射，形成以Ni为主成分、表面呈微细凹凸的氧化膜。通过该氧化膜，能够使浸润性下降。

Claims (9)

1.一种半导体装置，其特征在于，
具备：
半导体芯片(12)，在SiC基板中形成有元件，在一面及与上述一面在板厚方向上相反的背面分别形成有主电极；
第1散热片(16)及第2散热片(24)，是在上述板厚方向上夹着上述半导体芯片而配置的一对散热片，上述第1散热片(16)配置在上述一面侧，上述第2散热片(24)配置在上述背面侧；
接线部(20)，介于上述第2散热片与上述半导体芯片之间，将上述背面侧的主电极和上述第2散热片进行电中继；以及
接合部件(18、22、26)，分别配置在上述一面侧的主电极与上述第1散热片之间、上述背面侧的主电极与上述接线部之间、上述接线部与上述第2散热片之间；
上述接线部在上述板厚方向上层叠有多种金属层(20a、20b、20c、20d)；
作为上述接线部的整体，至少与上述板厚方向正交的方向的线膨胀系数被设为比上述半导体芯片大且比上述第2散热片小的范围内；
在上述接线部中，上述多种金属层在上述板厚方向上对称配置。
2.如权利要求1所述的半导体装置，其特征在于，
上述接线部中，作为上述金属层，具有Cu层和含有Cu的合金层，上述接线部是依次层叠了上述Cu层和上述合金层的3层以上的包层体。
3.如权利要求2所述的半导体装置，其特征在于，
在上述板厚方向上，上述接线部的表层为上述Cu层。
4.如权利要求2所述的半导体装置，其特征在于，
在上述板厚方向上，上述接线部的表层为上述合金层。
5.如权利要求2～4中任一项所述的半导体装置，其特征在于，
上述合金层含有Cr。
6.一种半导体装置，其特征在于，
具备：
半导体芯片(12)，在SiC基板中形成有元件，在一面及与该一面在板厚方向上相反的背面分别形成有主电极；
第1散热片(16)及第2散热片(24)，是在上述板厚方向上夹着上述半导体芯片而配置的一对散热片，上述第1散热片(16)配置在上述一面侧，上述第2散热片(24)配置在上述背面侧；
接线部(20)，介于上述第2散热片与上述半导体芯片之间，将上述背面侧的主电极和上述第2散热片进行电中继；以及
接合部件(18、22、26)，分别配置在上述一面侧的主电极与上述第1散热片之间、上述背面侧的主电极与上述接线部之间、上述接线部与上述第2散热片之间；
上述接线部是在上述板厚方向上依次层叠有Cu层(20a、20c)和含有Cu及Cr的合金层(20b)的3层以上的包层体，上述Cu层及上述合金层在上述板厚方向上对称配置。
7.如权利要求6所述的半导体装置，其特征在于，
上述第1散热片及上述第2散热片的至少1个包含具有Cu层(16d、24d)和含有Cu的合金层(16e、24e)、并且将上述Cu层和上述合金层依次层叠的3层以上的包层体。
8.如权利要求7所述的半导体装置，其特征在于，
还具备将上述半导体芯片、上述接线部、上述接合部件、上述第1散热片及上述第2散热片一体地封固的封固树脂体(14)；
上述散热片的合金层含有Cr，并且相对于上述封固树脂体的表面以共面的方式露出。
9.如权利要求1～8中任一项所述的半导体装置，其特征在于，
对于上述接合部件的至少1个，采用了含有3.2～3.8质量％的Ag、0.6～0.8质量％的Cu、0.01～0.2质量％的Ni并且含有Sb和Bi的无铅钎焊部。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11348866B2 (en) * 2020-06-16 2022-05-31 Infineon Technologies Austria Ag Package and lead frame design for enhanced creepage and clearance
JP7367631B2 (ja) * 2020-07-31 2023-10-24 株式会社デンソー 半導体装置
TW202211484A (zh) * 2020-08-07 2022-03-16 日商Ｆｌｏｓｆｉａ股份有限公司 半導體元件及半導體裝置
TW202215664A (zh) * 2020-08-07 2022-04-16 日商Ｆｌｏｓｆｉａ股份有限公司 半導體元件及半導體裝置
DE102021207389A1 (de) 2021-07-13 2023-01-19 Zf Friedrichshafen Ag Schaltungsanordnung für parallel geschaltete Leistungshalbleiter, sowie Elektronikmodul
US11929310B2 (en) * 2021-12-09 2024-03-12 Nxp Usa, Inc. Radio frequency packages containing substrates with coefficient of thermal expansion matched mount pads and associated fabrication methods
JP2023120061A (ja) * 2022-02-17 2023-08-29 株式会社デンソー 半導体装置

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1638076A (zh) * 2003-12-04 2005-07-13 罗姆股份有限公司 半导体芯片及其制造方法、和半导体装置
US20050215042A1 (en) * 2004-03-16 2005-09-29 Infineon Technologies Ag Metallization and its use in, in particular, an IGBT or a diode
US20060244128A1 (en) * 2005-04-19 2006-11-02 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
JP2013229472A (ja) * 2012-04-26 2013-11-07 Denso Corp 半導体装置
CN106463491A (zh) * 2014-06-02 2017-02-22 株式会社电装 半导体装置
CN107078115A (zh) * 2015-04-01 2017-08-18 富士电机株式会社 半导体模块
CN107112294A (zh) * 2014-11-21 2017-08-29 株式会社电装 半导体装置以及功率模块
JP6233677B1 (ja) * 2016-08-31 2017-11-22 Jfe精密株式会社 放熱板及びその製造方法
CN107534032A (zh) * 2015-05-18 2018-01-02 株式会社电装 半导体装置
JP2018116994A (ja) * 2017-01-17 2018-07-26 三菱マテリアル株式会社 パワーモジュール

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4016867B2 (ja) * 2003-03-27 2007-12-05 株式会社デンソー 半導体装置
JP2005117009A (ja) 2003-09-17 2005-04-28 Denso Corp 半導体装置およびその製造方法
JP4958735B2 (ja) * 2007-11-01 2012-06-20 株式会社日立製作所 パワー半導体モジュールの製造方法、パワー半導体モジュールの製造装置、パワー半導体モジュール、及び接合方法
JP5067267B2 (ja) * 2008-06-05 2012-11-07 三菱電機株式会社 樹脂封止型半導体装置とその製造方法
WO2011040044A1 (ja) * 2009-10-01 2011-04-07 Jfe精密株式会社 電子機器用放熱板およびその製造方法
JP5709299B2 (ja) 2010-09-29 2015-04-30 ローム株式会社 半導体パワーモジュールおよびその製造方法
JP5872193B2 (ja) 2011-06-14 2016-03-01 グローリー株式会社 遊技システム及び遊技方法
JP2013098228A (ja) 2011-10-28 2013-05-20 Denso Corp 半導体装置およびその製造方法
JP2015077601A (ja) 2013-04-02 2015-04-23 千住金属工業株式会社 鉛フリーはんだ合金
JP6069135B2 (ja) 2013-08-30 2017-02-01 株式会社日立製作所 電力用半導体装置及びその製造方法、並びに、そのための半田
JP6221542B2 (ja) * 2013-09-16 2017-11-01 株式会社デンソー 半導体装置
JP6406975B2 (ja) 2014-10-24 2018-10-17 三菱電機株式会社 半導体素子および半導体装置
JP6578900B2 (ja) * 2014-12-10 2019-09-25 株式会社デンソー 半導体装置及びその製造方法
JP6380076B2 (ja) * 2014-12-15 2018-08-29 トヨタ自動車株式会社 半導体装置
JP2016134601A (ja) 2015-01-22 2016-07-25 トヨタ自動車株式会社 半導体装置
JP6203307B2 (ja) 2016-03-10 2017-09-27 三菱電機株式会社 半導体装置及びその製造方法
JP6957195B2 (ja) 2017-05-16 2021-11-02 日置電機株式会社 測定装置
JP6981846B2 (ja) * 2017-10-26 2021-12-17 Jfe精密株式会社 放熱板及びその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1638076A (zh) * 2003-12-04 2005-07-13 罗姆股份有限公司 半导体芯片及其制造方法、和半导体装置
US20050215042A1 (en) * 2004-03-16 2005-09-29 Infineon Technologies Ag Metallization and its use in, in particular, an IGBT or a diode
US20060244128A1 (en) * 2005-04-19 2006-11-02 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
JP2013229472A (ja) * 2012-04-26 2013-11-07 Denso Corp 半導体装置
CN106463491A (zh) * 2014-06-02 2017-02-22 株式会社电装 半导体装置
CN107112294A (zh) * 2014-11-21 2017-08-29 株式会社电装 半导体装置以及功率模块
CN107078115A (zh) * 2015-04-01 2017-08-18 富士电机株式会社 半导体模块
CN107534032A (zh) * 2015-05-18 2018-01-02 株式会社电装 半导体装置
JP6233677B1 (ja) * 2016-08-31 2017-11-22 Jfe精密株式会社 放熱板及びその製造方法
JP2018116994A (ja) * 2017-01-17 2018-07-26 三菱マテリアル株式会社 パワーモジュール

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
贾松良: "功率半导体器件芯片背面多层金属层技术", 半导体技术, no. 04 *

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