WO2019161641A1 - 一种芯片及封装方法 - Google Patents

一种芯片及封装方法 Download PDF

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Publication number
WO2019161641A1
WO2019161641A1 PCT/CN2018/099006 CN2018099006W WO2019161641A1 WO 2019161641 A1 WO2019161641 A1 WO 2019161641A1 CN 2018099006 W CN2018099006 W CN 2018099006W WO 2019161641 A1 WO2019161641 A1 WO 2019161641A1
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Prior art keywords
substrate
chip
pin
pad
array
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PCT/CN2018/099006
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English (en)
French (fr)
Inventor
赵南
谢文旭
陶军磊
蒋尚轩
符会利
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18906810.9A priority Critical patent/EP3748672A4/en
Publication of WO2019161641A1 publication Critical patent/WO2019161641A1/zh
Priority to US16/997,003 priority patent/US11276645B2/en

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Definitions

  • the present invention relates to the field of semiconductor packaging technologies, and in particular, to a chip and a packaging method.
  • Silicon Interposer technology is a technical solution for implementing stacked chip interconnects in three-dimensional integrated circuits.
  • This technical solution uses a semiconductor process to fabricate interconnection lines on the silicon wafer with a much wider line width and node pitch than the resin substrate. Therefore, different functions of the chip such as CPU, DRAM, etc. can be connected to the same silicon interposer, and a large amount of operations and data exchange are completed through the silicon interposer, thereby greatly increasing the density of the chips stacked in the three-dimensional direction and shortening the mutual inter-chip. Wire, reduce form factor, significantly reduce noise, reduce RC delay, and improve chip speed and low power performance.
  • 3DIC still has many bottlenecks to be overcome, such as wafer thinning yield, high difficulty in stacking chip signal extraction process, difficult silicon via (TSV) process for chip interconnection, and high power chip. Heat dissipation after stacking, etc.
  • the Fan-out Wafer Level Package can pull out the I/O pins of a single chip through the rewiring layer on the wafer, increasing the area of a single package, thereby improving the overall I/ O number of pins.
  • the design difficulty is not only lower than the through-silicon via 3DIC, but the package structure is close to 2.5D IC. Therefore, the fan-out wafer level package is expected to become the development point of advanced packaging technology.
  • the pins on the bare chip for electrically connecting to the periphery of the package structure need to pass through the substrate to achieve electrical connection with the periphery of the package structure, thus resulting in the overall size of the package structure. Larger, can not meet the needs of chip miniaturization.
  • the embodiment of the present application provides a chip and a packaging method to reduce the overall size of the chip and meet the requirements of miniaturization of the chip.
  • a first aspect of the present application provides a chip comprising: a fan-out unit, a first substrate, and a molding body;
  • the fan-out unit includes a plurality of bare chips arranged in a preset position, and a first pin array and a second pin array are disposed on a first surface of each of the bare chips;
  • the pin array includes a plurality of first pins, the second pin array includes a plurality of second pins; and the second pin arrays on adjacent bare chips are adjacent;
  • the first substrate includes a first surface, and the first surface of the first substrate is provided with a first re-wiring layer and a first pad array electrically connected to the first re-wiring layer, and the first The pad array includes a plurality of first pads;
  • first substrate is located below the fan-out unit, and the first pad array is disposed opposite to the second pin array, and each second tube of the second pin array a first bonding pad corresponding to the first pad array is bonded together, so that interconnection between different bare chips is performed through the first substrate;
  • the molding body is configured to wrap the first pin, the second pin, and the first substrate, thereby molding the fan-out unit and the first substrate into a unitary structure.
  • each of the first pads on the first pad array on the first substrate is bonded to the corresponding second pin in the second pin array on the different bare chips. Together, to achieve short-distance, high-density interconnections between different bare chips.
  • the molding body is used for wrapping the first pin, the second pin, the first bonding pad and the first substrate, so that the fan-out unit and the first substrate are molded into a unitary structure.
  • the bottoms of the respective first pins of the first pin array for electrically connecting to the periphery of the chip on the bare chip are not covered by the molding body, and thus, the first pins can be directly electrically connected to the periphery of the chip.
  • the pin on the bare chip for electrically connecting to the periphery of the chip can be directly electrically connected to the periphery of the chip without passing through the substrate as an intermediary. Therefore, the overall size of the chip provided by the embodiment of the present application is mainly determined by the size of the plurality of bare chips that are integrated together. Compared with the prior art, the overall size of the chip provided by the embodiment of the present application is small, and the chip can be small. Demand.
  • the chip further includes a second substrate,
  • the second substrate is directly disposed under the molding body by a wiring layer build-up process
  • a second re-wiring layer is disposed on the second substrate, the second substrate includes opposite first and second surfaces, and the second surface of the second substrate is disposed on the second surface
  • An electrically connected second pad array the second pad array includes a plurality of second pads; a second pad array is disposed on the second surface of the second substrate, and the third pad array Including a plurality of third pads;
  • the second pad array is disposed opposite the first pin array, and each of the second pad arrays is electrically connected to a corresponding first tube of the first pin array foot.
  • the electrical connection of the chip to the peripheral circuitry of the chip is no longer limited by the size and arrangement of the pins of the bare chip. Therefore, the chip structure can reduce the limitation of the bare chip pin arrangement to electrically connect the chip to the peripheral circuit of the chip.
  • the inside of the first substrate is provided with a through hole electrically connected to the first re-wiring layer,
  • the through hole extends to a second surface of the first substrate, and the through hole is electrically connected to a periphery of the chip, wherein a second surface of the first substrate is opposite to a first surface of the first substrate.
  • the through hole facilitates signal transmission between the first substrate and the periphery of the chip.
  • the chip further includes: a third portion disposed under the second substrate Substrate
  • the third substrate includes an opposite first surface and a second surface, a first pad array is disposed on the first surface of the third substrate, and a fifth pad is disposed on the second surface of the third substrate An array, the fourth pad array includes a plurality of fourth pads, and the fifth pad array includes a plurality of fifth pads;
  • fourth pad array is opposite to the third pad array, and each of the fourth pad arrays is electrically connected to the third of the third pad arrays Solder pad
  • a fifth pad in the fifth pad array is used to implement signal transmission between the chip and the periphery of the chip.
  • the chip can further increase the routing resources of the chip and the number of pins of the package, improve the power integrity of the package, and improve the board level reliability of the chip.
  • the chip further includes a second surface disposed on the bare chip a heat sink, wherein a second surface of the bare chip is opposite to a first surface of the bare chip.
  • the heat dissipation performance of the chip can be improved.
  • the chip includes a third substrate disposed under the second substrate; A fan-out unit is masked, and an edge of the heat sink is fixed on the third substrate.
  • the second substrate and the third substrate are filled with a filler.
  • the filling effect of the gap between the first pads in the first pad array can be improved, thereby improving the reliability of the chip.
  • the gap is filled with a filler.
  • the stress between the first pin and the second substrate can be alleviated, thereby improving the reliability of the entire chip structure.
  • the material used for fabricating the first substrate is a silicon-based material or a resin material. And at least one of the glass materials. In this eighth possible implementation, the cost of the chip can be reduced.
  • the bare chip is a passive bare chip or a functional bare chip.
  • the second pin includes at least one of a copper post and a solder bump kind.
  • the flexibility of the chip structure can be improved.
  • At least one interconnect structure is formed between different bare chips implementing interconnection
  • Each of the interconnect structures includes a plurality of interconnect lines.
  • the lengths of the interconnect lines in the same interconnect structure are equal.
  • the signal quality and crosstalk between the signals can be improved.
  • the first re-wiring layer includes an n-layer first re-wiring sub- a layer, where n ⁇ 1, and n is an integer.
  • the n ⁇ 2, the n-layer first re-wiring The layer includes a reference layer and a circuit layer, and the plane in which the reference layer is located is the reference plane of the circuit layer.
  • signal quality and crosstalk between signals can be improved.
  • the third substrate is a multilayer substrate prepared by laser grinding or a multilayer substrate prepared by mechanical grinding.
  • the first substrate is provided with a logic chip.
  • a second aspect of the present application provides a chip packaging method, where the chip packaging method includes:
  • the fan-out unit includes a plurality of bare chips arranged in a preset position, and a first pin array is disposed on a first surface of each of the bare chips a second pin array;
  • the first pin array includes a plurality of first pins, the second pin array includes a plurality of second pins; and the second pin arrays on adjacent bare chips are adjacent;
  • the first substrate includes a first surface, and the first surface of the first substrate is provided with a first re-wiring layer and a first pad array electrically connected to the first re-wiring layer, and the first The pad array includes a plurality of first pads;
  • the fan-out unit and the first substrate that are bonded together are molded by using a molding compound to form a molding body that wraps the first pin, the second pin, and the first substrate.
  • the chip includes a fan-out unit, a first substrate, and a molding body.
  • each of the first pads on the first pad array on the first substrate is bonded to the corresponding second pins in the different die and the second pin array on the first substrate, thereby implementing different bare Short distance, high density interconnection between chips.
  • the molding body is used for wrapping the first pin, the second pin and the first substrate, so that the fan-out unit and the first substrate are molded into a unitary structure.
  • the bottoms of the respective first pins of the first pin array for electrically connecting to the periphery of the chip on the bare chip are not covered by the molding body, and thus, the first pins can be directly electrically connected to the periphery of the chip. Therefore, with the chip packaging method provided by the second aspect, the pins on the bare chip for electrically connecting to the periphery of the chip can be directly electrically connected to the periphery of the chip without using the substrate as an intermediary. Therefore, the overall size of the chip fabricated by the method mainly depends on the size of the fan-out unit. Compared with the prior art, the overall size of the chip fabricated by the method is small, which can meet the demand for miniaturization of the chip.
  • the method further includes:
  • a second substrate on a surface exposing the bottom of each of the first pins in the first pin array by a wiring layer build-up process, the second substrate being provided with a second re-wiring layer, the second substrate Including an opposite first surface and a second surface, the first surface of the second substrate is provided with a second pad array electrically connected to the second rewiring layer, and the second pad array comprises a plurality of a second pad; a second pad array is disposed on the second surface of the second substrate, and the third pad array includes a plurality of third pads;
  • the second pad array is disposed opposite to the first pin array, and each of the second pad arrays is electrically connected to a corresponding one of the first pin arrays One pin.
  • the electrical connection of the chip to the peripheral circuitry of the chip is no longer limited by the size and arrangement of the pins of the bare chip. Therefore, the chip structure fabricated by the method can reduce the limitation of the bare chip pin arrangement on the electrical connection between the chip and the peripheral circuit of the chip.
  • the fabricating the surface on the bottom of each of the first pins in the first pin array is exposed
  • the second substrate specifically includes:
  • the dielectric layer is continued to be coated, and then a third pad array composed of a plurality of third pads is formed on the surface of the dielectric layer.
  • the chip structure formed by the embodiment can reduce the bare chip.
  • the pin arrangement limits the electrical connection between the chip and the peripheral circuit of the chip.
  • the chip packaging method further includes:
  • the third substrate includes opposite first and second surfaces, and the first surface of the third substrate is provided with a fourth pad array, and the second substrate is disposed on the second surface There is a fifth pad array, the fourth pad array includes a plurality of fourth pads, and the fifth pad array includes a plurality of fifth pads;
  • the chip packaging method further includes:
  • the electrical connection of the chip to the peripheral circuitry of the chip is no longer limited by the size and arrangement of the pins of the bare chip. Therefore, the chip structure can reduce the limitation of the bare chip pin arrangement to electrically connect the chip to the peripheral circuit of the chip.
  • the placing the third substrate under the second substrate, and making the fourth After bonding each fourth pad in the pad array to the corresponding third pad in the third pad array further includes:
  • a filling glue is filled between the second substrate and the third substrate.
  • the filling effect of the gap between the first pads in the first pad array can be improved, thereby improving the reliability of the chip.
  • the fan-out unit and the first Before the substrate is plasticized also includes:
  • a gap is filled into the gap between each of the first pads in the first pad array.
  • the chip packaging method further includes:
  • a heat sink is disposed on the second surface of the bare chip, wherein a second surface of the bare chip is opposite to the first surface of the bare chip.
  • the chip made by the method has better heat dissipation performance.
  • a seventh possible implementation before the heat sink is disposed on the second surface of the bare chip, also includes:
  • the fan-out unit is ground away from the surface of the second substrate to expose the second surface of the bare chip.
  • the chip packaging method further includes:
  • a heat sink is disposed on a surface of the fan-out unit away from the second substrate, the heat sink shields the fan-out unit, and an edge of the heat sink is fixed on the third substrate.
  • the method can not only improve the heat dissipation performance of the chip, but also control the warpage of the entire chip structure and the reliability of the chip.
  • each of the first pads on the first pad array on the first substrate and the second pin array on the different bare chips The two pins are glued together to achieve short-distance, high-density interconnection between different bare chips.
  • the molding body is used for wrapping the first pin, the second pin, the first bonding pad and the first substrate, so that the fan-out unit and the first substrate are molded into a unitary structure.
  • the bottoms of the respective first pins of the first pin array for electrically connecting to the periphery of the chip on the bare chip are not covered by the molding body, and thus, the first pins can be directly electrically connected to the periphery of the chip.
  • the pin on the bare chip for electrically connecting to the periphery of the chip can be directly electrically connected to the periphery of the chip without passing through the substrate as an intermediary. Therefore, the overall size of the chip provided by the embodiment of the present application is mainly determined by the size of the plurality of bare chips that are integrated together. Compared with the prior art, the overall size of the chip provided by the embodiment of the present application is small, and the chip can be small. Demand.
  • FIG. 1 is a schematic cross-sectional view of a fan-out wafer level package structure commonly used in the art
  • FIG. 2 is a cross-sectional view showing another fan-out wafer level package structure commonly used in the art
  • 3A is a schematic cross-sectional view of a chip according to an embodiment of the present application.
  • FIG. 3B is a schematic diagram of a fan-out unit in a chip according to an embodiment of the present application.
  • FIG. 4 are respectively a schematic cross-sectional view and a plan view of a chip according to an embodiment of the present application;
  • FIG. 5 is a schematic structural view of a first surface of a bare chip according to an embodiment of the present application.
  • FIG. 6A to FIG. 6C are schematic diagrams showing interconnection structures between bare chips according to an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of another chip according to an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of still another chip provided by an embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional view of still another chip provided by an embodiment of the present application.
  • FIG. 10A is a schematic cross-sectional view of still another chip according to an embodiment of the present application.
  • FIG. 10B is a schematic structural view of a first surface of a second substrate according to an embodiment of the present application.
  • FIG. 11 are respectively a schematic cross-sectional view and a plan view of a chip according to an embodiment of the present application.
  • FIG. 12 is a schematic cross-sectional view of still another chip according to an embodiment of the present application.
  • FIG. 13 is a top view of still another chip according to an embodiment of the present application.
  • FIG. 14 is a schematic flowchart of a chip packaging method according to an embodiment of the present disclosure.
  • FIG. 15A1 to FIG. 15D are respectively schematic structural diagrams of a series of processes for a chip packaging method according to an embodiment of the present application.
  • 16 is a schematic flow chart of another chip packaging method according to an embodiment of the present application.
  • FIG. 17 is a cross-sectional structural diagram of a third substrate according to an embodiment of the present application.
  • the fan-out wafer-level package allows the I/O pins of a single chip to be pulled out through the rewiring layer on the wafer, increasing the individual package area and increasing the overall I/O pin count.
  • the design difficulty is not only lower than the through-silicon via 3DIC, but the package structure is close to 2.5D IC. Therefore, the fan-out wafer level package is expected to become the development point of advanced packaging technology.
  • the fan-out package structure is a 2.5D FOP package structure combining a conventional fan-out wafer level package and flip chip package (Flip Chip).
  • the packaging process of the package structure is as follows: First, a plurality of bare chips 10 and 11 to be integrated are placed side by side on the carrier at a certain pitch and position, and the size of the carrier can be the same as the original size of the wafer; then the molding compound 12 is used. The plurality of bare chips 10 and 11 to be integrated are molded to form a reconstructed wafer. Rewiring is then performed on the reconstituted wafer by preparing a fan-out wiring layer 13 on the front side of the bare chip on the reconstituted wafer, and the fan-out wiring layer 13 can be bare through the high-density interconnect structures 14 and 15.
  • the I/O pins on the chips 10 and 11 are electrically extended to areas other than the bare chips 10 and 11, so that the electrical connection between the bare chip and the PCB board 16 is not limited to the size of the bare chips 10 and 11 and Arrange.
  • the package structure shown in FIG. 1 adopts a wafer-level process process, so that packaging and testing can be completed on the wafer.
  • the package structure can effectively increase the number of package pins, and can solve advanced process nodes and higher chip function pairs. More pin count requirements.
  • the 2.5D FOP package enables integrated packaging of multiple bare chips and enables short-distance high-density interconnection between bare chips through a fan-out wiring layer without the need to pass through the substrate.
  • this package structure has the following disadvantages:
  • the interconnection between the bare chips 10 and 11 is achieved by fan-outing the wiring layer 13.
  • the reconstructed wafer is affected by photolithography, exposure, and development processes, resulting in uneven stress, warpage, and even warpage.
  • the deformation, and the bare chips on the reconstructed wafer are all tested qualified bare chips. If defects occur in the subsequent fan-out wiring layer 13 preparation process, the qualified bare chips are also wasted at the same time, resulting in an increase in cost.
  • the fan-out wiring layer prepared on the reconstituted wafer can only achieve a line width and a line pitch of only 2 ⁇ m, and the process is difficult to implement, thus limiting the chip interconnect density and the integrity of the chip signal and power supply. .
  • the fan-out package structure is a 2.5D TSV package structure combined with a silicon interposer with a through silicon via and a flip chip package.
  • the fan-out package structure is shown in FIG. 2 .
  • the packaging process of the fan-out package structure is as follows:
  • a through silicon via 211 is first formed on a silicon wafer, and a single or multiple layer rewiring layer 212 is formed on the surface of the silicon wafer to form a silicon interposer 21 for signal connection.
  • the plurality of bare chips 22 and 23 to be integrated are then placed on the front surface of the silicon interposer 21 in a pre-designed position, and then the bare chips 22 and 23 are soldered on the front surface of the silicon interposer 21 by a soldering process.
  • the I/O pins on the bare chip are fanned out onto the package substrate 24 through the rewiring layer 212 and the through silicon vias 211 on the silicon interposer 21, and the different bare chips are formed by the rewiring layer 212. Even structure.
  • the 2.5D TSV package structure shown in Figure 2 uses silicon interposer and TSV technology to interconnect different bare chips on a silicon wafer.
  • the use of mature semiconductor manufacturing processes and silicon materials to achieve very small linewidth and line spacing currently the minimum line width and line spacing of silicon interposers are 0.4 ⁇ m), greatly improving the signal interconnection density between chips, shortening the signal walking Line distance.
  • this package structure has the following drawbacks:
  • the plurality of bare chips to be integrated need to be soldered on the silicon interposer.
  • the size of the silicon interposer needs to be larger than the sum of the sizes of all the bare chips, and the consumables are high.
  • the embodiment of the present application provides a chip.
  • the specific structure of the chip is a 2.5D substrate bridge fan-out type package structure.
  • the chip includes:
  • the substrate 108, the fan-out unit 111, and the wiring layer 104, the fan-out unit 111 includes a first chip 101 and a second chip 102.
  • the structure of the fan-out unit 111 is schematically represented, in which hidden lines (lines invisible in the view direction) are indicated by broken lines.
  • the first chip 101 includes a first pin array A1, wherein the first pin array A1 includes a plurality of first pins 32a, and the second chip 102 includes a second pin array A2, wherein the second pin array A2 includes a plurality of second pins 32b.
  • the fan-out unit 111 further includes a third pin array A3, the third pin array A3 includes a plurality of third pins 41, the first pin array A1, the second pin array A2, and the The third pin A3 array is disposed facing the substrate 108.
  • the surface of the first chip 101 and the second chip 102 facing the substrate 108 is defined as a front surface, and the opposite surface is defined as a back surface, and the first pin array A1, the second pin array A2, and the third pin array A3 are distributed. On the front side of the first chip 101 and the second chip 102.
  • the first chip 101 and the second chip 102 are disposed adjacent to each other, the first pin array A1 is disposed adjacent to the second pin array A2, and the third pin array A3 is distributed in the fan-out unit.
  • the adjacent arrangement of the first chip 101 and the second chip 102 indicates that the first chip 101 and the second chip 102 have no other chips to separate the two.
  • the wiring layer 104 is connected across the first pin array A1 and the second pin array A2 for the first one of the first pin arrays A1.
  • the pin 32a is connected to the corresponding second pin 32b of the second pin array A2 to realize electrical connection between the first chip 101 and the second chip 102 without providing a through hole structure
  • the interposer and because the fabrication process of the wiring layer 104 is simple (achievable by a conventional build-up process), the cost is also low; and the direct connection of the third pin array A3 to the substrate 108 causes the fan-out unit 111
  • the connection to the substrate 108 does not require the provision of a large-area interposer, and the process of making vias in the interposer is also omitted. Therefore, the chip shown in FIG. 3A has the advantages of low process difficulty and low cost.
  • the third pin in the third pin array A3 on the fan-out unit 111 needs to be connected to the periphery of the chip through the substrate 108.
  • the components that affect the overall size of the chip include the fan-out unit 111 and the substrate 108, which results in a large overall size of the chip, which cannot meet the demand for miniaturization of the chip.
  • the embodiment of the present application provides another structure of the chip.
  • FIG. 4 is a schematic cross-sectional view of a chip structure according to an embodiment of the present application
  • FIG. 4' is a top view of a chip structure according to an embodiment of the present application.
  • a chip provided by an embodiment of the present application includes:
  • Fan-out unit 31 first substrate 32 and molding body 33;
  • the fan-out unit 31 includes a plurality of bare chips 341 and 342 which are integrated together in a predetermined position.
  • the plurality of bare chips integrated together may be two bare chips, or may be two or more bare chips.
  • the embodiment of the present application is described by taking two bare chips to be integrated as an example.
  • the bare chips 341 and 342 may be integrated together by a molding process using a molding compound to form a fan-out unit 31.
  • the embodiment of the present application further provides a schematic diagram of the first surface structure of the bare chips 341 and 342, as shown in FIG. 5.
  • a first pin array C1 and a second pin array C2 are disposed on the first surface of the bare chip 341 or 342; the first pin array C1 includes a plurality of first pins 351, and the second pin array C2 includes a plurality of a second pin 352; adjacent to the second pin array C2 on the adjacent bare chip;
  • the first substrate 32 includes a first surface, and the first surface of the first substrate 32 is provided with a first re-wiring layer 321 and a first pad array electrically connected to the first re-wiring layer 321 , the first pad array including A plurality of first pads 322.
  • the first surfaces of the bare chips 341 and 342 are opposite to the first surface of the first substrate 32, and the first substrate 32 is located below the fan-out unit 31, and the first pad array and the first
  • the two pin arrays C2 are oppositely disposed, and each of the second pins 352 of the second pin array C2 is attached to the corresponding first pad 322 of the first pad array, thereby Interconnection is achieved between the bare chips 341 and 342 through the first wiring layer 321 on the first substrate 32.
  • the molding body 33 is used to wrap the first pin 351, the second pin 352, the first pad 322, and the first substrate 32, thereby molding the fan-out unit 31 and the first substrate 32 into a unitary structure.
  • the molding body 33 is formed by the molding process after the first pad array on the first substrate 32 and the second pin array C2 of the bare chips 341 and 342 are bonded together.
  • the molding process may specifically be a compression mold process. Therefore, the molding body 33 wraps at least the side surface of the first pin 351, the side surface of the second pin 352, the side surface of the first pad 322, and the side surface of the first substrate 32.
  • the molding body 33 does not wrap the bottom of each of the first pins 351, that is, each The bottom of the first pin 351 is exposed outside the molded body 33.
  • the molding body 33 may wrap the back surface of the first substrate 32 in addition to the side surface of the first substrate 32, so that the area where the first pin array is molded together and the first substrate 32.
  • the area in which it is located is a flat surface structure, that is, the surface of the integral structure formed by the plastic seal is a flat surface.
  • the structure composed of the fan-out unit 31 and the first substrate 32 that are bonded together has no structural protection, so the structural stability is low, and the possibility of working alone is low.
  • the molded body 33 is based on this.
  • the side surface of the first pin 351, the side of the second pin 352, and the side of the first pad 322 are wrapped, so that the service life and reliability of the entire chip can be improved, and the mechanical strength of the molded body 33 is stabilized due to the structure. High, can strongly support the overall structure to work and work alone.
  • the overall structure formed by molding the fan-out unit 31 and the first substrate 32 by a compression molding process can be stably operated alone, or an RDL carrier plate can be formed thereon as needed, or bonded to the substrate as needed. , to form a larger package structure.
  • the bottoms of the respective first pins 351 may be provided with solder balls 36, and each solder ball 36 may be connected to an external circuit such as a PCB.
  • the board is electrically connected.
  • a pad 37 may be disposed between each of the first pin 351 and the solder ball 36.
  • the composition of the molding compound for forming the molded body 33 is different from that of the prior art underfill.
  • the molding compound and the filling compound are obtained by adding different additives to the epoxy resin molding compound (Epoxy Molding Compound).
  • the molded body 33 formed of a molding compound in the embodiment of the present application is generally realized by a compression molding process.
  • This compression molding process is very different from the glue dispensing process.
  • the compression molding process can be divided into two types, one is a face-up type, and the other is a face-down type.
  • the perfusion type is to place the molded structure under the flowing molding compound, the flowing molding compound flows downward, is poured on the molded structure, and then the infused structure is pressed by the mold.
  • the immersion type is to place the molded structure over the container containing the flowing molding material, and then immerse the molded structure into the container containing the flow molding compound, and then the molded structure is removed from the container.
  • the compression molding process can fill and solidify a large number of chips on the entire wafer at one time, and does not need to be filled one by one for a single chip, and the overall efficiency is high.
  • the curing of the compression molding process is divided into initial curing in a pressed state and completion of pressing and then placed in a heating furnace to complete final curing.
  • the filling glue dispensing process is specifically: when filling with the filling glue, all the chips on the whole wafer need to be glued one by one, and the dispensing position is at the four edges of each chip, which is filled by capillary action.
  • the glue is attracted to fill the gap between the chip and the substrate or other dielectric material to complete the filling process.
  • the filled structure is placed in a heating furnace to complete final curing. Therefore, the filling process takes a long time and the filling efficiency is low.
  • the fan-out unit 31 and the first substrate 32 are required.
  • the structure of the composition is connected to other structures such as a substrate, and the structure of the fan-out unit 31 and the first substrate 32 filled with the molding compound in the present application can be performed before the structure is connected to other structures such as the substrate.
  • the chip includes a fan-out unit 31, a first substrate 32, and a molding body 33.
  • the first pads 351 on the first pad array C1 on the first substrate 32 are bonded to the corresponding second pins 352 in the second pin array C2 on the different bare chips 341 and 342. Together, to achieve short-distance, high-density interconnections between different bare chips.
  • the molding body 33 is used to wrap the first pin 351, the second pin 352, and the first substrate 32, thereby molding the fan-out unit 31 and the first substrate 32 into a unitary structure.
  • the bottoms of the first pins of the first pin array C1 for electrically connecting to the periphery of the chip on the bare chip are not wrapped by the molding body 33, so that the first pins can be directly electrically connected to the chip. periphery. Therefore, with the chip provided by the embodiment of the present application, the pin on the bare chip for electrically connecting to the periphery of the chip can be directly electrically connected to the periphery of the chip without using the substrate as an intermediary. Therefore, the overall size of the chip provided by the embodiment of the present application is mainly determined by the size of the fan-out unit. Compared with the prior art, the overall size of the chip provided by the embodiment of the present application is small, which can meet the requirement of miniaturization of the chip.
  • the manner in which the bare chips 341 and 342 are interconnected by the first substrate 32 is also advantageous for miniaturization of the chip.
  • the first substrate 32 can be fabricated independently, and does not need to be directly fabricated on the fan-out unit 31. Therefore, if a defect occurs in the manufacturing process of the first substrate 32, the discarded bare chip is not discarded. Reduced packaging costs.
  • the size of the first substrate 32 can satisfy the bonding with the second pin 352 on the bare chip, and does not need to be greater than or equal to the sum of the sizes of all the integrated bare chips. Therefore, the embodiment of the present application can reduce the consumables of the first substrate 32, thereby greatly reducing the packaging cost. In addition, such a design is also advantageous for miniaturization of the chip.
  • the line width and the line pitch of the first re-wiring layer on the first substrate 32 can reach 0.4 ⁇ m. Therefore, the line width and the line pitch are small, and the manufacturing process is relatively simple.
  • the molding body 33 and the fan-out unit 31 may be an integrally formed structure, and thus, the molding body 33 and the fan-out unit 31 may be obtained by compression molding from the same molding process.
  • the molding body 33 and the fan-out unit 31 may also be a separate structure, and thus, the molding body 33 and the fan-out unit 31 are obtained by compression molding of different molding processes.
  • the embodiment of the present application further provides mutual mutual between the bare chips 341 and 342. Even structure. The details are shown in FIG. 6A and FIG. 6B, respectively.
  • the first re-wiring layer 321 is configured to include a three-layer rewiring sub-layer, which may be a first re-wiring sub-layer, a second re-wiring sub-layer, and a third re-wiring sub-layer, respectively.
  • a three-layer rewiring sub-layer which may be a first re-wiring sub-layer, a second re-wiring sub-layer, and a third re-wiring sub-layer, respectively.
  • 6A and 6B wherein the first rewiring sublayer and the third rewiring sublayer are used to implement interconnection of the bare chips 341 and 342, and the plane of the second rewiring sublayer is used as a bare
  • the reference plane of the rewiring sublayer of the interchip interconnect can improve signal quality and improve crosstalk between signals.
  • the first interconnect structure 51 may be formed by the first rewiring sublayer
  • the second interconnect structure 52 may be formed by the third rewiring sublayer.
  • the second pin array on the bare chip 341 includes a first pin group 511a for forming the first interconnect structure 51 and a second pin for forming the second interconnect structure.
  • the second pin array on bare die 342 includes a first pin set 511b for forming a first interconnect structure 51 and a second pin set 512b for forming a second interconnect structure.
  • At least one interconnect structure may be formed between different bare chips, and each interconnect structure may include at least one interconnect line.
  • each interconnect structure may include at least one interconnect line.
  • the lengths of the plurality of interconnect lines belonging to the same interconnect structure may be equal or unequal.
  • the lengths of the interconnection lines in the same interconnect structure are equal. Specifically, as shown in FIG.
  • the electrical connection structure columns in the same electrical connection structure group are sequentially named as the first column, the second column, and the third column in the order from left to right, according to the top-down
  • the electrical connection structure lines are sequentially named in the order of the first row, the second row, and the seventh row.
  • the first interconnect structure 51 the first row of electrical connection structures in the first pin group 511a are connected as shown in FIG. 6C.
  • the first row and the first row of pads in the first pin group 511a are connected to the first row and the first column of the first pin group 511b, and the first row and the second column of the first pin group 511a are solder joints.
  • the first row and the second row of pads in the first pin group 511b are connected, and the first row and the third row of pads in the first pin group 511a are connected to the first row and the third column in the first pin group 511b. point.
  • the electrical connection structure on the other rows is connected in the same manner as the electrical connection structure on the first row. I will not repeat them here.
  • the first re-wiring layer 321 may be a single-layer wiring layer or a multi-layer wiring layer according to the needs of the package structure design.
  • the first rewiring layer includes a plurality of first rewiring sublayers, for the signal quality and the crosstalk between the signals is improved, the plane in which any one of the first rewiring sublayers is located is set as the other first rewiring sublayer.
  • the reference plane, the other first rewiring sublayers are used to form an interconnect structure between different bare chips.
  • the multilayer wiring layer includes a reference layer and a wiring layer, wherein a plane in which the reference layer is located serves as a reference plane of the wiring layer.
  • the circuit layer is used to form an interconnection structure between different bare chips.
  • an insulating dielectric layer may be disposed between the different first rewiring sublayers, and the insulating dielectric layer may be an organic dielectric layer.
  • the insulating dielectric layer may be a dielectric layer made of a polymer material.
  • the polymeric material can be a PI, PBO or epoxy based polymer.
  • the minimum size of the via or via region on the dielectric layer can be 5 um/10 um or less.
  • the first re-wiring layer 321 on the first substrate 32 and the first pad 322 in the first pad array are respectively in the second pin array C2 on the bare chips 341 and 342.
  • An interconnection structure is formed between the second pins 352, thereby achieving interconnection of the bare chips 341 and 342.
  • the first re-wiring layer 321 on the first substrate 32 is like a bridge connecting the bare chip 341 and the bare chip 342, so the first substrate 32 can be referred to as a bridge substrate.
  • the cross-sectional dimension of the first substrate 32 only needs to meet the bonding of the second pin array of the bare chips 341 and 342, and does not need to be larger than the multiple bare chips to be integrated. Total size. Therefore, the consumables of the chip provided by the implementation of the present application are low.
  • the spacing between the bare chips should be as small as possible under the conditions of the process conditions, for example, between bare chips.
  • the pitch can be 50 ⁇ m or less.
  • the sides of the bare chips 341 and 342 are wrapped by the molding compound.
  • the epitaxial width of the outermost molding compound of the bare chips 341 and 342 can be flexibly designed, and generally can be less than 5 mm. . That is to say, the outermost molding compound of the fan-out unit 31 can be extended to a certain width in the thickness direction of the bare chip as needed, thereby simplifying the design and the number of layers of the substrate.
  • the bare chips 341 and 342 may be passive bare chips or functional bare chips. More specifically, the bare new films 341 and 342 can be homogenous or heterogeneous, for example, the integration of analog bare new films and digital bare new films, the integration of bare new films of different process nodes, the integration of different functions of bare new films, and the overlapping of different numbers of bare new films. After the integration. In addition, the bare chips 341 and 342 may also be stacked bare chips.
  • the first pin 351 is used to lead the I/O pins on the bare chip to the periphery of the chip, and the second pin 352 is used to realize the interconnection between different bare chips. Therefore, in order to facilitate pin and soldering The connection between the pads, as yet another alternative embodiment of the present application, the size of the first pin 351 is greater than the size of the second pin 352. More specifically, the height of the first pin 351 is greater than the height of the second pin 352, and the cross-sectional dimension of the first pin 351 is also greater than the cross-sectional dimension of the second pin 352.
  • a spacing between adjacent two first pins 351 is a first spacing d1
  • adjacent two The spacing between the two pins 352 is a second spacing d2
  • the first spacing d1 can be greater than the second spacing d2 to more facilitate the connection between the corresponding pins and the pads.
  • the first pad in the first pad array is used to connect with the second pin in the second pin array. Therefore, as an optional embodiment of the present application, a single The cross-sectional dimension of the first pad may be the same as the cross-sectional dimension of the single second pin.
  • the first pin 351 can be a Cu pillar and the second pin 352 can be a solder bump.
  • the first pad 322 may be in various forms of electrical connection structures.
  • it may be a solder bump, a protruding metal interface or a flat metal disk.
  • the solder bumps may be solder solder bumps.
  • first pin 351 and second pin 352 are not limited to the specific pin structures of the above examples.
  • first pin 351 is not limited to a copper post
  • second pin 352 is not limited to a solder bump.
  • the first pin 351 may be composed of at least one of a copper post and a solder bump.
  • the second pin 352 can also be composed of at least one of a copper post and a solder bump.
  • each of the first pins 351 includes a copper pillar portion 3511 and a solder bump portion 3512 which are connected to each other. It should be noted that since the first pin 351 has a large size, the first pin 351 adopts a structure composed of the interconnected copper post portion 3511 and the solder bump portion 3512, which facilitates the preparation of the first pin 351.
  • the gap between the first pads in the first pad array is small, if the molding compound is used to fill the gap by using a molding compound, the The problem of the gap filling effect is poor, in order to improve the filling effect of the gap between the first pads in the first pad array, and further improve the reliability of the chip, as shown in FIG. 8 , in the embodiment of the present application, different The gap between the first pads 322 is filled with a filler 71.
  • the package structure shown in FIG. 8 is substantially the same as the chip structure shown in FIG. 4, except that the chip structure shown in FIG. 8 includes each of the first pads filled in the first pad array. Filler 71 in the gap between 322.
  • the material used to fabricate the first substrate 32 may be any dielectric material such as a silicon-based material, a resin material, and a glass material. More specifically, the first substrate 32 may be a silicon substrate. Further, the first substrate 32 may be a substrate processed by a fan-out rewiring layer technique. In this specific example, the first substrate 32 may be usually made of a resin material and The electroplating copper technology was completed. In addition, the first substrate 32 may also be surface-made with a glass substrate having an interconnection circuit, wherein the interconnection circuit may be processed on the surface of the glass material by an etching and electroplating process. It should be noted that, in the embodiment of the present application, the line width and the line pitch of the first re-wiring layer formed on the first substrate 32 can reach 0.4 ⁇ m.
  • the first substrate 32 functions to implement a bare chip interconnection, and only a rewiring layer and an electrical connection structure for implementing bare die interconnection are disposed thereon.
  • the inside of the first substrate 32 may also be provided with the first
  • the rewiring layer 321 is electrically connected to the through hole 323, and the through hole 323 extends to the second surface of the first substrate 32.
  • the second surface of the first substrate 32 is opposite to the first surface of the first substrate 32.
  • the through hole 323 can be electrically connected to the circuit on the periphery of the chip, and thus, the power of the periphery of the chip can be transmitted to the first rewiring layer 321 through the first through hole 323 through the through hole 323.
  • a logic chip may also be disposed on the first substrate 32.
  • a logic layer (not shown in FIG. 9) may be disposed inside the logic chip, and the logic layer is electrically connected to the via 323.
  • the logic layer and the outside world can be realized through the through hole 323. Signal transmission between. That is, the via 323 can extract the signal on the logic layer to the second surface of the first substrate 32 and perform signal transmission with the outside.
  • the chips described in the above embodiments lead the I/O pins of the bare chip to the peripheral area of the chip through the respective first pins 351 of the first pin array disposed on the first surface of the bare chip. In this way, the miniaturization of the chip can be realized, thereby meeting the miniaturization demand of the terminal consumer chip.
  • the pitch of the pins on the bare chip becomes smaller and smaller, which makes it difficult to directly connect the pins on the bare chip to the peripheral circuits of the chip. That is to say, for the chip structure in which the bare chip pin is directly connected to the chip peripheral circuit, the electrical connection with the chip peripheral circuit is limited by the size and arrangement of the pins of the bare chip.
  • the electrical connection between the chip and the peripheral circuit of the chip is not limited to the size and arrangement of the pins on the bare chip.
  • a substrate for directly electrically connecting the pins on the bare chip may be added under the molding body, as specifically shown in FIG. 10A.
  • the chip shown in FIG. 10A is improved on the basis of the chip shown in FIG. 4 described above.
  • FIG. 10A another specific implementation manner of the chip provided by the embodiment of the present application may include:
  • the second substrate 91 is directly disposed under the molding body 33 by a wiring layer build-up process
  • a second re-wiring layer (not shown) is disposed on the second substrate 91, and the second substrate 91 includes opposing first and second surfaces for clearly understanding the first surface of the second substrate 91.
  • Structures of the present application also provide a schematic diagram of a first surface structure of the second substrate 91.
  • the second surface of the second substrate 91 is provided with a second pad array electrically connected to the second rewiring layer, and the second pad array includes a plurality of second pads 911.
  • the second pad 911 may be a metal bump or a metal pad, or may be a protruding metal interface. Wherein, the metal bumps may be solder solder bumps.
  • the second rewiring layer may include a plurality of rewiring layers, and the multilayer rewiring layer may be uniformly distributed throughout the entire thickness of the second substrate 91. As such, the second rewiring layer may be distributed not only on the first surface of the second substrate 91 but also on the inside of the second substrate 91.
  • a second pad array is disposed on the second surface of the second substrate 91.
  • the third pad array includes a plurality of third pads 912.
  • the third pad 912 is used for The electrical connection between the chip and the peripheral circuit of the chip is realized.
  • the third pad 912 can be a metal solder ball.
  • the second pad array is opposite to the first pin array, and each second pad 912 of the second pad array is electrically connected to the corresponding first pin of the first pin array. 351.
  • each of the first pins 351 of the first pin array on the bare chips 341 and 342 is first electrically connected to a corresponding one of the second pad arrays on the second substrate 91.
  • each of the third pads in the third pad array on the second substrate 91 is electrically connected to the chip peripheral circuit.
  • the first pins 351 on the bare chips 341 and 342 are electrically connected to the chip peripheral circuits through the second substrate 91.
  • the density between the third pads 912 thereon can be smaller than the density of the first pins 351 on the bare chip, and thus, compared to the bare chip 341 and The first pin 351 on the 342, the third pad 912 on the second substrate 91 can be electrically connected to the chip peripheral circuit by a soldering process. Therefore, even the high pin is included on the chip provided by the embodiment of the present application.
  • the bare chip of the density can also conveniently realize the electrical connection between the bare chip and the peripheral circuit of the chip. Therefore, in the chip shown in FIG. 10A, the electrical connection with the peripheral circuit of the chip is no longer limited by the pins of the bare chip.
  • the size and arrangement. Therefore, the chip structure can reduce the limitation of the bare chip pin arrangement to electrically connect the chip to the peripheral circuit of the chip.
  • the first substrate 32 may be in contact with the second substrate 91.
  • the first substrate 32 may not be in contact with the second substrate 91, and there is a certain gap between the first substrate 32 and the second substrate 91, that is, the first substrate 32 is suspended on the second substrate.
  • the thickness of the first substrate 32 is not particularly limited as long as the first substrate 32 can be placed between the fan-out unit 31 and the second substrate 91.
  • the cross-sectional dimension of the second substrate 91 may be equivalent to the cross-sectional size of the fan-out unit 31. In this way, the miniaturization of the package structure can be realized to meet the miniaturization requirements of the terminal consumer chip.
  • the second substrate 91 may be directly formed on the surface of the molding body 33 away from the fan-out unit 31. Specifically, by coating a dielectric layer, such as a PI/PBO material, on the surface of the molding body 33 away from the fan-out unit 31, and then growing a copper conductive line on the surface of the dielectric layer, layer by layer until the second rewiring layer is completed. While the second rewiring layer is being formed, a second pad array corresponding thereto is formed at a position opposite to the first pin array. After the second rewiring layer and the second pad array are fabricated, the dielectric layer is continued to be coated, and then a third pad array composed of a plurality of third pads 912 is formed on the surface of the dielectric layer.
  • a dielectric layer such as a PI/PBO material
  • the I/O pins on the bare chip are led out to the peripheral area of the chip through a second substrate 91 to realize electrical connection with the PCB board.
  • the second substrate 91 can provide a large circuit design space for facilitating electrical connection between the chip and the peripheral circuits of the chip.
  • the embodiment of the present application further provides another specific implementation manner of the chip.
  • FIG. 11 is a cross-sectional view of another chip according to an embodiment of the present application
  • FIG. 11 is a top view of another chip structure according to an embodiment of the present application.
  • the chip structure shown in Fig. 11 and Fig. 11' is improved on the basis of the chip structure shown in Fig. 10A described above.
  • FIG. 11 and FIG. 11 ′ another specific implementation manner of the chip structure provided by the embodiment of the present application may include, in addition to the components described in the foregoing specific implementation manners,
  • the third substrate 101 disposed under the second substrate 91, the third substrate 101 includes opposite first and second surfaces, and the first surface of the third substrate 101 is provided with a fourth pad array, the third A fifth pad array is disposed on the second surface of the substrate 101, the fourth pad array includes a plurality of fourth pads 1011, and the fifth pad array includes a plurality of fifth pads 1012.
  • the fourth pad array is opposite to the third pad array, and each of the fourth pads 1011 is electrically connected to the third pad 912 in the third pad array. ;
  • the fifth pad 1012 in the fifth pad array is used to implement signal transmission between the chip and the periphery of the chip.
  • the fourth pad 1011 may be a metal bump
  • the fifth pad 1012 may be a metal solder ball.
  • the metal solder ball may be a solder ball and connected to the PCB by soldering.
  • the fifth pad 1012 may also be a metal pad that is connected to the PCB board of the peripheral area by a socket.
  • the cross-sectional dimension of the third substrate 101 may be larger than the cross-sectional size of the fan-out unit 31.
  • the cross-sectional dimension of the third substrate 101 may also be equal to the cross-sectional size of the fan-out unit 31.
  • the I/O pins on the bare chip are led out to the peripheral region of the chip through the second substrate 91 and the third substrate 101.
  • the I/O pins on the bare chip are taken out through the two substrates, thereby increasing the wiring resources of the chip structure and the number of pins of the package, improving the power integrity of the package, and improving the chip structure. Board level reliability.
  • the chip structure shown in FIG. 11 may further include padding.
  • the embodiment of the present application further provides another specific implementation manner of the chip structure.
  • the package structure shown in FIG. 12 may include: in addition to the components of the package structure shown in FIG.
  • the fins 111 are disposed on the second surfaces of the bare chips 341 and 342, wherein the second surfaces of the bare chips 341 and 342 are opposed to the first surfaces of the bare chips 341 and 342.
  • the heat sink 111 may be bonded to the second surfaces of the bare chips 341 and 342 through the thermal conductive paste, thereby providing a good heat dissipation path for the chip with high power consumption.
  • each bare chip is not wrapped by the molding compound, and if the heat dissipation requirement is met, each bare chip The second surface can also be wrapped by a molding compound. It should be noted that if the bare chip has less power and generates less heat, the second surface of each bare chip can also be wrapped by the molding compound.
  • the heat sink 111 it is also possible to be connected to the third substrate 101. More specifically, the heat sink 111 may be bonded to the front surface of the third substrate 101 by an adhesive.
  • the heat sink 111 may be a unitary structure or a split structure.
  • the heat sink 111 may have a cap structure or a curved structure.
  • the heat sink 111 masks the fan-out unit 31, and the edge of the heat sink 111 is fixed on the third substrate 101.
  • FIG. 13 shows a top view of a fan-out wafer level package with four bare chips integrated. As shown in FIG. 13, the integrated four bare chips 341 to 344 are interconnected by the first substrate 32.
  • the embodiment of the present application further provides a specific implementation manner of the chip packaging method. See the following examples for details.
  • a method for packaging a fan-out wafer level package structure includes the following steps:
  • the implementation of the fan-out unit 31 may specifically include the following steps:
  • A1 The original wafer of the bare chip is thinned according to the design requirements, and then the thinned wafer is cut into a single bare chip.
  • a first pin window array and a second pin window array are disposed on the first surface of each bare chip, wherein the first pin window array includes a plurality of first pin windows spaced apart by a first pitch d1
  • the second pin window array includes a plurality of second pin windows spaced apart by a second pitch d2.
  • the size of the first pin window is larger than the size of the second pin window, and the first spacing d1 is greater than the second spacing d2.
  • A2 The plurality of bare chips 341 and 342 to be integrated are placed on the temporary carrier 140 in a preset position.
  • a plurality of bare chips 341 and 342 to be integrated are placed on the temporary carrier 140 in a predetermined position according to design requirements.
  • the size of the temporary carrier 140 may be the same as the size of the original wafer.
  • the temporary carrier 140 may be a film material layer, and the film material layer may be a film made of a resin material.
  • the spacing between bare chips should be as small as possible, as the process conditions allow, for example, the spacing between bare chips can be 50 ⁇ m or less.
  • the sides of the bare chips 341 and 342 are wrapped by the molding compound.
  • the epitaxial width of the outermost molding compound of the bare chips 341 and 342 can be flexibly designed, and generally can be less than 5 mm. That is to say, the outermost molding compound of the fan-out unit 31 can be extended by a certain width in the thickness direction of the bare chip, so that the design and the number of layers of the substrate can be simplified.
  • A3 A plurality of bare chips 341 and 342 placed on the temporary carrier 140 are molded with a molding compound to form a fan-out unit 31.
  • the plurality of bare chips molded together are removed from the temporary carrier, and the plurality of bare chips molded together form a fan-out unit.
  • the fan-out unit 31 is formed as shown in Fig. 15A2, in which the side surface of each bare chip is wrapped by the molding compound 141.
  • the front side of each bare chip is not covered by the molding compound, that is, the front side of each bare chip is exposed, so that the array of the first pin window and the second pin window array of each bare chip are exposed.
  • A4 forming a first pin 351 in each first pin window of the first pin window array of each bare chip, thereby forming a first pin array C1, and a second pin window in each bare chip
  • the second pin 352 is formed to form the second pin array C2.
  • a first pin 351 is formed in each first pin window of the first pin window array of each bare chip, thereby forming a first pin array C1, in each bare chip
  • a second pin 352 is formed in the two pin windows to form a second pin array C2.
  • the first pin 351 can be a copper post and the second pin 352 can be a solder bump.
  • first pin 351 in each of the first pin windows and before forming the second pin 352 in each of the second pin windows, it is also required on the surface of each of the first pin windows.
  • An under bump metal is formed on the surface of each of the second pin windows.
  • first substrate 32 A specific implementation of the first substrate 32 will be described below. It should be noted that the first substrate 32 may be provided with a through hole for signal transmission with the outside world, or may not be provided with a through hole for signal transmission with the outside, and the specific implementation manner of the first substrate 32 will be separately described below. .
  • a specific implementation of the first substrate 32 that is not provided with a through-hole for signal transmission is described.
  • the implementation of the first substrate 32 may specifically include the following steps:
  • the original wafer surface is divided into a first region and a second region according to the design requirements of the package structure.
  • each under bump metal can be fabricated in the second region by electroplating or ball placement.
  • the first pad 322 may be 322, which may be a copper pillar or a metal bump.
  • a schematic cross-sectional view of the formed single first substrate 32 is shown in Fig. 15A4.
  • the implementation of the first substrate 32 may include the following steps:
  • B'1 The front side of the original wafer is divided into a first area and a second area according to the design requirements of the package structure.
  • a first re-wiring layer 321 is formed in the first region of the original wafer, and then each bump under-metal is fabricated in the second region of the original wafer, and a first pad 322 is formed over the metal under each bump. Thereby forming a first pad array.
  • each under bump metal can be fabricated in the second region by electroplating or ball placement.
  • the first pad may be 322, which may be a copper pillar or a solder bump.
  • a via hole is formed inside the original wafer, and the via hole is electrically connected to the first re-wiring layer 321 .
  • a via hole can be formed inside the original wafer by the TSV process.
  • B'4 A metal pad electrically connected to the via hole is formed on the back side of the original wafer.
  • FIG. 15A5 a schematic cross-sectional structure of the formed single first substrate 32 is as shown in FIG. 15A5.
  • each bare chip is realized by the first substrate 32. Therefore, as shown in FIG. 15B, each of the first pads in the first pad array disposed on the first surface of the first substrate 32 and the second tube on the respective bare chips 341 and 342 corresponding thereto are disposed. The second pins 352 in the array of legs are bonded together so that interconnection is achieved between the different bare chips by the first re-wiring layer 321 disposed on the first substrate 32.
  • hot air may be used between the first substrate 32 and the fan-out unit 31. Mass Reflow or Thermo Compression Bonding is connected together.
  • the fan-out unit 31 and the first substrate 32 that are bonded together are molded by using a molding compound to form a molding body 33 that wraps each of the first pins 351, the respective second pins 352, and the first substrate 32.
  • the surface of the first pin array needs to be in the same plane as the back surface of the first substrate 32. Therefore, in the embodiment of the present application, the fan-out unit 31 and the first pair of molded plastics are used.
  • a substrate 32 is plastically sealed to form a molding body 33 that wraps each of the first pins 351, the respective second pins 352, and the first substrate 32.
  • a schematic diagram of the corresponding cross-sectional structure performed in this step is shown in Fig. 15C.
  • the formation of the molding body 33 can also improve the reliability of the entire package structure.
  • the abrasive molding body 33 is away from the surface of the fan-out unit 31 to expose the bottom of each of the first pins in the first pin array.
  • This step may be specifically: grinding the plastic body 33 away from the surface of the fan-out unit 31 by mechanical grinding to expose the bottom of each of the first pins 351 in the first pin array.
  • a solder ball 36 electrically connected to the outside is formed at the bottom of each of the exposed first pins 351.
  • a metal solder ball 36 is formed on the bottom of each of the exposed first pins 351.
  • a pad 37 may be formed between each of the first pin 351 and the solder ball 36.
  • the above is a specific implementation manner of a chip packaging method provided by an embodiment of the present application.
  • the chip structure packaged by the specific implementation short-distance, high-density interconnection between bare chips is realized by the first substrate 32.
  • the molding body 33 is used to wrap the first pin 351, the second pin 352, and the first substrate 32, thereby molding the fan-out unit 31 and the first substrate 32 into a unitary structure.
  • the bottoms of the first pins of the first pin array for barely electrically connecting to the periphery of the chip on the bare chips 341 and 342 are not wrapped by the molding body 33, so that the first pins can be directly electrically connected. To the periphery of the chip.
  • the pin on the bare chip for electrically connecting to the periphery of the chip can be directly electrically connected to the periphery of the chip without passing through the substrate as an intermediary. Therefore, the overall size of the chip provided by the embodiment of the present application is mainly determined by the size of the plurality of bare chips that are integrated together. Compared with the prior art, the overall size of the chip provided by the embodiment of the present application is small, and the chip can be small. Demand.
  • the manner in which the bare chips 341 and 342 are interconnected through the first substrate 32 also facilitates miniaturization of the chip.
  • the first substrate 32 can be fabricated independently, and does not need to be fabricated on the integrated bare chip. Therefore, if defects occur in the manufacturing process of the first substrate 32, the discarded bare chips are not discarded. Thereby reducing the packaging cost.
  • the size of the first substrate 32 can satisfy the bonding with the second pin 352 on the bare chip, and does not need to be greater than or equal to the sum of the sizes of all the integrated bare chips. Therefore, the embodiment of the present application can reduce the consumables of the first substrate 32, thereby greatly reducing the packaging cost. On the other hand, this design is also conducive to the miniaturization of the chip.
  • the line width and the line pitch of the first re-wiring layer on the first substrate 32 can reach 0.4 ⁇ m. Therefore, the line width and the line pitch are small, and the manufacturing process is relatively simple.
  • the electrical connection between the chip and the peripheral circuits of the chip is not limited to the size and arrangement of the pins on the bare chip.
  • the first pin 351 can be connected to an external circuit through a substrate. Based on this, the embodiment of the present application further provides another implementation manner of the chip packaging method.
  • Another chip packaging method provided by the embodiment of the present application includes the following steps:
  • S161 to S164 are the same as S141 to S144, and will not be described in detail herein for the sake of brevity.
  • S165 forming a second substrate 91 on the surface exposing the bottom of each of the first pins in the first pin array by a wiring layer build-up process, where the second substrate 91 is provided with a second re-wiring layer (not shown) And the second substrate 91 includes opposite first and second surfaces, and the first surface of the second substrate 91 is provided with a second pad array electrically connected to the second rewiring layer, the second pad The array includes a plurality of second pads 911; a second pad array is disposed on the second surface of the second substrate 91, and the third pad array includes a plurality of third pads 912.
  • This step can specifically include:
  • a dielectric layer is coated on the surface of the molded plastic body 33 away from the fan-out unit 31, and then a re-wiring layer is formed on the surface of the dielectric layer, and stacked layer by layer until the second rewiring layer is completed (not shown in the figure) Two rewiring layers). While the second rewiring layer is being formed, a second soldering array corresponding thereto is formed at a position opposite to the first pin array.
  • the second pad array includes a plurality of second pads 911; the second pads 911 form an electrical connection with the second rewiring layer.
  • the dielectric layer is continuously coated, and then a third pad array is formed on the surface of the dielectric layer, and the third pad array includes a plurality of third pads 912 .
  • the second substrate 91 is directly formed on the surface of the molding body 33 away from the fan-out unit 31. After the second substrate 91 is completed, electrical connection between the first pin on the bare chip and the second substrate 91 can be achieved.
  • a plurality of rewiring layers are disposed directly on the second substrate 91 formed on the surface of the molded body 33 after the grinding away from the fan-out unit 31. Therefore, the second substrate 91 is also disposed. It can be called an RDL carrier.
  • the cross-sectional dimension of the first substrate 91 is the same as the cross-sectional size of the molded body 33.
  • the cross-sectional dimension of the molded body 33 is the same as the cross-sectional size of the fan-out unit 31, so the cross-sectional size of the first substrate 91 is the same as the cross-sectional size of the fan-out unit 31.
  • each of the first pins 351 in the first pin array on the bare chips 341 and 342 is first electrically connected to a corresponding one of the second pad arrays on the second substrate 91.
  • each of the third pads in the third pad array on the second substrate 91 is electrically connected to the chip peripheral circuit.
  • the first pins 351 on the bare chips 341 and 342 are electrically connected to the chip peripheral circuits through the second substrate 91.
  • the density between the third pads 912 thereon can be smaller than the density of the first pins 351 on the bare chip, and thus, compared to the bare chip 341 and The first pin 351 on the 342, the third pad 912 on the second substrate 91 can be relatively easily electrically connected to the chip peripheral circuit by a soldering process, so even the upper tube is included on the chip formed by the embodiment of the present application.
  • the bare chip of the foot density can also conveniently realize the electrical connection between the bare chip and the peripheral circuit of the chip. Therefore, the chip structure formed by this embodiment can reduce the limitation of the bare chip pin arrangement on the electrical connection between the chip and the peripheral circuit of the chip.
  • steps S1 to S2 may also be included:
  • the third substrate 101 includes opposing first and second surfaces.
  • the first surface of the third substrate 101 is provided with a fourth pad array, and the second surface of the third substrate 101 is disposed on the second substrate 101.
  • the fifth pad array, the fourth pad array includes a plurality of fourth pads 1011, and the fifth pad array includes a plurality of fifth pads 1012.
  • each of the fourth pads in the fourth pad array on the third substrate 101 respectively corresponds to the third pad in the third pad array on the second substrate 91.
  • Each of the fifth pads 1012 in the fifth pad array on the third substrate 101 is for electrical connection with a chip peripheral circuit. More specifically, each of the fifth pads 1012 in the fifth pad array on the third substrate 101 is for electrical connection with the PCB board of the peripheral region of the chip.
  • each third pad 912 in the third pad array on the second substrate 91 is no longer used for connection with an external circuit, but for the first surface of the third substrate 101.
  • Each of the fourth pads 1011 in the fourth pad array is connected.
  • each of the fifth pads 1012 in the fifth pad array on the second surface of the third substrate 101 is electrically connected to the PCB board of the peripheral region of the chip.
  • the chip package method provided by the embodiment of the present application can also include:
  • FIG. 1 A schematic diagram of the cross-sectional structure corresponding to the execution of this step is shown in FIG. 1
  • the fan-out unit 31 and the first one are bonded together by the molding compound pair.
  • the molding compound may not completely wrap the respective first pads 322, resulting in a decrease in the reliability of the entire chip structure. Therefore, in order to improve the filling effect between the first pads 322 in the first pad array, in the packaging method of any of the above embodiments, the fan-out unit 31 and the first substrate which are bonded together using the molding compound pair are used. Before the plastic molding is carried out, the following steps can also be included:
  • FIG. 1 A schematic diagram of the cross-sectional structure corresponding to the execution of this step is shown in FIG. 1
  • the package method described in any of the above optional embodiments may further include the following steps:
  • FIG. 1 A schematic diagram of the cross-sectional structure corresponding to the execution of this step is shown in FIG. 1
  • the heat sink 111 can be bonded to the second surface of the bare chip through the thermal paste, thereby providing a good heat dissipation path for the chip with high power consumption.
  • the grinding fan-out unit 31 is away from the surface of the second substrate 91 to expose the second surfaces of the bare chips 341 and 342.
  • the heat sink 111 may be connected to the third substrate 101. Therefore, as a further optional embodiment of the present application, based on the foregoing optional embodiments, the following steps may also be included:
  • the fan-out unit 31 is masked in the heat sink 111, and the edge of the heat sink 111 is fixedly connected to the third substrate 101.
  • the heat sink 111 may be adhered to the first surface of the third substrate 101 by an adhesive.

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Abstract

本申请实施例公开了一种芯片及其封装方法。该芯片中，第一基板上的第一焊垫阵列上的各个第一焊垫与不同裸芯片上的第二管脚阵列中的相对应的各个第二管脚贴合在一起，从而实现不同裸芯片之间的短距离、高密度互连。塑封体用于包裹第一管脚、第二管脚、第一焊垫以及第一基板，从而使扇出单元和第一基板塑封成一整体结构。在该整体结构中，裸芯片上用于与芯片外围电连接的第一管脚阵列的各个第一管脚底部不被塑封体包裹，如此，各个第一管脚可以直接电连接至芯片外围。本申请实施例提供的芯片的整体尺寸主要取决于集成在一起的多颗裸芯片的尺寸，相较于现有技术，本申请实施例提供的芯片的整体尺寸较小，能够满足芯片小型化的需求。

Description

一种芯片及封装方法
本申请要求于2018年02月24日提交中国专利局、申请号为201810157259.5、发明名称为“一种芯片及封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本领域涉及半导体封装技术领域，尤其涉及一种芯片及封装方法。
背景技术
随着集成电子技术的不断发展，对芯片性能要求也日渐提高，如功能增强、尺寸减小、耗能与成本降低等，从而催生了3DIC(Three Dimensional Integrated Circuit，三维集成电路)技术。硅中介层(Silicon Interposer)技术是三维集成电路中实现堆叠芯片互连的一种技术解决方案。该技术方案使用半导体工艺在硅片上制作线宽、节点间距都比树脂基板小得多的互连线路。从而能够将不同功能的芯片比如CPU、DRAM等可以连到同一块硅中介层上面，通过硅中介层完成大量运算和数据交流，从而大大增加芯片在三维方向堆叠的密度、缩短芯片之间的互连线、减小外观尺寸、显著降低噪声、减小RC延迟，并改善芯片速度和低功耗的性能等。
然而，3DIC目前由于仍有许多瓶颈尚待克服，例如晶圆薄化良率、堆叠芯片信号引出工艺难度高、用于芯片互连的硅通孔(Through Silicon Via，TSV)工艺难度高以及高功率芯片堆叠后散热问题等。
而扇出型晶圆级封装(Fan-out Wafer Level Package，FoWLP)可以在晶圆上通过再布线层将单个芯片的I/O管脚进行引出，增大单个封装面积，从而提高整体I/O管脚数量。其设计难度不仅低于硅通孔3DIC，且封装结构接近2.5D IC，因此，扇出型晶圆级封装有望成为先进封装技术的发展要点。
然而，现有的扇出型晶圆级封装结构中，裸芯片上用于与封装结构外围电连接的管脚需要通过基板才能实现与封装结构外围的电连接，如此，导致封装结构的整体尺寸较大，不能满足芯片小型化的需求。
发明内容
有鉴于此，本申请实施例提供了一种芯片及封装方法，以减小芯片整体尺寸，满足芯片小型化的需求。
为了达到上述发明目的，本申请采用了如下技术方案：
本申请的第一方面提供了一种芯片，包括：扇出单元、第一基板和塑封体；
所述扇出单元包括集成在一起的多颗按照预设位置排列的裸芯片，每颗所述裸芯片的第一表面上设置有第一管脚阵列和第二管脚阵列；所述第一管脚阵列包括多个第一管脚，所述第二管脚阵列包括多个第二管脚；相邻裸芯片上的第二管脚阵列相邻；
所述第一基板包括第一表面，所述第一基板的第一表面上设置有第一再布线层以及与 所述第一再布线层电连接的第一焊垫阵列，且所述第一焊垫阵列包括多个第一焊垫；
其中，所述第一基板位于所述扇出单元的下方，并且所述第一焊垫阵列与所述第二管脚阵列相对设置，且所述第二管脚阵列中的每个第二管脚与所述第一焊垫阵列中相对应的第一焊垫贴合在一起，从而使不同所述裸芯片之间通过所述第一基板实现互连；
所述塑封体用于包裹所述第一管脚、所述第二管脚以及所述第一基板，从而使所述扇出单元和第一基板塑封成一整体结构。
在上述第一方面提供的芯片中，第一基板上的第一焊垫阵列上的各个第一焊垫与不同裸芯片上的第二管脚阵列中的相对应的各个第二管脚贴合在一起，从而实现不同裸芯片之间的短距离、高密度互连。塑封体用于包裹第一管脚、第二管脚、第一焊垫以及第一基板，从而使扇出单元和第一基板塑封成一整体结构。在该整体结构中，裸芯片上用于与芯片外围电连接的第一管脚阵列的各个第一管脚底部不被塑封体包裹，如此，各个第一管脚可以直接电连接至芯片外围。因此，通过本申请实施例提供的芯片，裸芯片上用于与芯片外围电连接的管脚可以直接电连接至芯片外围，无需通过基板作为中介。因此，本申请实施例提供的芯片的整体尺寸主要取决于集成在一起的多颗裸芯片的尺寸，相较于现有技术，本申请实施例提供的芯片的整体尺寸较小，能够满足芯片小型化的需求。
结合本申请的第一方面，在第一种可能的实施方式中，所述芯片还包括第二基板，
所述第二基板通过布线层增层工艺直接设置于所述塑封体的下方；
所述第二基板上设置有第二再布线层，所述第二基板包括相对的第一表面和第二表面，所述第二基板的第一表面上设置有与所述第二再布线层电连接的第二焊垫阵列，所述第二焊垫阵列包括多个第二焊垫；所述第二基板的第二表面上设置有第三焊垫阵列，且所述第三焊垫阵列包括多个第三焊垫；
所述第二焊垫阵列与所述第一管脚阵列相对设置，且所述第二焊垫阵列中的每个第二焊垫电连接至所述第一管脚阵列中对应的第一管脚。
在该第一种可能的实施方式中，该芯片与芯片外围电路的电性连接不再受限于裸芯片的管脚的尺寸和排布。因而，该芯片结构能够减少裸芯片管脚排布对芯片与芯片外围电路电性连接的限制。
结合本申请的第一方面及其第一种可能的实施方式，在第二种可能的实施方式中，所述第一基板的内部设置有与所述第一再布线层电连接的通孔，所述通孔延伸至所述第一基板的第二表面，并且所述通孔与芯片外围电连接，其中，所述第一基板的第二表面与所述第一基板的第一表面相对。
在该第二种可能的实施方式中，通过该通孔方便第一基板与芯片外围的信号传输。
结合本申请的第一方面及其第一种至第二种任一可能的实施方式，在第三种可能的实施方式中，所述芯片还包括：设置于所述第二基板下方的第三基板；
所述第三基板包括相对的第一表面和第二表面，所述第三基板的第一表面上设置有第四焊垫阵列，所述第三基板的第二表面上设置有第五焊垫阵列，所述第四焊垫阵列包括多个第四焊垫，所述第五焊垫阵列包括多个第五焊垫；
其中，所述第四焊垫阵列与所述第三焊垫阵列相对，且所述第四焊垫阵列中的每个第 四焊垫电连接至所述第三焊垫阵列中相对的第三焊垫；
所述第五焊垫阵列中的第五焊垫用于实现所述芯片与所述芯片外围的信号传输。
在该第三种可能的实施方式中，该芯片能够进一步增加芯片的布线资源和封装的管脚数，改善封装的电源完整性，同时改善芯片的板级可靠性。
结合本申请的第一方面及其第一种至第三种任一可能的实施方式，在第四种可能的实施方式中，所述芯片还包括设置在所述裸芯片的第二表面上的散热片，其中，所述裸芯片的第二表面与所述裸芯片的第一表面相对。
在该第四种可能的实施方式中，能够提高芯片的散热性能。
结合本申请的第一方面的第四种可能的实施方式，在第五种可能的实施方式中，所述芯片包括设置于所述第二基板下方的第三基板；所述散热片将所述扇出单元遮罩，并且所述散热片的边缘固定在所述第三基板上。
在该第五种可能的实施方式中，不仅能够提高芯片的散热性能，还能够控制整个芯片结构的翘曲和芯片的可靠性。
结合本申请的第一方面的第三种可能的实施方式，在第六种可能的实施方式中，所述第二基板和所述第三基板之间填充有填充胶。
在该第六种可能的实施方式中，能够提高第一焊垫阵列中的各个第一焊垫之间的间隙的填充效果，进而提高芯片的可靠性。
结合本申请的第一方面及其第一种至第六种任一可能的实施方式，在第七种可能的实施方式中，所述第一焊垫阵列中的各个第一焊垫之间的间隙内填充有填充胶。
在该第七种可能的实施方式中，能够缓解第一管脚与第二基板之间的应力，进而提高整个芯片结构的可靠性。
结合本申请的第一方面及其第一种至第七种任一可能的实施方式，在第八种可能的实施方式中，用于制作所述第一基板的材料为硅基材料、树脂材料和玻璃材料中的至少一种。在该第八种可能的实施方式中，能够降低芯片成本。
结合本申请的第一方面及其第一种至第八种任一可能的实施方式，在第九种可能的实施方式中，所述裸芯片为无源裸芯片或功能裸芯片。
结合本申请的第一方面及其第一种至第九种任一可能的实施方式，在第十种可能的实施方式中，所述第二管脚包含铜柱和焊接凸块中的至少一种。在该第十种可能的实施方式中，能够提高芯片结构的灵活性。
结合本申请的第一方面及其第一种至第十种任一可能的实施方式，在第十一种可能的实施方式中，实现互连的不同裸芯片之间形成有至少一个互连结构，每个所述互连结构中包括多条互连线。
结合本申请的第一方面的第十一种可能的实施方式，在第十二种可能的实施方式中，同一互连结构中的各条互连线的长度均相等。该在第十二种可能的实施方式中，能够信号质量和改善信号间的串扰。
结合本申请的第一方面及其第一种至第十二种任一可能的实施方式，在第十三种可能的实施方式中，所述第一再布线层包括n层第一再布线子层，其中，n≥1，且n为整数。
结合本申请的第一方面及其第一种至第十三种任一可能的实施方式，在第十四种可能的实施方式中，所述n≥2，所述n层第一再布线子层包括参考层和线路层，所述参考层所在的平面为所述线路层的参考面。该在第十四种可能的实施方式中，能够信号质量和改善信号间的串扰。
结合本申请的第一方面的第三种可能的实施方式，在第十五种可能的实施方式中，所述第三基板为激光研磨制备的多层基板或采用机械研磨制备的多层基板。
结合本申请的第一方面及其第一种至第十五种任一可能的实施方式，在第十六种可能的实施方式中，所述第一基板上设置有逻辑芯片。
本申请的第二方面提供了一种芯片封装方法，所述芯片封装方法包括：
分别制作扇出单元和第一基板；所述扇出单元包括集成在一起的多颗按照预设位置排列的裸芯片，每颗所述裸芯片的第一表面上设置有第一管脚阵列和第二管脚阵列；所述第一管脚阵列包括多个第一管脚，所述第二管脚阵列包括多个第二管脚；相邻裸芯片上的第二管脚阵列相邻；所述第一基板包括第一表面，所述第一基板的第一表面上设置有第一再布线层以及与所述第一再布线层电连接的第一焊垫阵列，且所述第一焊垫阵列包括多个第一焊垫；
将所述第一基板置于所述扇出单元的下方，并且使所述第二管脚阵列中的每个第二管脚与所述第一焊垫阵列中相对应的第一焊垫贴合在一起，从而使不同所述裸芯片之间通过所述第一基板实现互连；
使用模塑料对贴合在一起的扇出单元和第一基板进行塑封，形成包裹所述第一管脚、所述第二管脚以及所述第一基板的塑封体。
在该第二方面提供的芯片封装方法中，芯片包括扇出单元、第一基板和塑封体。其中，第一基板上的第一焊垫阵列上的各个第一焊垫与不同裸芯片和上的第二管脚阵列中的相对应的各个第二管脚贴合在一起，从而实现不同裸芯片之间的短距离、高密度互连。塑封体用于包裹第一管脚、第二管脚以及第一基板，从而使扇出单元和第一基板塑封成一整体结构。在该整体结构中，裸芯片上用于与芯片外围电连接的第一管脚阵列的各个第一管脚底部不被塑封体包裹，如此，各个第一管脚可以直接电连接至芯片外围。因此，通过第二方面提供的芯片封装方法，裸芯片上用于与芯片外围电连接的管脚可以直接电连接至芯片外围，无需利用基板作为中介。因此，通过该方法制作出的芯片的整体尺寸主要取决于扇出单元尺寸，相较于现有技术，通过该方法制作出的芯片的整体尺寸较小，能够满足芯片小型化的需求。
结合本申请的第二方面，在第一种可能的实施方式中，所述方法还包括：
当所述塑封体包裹所述第一管脚阵列中的各个第一管脚的底部时，研磨所述塑封体远离所述扇出单元的表面，以露出所述第一管脚阵列中的各个第一管脚的底部；
通过布线层增层工艺在露出所述第一管脚阵列中的各个第一管脚底部的表面上制作第二基板，所述第二基板上设置有第二再布线层，所述第二基板包括相对的第一表面和第二表面，所述第二基板的第一表面上设置有与所述第二再布线层电连接的第二焊垫阵列，所述第二焊垫阵列包括多个第二焊垫；所述第二基板的第二表面上设置有第三焊垫阵列， 且所述第三焊垫阵列包括多个第三焊垫；
其中，所述第二焊垫阵列与所述第一管脚阵列相对设置，且所述第二焊垫阵列中的每个第二焊垫电连接至所述第一管脚阵列中对应的第一管脚。
在该第一种可能的实施方式中，该芯片与芯片外围电路的电性连接不再受限于裸芯片的管脚的尺寸和排布。因而，该方法制作出的芯片结构能够减少裸芯片管脚排布对芯片与芯片外围电路电性连接的限制。
结合本申请的第二方面的第一种可能的实施方式，在第二种可能的实施方式中，所述在露出所述第一管脚阵列中的各个第一管脚底部的表面上制作第二基板，具体包括：
在露出所述第一管脚阵列中的各个第一管脚底部的表面上涂覆介质层，然后在所述介质层表面制作再布线层，逐层叠加，直至完成第二再布线层的制作；在制作所述第二再布线层的同时，在第一管脚阵列相对的位置上制作第二焊垫阵列，其中，所述第二焊垫阵列包括多个第二焊垫；且一个所述第二焊垫对应一个第二焊垫，；
在制作完第二再布线层和第二焊垫阵列之后，继续涂覆介质层，然后在该介质层的表面上制作由多个第三焊垫组成的第三焊垫阵列。
在该第二种可能的实施方式中，即使包括高管脚密度的裸芯片，也能够很方便地实现裸芯片与芯片外围电路的电连接，因此，该实施例形成的芯片结构能够减少裸芯片管脚排布对芯片与芯片外围电路电连接的限制。
结合本申请的第二方面的第一种至第二种任一可能的实施方式中，在第三种可能的实施方式中，所述芯片封装方法还包括：
制作第三基板，所述第三基板包括相对的第一表面和第二表面，所述第三基板的第一表面上设置有第四焊垫阵列，所述第三基板的第二表面上设置有第五焊垫阵列，所述第四焊垫阵列包括多个第四焊垫，所述第五焊垫阵列包括多个第五焊垫；
所述在露出所述第一管脚阵列中的各个第一管脚底部的表面上制作第二基板之后，所述芯片封装方法还包括：
将所述第三基板置于所述第二基板的下方，并且使所述第四焊垫阵列与所述第三焊垫阵列相对，且使所述第四焊垫阵列中的每个第四焊垫与所述第三焊垫阵列中相对应的第三焊垫贴合，以使所述第四焊垫阵列中的每个第四焊垫电连接至所述第三焊垫阵列中相对应的第三焊垫。
在该第三种可能的实施方式中，该芯片与芯片外围电路的电性连接不再受限于裸芯片的管脚的尺寸和排布。因而，该芯片结构能够减少裸芯片管脚排布对芯片与芯片外围电路电性连接的限制。
结合本申请的第二方面的第三种可能的实施方式，在第四种可能的实施方式中，所述将所述第三基板置于所述第二基板的下方，并且使所述第四焊垫阵列中的每个第四焊垫与所述第三焊垫阵列中相对应的第三焊垫贴合后，还包括：
向所述第二基板和所述第三基板之间填充填充胶。
在该第四种可能的实施方式中，能够提高第一焊垫阵列中的各个第一焊垫之间的间隙的填充效果，进而提高芯片的可靠性。
结合本申请的第二方面的第一种至第四种任一可能的实施方式中，在第五种可能的实施方式中，所述使用模塑料对贴合在一起的扇出单元和第一基板进行塑封前，还包括：
向所述第一焊垫阵列中的各个第一焊垫之间的间隙内填充填充胶。
结合本申请的第二方面的第一种至第五种任一可能的实施方式，在第六种可能的实施方式中，所述芯片封装方法还包括：
在所述裸芯片的第二表面上设置散热片，其中，所述裸芯片的第二表面与所述裸芯片的第一表面相对。
在该第六种可能的实施方式中，该方法制成的芯片的散热性能较好。
结合本申请的第二方面的第一种至第六种任一可能的实施方式中，在第七种可能的实施方式中，所述在所述裸芯片的第二表面上设置散热片之前，还包括：
研磨所述扇出单元远离所述第二基板的表面，以露出所述裸芯片的第二表面。
结合本申请的第二方面的第三种可能的实施方式，在第八种可能的实施方式中，所述芯片封装方法还包括：
在所述扇出单元远离所述第二基板的表面上设置散热片，所述散热片将所述扇出单元遮罩，并且所述散热片的边缘固定在所述第三基板上。
在该第八种可能的实施方式中，该方法不仅能够提高芯片的散热性能，还能够控制整个芯片结构的翘曲和芯片的可靠性。
相较于现有技术，本申请具有以下有益效果：
基于以上技术方案可知，本申请实施例提供的芯片中，第一基板上的第一焊垫阵列上的各个第一焊垫与不同裸芯片上的第二管脚阵列中的相对应的各个第二管脚贴合在一起，从而实现不同裸芯片之间的短距离、高密度互连。塑封体用于包裹第一管脚、第二管脚、第一焊垫以及第一基板，从而使扇出单元和第一基板塑封成一整体结构。在该整体结构中，裸芯片上用于与芯片外围电连接的第一管脚阵列的各个第一管脚底部不被塑封体包裹，如此，各个第一管脚可以直接电连接至芯片外围。因此，通过本申请实施例提供的芯片，裸芯片上用于与芯片外围电连接的管脚可以直接电连接至芯片外围，无需通过基板作为中介。因此，本申请实施例提供的芯片的整体尺寸主要取决于集成在一起的多颗裸芯片的尺寸，相较于现有技术，本申请实施例提供的芯片的整体尺寸较小，能够满足芯片小型化的需求。
附图说明
图1是本领域常用的一种扇出型晶圆级封装结构的剖面示意图；
图2是本领域常用的另一种扇出型晶圆级封装结构的剖面示意图；
图3A是本申请实施例提供的一种芯片的剖面示意图；
图3B是本申请实施例提供的芯片中的扇出单元示意图；
图4至图4’分别为本申请实施例提供的一种芯片剖面示意图和俯视图；
图5是本申请实施例提供的裸芯片的第一表面结构示意图；
图6A至图6C是本申请实施例提供的裸芯片之间的互连结构示意图；
图7是本申请实施例提供的另一种芯片剖面示意图；
图8是本申请实施例提供的又一种芯片剖面示意图；
图9是本申请实施例提供的又一种芯片剖面示意图；
图10A是本申请实施例提供的又一种芯片剖面示意图；
图10B是本申请实施例提供的第二基板的第一表面结构示意图；
图11至图11’分别为本申请实施例提供的又一种芯片剖面示意图和俯视图；
图12为本申请实施例提供的又一种芯片剖面示意图；
图13为本申请实施例提供的又一种芯片俯视图；
图14是本申请实施例提供的一种芯片封装方法流程示意图；
图15A1至图15D分别为本申请实施例提供的一种芯片封装方法一系列制程对应的结构示意图；
图16是本申请实施例提供的另一种芯片封装方法流程示意图；
图17是本申请实施例提供的第三基板的剖面结构示意图。
具体实施方式
在介绍本申请实施例的具体实现方式之前，首先描述本申请实施例用到的缩略语与关键术语定义。
Figure PCTCN2018099006-appb-000001
扇出型晶圆级封装可以在晶圆上通过再布线层将单颗芯片的I/O管脚引出，增大单个封装面积，从而提高整体I/O管脚数量。其设计难度不仅低于硅通孔3DIC，且封装结构接近2.5D IC，因此，扇出型晶圆级封装有望成为先进封装技术的发展要点。
目前，业界出现了一些扇出型晶圆级封装技术。其中，现有的一种扇出型封装结构如图1所示。该扇出型封装结构是结合传统扇出型晶圆级封装与覆晶封装(Flip Chip)的2.5D FOP封装结构。
该封装结构的封装过程具体如下：首先将待集成的多颗裸芯片10和11按照一定间距和位置并列放置在载体上，该载体的尺寸可以与晶圆的原始尺寸相同；然后采用模塑料12对待集成的多颗裸芯片10和11进行模封形成重构的晶圆。然后在重构的晶圆上进行再布线，即在重构的晶圆上的裸芯片的正面上制备扇出布线层13，扇出布线层13通过高密度互连结构14和15可把裸芯片10和11上的I/O管脚电扩展到到裸芯片10和11之外的区域，使得裸芯片和PCB板16之间的电性连接不受限于裸芯片10和11的尺寸和排布。
图1所示的封装结构采用晶圆级的工艺制程，使得封装、测试均可以在晶圆上完成，该封装结构能够有效增加封装管脚的数量，能够解决先进工艺节点及更高芯片功能对更多管脚数量的要求。而且，该2.5D FOP封装可以实现多颗裸芯片的集成封装，并通过扇出布线层实现裸芯片间的短距离高密度互连，而不再需要经过基板。但是该封装结构存在以下缺点：
第一：裸芯片10和11之间的互连是通过扇出布线层13实现的。而在重构的晶圆上制备多层大面积尺寸的扇出布线层13的过程中，重构的晶圆受到光刻、曝光和显影工艺的影响，会造成应力不均匀，产生翘曲甚至变形，而重构的晶圆上的裸芯片都是经过测试的合格的裸芯片，如果后续扇出布线层13制备过程中产生缺陷，会导致合格的裸芯片也同时浪费掉，导致成本上升。
第二：在重构的晶圆上制备出的扇出布线层的线宽、线距均只能达到2μm，且工艺实现难度大，如此限制了芯片互连密度以及芯片信号和电源的完整性。
为了克服图1所示的扇出型封装结构的缺陷，业界还出现了另一种扇出型封装结构。该扇出型封装结构是结合带有硅通孔的硅中介层(Si Interposer)和覆晶封装的2.5D TSV封装结构。该扇出型封装结构如图2所示。该扇出型封装结构的封装过程具体如下：
首先在一片硅晶圆上制作硅通孔211，并在硅晶圆的表面上制备单层或多层再布线层212，从而形成用于信号连接的硅中介层21。
然后将待集成的多颗裸芯片22和23按照预先设计位置放置在硅中介层21的正面上，然后通过焊接工艺将裸芯片22和23焊接在硅中介层21的正面上。
最后通过硅中介层21背面上的电连接结构213与封装基板24焊接在一起。如此，裸芯片上的I/O管脚藉由硅中介层21上的再布线层212和硅通孔211扇出到封装基板24上，而不同裸芯片之间则通过再布线层212形成互连结构。
图2所示的2.5D TSV封装结构采用硅中介层和TSV技术，在硅晶片上实现了不同裸芯片的互连。利用成熟的半导体制造工艺以及硅材料实现极小线宽线距(目前硅中介层的最 小线宽和线距均为0.4μm)，大大提高了芯片之间的信号互连密度，缩短了信号走线距离。但是，该封装结构存在以下缺陷：
待集成的多颗裸芯片需要焊接在硅中介层上，如此，硅中介层的尺寸需要大于所有裸芯片的尺寸之和，耗材高。
基于此，为了能够解决现有的扇出型晶圆级封装技术存在的封装成本高且线宽线距较大，工艺实现难度大的问题，本申请实施例提供了一种芯片。请参见图3A，该芯片的具体结构为2.5D基板桥式扇出型封装结构。如图3A所示，该芯片包括：
基板108、扇出单元111及布线层104，所述扇出单元111包括第一芯片101和第二芯片102。请结合参阅图3B，图3B示意性地表达了扇出单元111的结构，其中隐藏的线(视图方向看不到的线)用虚线表示。所述第一芯片101包括第一管脚阵列A1，其中第一管脚阵列A1包括多个第一管脚32a，所述第二芯片102包括第二管脚阵列A2，其中第二管脚阵列A2包括多个第二管脚32b。所述扇出单元111还包括第三管脚阵列A3，第三管脚阵列A3包括多个第三管脚41，所述第一管脚阵列A1、所述第二管脚阵列A2及所述第三管脚A3阵列均面对所述基板108设置。第一芯片101和第二芯片102的面对基板108的表面被定义为正面，相反的表面被定义为背面，第一管脚阵列A1、第二管脚阵列A2和第三管脚阵列A3分布于第一芯片101和第二芯片102的正面。本实施方式中，第一芯片101和第二芯片102相邻设置，第一管脚阵列A1与第二管脚阵列A2相邻设置，所述第三管脚阵列A3分布于所述扇出单元111之除所述第一管脚阵列A1和所述第二管脚阵列A2之外的区域。第一芯片101和第二芯片102相邻设置表明第一芯片101和第二芯片102没有其他芯片将二者区隔开。
图3A所示的芯片中，通过布线层104跨接于所述第一管脚阵列A1和所述第二管脚阵列A2之间，用于将所述第一管脚阵列A1中的第一管脚32a连接至所述第二管脚阵列A2中的对应的第二管脚32b，以实现所述第一芯片101和所述第二芯片102之间的电连接，无需设置具有通孔结构的中介板，而且，因为布线层104的制作工艺简单(通过普通的增层工艺即可实现)，成本也低；且通过第三管脚阵列A3与基板108的直接连接，使得扇出单元111与基板108之间的连接无需设置大面积的中介板，也省去了在中介板是制作通孔的工艺。因此，图3A所示的芯片具有工艺难度小，成本低的优势。
然而，在图3A所示的芯片中，扇出单元111上的第三管脚阵列A3中的第三管脚需要通过基板108才能连接至芯片外围。使得影响芯片整体尺寸的部件包括扇出单元111和基板108，如此导致芯片的整体尺寸较大，不能满足芯片小型化的需求。
为了减小芯片的整体尺寸，满足芯片小型化的需求，本申请实施例提供了芯片的另一种结构。
下面结合附图详细描述本申请实施例提供的芯片的具体实现方式。
请参见图4和图4’，其中，图4为本申请实施例提供的一种芯片结构剖面示意图，图4’为本申请实施例提供的一种芯片结构俯视图。如图4和图4’所示，本申请实施例提供的一种芯片包括：
扇出单元31、第一基板32和塑封体33；
该扇出单元31包括集成在一起的多颗按照预设位置排列的裸芯片341和342。在本申请实施例中，集成在一起的多颗裸芯片可以为两颗裸芯片，也可以为两颗以上裸芯片。作为示例，本申请实施例以待集成的多颗裸芯片以两颗为例进行说明。
在本申请实施例中，裸芯片341和342可以利用模塑料通过模塑工艺集成在一起，形成扇出单元31。
为了清楚地理解裸芯片341和342的正面结构，本申请实施例还提供了裸芯片341和342的第一表面结构示意图，具体如图5所示。裸芯片341或342的第一表面上设置有第一管脚阵列C1和第二管脚阵列C2；第一管脚阵列C1包括多个第一管脚351，第二管脚阵列C2包括多个第二管脚352；相邻裸芯片上的第二管脚阵列C2相邻；
第一基板32包括第一表面，第一基板32的第一表面上设置有第一再布线层321以及与第一再布线层321电连接的第一焊垫阵列，该第一焊垫阵列包括多个第一焊垫322。
在本申请实施例中，裸芯片341和342的第一表面与第一基板32的第一表面相对，并且第一基板32位于扇出单元31的下方，并且第一焊垫阵列与所述第二管脚阵列C2相对设置，且所述第二管脚阵列C2中的每个第二管脚352与所述第一焊垫阵列中相对应的第一焊垫322贴合在一起，从而使不同所述裸芯片341和342之间通过第一基板32上的第一在布线层321实现互连。
塑封体33用于包裹第一管脚351、第二管脚352、第一焊垫322以及第一基板32，从而使扇出单元31和第一基板32塑封成一整体结构。
需要说明，在本申请实施例中，塑封体33是在第一基板32上的第一焊垫阵列与裸芯片341和342的第二管脚阵列C2贴合在一起后通过模塑工艺形成的。该模塑工艺具体可以为压塑成型工艺(compression mold process)。因此，塑封体33至少包裹第一管脚351的侧面、第二管脚352的侧面、第一焊垫322的侧面以及第一基板32的侧面。而且，为了能够将裸芯片341和342上的第一管脚阵列C1中的各个第一管脚351引出到芯片外围，塑封体33不包裹各个第一管脚351的底部，也就是说，各个第一管脚351的底部露出塑封体33之外。
作为本申请的一具体示例，塑封体33除了包裹第一基板32的侧面外，还可以包裹第一基板32的背面，从而使塑封在一起的第一管脚阵列所在的区域与第一基板32所在的区域为一表面平整的结构，也就是说，使塑封形成的整体结构的表面为平整表面。
需要说明，贴合在一起的扇出单元31和第一基板32组成的结构，因没有保护层保护，所以，其结构稳定性较低，单独工作的可能性较低，基于此，塑封体33将第一管脚351的侧面、第二管脚352的侧面、第一焊垫322的侧面包裹起来，如此能够提高整个芯片的使用寿命和可靠性，而且因塑封体33的结构稳定，机械强度高，可以有力支撑该整体结构单独使用和工作。因此，通过压塑成型工艺将扇出单元31和第一基板32塑封在一起形成的整体结构可以单独稳定工作，也可以根据需要在其上制作RDL载板，或者根据需要将其与基板键合，组成更大的封装结构。
为了能够将各颗裸芯片341和342上的各个第一管脚351引出到芯片的外围，各个第一管脚351的底部可以设置有焊球36，每个焊球36可以与外部电路例如PCB板实现电连 接。作为本申请的一具体示例，为了实现第一管脚351与焊球36之间更好的电连接，在每个第一管脚351与焊球36之间还可以设置有焊垫37。
需要说明，在本申请实施例中，用于形成塑封体33的塑封料的成分与现有技术的填充胶(under fill)不同。塑封料和填充胶是在环氧树脂模塑料(Epoxy Molding Compound)的基础上添加不同的添加剂得到。
在本申请实施例中由塑封料形成的塑封体33一般通过压塑成型工艺实现。该压塑成型工艺与填充胶点胶工艺有很大不同。其中，压塑成型工艺可以分为两类，一类是灌注式(face-up type)，另一类是浸入式(face-down type)。其中，灌注式是将被模塑的结构放在流动的塑封料的下方，流动的塑封料向下流，灌注在被模塑的结构上，然后利用模具压合被灌注的结构。浸入式是将被模塑的结构放在盛放有流动的塑封料容器的上方，然后将该被模塑的结构浸入到盛放有流动塑封料容器中，然后将被塑封的结构从容器中取出，接着利用模具压合该被塑封的结构。如此，压塑成型工艺能够一次性完整整片晶圆上大量芯片的填充和固化，不需要针对单一芯片逐个填充，整体效率较高。
此外，压塑成型工艺的固化分为在压合状态时的初始固化以及完成压合后再放置到加热炉内完成最终固化。
通过塑封体33包裹裸芯片和基板能够形成一个结构稳定的结构体，该结构体能够直接被装载在终端设备中。
而填充胶点胶工艺具体为：在利用填充胶填充时，需要对整片晶圆上的所有芯片逐个依次一一点胶，点胶位置在每个芯片的四个边缘，通过毛细作用将填充胶吸引填充到芯片与基板或其他介质材料之间的空隙中，从而完成填充过程。填充完后，在将该填充后的结构放入加热炉完成最终的固化。因此，该填充过程耗费的时间较长，填充效率较低。
此外，若采用上述填充胶点胶工艺来填充上述由扇出单元31和第一基板32组成的结构，以实现对裸芯片及整个结构保护的话，则需要在扇出单元31和第一基板32组成的结构连接到其它结构例如基板上之后再执行，而本申请中由塑封料填充上述由扇出单元31和第一基板32组成的结构则可以在该结构与其它结构例如基板连接之前执行。
以上为本申请实施例提供的一种芯片的具体实现方式。在该具体实现方式中，芯片包括扇出单元31、第一基板32和塑封体33。其中，第一基板32上的第一焊垫阵列C1上的各个第一焊垫351与不同裸芯片341和342上的第二管脚阵列C2中的相对应的各个第二管脚352贴合在一起，从而实现不同裸芯片之间的短距离、高密度互连。塑封体33用于包裹第一管脚351、第二管脚352以及第一基板32，从而使扇出单元31和第一基板32塑封成一整体结构。在该整体结构中，裸芯片上用于与芯片外围电连接的第一管脚阵列C1的各个第一管脚底部不被塑封体33包裹，如此，各个第一管脚可以直接电连接至芯片外围。因此，通过本申请实施例提供的芯片，裸芯片上用于与芯片外围电连接的管脚可以直接电连接至芯片外围，无需利用基板作为中介。因此，本申请实施例提供的芯片的整体尺寸主要取决于扇出单元尺寸，相较于现有技术，本申请实施例提供的芯片的整体尺寸较小，能够满足芯片小型化的需求。
此外，在本申请实施例中，裸芯片341和342通过第一基板32实现互连的方式也有利 于芯片的小型化。
此外，在本申请实施例中，第一基板32可以独立制作，无需在扇出单元31上直接制作，因此，若第一基板32制作过程中出现缺陷，不会导致合格裸芯片的废弃，从而降低了封装成本。
而且，在本申请实施例中，第一基板32的尺寸只要能够满足与裸芯片上的第二管脚352的贴合即可，无需大于或者等于所有集成在一起的裸芯片的尺寸之和，因此，本申请实施例能够降低第一基板32的耗材，从而能够大大降低封装成本。另外，如此设计，也有利于芯片的小型化。
此外，在本申请实施例中，第一基板32上的第一再布线层的线宽和线距均可以达到0.4μm，因此，该线宽和线距较小，且制作工艺较为简单。
作为本申请的一具体实施例，塑封体33与扇出单元31可以为一体成型结构，如此，塑封体33和扇出单元31可以由同一次模塑工艺压塑成型得到。此外，作为本申请的另一具体实施例，塑封体33与扇出单元31也可以为分体结构，如此，塑封体33和扇出单元31由不同次模塑工艺压塑成型得到。
作为本申请的一可选实施例，为了清楚地理解本申请实施例所述的裸芯片341和342之间的具体互连结构，本申请实施例还提供了裸芯片341和342之间的互连结构。具体分别如图6A和图6B所示。
在该可选实施例中，设定第一再布线层321包括三层再布线子层，其可以分别为第一再布线子层、第二再布线子层和第三再布线子层。如图6A和图6B所示，其中，第一再布线子层和第三再布线子层用于实现裸芯片341和342的互连，第二再布线子层所在的平面作为用于实现裸芯片间互连的再布线子层的参考平面，如此，可以提高信号质量和改善信号间的串扰。
在图6A和图6B所示的互连结构中，裸芯片341和342之间形成两个互连结构，分别为第一互连结构51和第二互连结构52。其中，第一互连结构51可以由第一再布线子层形成，第二互连结构52可以由第三再布线子层形成。
如图6A和图6B所示，裸芯片341上的第二管脚阵列包括用于形成第一互连结构51的第一管脚组511a和用于形成第二互连结构的第二管脚组512a。裸芯片342上的第二管脚阵列包括用于形成第一互连结构51的第一管脚组511b和用于形成第二互连结构的第二管脚组512b。
在本申请实施例中，不同裸芯片之间可以形成至少一个互连结构，每一互连结构可以包括至少一条互连线。当一个互连结构中包括多条互连线时，属于同一互连结构中的多条互连线的长度可以相等，也可以不等。作为本申请的一可选实施例，为了提高信号传输质量，同一互连结构中的各条互连线的长度均相等。具体到图6A来说，设定按照由左到右的顺序将同一电连接结构组内的电连接结构列依次分别命名为第1列、第2列和第3列，按照自上而下的顺序将电连接结构行命名依次分别为第1行、第2行直至第7行。在第一互连结构51中，该第一管脚组511a内的第1行电连接结构的连接方式如图6C所示。第一管脚组511a内的第1行第1列焊点连接第一管脚组511b内的第1行第1列焊点，第一管 脚组511a内的第1行第2列焊点连接第一管脚组511b内的第1行第2列焊点，第一管脚组511a内的第1行第3列焊点连接第一管脚组511b内的第1行第3列焊点。其它行上的电连接结构与第1行的电连接结构的连接方式相同。在此不再赘述。
需要说明，在本申请实施例中，根据封装结构设计的需要，第一再布线层321可以为单层布线层，也可以为多层布线层。当第一再布线层包括多层第一再布线子层时，为了信号质量和改善信号间的串扰，设定任意一层第一再布线子层所在的平面作为其它第一再布线子层的参考平面，其它第一再布线子层用于形成不同裸芯片之间的互连结构。换句话说，当第一再布线层321包括多层布线层时，该多层布线层包括参考层和线路层，其中，参考层所在的平面作为线路层的参考面。其中，线路层用于形成不同裸芯片之间的互连结构。
在本申请实施例中，当第一再布线层包括多层第一再布线子层时，不同第一再布线子层之间可以设置有绝缘介质层，该绝缘介质层可以为有机介质层，例如可以为聚合物材料制成的介质层。该聚合物材料可以为PI，PBO或环氧树脂基聚合物。此外，绝缘介质层上的通孔或通孔区域的最小尺寸可达5um/10um或更小。
在本申请实施例中，通过第一基板32上的第一再布线层321以及第一焊垫阵列中的第一焊垫322分别与裸芯片341和342上的第二管脚阵列C2中的第二管脚352之间形成互连结构，从而实现裸芯片341和342的互连。在该互连结构中，第一基板32上的第一再布线层321像连接裸芯片341和裸芯片342的桥梁，所以，可以将第一基板32称为桥式基板。
作为本申请的一可选实施例，第一基板32的横截面尺寸只需要满足能够与裸芯片341和342的第二管脚阵列的贴合即可，无需大于待集成的多颗裸芯片的总尺寸。因此，本申请实施提供的芯片的耗材较低。
作为本申请的另一可选实施例，为了保证裸芯片之间的高密度互连的性能要求，在工艺条件允许的条件下，裸芯片之间的间距要尽量小，例如裸芯片之间的间距可以为50μm甚至更小。在扇出单元31中，裸芯片341和342的侧面被模塑料包裹。并且，在本申请实施例中，裸芯片341和342最外侧的模塑料的外延宽度可以灵活设计，一般可以小于5mm。。也就是说，扇出单元31最外侧的模塑料在裸芯片的厚度方向上可以根据需要外延一定的宽度，从而可以简化基板的设计及层数。
此外，在本申请实施例中，裸芯片341和342可以为无源裸芯片，也可以为功能裸芯片。更具体地说，裸新片341和342可以为同质或异质，例如模拟裸新片与数字裸新片的集成，不同工艺节点的裸新片的集成，不同功能裸新片的集成，不同数量裸新片叠加后的集成。此外，裸芯片341和342还可以为堆叠裸芯片。
需要说明，第一管脚351用于将裸芯片上的I/O管脚引出到芯片外围，第二管脚352用于实现不同裸芯片之间的互连，因此，为了方便管脚与焊垫之间的连接，作为本申请的又一可选实施例，第一管脚351的尺寸大于第二管脚352的尺寸。更具体地说，第一管脚351的高度大于第二管脚352的高度，并且第一管脚351的横截面尺寸也大于第二管脚352的横截面尺寸。
作为本申请的一可选实施例，在第一管脚阵列中，相邻两个第一管脚351之间的间距为第一间距d1，在第二管脚阵列中，相邻两个第二管脚352之间的间距为第二间距d2，其 中，第一间距d1可以大于第二间距d2，以更加有利于相对应的管脚与焊垫之间的连接。
需要说明，在本申请实施例中，第一焊垫阵列中的第一焊垫用于与第二管脚阵列中的第二管脚连接，因此，作为本申请的一可选实施例，单个第一焊垫的横截面尺寸与单个第二管脚的横截面尺寸可以相同。
作为示例，第一管脚351可以为铜柱(Cu pillar)，第二管脚352可以为焊接凸块(solder bump)。
在本申请实施例中，第一焊垫322可以为各种形式的电连接结构。例如其可以为焊接凸块、突出的金属接口或者平的金属盘。其中，焊接凸块可以为钎料焊块。
此外，作为本申请实施例的扩展，上述第一管脚351和第二管脚352不限于上述示例的各个具体管脚结构。举例来说，第一管脚351不限定为铜柱，第二管脚352也不限定为焊接凸块。实际上，在本申请实施例中，第一管脚351可以由铜柱和焊接凸块中的至少一种组成。同理，第二管脚352也可以由铜柱和焊接凸块中的至少一种组成。
当第一管脚351为铜柱和焊接凸块共同组成的结构时，对应的芯片的剖面示意图如图7所示。需要说明，图7所示的芯片结构与图4所示的芯片除了第一管脚351的结构不同外，其它部件及其结构均相同。在图7所示的芯片结构中，每个第一管脚351包括相互连接的铜柱部分3511和焊接凸块部分3512。需要说明，因第一管脚351的尺寸较大，第一管脚351采用由相互连接的铜柱部分3511和焊接凸块部分3512组成的结构，可以方便第一管脚351的制备。
此外，作为本申请的又一可选实施例，因第一焊垫阵列中的各个第一焊垫之间的间隙较小，若采用模塑料通过模塑工艺来填充其间隙，可能会导致该间隙的填充效果差的问题，为了提高第一焊垫阵列中的各个第一焊垫之间的间隙的填充效果，进而提高芯片的可靠性，如图8所示，本申请实施例中，不同第一焊垫322之间的间隙内填充有填充胶71。需要说明，图8所示的封装结构与图4所示的芯片结构基本相同，其不同之处仅在于图8所示的芯片结构中包括填充在第一焊垫阵列中的各个第一焊垫322之间的间隙内的填充胶71。
作为本申请的又一可选实施例，用于制作第一基板32的的材料可以为硅基材料、树脂材料和玻璃材料等任何介质材料。更具体地说，第一基板32可以为硅基板，此外，第一基板32可以为通过扇出再布线层技术加工成的基板，在该具体示例下，第一基板32可以常采用树脂材料和电镀铜技术制作完成。此外，第一基板32也可以表面制作有互连电路的玻璃基板，其中，互连电路可以通过刻蚀和电镀工艺在玻璃材料表面上加工而成。需要说明，在本申请实施例中，形成于第一基板32上的第一再布线层的线宽和线距均可以达到0.4μm。
需要说明，上述实施例中所述的芯片中，第一基板32的作用为实现裸芯片互连，其上仅设置有实现裸芯片互连的再布线层和电连接结构。实际上，作为本申请实施例的扩展，为了能够向第一基板32上的第一再布线层32供电，如图9所示的封装结构，第一基板32的内部还可以设置有与第一再布线层321电连接的通孔323，该通孔323延伸至第一基板32的第二表面。其中，第一基板32的第二表面与第一基板32的第一表面相对。
该通孔323可以电连接至芯片外围的电路上，如此，通过该通孔323，芯片外围的电能能够通过第一通孔323传输至第一再布线层321上。
作为本申请的另一可选实施例，第一基板32上还可以设置有逻辑芯片。作为更具体示例，可以在该逻辑芯片内部设置有逻辑层(图9中未示出)，该逻辑层与通孔323电连接，如此，通过该通孔323能够实现所述逻辑层与外界之间的信号传输。也就是说，通孔323能够将逻辑层上的信号引出到第一基板32的第二表面，并与外界进行信号传输。
需要说明，上述各个实施例所述的芯片通过设置在裸芯片第一表面上的第一管脚阵列中的各个第一管脚351将裸芯片的I/O管脚引出到芯片外围区域。如此，可以实现芯片的小型化，从而满足终端消费类芯片的小型化需求。
另外，随着裸芯片管脚密度的增加，裸芯片上的管脚间距越来越小，导致裸芯片上的管脚很难直接与芯片外围电路电连接。也就是说，针对裸芯片管脚直接与芯片外围电路的连接的芯片结构，其与芯片外围电路的电性连接受限于裸芯片的管脚的尺寸和排布。
基于此，为了方便裸芯片上的管脚与芯片外围电路的电连接，使得芯片与芯片外围电路的电性连接不受限于裸芯片上管脚的尺寸和排布，本申请实施例在上述任一实施例的基础上还可以在塑封体的下方增设一用于与裸芯片上的管脚直接电连接的基板，具体参见图10A。
需要说明，作为示例，图10A所示的芯片是在上述图4所示的芯片的基础上进行改进得到的。
如图10A所示，本申请实施例提供的芯片的另一种具体实现方式除了包括上述具体实现方式中所述的各个部件之外，还可以包括：
第二基板91，该第二基板91通过布线层增层工艺直接设置于塑封体33的下方；
该第二基板91上设置有第二再布线层(图中未示出)，并且该第二基板91包括相对的第一表面和第二表面，为了清楚地理解第二基板91的第一表面结构，本申请实施例还提供了第二基板91的第一表面结构示意图。如图10B所示，该第二基板91的第一表面上设置有与第二再布线层电连接的第二焊垫阵列，该第二焊垫阵列包括多个第二焊垫911。第二焊垫911可以为金属凸块或金属焊盘，也可以为凸出的金属接口。其中，金属凸块可以为钎料焊块。
需要说明，在本申请实施例中，第二再布线层可以包括多层再布线层，该多层再布线层可以均匀分布在第二基板91的整个厚度内。如此，第二再布线层可以不仅分布在第二基板91的第一表面上，还可以分布在第二基板91的内部。
此外，该第二基板91的第二表面上设置有第三焊垫阵列，该第三焊垫阵列包括多个第三焊垫912；在本申请实施例中，该第三焊垫912用于实现芯片与芯片外围电路的电连接。作为示例，第三焊垫912可以为金属焊球。
在本申请实施例中，第二焊垫阵列与第一管脚阵列相对，且第二焊垫阵列中的每个第二焊垫912电连接至第一管脚阵列中对应的第一管脚351。
在图10A所示的芯片实施例中，裸芯片341和342上的第一管脚阵列中的各个第一管脚351先电连接至第二基板91上的第二焊垫阵列中的对应的各个第二焊垫上，第二基板 91上的第三焊垫阵列中的各个第三焊垫与芯片外围电路电连接。如此，裸芯片341和342上的第一管脚351通过第二基板91电连接至芯片外围电路上。因第二基板91可以提供更大的线路设计空间，其上的第三焊垫912之间的密度可以比裸芯片上的第一管脚351的密度小，因此，相较于裸芯片341和342上的第一管脚351，第二基板91上的第三焊垫912可以比较容易地通过焊接工艺电连接至芯片外围电路上，所以，本申请实施例提供的芯片上即使包括高管脚密度的裸芯片，也能够很方便地实现裸芯片与芯片外围电路的电连接，因此，图10A所示的芯片中，其与芯片外围电路的电性连接不再受限于裸芯片的管脚的尺寸和排布。因而，该芯片结构能够减少裸芯片管脚排布对芯片与芯片外围电路电性连接的限制。
作为本申请的又一可选实施例，如图10A所示的芯片结构，第一基板32可以与第二基板91相接触。实际上，作为本申请实施例的扩展，第一基板32也可以不与第二基板91接触，其与第二基板91之间存在一定间隙，也就是说，第一基板32悬空在第二基板91的上方。更具体地说，在本申请实施例中，只要能够将第一基板32放置在扇出单元31和第二基板91之间即可，对第一基板32的厚度不做具体限定。
此外，如图10A所示，第二基板91的横截面尺寸可以与扇出单元31的横截面尺寸相当。如此，可以实现封装结构的小型化，以满足终端消费类芯片的小型化需求。
此外，第二基板91可以直接在塑封体33远离扇出单元31的表面上制作。具体地，通过在塑封体33远离扇出单元31的表面上涂覆介质层，例如PI/PBO材料，然后在介质层表面生长铜导电线路，逐层叠加，直至完成第二再布线层的制作；在制作第二再布线层的同时，在第一管脚阵列相对的位置上制作与其相对应的第二焊垫阵列。在制作完第二再布线层和第二焊垫阵列之后，继续涂覆介质层，然后在该介质层的表面上制作由多个第三焊垫912组成的第三焊垫阵列。
上述图10A所示的芯片中，通过一块第二基板91将裸芯片上的I/O管脚引出到芯片的外围区域，实现其与PCB板的电连接。该第二基板91能够提供较大的线路设计空间，便于芯片与芯片外围电路的电连接。
此外，为了进一步增加芯片的布线资源和封装的管脚数，改善封装的电源完整性，同时改善芯片的板级可靠性，本申请实施例还提供了芯片的另一种具体实现方式。
请参见图11和图11’。其中，图11为本申请实施例提供的另一种芯片剖面示意图，图11’为本申请实施例提供的另一种芯片结构俯视图。
需要说明，作为示例，图11和图11’所示的芯片结构是在上述图10A所示的芯片结构的基础上进行改进得到的。
如图11和图11’所示，本申请实施例提供的芯片结构的另一种具体实现方式除了包括上述具体实现方式中所述的各个部件之外，还可以包括：
设置于第二基板91下方的第三基板101，该第三基板101包括相对的第一表面和第二表面，该第三基板101的第一表面上设置有第四焊垫阵列，该第三基板101的第二表面上设置有第五焊垫阵列，第四焊垫阵列包括多个第四焊垫1011，第五焊垫阵列包括多个第五焊垫1012。
其中，第四焊垫阵列与第三焊垫阵列相对，且所述第四焊垫阵列中的每个第四焊垫1011电连接至所述第三焊垫阵列中相对的第三焊垫912；
第五焊垫阵列中的第五焊垫1012用于实现芯片与所述芯片外围的信号传输。
作为一示例，第四焊垫1011可以为金属凸点，第五焊垫1012可以为金属焊球。作为更具体示例，该金属焊球可以为钎料焊球，通过焊接的方式与PCB板连接在一起。作为另一示例，第五焊垫1012还可以为金属焊盘，通过插接(socket)的方式与外围区域的PCB板连接在一起。
需要说明，在本申请实施例中，第三基板101的横截面尺寸可以大于扇出单元31的横截面尺寸。作为另一示例，第三基板101的横截面尺寸也可以等于扇出单元31的横截面尺寸。
在图11和图11’所示的芯片结构中，裸芯片上的I/O管脚通过第二基板91和第三基板101布线引出到芯片外围区域。在该具体实现方式中，通过两块基板将裸芯片上的I/O管脚引出，增加了芯片结构的布线资源和封装的管脚数，改善了封装的电源完整性，同时改善了芯片结构的板级可靠性。
作为本申请的一可选实施例，为了缓解第一管脚351与第二基板91之间的应力，进而提高整个芯片结构的可靠性，在图11所示的芯片结构中，还可以包括填充在第二基板91和第三基板101之间的填充胶102。
此外，为了提高芯片结构的散热性能，本申请实施例还提供了芯片结构的又一种具体实现方式。
请参见图12。图12所示的芯片结构是在图11所示的芯片结构的基础上进行改进得到的。因此，图12所示的封装结构除了包括图11所示的封装结构的各个部件以外，还可以包括：
设置在裸芯片341和342第二表面上的散热片111，其中，裸芯片341和342的第二表面与裸芯片341和342的第一表面相对。
作为本申请的具体示例，散热片111可以通过导热胶与裸芯片341和342第二表面粘合在一起，从而能够为大功耗的芯片提供良好的散热途径。
另外，为了有利于裸芯片341和342工作时产生的热量，作为本申请的一可选实施例，每颗裸芯片的第二表面不被模塑料包裹，同时若满足散热需求，每颗裸芯片的第二表面也可以被模塑料包裹。需要说明，若裸芯片的功率较小，产生的热量较少，每颗裸芯片的第二表面也可以被模塑料包裹。
此外，作为本申请的另一可选实施例，当第三基板101的横截面尺寸可以大于扇出单元的横截面尺寸时，为了能够控制封装结构的翘曲和结构的可靠性，散热片111还可以与第三基板101连接在一起。更具体地说，散热片111可以通过粘合剂粘合在第三基板101 的正面上。
作为示例，散热片111可以为整体结构，也可以为分体结构，当为整体结构时，散热片111可以呈帽状结构，也可以呈曲面型结构。当散热片111呈帽状结构时，散热片111将扇出单元31遮罩，并且散热片111的边缘固定在第三基板101上。
需要说明，当散热片111固定在第三基板101上时，可以控制整个芯片结构的翘曲和芯片的可靠性。
以上所述的芯片的具体实现方式是以两颗裸芯片作为待集成的裸芯片为例说明的。实际上，在本申请实施例提供的芯片中不限于两颗裸芯片的互连，其可以为三颗或者更多颗裸芯片的互连。图13展示了集成有四颗裸芯片的扇出型晶圆级封装结构的俯视图。如图13所示，该集成的四颗裸芯片341至344通过第一基板32实现互连。
以上为本申请实施例提供的芯片结构的具体实现方式。基于该芯片结构的具体实现方式，本申请实施例还提供了芯片封装方法的具体实现方式。具体参见以下实施例。
请参见图14至图15D。本申请实施例提供的一种扇出型晶圆级封装结构的封装方法包括以下步骤：
S141：分别制作扇出单元31和第一基板32。
作为一具体示例，制作扇出单元31的实现方式可以具体包括以下步骤：
A1：根据设计要求把裸芯片的原始晶圆进行减薄，然后将该减薄后的晶圆切割成单颗裸芯片。
每颗裸芯片的第一表面上均设置有第一管脚窗口阵列和第二管脚窗口阵列，其中，第一管脚窗口阵列中包括多个间距为第一间距d1的第一管脚窗口，第二管脚窗口阵列中包括多个间距为第二间距d2的第二管脚窗口。其中，第一管脚窗口的尺寸大于第二管脚窗口的尺寸，第一间距d1大于第二间距d2。
A2：把待集成的多颗裸芯片341和342按照预设位置排列放置在临时载体上140。
如图15A1所示，按照设计要求将待集成的多颗裸芯片341和342按照预设位置排列放置在临时载体140上。
需要说明，在本申请实施例中，临时载体140的尺寸可以与原始晶圆的尺寸相同。该临时载体140可以为膜材料层，该膜材料层可以为采用树脂类材料制作成的膜。
为了保证裸芯片之间的高密度互连的性能要求，在工艺条件允许的前提下，裸芯片之间的间距要尽量小，例如裸芯片之间的间距可以为50μm甚至更小。裸芯片341和342的侧面被模塑料包裹。并且，在本申请实施例中，裸芯片341和342最外侧的模塑料的外延宽度可以灵活设计，一般可以小于5mm。也就是说，扇出单元31最外侧的模塑料在裸芯片的厚度方向上可以外延一定的宽度，从而可以简化基板的设计及层数。
A3：采用模塑料对放置在临时载体140上的多颗裸芯片341和342进行模封，从而形成扇出单元31。
需要说明，在本申请示例中，模封完成后，将模封在一起的多颗裸芯片从临时载体上取下来，该模封在一起的多颗裸芯片形成了扇出单元。形成的扇出单元31如图15A2所示， 在该扇出单元31中，每颗裸芯片的侧面被模塑料141包裹。每颗裸芯片的正面不被模塑料所包裹，即每颗裸芯片的正面暴露在外，如此，每颗裸芯片的第一管脚窗口阵列和第二管脚窗口阵列暴露在外。
A4：在每颗裸芯片的第一管脚窗口阵列的每个第一管脚窗口中形成第一管脚351，从而形成第一管脚阵列C1，在每颗裸芯片的第二管脚窗口中形成第二管脚352，从而形成第二管脚阵列C2。
如图15A3所示，在每颗裸芯片的第一管脚窗口阵列的每个第一管脚窗口中形成第一管脚351，从而形成第一管脚阵列C1，在每颗裸芯片的第二管脚窗口中形成第二管脚352，从而形成第二管脚阵列C2。
作为示例，第一管脚351可以为铜柱，第二管脚352可以为钎料凸块。
需要说明，在每个第一管脚窗口中形成第一管脚351之前以及在每个第二管脚窗口中形成第二管脚352之前，还需要在每个第一管脚窗口表面上和每个第二管脚窗口表面上形成凸点下金属。
下面介绍制作第一基板32的具体实现方式。需要说明，第一基板32上可以设置有与外界进行信号传输的通孔，也可以不设置有与外界进行信号传输的通孔，下面分这两种情况分别介绍第一基板32的具体实现方式。
首先介绍不设置有与外界进行信号传输的通孔的第一基板32的具体实现方式，作为一具体示例，制作第一基板32的实现方式可以具体包括以下步骤：
B1：根据封装结构的设计要求，将原始晶圆表面划分为第一区域和第二区域。
B2：在原始晶圆的第一区域制作第一再布线层321，然后在原始晶圆的第二区域制作各个凸点下金属，并在每个凸点下金属上方制作第第一焊垫322，从而形成第一焊垫阵列。
作为示例，可以通过电镀或植球的方式在第二区域制作各个凸点下金属。
此外，第一焊垫322可以为322可以为铜柱，也可以为金属凸点。
B3：将制作好第一再布线层321和第三电连接结构322的晶圆切割分成单个第一基板32。
在该情形下，形成的单个第一基板32的剖面结构示意图如图15A4所示。
下面介绍设置有与外界进行信号传输的通孔的第一基板32的具体实现方式。在该情形下，制作第一基板32的实现方式可以包括以下步骤：
B’1：根据封装结构的设计要求，将原始晶圆正面划分为第一区域和第二区域。
B’2：原始晶圆的第一区域制作第一再布线层321，然后在原始晶圆的第二区域制作各个凸点下金属，并在每个凸点下金属上方制作第一焊垫322，从而形成第一焊垫阵列。
作为示例，可以通过电镀或植球的方式在第二区域制作各个凸点下金属。
此外，第一焊垫可以为322可以为铜柱，也可以为钎料凸点。
B’3：在原始晶圆内部制作通孔，该通孔与第一再布线层321实现电连接。
需要说明，可以采用TSV工艺在原始晶圆内部制作通孔。
B’4：在原始晶圆的背面制作与通孔电连接的金属焊垫。
B’4：将制作好的第一再布线层321和第一焊垫322、通孔以及金属焊垫的晶圆切割分成单块第一基板32。
在该情形下，形成的单块第一基板32的剖面结构示意图如图15A5所示。
S142：将第一基板32置于扇出单元31的下方，并且使第二管脚阵列中的每个第二管脚352与第一焊垫阵列中相对应的第一焊垫322贴合在一起，从而使不同裸芯片341和342之间通过第一基板32实现互连。
在本申请实施例中，通过第一基板32实现各颗裸芯片的互连。因此，如图15B所示，将设置在第一基板32第一表面上的第一焊垫阵列中的各个第一焊垫和与之相对应的各颗裸芯片341和342上的第二管脚阵列中的第二管脚352贴合连接在一起，从而使得不同裸芯片之间通过设置在第一基板32上的第一再布线层321实现互连。
为了便于第一焊垫阵列中的各个第一焊垫与第二管脚阵列中对应的第二管脚的贴合，作为一具体示例，第一基板32与扇出单元31之间可以采用热风重熔(Mass Reflow)或热压键合(Thermo Compression Bonding)方式连接在一起。
S143：使用模塑料对贴合在一起的扇出单元31和第一基板32进行塑封，形成包裹各个第一管脚351、各个第二管脚352和第一基板32的塑封体33。
为了方便装配，需要使第一管脚阵列的表面与第一基板32的背面处于同一平面上，因此，在本申请实施例中，需要使用模塑料对贴合在一起的扇出单元31和第一基板32进行塑封，形成包裹各个第一管脚351、各个第二管脚352和第一基板32的塑封体33。本步骤执行完对应的剖面结构示意图如图15C所示。
此外，因各个第一管脚351、各个第二管脚352被模塑料包裹，所以，该塑封体33的形成也能提高整个封装结构的可靠性。
S144：研磨塑封体33远离扇出单元31的表面，以露出第一管脚阵列中各个第一管脚的底部。
本步骤可以具体为：采用机械研磨的方法研磨塑封体33远离扇出单元31的表面，以露出第一管脚阵列中的各个第一管脚351的底部。
本步骤执行完对应的剖面结构示意图如图15D所示
S145：在露出的各个第一管脚351的底部形成与外部电连接的焊球36。
为了能够将第一管脚351与外部电路例如PCB板电连接，如图3A所示，在露出的各个第一管脚351的底部上形成金属焊球36。此外，为了实现第一管脚351与焊球36之间更好的电连接，在每个第一管脚351与焊球36之间还可以形成焊垫37。
以上为本申请实施例提供的一种芯片封装方法的具体实现方式。由该具体实现方式封装成的芯片结构中，通过第一基板32实现了裸芯片之间的短距离、高密度的互连。塑封体33用于包裹第一管脚351、第二管脚352以及第一基板32，从而使扇出单元31和第一基板32塑封成一整体结构。在该整体结构中，裸芯片341和342上用于与芯片外围电连接的第一管脚阵列的各个第一管脚底部不被塑封体33包裹，如此，各个第一管脚可以直接电连接至芯片外围。因此，通过本申请实施例提供的芯片，裸芯片上用于与芯片外围电连接的管脚可以直接电连接至芯片外围，无需通过基板作为中介。因此，本申请实施例提供的芯 片的整体尺寸主要取决于集成在一起的多颗裸芯片的尺寸，相较于现有技术，本申请实施例提供的芯片的整体尺寸较小，能够满足芯片小型化的需求。
此外，在本申请实施例中，裸芯片341和342通过第一基板32实现互连的方式也有利于芯片的小型化。
此外，在本申请实施例中，第一基板32可以独立制作，无需在集成在一起的裸芯片上制作，因此，若第一基板32制作过程中出现缺陷，不会导致合格裸芯片的废弃，从而降低了封装成本。
而且，在本申请实施例中，第一基板32的尺寸只要能够满足与裸芯片上的第二管脚352的贴合即可，无需大于或者等于所有集成在一起的裸芯片的尺寸之和，因此，本申请实施例能够降低第一基板32的耗材，从而能够大大降低封装成本。从另一方面来说，如此设计，也有利于芯片的小型化。
此外，在本申请实施例中，第一基板32上的第一再布线层的线宽和线距均可以达到0.4μm，因此，该线宽和线距较小，且制作工艺较为简单。
作为本申请的另一实施例，为了方便裸芯片上的管脚与芯片外围电路的电连接，使得芯片与芯片外围电路的电性连接不受限于裸芯片上管脚的尺寸和排布，第一管脚351可以通过一基板与外部电路连接。基于此，本申请实施例还提供了芯片封装方法的另一种实现方式。
请参见图16。本申请实施例提供的另一种芯片封装方法包括以下步骤：
S161至S164与S141至S144相同，为了简要起见，在此不再详细描述。
S165：通过布线层增层工艺在露出第一管脚阵列中的各个第一管脚底部的表面上制作第二基板91，该第二基板91上设置有第二再布线层(图中未示出)，并且第二基板91包括相对的第一表面和第二表面，第二基板91的第一表面上设置有与第二再布线层电连接的第二焊垫阵列，该第二焊垫阵列包括多个第二焊垫911；所述第二基板91的第二表面上设置有第三焊垫阵列，且所述第三焊垫阵列包括多个第三焊垫912。
本步骤可以具体包括：
在研磨后的塑封体33远离扇出单元31的表面上涂覆介质层，然后在介质层表面制作再布线层，逐层叠加，直至完成第二再布线层的制作(图中未示出第二再布线层)。在制作第二再布线层的同时，在第一管脚阵列相对的位置上制作与其对应的第二焊接阵列。该第二焊垫阵列包括多个第二焊垫911；该第二焊垫911与第二再布线层之间形成电连接。
在制作完第二再布线层和第二焊垫阵列之后，继续涂覆介质层，然后在该介质层的表面上制作第三焊垫阵列，第三焊垫阵列包括多个第三焊垫912。
执行完S165后，对应的剖面结构示意图如图10A所示。
在该实施例中，第二基板91直接制作在塑封体33远离所述扇出单元31的表面上。当第二基板91制作完成后，即可实现裸芯片上的第一管脚与第二基板91的电连接。
需要说明，在本申请实施例中，直接在研磨后的塑封体33远离扇出单元31的表面上制成的第二基板91上布置有多层再布线层，因此，该第二基板91也可以称为RDL载板。
在本申请实施例中，因第二基板91直接制作在研磨后的塑封体33远离扇出单元31的表 面上，因此，第一基板91的横截面尺寸与塑封体33的横截面尺寸相同。而塑封体33的横截面尺寸与扇出单元31的横截面尺寸相同，所以，第一基板91的横截面尺寸与扇出单元31的横截面尺寸相同。
在该实施例形成的芯片结构中，裸芯片341和342上的第一管脚阵列中的各个第一管脚351先电连接至第二基板91上的第二焊垫阵列中的对应的各个第二焊垫上，第二基板91上的第三焊垫阵列中的各个第三焊垫与芯片外围电路电连接。如此，裸芯片341和342上的第一管脚351通过第二基板91电连接至芯片外围电路上。因第二基板91可以提供更大的线路设计空间，其上的第三焊垫912之间的密度可以比裸芯片上的第一管脚351的密度小，因此，相较于裸芯片341和342上的第一管脚351，第二基板91上的第三焊垫912可以比较容易地通过焊接工艺电连接至芯片外围电路上，所以，通过本申请实施例形成的芯片上即使包括高管脚密度的裸芯片，也能够很方便地实现裸芯片与芯片外围电路的电连接，因此，该实施例形成的芯片结构能够减少裸芯片管脚排布对芯片与芯片外围电路电连接的限制。
作为本申请的一可选实施例，为了进一步增加封装结构的布线资源和封装的管脚数，改善封装的电源完整性，同时改善封装结构的板级可靠性，在上述任一封装方法的具体实现方式中，还可以包括以下步骤S1至S2：
S1：制作第三基板101。
如图17所示，第三基板101包括相对的第一表面和第二表面，第三基板101的第一表面上设置有第四焊垫阵列，该第三基板101的第二表面上设置有第五焊垫阵列，第四焊垫阵列包括多个第四焊垫1011，第五焊垫阵列包括多个第五焊垫1012。
在本申请实施例中，第三基板101上的第四焊垫阵列中的各个第四焊垫分别与第二基板91上的第三焊垫阵列中的第三焊垫相对应。
第三基板101上的第五焊垫阵列中的各个第五焊垫1012用于与芯片外围电路电连接。更具体地，第三基板101上的第五焊垫阵列中的各个第五焊垫1012用于与芯片外围区域的PCB板电连接。
需要说明，该可选实施例中，第二基板91上的第三焊垫阵列中的各个第三焊垫912不再用于与外部电路连接，而是用于与第三基板101第一表面上的第四焊垫阵列中的各个第四焊垫1011连接。并且，在该可选实施例中，由第三基板101第二表面上的第五焊垫阵列中的各个第五焊垫1012与芯片外围区域的PCB板电连接。
在制作完第三基板101和通过布线层增层工艺在露出第一管脚阵列中的各个第一管脚底部的表面上制作第二基板91之后，本申请实施例提供的芯片封装方法还可以包括：
S2：将第三基板101置于第二基板91的下方，并且使第四焊垫阵列中的每个第四焊垫1011与第三焊垫阵列中相对应的第三焊垫912贴合，以使第四焊垫阵列中的每个第四焊垫1011电连接至第三焊垫阵列中相对应的第三焊垫912。
作为本申请的另一可选实施例，为了缓解第一管脚351与第二基板91之间的应力，进而提高整个芯片结构的可靠性，上述可选实施例所述的封装方法中，在S2之后，还可以包括以下步骤：
S3：向第二基板91和第三基板101之间填充填充胶102。
执行完该步骤对应的剖面结构示意图如图11所示。
此外，作为本申请的又一可选实施例，因第一焊垫阵列中的第一焊垫322之间的间距较小，在利用模塑料对贴合在一起的扇出单元31和第一基板32进行塑封的过程中，模塑料有可能不能完全包裹各个第一焊垫322，从而导致整个芯片结构的可靠性下降。因此，为了提高第一焊垫阵列中的第一焊垫322之间的填充效果，在上任一实施例的封装方法中，在使用模塑料对贴合在一起的扇出单元31和第一基板32进行塑封前，还可以包括以下步骤：
S4：向第一焊垫阵列中的第一焊垫322之间的间隙内填充填充胶71。
执行完该步骤对应的剖面结构示意图如图8所示。
此外，作为本申请的又一可选实施例，为了提高封装结构的散热性能，上述任一可选实施例所述的封装方法中还可以包括以下步骤：
S5：在裸芯片的第二表面上设置散热片111。
执行完该步骤对应的剖面结构示意图如图12所示。
作为本申请的具体示例，散热片111可以通过导热胶与裸芯片的第二表面粘合在一起，从而能够为大功耗的芯片提供良好的散热途径。
另外，为了更加有利于裸芯片341和342工作时产生的热量，若裸芯片341和342的背面被模塑料包裹，作为本申请的一可选实施例，在S5之前，还可以包括以下步骤：
S6：研磨扇出单元31远离第二基板91的表面，以露出裸芯片341和342的第二表面。
此外，为了能够控制封装结构的翘曲和结构的可靠性，散热片111还可以与第三基板101连接在一起。因此，作为本申请的又一可选实施例，在上述可选实施例的基础上，还可以包括以下步骤：
S7：将扇出单元31遮罩在散热片111内，并将散热片111的边缘固定连接在所述第三基板101上。
当第三基板101的横截面尺寸可以大于扇出单元的横截面尺寸时，散热片111可以通过粘合剂粘合在第三基板101的第一表面上。
以上为本申请实施例提供的芯片及其封装方法的具体实现方式。

Claims (26)

  1. 一种芯片，其特征在于，包括：扇出单元、第一基板和塑封体；
    所述扇出单元包括集成在一起的多颗按照预设位置排列的裸芯片，每颗所述裸芯片的第一表面上设置有第一管脚阵列和第二管脚阵列；所述第一管脚阵列包括多个第一管脚，所述第二管脚阵列包括多个第二管脚；相邻裸芯片上的第二管脚阵列相邻；
    所述第一基板包括第一表面，所述第一基板的第一表面上设置有第一再布线层以及与所述第一再布线层电连接的第一焊垫阵列，且所述第一焊垫阵列包括多个第一焊垫；
    其中，所述第一基板位于所述扇出单元的下方，并且所述第一焊垫阵列与所述第二管脚阵列相对设置，且所述第二管脚阵列中的每个第二管脚与所述第一焊垫阵列中相对应的第一焊垫贴合在一起，从而使不同所述裸芯片之间通过所述第一基板实现互连；
    所述塑封体用于包裹所述第一管脚、所述第二管脚以及所述第一基板，从而使所述扇出单元和第一基板塑封成一整体结构。
  2. 根据权利要求1所述的芯片，其特征在于，所述芯片还包括第二基板，
    所述第二基板通过布线层增层工艺直接设置于所述塑封体的下方；
    所述第二基板上设置有第二再布线层，所述第二基板包括相对的第一表面和第二表面，所述第二基板的第一表面上设置有与所述第二再布线层电连接的第二焊垫阵列，所述第二焊垫阵列包括多个第二焊垫；所述第二基板的第二表面上设置有第三焊垫阵列，且所述第三焊垫阵列包括多个第三焊垫；
    所述第二焊垫阵列与所述第一管脚阵列相对设置，且所述第二焊垫阵列中的每个第二焊垫电连接至所述第一管脚阵列中对应的第一管脚。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述第一基板的内部设置有与所述第一再布线层电连接的通孔，所述通孔延伸至所述第一基板的第二表面，并且所述通孔与芯片外围电连接，其中，所述第一基板的第二表面与所述第一基板的第一表面相对。
  4. 根据权利要求1-3任一项所述的芯片，其特征在于，所述芯片还包括：设置于所述第二基板下方的第三基板；
    所述第三基板包括相对的第一表面和第二表面，所述第三基板的第一表面上设置有第四焊垫阵列，所述第三基板的第二表面上设置有第五焊垫阵列，所述第四焊垫阵列包括多个第四焊垫，所述第五焊垫阵列包括多个第五焊垫；
    其中，所述第四焊垫阵列与所述第三焊垫阵列相对，且所述第四焊垫阵列中的每个第四焊垫电连接至所述第三焊垫阵列中相对的第三焊垫；
    所述第五焊垫阵列中的第五焊垫用于实现所述芯片与所述芯片外围的信号传输。
  5. 根据权利要求1-4任一项所述的芯片，其特征在于，所述芯片还包括设置在所述裸芯片的第二表面上的散热片，其中，所述裸芯片的第二表面与所述裸芯片的第一表面相对。
  6. 根据权利要求5所述的芯片，其特征在于，所述芯片包括设置于所述第二基板下方的第三基板；所述散热片将所述扇出单元遮罩，并且所述散热片的边缘固定在所述第三基板上。
  7. 根据权利要求4所述的芯片，其特征在于，所述第二基板和所述第三基板之间填充有填充胶。
  8. 根据权利要求1-7任一项所述的芯片，其特征在于，所述第一焊垫阵列中的各个第一焊垫之间的间隙内填充有填充胶。
  9. 根据权利要求1-8任一项所述的芯片，其特征在于，用于制作所述第一基板的材料为硅基材料、树脂材料和玻璃材料中的至少一种。
  10. 根据权利要求1-9任一项所述的芯片，其特征在于，所述裸芯片为无源裸芯片或功能裸芯片。
  11. 根据权利要求1-10任一项所述的芯片，其特征在于，所述第二管脚包含铜柱和焊接凸块中的至少一种。
  12. 根据权利要求1-11任一项所述的芯片，其特征在于，实现互连的不同裸芯片之间形成有至少一个互连结构，每个所述互连结构中包括多条互连线。
  13. 根据权利要求12所述的芯片，其特征在于，同一互连结构中的各条互连线的长度均相等。
  14. 根据权利要求1-13任一项所述的芯片，其特征在于，所述第一再布线层包括n层第一再布线子层，其中，n≥1，且n为整数。
  15. 根据权利要求14所述的芯片，其特征在于，所述n≥2，所述n层第一再布线子层包括参考层和线路层，所述参考层所在的平面为所述线路层的参考面。
  16. 根据权利要求4所述的芯片，其特征在于，所述第三基板为激光研磨制备的多层基板或采用机械研磨制备的多层基板。
  17. 根据权利要求1-16任一项所述的芯片，其特征在于，所述第一基板上设置有逻辑芯片。
  18. 一种芯片封装方法，其特征在于，所述芯片封装方法包括：
    分别制作扇出单元和第一基板；所述扇出单元包括集成在一起的多颗按照预设位置排列的裸芯片，每颗所述裸芯片的第一表面上设置有第一管脚阵列和第二管脚阵列；所述第一管脚阵列包括多个第一管脚，所述第二管脚阵列包括多个第二管脚；相邻裸芯片上的第二管脚阵列相邻；所述第一基板包括第一表面，所述第一基板的第一表面上设置有第一再布线层以及与所述第一再布线层电连接的第一焊垫阵列，且所述第一焊垫阵列包括多个第一焊垫；
    将所述第一基板置于所述扇出单元的下方，并且使所述第二管脚阵列中的每个第二管脚与所述第一焊垫阵列中相对应的第一焊垫贴合在一起，从而使不同所述裸芯片之间通过所述第一基板实现互连；
    使用模塑料对贴合在一起的扇出单元和第一基板进行塑封，形成包裹所述第一管脚、所述第二管脚以及所述第一基板的塑封体。
  19. 根据权利要求18所述的芯片封装方法，其特征在于，所述方法还包括：
    当所述塑封体包裹所述第一管脚阵列中的各个第一管脚的底部时，研磨所述塑封体远离所述扇出单元的表面，以露出所述第一管脚阵列中的各个第一管脚的底部；
    通过布线层增层工艺在露出所述第一管脚阵列中的各个第一管脚底部的表面上制作第二基板，所述第二基板上设置有第二再布线层，所述第二基板包括相对的第一表面和第 二表面，所述第二基板的第一表面上设置有与所述第二再布线层电连接的第二焊垫阵列，所述第二焊垫阵列包括多个第二焊垫；所述第二基板的第二表面上设置有第三焊垫阵列，且所述第三焊垫阵列包括多个第三焊垫；
    其中，所述第二焊垫阵列与所述第一管脚阵列相对设置，且所述第二焊垫阵列中的每个第二焊垫电连接至所述第一管脚阵列中对应的第一管脚。
  20. 根据权利要求19所述的芯片封装方法，其特征在于，所述在露出所述第一管脚阵列中的各个第一管脚底部的表面上制作第二基板，具体包括：
    在露出所述第一管脚阵列中的各个第一管脚底部的表面上涂覆介质层，然后在所述介质层表面制作再布线层，逐层叠加，直至完成第二再布线层的制作；在制作所述第二再布线层的同时，在第一管脚阵列相对的位置上制作第二焊垫阵列，其中，所述第二焊垫阵列包括多个第二焊垫；且一个所述第二焊垫对应一个第二焊垫，；
    在制作完第二再布线层和第二焊垫阵列之后，继续涂覆介质层，然后在该介质层的表面上制作由多个第三焊垫组成的第三焊垫阵列。
  21. 根据权利要求19或20所述的芯片封装方法，其特征在于，所述芯片封装方法还包括：
    制作第三基板，所述第三基板包括相对的第一表面和第二表面，所述第三基板的第一表面上设置有第四焊垫阵列，所述第三基板的第二表面上设置有第五焊垫阵列，所述第四焊垫阵列包括多个第四焊垫，所述第五焊垫阵列包括多个第五焊垫；
    所述在露出所述第一管脚阵列中的各个第一管脚底部的表面上制作第二基板之后，所述芯片封装方法还包括：
    将所述第三基板置于所述第二基板的下方，并且使所述第四焊垫阵列与所述第三焊垫阵列相对，且使所述第四焊垫阵列中的每个第四焊垫与所述第三焊垫阵列中相对应的第三焊垫贴合，以使所述第四焊垫阵列中的每个第四焊垫电连接至所述第三焊垫阵列中相对应的第三焊垫。
  22. 根据权利要求21所述的芯片封装方法，其特征在于，所述将所述第三基板置于所述第二基板的下方，并且使所述第四焊垫阵列中的每个第四焊垫与所述第三焊垫阵列中相对应的第三焊垫贴合后，还包括：
    向所述第二基板和所述第三基板之间填充填充胶。
  23. 根据权利要求18-22任一项所述的芯片封装方法，其特征在于，所述使用模塑料对贴合在一起的扇出单元和第一基板进行塑封前，还包括：
    向所述第一焊垫阵列中的各个第一焊垫之间的间隙内填充填充胶。
  24. 根据权利要求18-23任一项所述的芯片封装方法，其特征在于，所述芯片封装方法还包括：
    在所述裸芯片的第二表面上设置散热片，其中，所述裸芯片的第二表面与所述裸芯片的第一表面相对。
  25. 根据权利要求24所述的芯片封装方法，其特征在于，所述在所述裸芯片的第二表面上设置散热片之前，还包括：
    研磨所述扇出单元远离所述第二基板的表面，以露出所述裸芯片的第二表面。
  26. 根据权利要求21所述的芯片封装方法，其特征在于，所述芯片封装方法还包括：
    在所述扇出单元远离所述第二基板的表面上设置散热片，所述散热片将所述扇出单元遮罩，并且所述散热片的边缘固定在所述第三基板上。
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