CN112599427B - 一种形成封装件的方法及封装件 - Google Patents
一种形成封装件的方法及封装件 Download PDFInfo
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- CN112599427B CN112599427B CN202011411137.8A CN202011411137A CN112599427B CN 112599427 B CN112599427 B CN 112599427B CN 202011411137 A CN202011411137 A CN 202011411137A CN 112599427 B CN112599427 B CN 112599427B
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- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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Abstract
本发明提供了一种形成封装件的方法和封装件,方法包括:提供载体和至少一组芯片,每组芯片至少包括第一芯片和第二芯片;将每组芯片的第一芯片和第二芯片正面朝上装设于载体表面,其中第一芯片和第二芯片的上方表面具有第一凸点;将互联器件附接至第一芯片和第二芯片的上方表面,以使每组芯片的第一芯片通过互联器件能够电性连接至第二芯片;在第一芯片和第二芯片的周围形成一塑封层,其中第一芯片和第二芯片和互联器件嵌于塑封层内;在塑封层远离载体的一侧表面进行减薄处理,以暴露出第一芯片和第二芯片的第一凸点;在塑封层暴露出第一凸点的一侧表面形成第二凸点以及,移除载体。利用上述方法,为多芯片联接提供了灵活,高效和低成本的封装方案。
Description
技术领域
本发明属于半导体领域,具体涉及一种形成封装件的方法及封装件。
背景技术
本部分旨在为权利要求书中陈述的本发明的实施方式提供背景或上下文。此处的描述不因为包括在本部分中就承认是现有技术。
随着人工智能时代的到来,半导体集成电路的发展趋势是功能越多且计算速度越快。如果简单使用大芯片的SOC集成来满足这个发展趋势,无疑会使电路设计的难度越来越高,制造成本越来越昂贵。更为实际的解决方案则是采用多个小芯片的异质集成技术来完成功能集成的目的。基于此,目前对于高端封装的重要任务是发展高效率,高密度的多芯片互联技术,通过裸芯片之间的直接联接来形成芯片的物理层功能区块,以此来代替大芯片的SOC集成,实现低成本和高自由度,并具有相同的功能性。
现有的多芯片互联技术中,诸如嵌入式多芯片互联桥接(EMIB)通常采用在基板中嵌入硅桥以实现芯片互联,可以增加互联密度和互联效率。然而现有技术中的EMIB需要采用复杂的封装工艺,且成本高昂。
发明内容
针对上述现有技术中存在的问题,提出了一种形成封装件的方法以及封装件,利用这种方法和封装件,能够解决上述问题。
本发明提供了以下方案。
第一方面,提供一种形成封装件的方法,包括:提供载体和至少一组芯片,其中每组芯片至少包括第一芯片和第二芯片;将每组芯片包含的第一芯片和第二芯片正面朝上装设于载体的表面,其中第一芯片和第二芯片的上方表面具有第一凸点;将互联器件附接至第一芯片和第二芯片的上方表面,以使每组芯片包含的第一芯片通过互联器件能够电性连接至第二芯片;在第一芯片和第二芯片的周围形成一塑封层,其中第一芯片和第二芯片和互联器件嵌于塑封层内;在塑封层远离载体的一侧表面进行减薄处理,以暴露出第一芯片和第二芯片的第一凸点;在塑封层暴露出第一凸点的一侧表面形成第二凸点;以及,移除载体。
在一些实施例中,芯片组数大于1,方法还包括:移除载体之后,对形成的封装件进行切割以获得多个单元封装体,其中每个单元封装体包含一组芯片。
在一些实施例中,互联器件的第一侧面的第一区域形成有多个第一焊盘,用于分别接合至第一芯片的第一凸点,互联器件的第一侧面的第二区域形成有多个第二焊盘,用于分别接合至第二芯片的第一凸点,在互联器件的多个第一焊盘和多个第二焊盘之间形成有扇出电路。
在一些实施例中,互联器件形成为无源器件或有源器件。
在一些实施例中,互联器件形成为具有垂直互联通孔的互联器件。
在一些实施例中,将互联器件附接至第一芯片和第二芯片的上方表面,还包括:将互联器件热压接合至第一芯片和第二芯片的上方表面,其中,互联器件形成为柔性电路。
在一些实施例中,方法还包括:在塑封层暴露出第一凸点的一侧表面形成重布线层,在重布线层上形成多个第二凸点。
在一些实施例中,在塑封层暴露出第一凸点的一侧表面形成第二凸点,包括:在塑封层暴露出第一凸点的一侧表面形成焊料覆盖(solder capping)层。
在一些实施例中,第一芯片的上方表面具有多个高密度第一凸点,第二芯片的上方表面具有多个低密度第一凸点,其中,高密度第一凸点的接触面小于低密度第一凸点,方法还包括:将互联器件的第一焊盘对准接合至第一芯片的高密度第一凸点,以使互联器件的第二焊盘以高密度第一凸点为参考基准自对准接合至第二芯片的低密度第一凸点。
在一些实施例中,第一芯片为处理器芯片,第二芯片为存储芯片。
第二方面,提供一种封装件,包括:第一芯片和第二芯片,其中第一芯片和第二芯片的上方表面具有多个第一凸点;互联器件,形成于第一芯片和第二芯片的上方表面,第一芯片通过互联器件能够电性连接至第二芯片;塑封层,形成于第一芯片和第二芯片的周围,其中第一芯片和第二芯片和互联器件嵌于塑封层内,第一芯片和第二芯片的第一凸点暴露于塑封层的上方表面;多个第二凸点,形成在塑封层的上方表面。
在一些实施例中,互联器件的第一侧面的第一区域形成有多个第一焊盘,用于分别接合至第一芯片的第一凸点,互联器件的第一侧面的第二区域形成有多个第二焊盘,用于分别接合至第二芯片的第一凸点,在互联器件的多个第一焊盘和多个第二焊盘之间形成有扇出电路。
在一些实施例中,互联器件形成为无源器件或有源器件。
在一些实施例中,在一些实施例中,互联器件形成为具有垂直互联通孔的互联器件。
在一些实施例中,互联器件形成为热压接合至第一芯片和第二芯片的上方表面的柔性电路。
在一些实施例中,封装件还包括:重布线层,形成在塑封层暴露出第一凸点的一侧表面,重布线层上形成多个第二凸点。
在一些实施例中,多个第二凸点形成为:在塑封层暴露出第一凸点的一侧表面形成的焊料覆盖(solder capping)层。
在一些实施例中,第一芯片的上方表面具有多个高密度第一凸点,第二芯片的上方表面具有多个低密度第一凸点,其中,高密度第一凸点的接触面小于低密度第一凸点,其中,在封装件中,互联器件的第一焊盘对准接合至第一芯片的高密度第一凸点,以使互联器件的第二焊盘以高密度第一凸点为参考基准自对准接合至第二芯片的低密度第一凸点。
在一些实施例中,第一芯片为逻辑芯片,第二芯片为存储芯片。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果:根据以上实施例的各个方面,通过采用了新的封装结构设计和独特的工艺流程,以更低的成本和更简单的制造过程实现与EMIB技术相同或类似的效果。一方面,其不需要在衬底(substrate)中嵌入互联器件,减少了设计和制造的复杂性和周期时间。另一方面,消除基板的相关成本,从而为多芯片联接提供了灵活和低成本的解决方案。
应当理解,上述说明仅是本发明技术方案的概述,以便能够更清楚地了解本发明的技术手段,从而可依照说明书的内容予以实施。为了让本发明的上述和其它目的、特征和优点能够更明显易懂,以下特举例说明本发明的具体实施方式。
附图说明
通过阅读下文的示例性实施例的详细描述,本领域普通技术人员将明白本文所述的优点和益处以及其他优点和益处。附图仅用于示出示例性实施例的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的标号表示相同的部件。在附图中:
图1为根据本发明一实施例的形成封装件的方法的流程示意图;
图2A至图2E为根据本发明一实施例在形成封装件的过程中的中间阶段的截面示意图;
图3A至图3E为根据本发明另一实施例在形成封装件的过程中的中间阶段的截面示意图;
图4A至图4E为根据本发明又一实施例在形成封装件的过程中的中间阶段的截面示意图;
图5A至图5C为根据本发明一实施例将互联器件和芯片接合的中间阶段的顶视图;
图6A至图6E为根据本发明又一实施例在形成封装件的过程中的中间阶段的截面示意图。
在附图中,相同或对应的标号表示相同或对应的部分。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反,提供这些实施例是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,将互联器件(13、14、15)附接至第一芯片11和第二芯片12的上方表面可以包括第一芯片11、第二芯片12和互联器件(13、14、15)直接接触形成的实施例,并且也可以包括在第一芯片11、第二芯片12和互联器件(13、14、15)之间可以形成额外的部件,从而使得第一芯片11、第二芯片12和互联器件(13、14、15)可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
应理解,诸如“包括”或“具有”等术语旨在指示本说明书中所公开的特征、数字、步骤、行为、部件、部分或其组合的存在,并且不旨在排除一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在的可能性。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上方”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
另外还需要说明的是,在不冲突的情况下,本发明中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本发明。
图1为根据本申请一实施例的形成封装件的方法100的流程示意图。如图1所示,该方法100可以包括步骤101~106。
图2A至图2E示出根据一些实施例的在形成封装件的过程中的中间阶段的截面图。其中,示出了对一组芯片进行封装的过程,以下参考图2A至图2E对上述步骤101~106进行详细描述。
首先参考图2A,首先,执行步骤101:提供载体10、第一芯片11和第二芯片12,将第一芯片11和第二芯片12正面朝上装设于载体10的表面。其中,第一芯片11和第二芯片12的上方表面具有第一凸点20,也可称为芯片管脚,将芯片具有芯片管脚的一侧表面称之为正面,将与正面相对的一侧表面称之为背面。例如,在一些实施例中,第一凸点20可以形成为由导电材料制成的焊料凸点,导电材料包括Cu、Ag、Au等或它们的合金,也可以包括其他材料。例如,在一些实施例中,可以使用诸如封装机器的自动化机器或手工地将两个或多个芯片联接至载体10。在一些实施例中,可以使用粘合膜(未示出)或管芯贴膜(未示出)将第一芯片11和第二芯片12的背面联接至载体10的任意一侧面,使得第一芯片11和第二芯片12的正面远离载体10向外示出,在半导体封装中,也可称之为正面朝上(face-up)。在一些实施例中,包括相同或不同功能的多个芯片可以封装在一起。
接下来,执行步骤102:将互联器件13附接至第一芯片11和第二芯片12的上方表面,以使第一芯片11通过互联器件13能够电性连接至第二芯片12。例如,在一些实施例中,可以将互联器件其中一个区域焊接至第一芯片11的上方表面的边缘区域,将互联器件的另一区域焊接至第二芯片12的上方表面的边缘。例如,在一些实施例中,互联器件13形成为无源器件。在另一些实施例子中,互联器件13也可以形成为有源器件。
参考图2B,接下来,执行步骤103:在第一芯片11和第二芯片12的周围形成一塑封层30,其中第一芯片11和第二芯片12和互联器件13嵌于塑封层30内。例如,在一些实施例中,塑封层30的材料可以包括添加或没有添加硅基或玻璃填料的环氧树脂、有机聚合物或聚合物。在一些实施例中,塑封层30的材料可以包括凝胶型液体的液态模塑化合物。塑封层30也可以包括其他绝缘材料和/或包裹材料或其他材料。
参考图2C,接下来,执行步骤104:在塑封层30远离载体10的一侧表面进行减薄处理,以暴露出第一芯片11和第二芯片12的第一凸点20。例如,在一些实施例中,可以使用化学机械抛光工艺、蚀刻工艺、其他方法将部分的塑封料从第一芯片11和第二芯片12的上方去除。在减薄处理之后,第一芯片11、第二芯片12的第一凸点20(也即芯片管脚)以及互联结构的上部可能会被移除,暴露出第一芯片11、第二芯片12的第一凸点20的导电接触面以及互联结构。
参考图2D,接下来,执行步骤105:在塑封层30暴露出第一凸点20的一侧表面形成第二凸点40。例如,在一些实施例中,可以直接在暴露于塑封层30的一侧表面的第一凸点20的金属接触面上形成第二凸点40,也即在第一凸点20的金属接触面上形成导电材料的焊料凸点作为该第二凸点40。
在另外一些实施例中,也可以在塑封层30暴露出第一凸点20的金属接触面的一侧表面形成重布线(Redistribution Layers,RDL)层50,在重布线层50上形成多个第二凸点40。例如,可以在塑封层30暴露出第一凸点20的一侧表面光刻、电镀出重布线层50,塑封层30的介质材料可以是光敏材料、非光敏材料、液体材料和干膜材料等。在另外一些实施例中,还可以在塑封层30暴露出第一凸点20的一侧表面形成焊料覆盖(solder capping)层,该焊料覆盖层在塑封层30暴露出第一凸点20的一侧表面累计多个导电凸点,用于实现封装件和外部半导体的电性连接,焊料覆盖(solder capping)层制作简单,能够节省成本。
参考图2E,接下来,执行步骤106:移除载体10。例如,在一些实施例中,可以进行切割工艺以去除载体10,上述去除载体10可以利用激光工艺或紫外线(UV)照射工艺,但不限于此。在另一些实施例中,可以利用可撕粘连材料将载体10和芯片联接,并在步骤106中撕掉该载体10以移除,但不限于此。在去除载体10之后,第一芯片11和第二芯片12的背面被暴露出来。
图3A至图3E示出根据另外一些实施例的在形成封装件的过程中的中间阶段的截面图。以下参考图3A至图3E对上述步骤101~106进行详细描述。
参考图3A,首先,执行步骤101:提供载体10、第一芯片11和第二芯片12,将第一芯片11和第二芯片12正面朝上装设于载体10的表面。其中第一芯片11和第二芯片12的上方表面具有第一凸点20;接下来,执行步骤102:将互联器件14附接至第一芯片11和第二芯片12的上方表面,以使第一芯片11通过互联器件14能够电性连接至第二芯片12。相较于上述实施例,图3A至图3E示出封装方法的区别主要在于,其中互联器件14形成为具有垂直互联通孔141的互联器件,垂直互联通孔141具体为TSV(Through Silicon Vias,硅通孔141),这样在封装件的互联器件14的上方表面同样可以形成有I/O管脚。此时,若互联器件14形成为无源器件,则形成为2.5D封装,若互联器件14形成为有源器件,则可以形成为3D封装。
参考图3B,接下来,执行步骤103:在第一芯片11和第二芯片12的周围形成一塑封层30,其中第一芯片11和第二芯片12和互联器件14嵌于塑封层30内。
参考图3C,接下来,执行步骤104:在塑封层30远离载体10的一侧表面进行减薄处理,以暴露出第一芯片11和第二芯片12的第一凸点20。
参考图3D,接下来,执行步骤105:在塑封层30暴露出第一凸点20的一侧表面形成第二凸点40。可以在塑封层30暴露出第一凸点20的金属接触面的一侧表面形成重布线层50,在重布线层50上形成多个第二凸点40。例如,可以在塑封层30暴露出第一凸点20的一侧表面光刻、电镀出重布线层50,塑封层30的介质材料可以是光敏材料、非光敏材料、液体材料和干膜材料等。在一些替代的实施例中,也可以直接在暴露于塑封层30的一侧表面的第一凸点20的金属接触面上形成第二凸点40;还可以在塑封层30暴露出第一凸点20的一侧表面形成焊料封盖层,在上文中已经进行了详细解释,此处不再赘述。
参考图3E,接下来,执行步骤106:移除载体10。
图3A至图3E中示出的在载体10上装设第一芯片11和第二芯片12、将互联器件14附接至第一芯片11和第二芯片12、形成塑封层30、减薄处理、移除载体10各个步骤和上述实施例中所描述的各个步骤相同或类似,此处不再赘述。
图4A至图4E示出根据又一些实施例的在形成封装件的过程中的中间阶段的截面图。以下参考图4A至图4E对上述步骤101~106进行详细描述。
参考图4A,首先,执行步骤101:提供载体10、第一芯片11和第二芯片12,将第一芯片11和第二芯片12正面朝上装设于载体10的表面。其中,第一芯片11和第二芯片12的上方表面具有第一凸点20,也即芯片管脚;接下来,执行步骤102:将互联器件15附接至第一芯片11和第二芯片12的上方表面,以使第一芯片11通过互联器件15能够电性连接至第二芯片12。
相较于上述实施例,图4A至图4E示出封装方法的区别主要在于,其中互联器件15形成为柔性电路,进而上述步骤102可以具体包括:将互联器件15热压接合至第一芯片11和第二芯片12的上方表面。
参考图4B,接下来,执行步骤103:在第一芯片11和第二芯片12的周围形成一塑封层30,其中第一芯片11和第二芯片12和互联器件15嵌于塑封层30内;
参考图4C,接下来,执行步骤104:在塑封层30远离载体10的一侧表面进行减薄处理,以暴露出第一芯片11和第二芯片12的第一凸点20。
参考图4D,接下来,执行步骤105:在塑封层30暴露出第一凸点20的一侧表面形成第二凸点40。
参考图4E,接下来,执行步骤106:移除载体10。
图4A至图4E中示出的在载体10上装设第一芯片11和第二芯片12、将互联器件15附接至第一芯片11和第二芯片12、形成塑封层30、减薄处理、移除载体10等各个步骤和上述实施例中所描述的各个步骤相同或类似,此处不再赘述。
根据以上实施例的各个方面,通过采用了新的封装结构设计和独特的工艺流程,以更低的成本和更简单的制造过程实现与EMIB技术相同或类似的效果。一方面,其不需要在衬底(substrate)中嵌入互联器件,减少了设计和制造的复杂性和周期时间。另一方面,消除基板的相关成本,从而为多芯片联接提供了灵活和低成本的解决方案。
图5A至图5C示出根据一些实施例的将互联器件13接合至第一芯片11和第二芯片12的上方表面的示意图。
参考图5A,在一些实施例中,互联器件的第一侧面的第一区域形成有多个第一焊盘131,用于分别接合至第一芯片11的第一凸点20,互联器件13的第一侧面的第二区域形成有多个第二焊盘132,用于分别接合至第二芯片12的第一凸点21,在互联器件13的多个第一焊盘131和多个第二焊盘132之间形成有扇出电路133。可以根据封装件设计预先确定并制造出该互联器件13,其中根据第一芯片11在边缘处的设定区域中的多个第一凸点20的位置在互联器件13中形成对应的多个第一焊盘131,据第一芯片11和第二芯片12之间的设定间距以及第二芯片12在边缘处的设定区域中的多个第一凸点21的位置在互联器件13中形成对应的多个第二焊盘132,以及在对应的第一焊盘131和第二焊盘132之间形成扇出电路133。
可以理解,在半导体芯片的封装过程中,难以避免地存在安装误差,比如第一芯片11和第二芯片12装设于载体10的一侧表面时,产生一定程度的安装间距误差,而互联器件13中的第一焊盘131和第二焊盘132仍然具有芯片设计时确定的标准间距,此时可能导致后续将互联器件13附接在第一芯片11和第二芯片12上方表面时,对应的焊盘和凸点之间难以对准接合。
参考图5A至图5C,根据一些实施例,第一芯片11的上方表面具有多个高密度第一凸点21,第二芯片12的上方表面具有多个低密度第一凸点22,其中,高密度第一凸点21的接触面小于低密度第一凸点22,进而可以首先将互联器件13的第一焊盘131对准接合至第一芯片11的高密度第一凸点21,使将互联器件13的第二焊盘132以第一芯片11的高密度第一凸点21为参考基准自对准接合至第二芯片12的低密度第一凸点22。由此,高密度第一凸点21和第一焊盘131能够实现对准接合,而低密度第一凸点22由于其更大的接触面积而具有更大的容纳误差空间,避免由于误差而导致的难以对准接合的问题。
根据一些实施例,第一芯片11可以为诸如处理器芯片的逻辑芯片,第二芯片12可以为存储芯片。
图6A至图6E示出根据另外一些实施例的在形成封装件的过程中的中间阶段的截面图。其中,示出了对两组芯片进行封装的过程,以下参考图6A至图6E对上述步骤101~106进行详细描述。
首先参考图6A,首先,执行步骤101:提供载体10和两组芯片,其中每组芯片至少包括第一芯片11和第二芯片12,将第一芯片11和第二芯片12正面朝上装设于载体10的表面。
接下来,执行步骤102:将互联器件13附接至每组芯片的第一芯片11和第二芯片12的上方表面,以使每组芯片的第一芯片11通过互联器件13能够电性连接至第二芯片12。
参考图6B,接下来,执行步骤103:在每组芯片的第一芯片11和第二芯片12的周围形成一塑封层30,其中第一芯片11和第二芯片12和互联器件13嵌于塑封层30内。
参考图6C,接下来,执行步骤104:在塑封层30远离载体10的一侧表面进行减薄处理,以暴露出第一芯片11和第二芯片12的第一凸点20。
参考图6D,接下来,执行步骤105:在塑封层30暴露出第一凸点20的一侧表面形成第二凸点40。
参考图6E,接下来,执行步骤106:移除载体10。相较于上述实施例,图6A至图6E示出封装方法的区别主要在于,其中用于封装的芯片组数大于1,进而上述步骤106之后,还需要执行:对形成的封装件进行切割以获得多个单元封装体,其中每个所述单元封装体包含一组芯片。
图6A至图6E中示出的在载体10上装设第一芯片11和第二芯片12、将互联器件14附接至第一芯片11和第二芯片12、形成塑封层30、减薄处理、移除载体10各个步骤和上述实施例中所描述的各个步骤相同或类似,此处不再赘述。
本实施例示出了芯片组数为2的示例,应当理解,芯片组数可以是大于等于1的任意整数,从而可以实现大规模的芯片封装。
本申请实施例还提供了一种封装件。参考图2E,示出根据一些实施例的封装件的截面图,包括:第一芯片11和第二芯片12,其中第一芯片11和第二芯片12的上方表面具有多个第一凸点20;互联器件13,形成于第一芯片11和第二芯片12的上方表面,第一芯片11通过互联器件13能够电性连接至第二芯片12;塑封层30,形成于第一芯片11和第二芯片12的周围,其中第一芯片11和第二芯片12和互联器件13嵌于塑封层30内,第一芯片11和第二芯片12的第一凸点20暴露于塑封层30的上方表面;多个第二凸点40,形成在塑封层30的上方表面。
参考图5A至图5C,在一些实施例中,互联器件13的第一侧面的第一区域形成有多个第一焊盘131,用于分别接合至第一芯片11的第一凸点20,互联器件13的第一侧面的第二区域形成有多个第二焊盘132,用于分别接合至第二芯片12的第一凸点20,在互联器件13的多个第一焊盘131和多个第二焊盘132之间形成有扇出电路133。在一些实施例中,第一芯片11的上方表面具有多个高密度第一凸点21,第二芯片12的上方表面具有多个低密度第一凸点22,其中,高密度第一凸点21的接触面小于低密度第一凸点22,其中,在封装件中,互联器件13的第一焊盘131对准接合至第一芯片11的高密度第一凸点21,互联器件13的第二焊盘132以第一芯片11的高密度第一凸点21为参考基准自对准接合至第二芯片12的低密度第一凸点22。
参考图3E,在另外一些实施例中,互联器件14还可以形成为具有垂直互联通孔141的互联器件。参考图4E,在另外一些实施例中,互联器件15还可以形成为热压接合至第一芯片11和第二芯片12的上方表面的柔性电路15。
参考图3E,在一些实施例中,封装件还可以包括:重布线层50,形成在塑封层30暴露出第一凸点20的一侧表面,重布线层50上形成多个第二凸点40。在另外一些实施例中,多个第二凸点40还可以形成为:在塑封层30暴露出第一凸点20的一侧表面形成的焊料覆盖(solder capping)层。
在一些实施例中,互联器件(13、14、15)可以形成为无源器件或有源器件。
在一些实施例中,第一芯片11为处理器芯片,第二芯片12为存储芯片。
虽然已经参考若干具体实施方式描述了本发明的精神和原理,但是应该理解,本发明并不限于所公开的具体实施方式,对各方面的划分也不意味着这些方面中的特征不能组合以进行受益,这种划分仅是为了表述的方便。本发明旨在涵盖所附权利要求的精神和范围内所包括的各种修改和等同布置。
Claims (15)
1.一种形成封装件的方法,其特征在于,包括:
提供载体和至少一组芯片,其中每组芯片至少包括第一芯片和第二芯片;
将每组芯片包含的所述第一芯片和所述第二芯片正面朝上装设于所述载体的表面,其中所述第一芯片和所述第二芯片的上方表面具有第一凸点;
将互联器件附接至所述第一芯片和所述第二芯片的上方表面,以使每组芯片包含的所述第一芯片通过所述互联器件能够电性连接至所述第二芯片;
在所述第一芯片和所述第二芯片的周围形成一塑封层,其中所述第一芯片和所述第二芯片和所述互联器件嵌于所述塑封层内;
在所述塑封层远离所述载体的一侧表面进行减薄处理,以暴露出所述第一芯片和所述第二芯片的所述第一凸点以及经减薄的互联器件;
在所述塑封层暴露出所述第一凸点的一侧表面形成第二凸点;以及,移除所述载体,
其中,所述互联器件形成为具有垂直互联通孔的互联器件,
其中,在所述塑封层暴露出所述第一凸点和所述经减薄的互联器件的一侧表面形成重布线层,使得所述重布线层能够电性连接至所述第一凸点和所述经减薄的互联器件。
2.根据权利要求1所述的方法,其特征在于,所述芯片组数大于1,所述方法还包括:
移除所述载体之后,对形成的所述封装件进行切割以获得多个单元封装体,其中每个所述单元封装体包含一组芯片。
3.根据权利要求1所述的方法,其特征在于,所述互联器件的第一侧面的第一区域形成有多个第一焊盘,用于分别接合至所述第一芯片的第一凸点,所述互联器件的第一侧面的第二区域形成有多个第二焊盘,用于分别接合至所述第二芯片的第一凸点,在所述互联器件的所述多个第一焊盘和所述多个第二焊盘之间形成有扇出电路。
4.根据权利要求3所述的方法,其特征在于,所述互联器件形成为无源器件或有源器件。
5.根据权利要求1所述的方法,其特征在于,将互联器件附接至所述第一芯片和所述第二芯片的上方表面,还包括:
将所述互联器件热压接合至所述第一芯片和所述第二芯片的上方表面,其中,所述互联器件形成为柔性电路。
6.根据权利要求1所述的方法,其特征在于,所述方法还包括:
在所述重布线层上形成多个所述第二凸点。
7.根据权利要求1所述的方法,其特征在于,在所述塑封层暴露出所述第一凸点的一侧表面形成第二凸点,包括:
在所述塑封层暴露出所述第一凸点的一侧表面形成焊料覆盖层。
8.根据权利要求1所述的方法,其特征在于,所述第一芯片的上方表面具有多个高密度第一凸点,所述第二芯片的上方表面具有多个低密度第一凸点,其中,所述高密度第一凸点的接触面小于所述低密度第一凸点,所述方法还包括:
将所述互联器件的第一焊盘对准接合至所述第一芯片的所述高密度第一凸点,以使所述互联器件的第二焊盘以所述高密度第一凸点为参考基准自对准接合至所述第二芯片的所述低密度第一凸点。
9.一种封装件,其特征在于,包括:
第一芯片和第二芯片,其中所述第一芯片和所述第二芯片的上方表面具有多个第一凸点;
互联器件,附接于所述第一芯片和所述第二芯片的上方表面,所述第一芯片通过所述互联器件能够电性连接至所述第二芯片;
塑封层,形成于所述第一芯片和所述第二芯片的周围,其中所述第一芯片和所述第二芯片和所述互联器件嵌于所述塑封层内,所述第一芯片和所述第二芯片的所述第一凸点以及所述互联器件暴露于所述塑封层的上方表面;
多个第二凸点,形成在所述塑封层的上方表面,
其中,所述互联器件形成为具有垂直互联通孔的互联器件,
所述封装件还包括:重布线层,其形成在所述塑封层暴露出所述第一凸点和所述互联器件的一侧表面,其中,所述重布线层能够电性连接至所述第一凸点和所述互联器件。
10.根据权利要求9所述的封装件,其特征在于,所述互联器件的第一侧面的第一区域形成有多个第一焊盘,用于分别接合至所述第一芯片的第一凸点,所述互联器件的第一侧面的第二区域形成有多个第二焊盘,用于分别接合至所述第二芯片的第一凸点,在所述互联器件的所述多个第一焊盘和所述多个第二焊盘之间形成有扇出电路。
11.根据权利要求10所述的封装件,其特征在于,所述互联器件形成为无源器件或有源器件。
12.根据权利要求9所述的封装件,其特征在于,所述互联器件形成为热压接合至所述第一芯片和所述第二芯片的上方表面的柔性电路。
13.根据权利要求9所述的封装件,其特征在于,所述重布线层上形成多个所述第二凸点。
14.根据权利要求9所述的封装件,其特征在于,所述多个第二凸点形成为:
在所述塑封层暴露出所述第一凸点的一侧表面形成的焊料覆盖层。
15.根据权利要求10所述的封装件,其特征在于,所述第一芯片的上方表面具有多个高密度第一凸点,所述第二芯片的上方表面具有多个低密度第一凸点,其中,所述高密度第一凸点的接触面小于所述低密度第一凸点;
其中,在所述封装件中,所述互联器件的第一焊盘对准接合至所述第一芯片的所述高密度第一凸点,以使所述互联器件的第二焊盘以所述高密度第一凸点为参考基准自对准接合至所述第二芯片的所述低密度第一凸点。
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