WO2018209736A1 - 薄膜晶体管及其制作方法 - Google Patents

薄膜晶体管及其制作方法 Download PDF

Info

Publication number
WO2018209736A1
WO2018209736A1 PCT/CN2017/087368 CN2017087368W WO2018209736A1 WO 2018209736 A1 WO2018209736 A1 WO 2018209736A1 CN 2017087368 W CN2017087368 W CN 2017087368W WO 2018209736 A1 WO2018209736 A1 WO 2018209736A1
Authority
WO
WIPO (PCT)
Prior art keywords
strip
active layer
thin film
film transistor
source electrode
Prior art date
Application number
PCT/CN2017/087368
Other languages
English (en)
French (fr)
Inventor
曾勉
陈书志
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/551,637 priority Critical patent/US10403755B2/en
Publication of WO2018209736A1 publication Critical patent/WO2018209736A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of display panel technologies, and in particular, to a thin film transistor and a method of fabricating the same.
  • TFT-LCD thin film transistor liquid crystal display
  • IGZO Indium Gallium Zinc Oxide
  • FIG. 1a a schematic diagram of a top-gate IGZO TFT structure in the prior art as viewed along the normal direction of the substrate
  • FIG. 1b is a schematic cross-sectional view of the top-gate IGZO TFT structure in FIG. 1a.
  • the gate electrode 11 partially overlaps the IGZO active layer 12, and the drain electrode 13 and the source electrode 14 also overlap with the IGZO active layer 12 and are respectively disposed on the upper and lower sides of the gate electrode 11, and the drain electrode 13
  • the source electrode 14 is connected to the IGZO active layer 12 through the via 15 and the B via 16, respectively. Since the gate electrode 11 and the drain electrode 13 and the source electrode 14 do not overlap, the parasitic capacitance generated by the gate electrode 11 is small. Therefore, the top gate IGZO TFT structure has a great development prospect in the field of display panel applications.
  • FIG. 2a is a schematic cross-sectional view of the ESL IGZO TFT structure of FIG. 2a.
  • the IGZO active layer 22 is disposed inside the gate electrode 21, and the drain electrode 23 and the source electrode 24 are respectively overlapped with the IGZO active layer 22 and sequentially disposed on the upper portion of the IGZO active layer 22 and In the lower portion, the drain electrode 23 and the source electrode 24 are connected to the IGZO active layer 22 through the via hole 25 and the B via hole 26, respectively.
  • the ESL 27 in this TFT structure is used as a protective layer of IGZO to prevent the IGZO active layer 22 from being affected by the metal etching solution in the post process.
  • the electrical structure of the TFT structure can be excellent, so the ESL IGZO TFT structure also has a great development prospect in the field of display panel applications.
  • the width of the TFT channel needs to be made large, so that the TFT is occupied.
  • the larger space is not conducive to the design of the narrow bezel display panel.
  • the present invention proposes a thin film transistor and its fabrication method.
  • the thin film transistor provided by the present invention is disposed on a substrate, and includes a drain electrode, a source electrode, a gate electrode and an active layer, wherein the drain electrode has a comb shape, and the drain electrode includes a plurality of strips arranged in parallel with each other a tooth portion and a first stem portion that communicates the first tooth portions at one end of the first tooth portion; the source electrode is comb-shaped, and the source electrode includes a plurality of second teeth disposed in parallel with each other And a second stem portion that communicates the second tooth portions at one end of the second tooth portion; the first tooth portion and the second tooth portion are arranged in parallel with each other in parallel, the first stem portion and the first stem portion The second stem is oppositely disposed, the drain electrode is connected to the active layer through a first via, and the source electrode is connected to the active layer through a second via.
  • the drain electrode and the source electrode are arranged in a comb-tooth shape, the width of the channel between the drain electrode and the source electrode is increased, and the layout size of the thin film transistor is reduced, thereby achieving space saving. purpose.
  • the active layer is indium gallium zinc oxide.
  • the electron mobility of indium gallium zinc oxide is several tens of times that of the amorphous silicon layer. Therefore, when indium gallium zinc oxide is used as the active layer, the electron mobility of the active layer can be greatly improved, so that the thin film transistor has more High resolution and high frequency drive performance. It is advantageous to apply the thin film transistor to a high performance, large size display device.
  • the active layer when viewed along a normal direction of the substrate, the active layer includes a first strip shape, and the first strip shape overlaps a portion of the first tooth portion while Overlaid with a portion of the second tooth portion.
  • the first via hole may be disposed in an overlapping area of the first strip shape and the first tooth portion, and the second via hole may be disposed in an overlapping area of the first strip shape and the second tooth portion, thereby making the first
  • the strip serves as a channel between the drain electrode and the source electrode, such a channel width is greatly increased, which is advantageous for high resolution and high frequency performance, and the arrangement of the active layer does not increase the overall size of the thin film transistor, which is advantageous for Achieve the design of a narrow bezel display panel.
  • the active layer further includes a second strip shape combined with the first strip shape, A combination of the second strip and the first strip overlaps the source electrode or the drain electrode.
  • a second via may be disposed at both the second tooth portion and the second stem portion of the source electrode as needed, thereby further increasing the source electrode and The width of the channel between the drain electrodes.
  • the first via hole may be disposed at the first tooth portion and the first stem portion of the drain electrode as needed, thereby further increasing the source electrode and The width of the channel between the drain electrodes.
  • the active layer further includes a third strip shape combined with the first strip shape, the third strip shape and the first strip shape, the second strip shape
  • the combined body overlaps the drain electrode and the source electrode. Therefore, the first via hole can be disposed at the first tooth portion and the first stem portion of the drain electrode as needed, and the second via hole is disposed at both the second tooth portion and the second stem portion of the source electrode, thereby further increasing The width of the channel between the source and drain electrodes.
  • the third strip overlaps the drain electrode;
  • the third strip overlaps the source electrode.
  • the gate electrode of the thin film transistor has a wave shape and is disposed in a gap between the drain electrode and the source electrode. This can further reduce the layout space of the thin film transistor and promote the design of the narrow bezel display panel.
  • the orthographic projection of the active layer is located inside the orthographic projection of the gate electrode as viewed in the normal direction of the substrate.
  • the invention also proposes a method for fabricating a thin film transistor comprising the above features, comprising the following steps:
  • S16 forming an interlayer dielectric layer on the entire surface of the substrate, and disposing, on the interlayer dielectric layer, a first via hole and a second pass through the interlayer dielectric layer and exposing the active layer hole;
  • the drain electrode has a comb shape, and the drain electrode includes a plurality of first tooth portions disposed in parallel with each other and a first dry portion that connects the first tooth portions to each other at one end of the first tooth portion;
  • the source electrode has a comb shape, and the source electrode includes a plurality of second tooth portions disposed in parallel with each other and a second dry portion that communicates the second tooth portions at one end of the second tooth portion;
  • the first tooth portion and the second tooth portion are arranged in parallel with each other in parallel, the first stem portion is disposed opposite to the second stem portion, and the drain electrode passes through the first via hole and the active layer Connecting, the source electrode is connected to the active layer through the second via;
  • a protective layer is formed on the entire surface of the substrate.
  • the gate electrode has a wave shape as viewed in the normal direction of the substrate, and is disposed in a gap between the drain electrode and the source electrode.
  • step S15 after the gate electrode is completed, the active layer is electrically connected by an automatic adjustment method.
  • the invention also proposes another manufacturing method of the thin film transistor including the above features, comprising the following steps:
  • the drain electrode has a comb shape, and the drain electrode includes a plurality of first tooth portions disposed in parallel with each other and a first dry portion that connects the first tooth portions to each other at one end of the first tooth portion,
  • the source electrode has a comb shape, and the source electrode includes a plurality of second tooth portions disposed in parallel with each other and a second dry portion that communicates the second tooth portions at one end of the second tooth portion.
  • the first tooth portion and the second tooth portion are arranged in parallel with each other in parallel, the first stem portion is disposed opposite to the second stem portion, and the drain electrode passes through the first via hole and the active layer Connecting, the source electrode is connected to the active layer through the second via;
  • a protective layer is formed on the entire surface of the substrate.
  • the orthographic projection of the active layer is located inside the orthographic projection of the gate electrode as viewed in the normal direction of the substrate.
  • the thin film transistor proposed by the present invention has a comb-tooth shape in which the drain electrode and the source electrode are arranged in a crosswise manner, thereby increasing the width of the channel between the drain electrode and the source electrode, and reducing the layout of the thin film transistor.
  • the size has reached the goal of saving space.
  • the active layer is indium gallium zinc oxide
  • the electron mobility of the channel between the drain electrode and the source electrode is several tens of times that of amorphous silicon, thereby making the thin film transistor have higher resolution and high frequency driving performance. .
  • 1a is a schematic view of a top gate IGZO TFT structure in the prior art as viewed along the normal direction of the substrate.
  • Figure 1b is a schematic cross-sectional view of the top gate IGZO TFT structure of Figure 1a;
  • FIG. 2a is a schematic view showing a structure of an ESL IGZO TFT in the prior art as viewed along a normal direction of the substrate;
  • FIG. 2b is a schematic cross-sectional view of the ESL IGZO TFT structure of FIG. 2a;
  • FIG. 3 is a schematic structural view of a thin film transistor when viewed along a normal direction of a substrate in the first embodiment
  • FIG. 4 is a schematic structural view of a thin film transistor when viewed along a normal direction of a substrate in Embodiment 2;
  • FIG. 5 is a schematic structural view of a thin film transistor when viewed along a normal direction of a substrate in the third embodiment
  • FIG. 6 is a schematic cross-sectional view of the thin film transistor of FIG. 5 at 100;
  • FIG. 7 is a schematic structural view of a thin film transistor when viewed along a normal direction of a substrate in Embodiment 5;
  • FIG. 8 is a schematic structural view of a thin film transistor when viewed along a normal direction of a substrate in Embodiment 6;
  • FIG. 9 is a schematic structural view of a thin film transistor when viewed along a normal direction of a substrate in Embodiment 7;
  • FIG. 10 is a schematic cross-sectional view of the thin film transistor of FIG. 9 at 200.
  • FIG. 10 is a schematic cross-sectional view of the thin film transistor of FIG. 9 at 200.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the comb-shaped drain electrode 310 includes a plurality of first tooth portions 311 disposed in parallel with each other, and also includes a first stem portion 312 that communicates with each other at the upper end of the first tooth portion 311.
  • the comb-shaped source electrode 410 includes a plurality of second tooth portions 411 disposed in parallel with each other, and further includes a second stem portion 412 that communicates with each other at the lower end of the second tooth portion 411.
  • the first tooth portion 311 and the second tooth portion 411 are sequentially parallel to each other, and the first stem portion 312 and the second stem portion 412 are oppositely disposed.
  • the first stem portion 312 is disposed perpendicular to the first tooth portion 311, and the second stem portion 412 is disposed perpendicular to the second tooth portion 411.
  • the first tooth portion 311 includes a first insertion portion 3111 into which the second tooth portion 411 is inserted.
  • the second tooth portion 411 includes a second insertion portion 4111 into which the first tooth portion 311 is inserted.
  • the active layer 50 includes a first strip 51 covering the first insertion portion 3111 and the second insertion portion 4111. That is, the first strip 51 overlaps with a portion of the first tooth portion 311 while overlapping a portion of the second tooth portion 411.
  • the lower end of the first tooth portion 311 and the upper end of the second tooth portion 411 overlap with the first strip 51; that is, the orthographic projection of the first strip 51 is a rectangular structure as viewed along the normal direction of the substrate.
  • first insertion portion 3111 and the second insertion portion 4111 are overlap portions of the first tooth portion 311 and the second tooth portion 411 and the first strip 51, respectively.
  • the gate electrode 40 of the thin film transistor has a wave shape and is disposed in a gap between the drain electrode 310 and the source electrode 410.
  • the first strip 51 since the first strip 51 is disposed in a strip shape, the first strip 5 overlaps with the gate electrode 40 disposed in the gap between the drain electrode 310 and the source electrode 410, as shown in FIG.
  • the first strip 51 overlaps with the middle of the gate electrode 40.
  • a first via 3112 that is connected to the active layer 50 is preferably disposed at the first insertion portion 3111.
  • a second via 4112 that is connected to the active layer 50 is provided at the second insertion portion 4111. Therefore, the drain electrode 310 is connected to the first strip 51 of the active layer 50 through the first via 3112, and the source electrode 410 is connected to the first strip 51 of the active layer 50 through the second via 4112.
  • the layout size of the thin film transistor is reduced, and the channel width between the drain electrode and the source electrode is increased. Conducive to high resolution and high frequency performance.
  • the thin film transistor is applied to a GOA circuit or other circuits, it is advantageous to realize the design of the narrow bezel display panel.
  • the active layer is indium gallium zinc oxide.
  • the electron mobility of indium gallium zinc oxide is several tens of times that of the amorphous silicon layer. Therefore, when indium gallium zinc oxide is used as the active layer, the electron mobility of the active layer can be greatly improved, so that the thin film transistor has more High resolution and high frequency drive performance. It is advantageous to apply the thin film transistor to a high performance, large size display device.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the present embodiment differs from the first embodiment in that the active layer 50 in this embodiment includes not only the first strip 51 but also the second strip 52, the second strip 52 and The first strip 51 is combined, and the two may be a unitary structure.
  • the active layer 50 in this embodiment includes not only the first strip 51 but also the second strip 52, the second strip 52 and The first strip 51 is combined, and the two may be a unitary structure.
  • the second strip 52 and the first strip 51 are of a unitary structure, such an active layer has a simple structure and is convenient to manufacture.
  • the first strip 51 and the second strip 52 have overlapping portions, but this does not affect the performance of the thin film transistor.
  • the first strip 51 and the second strip 52 have a mutual overlap with the source or the drain.
  • the two are now defined as a combination, that is, the second strip 52 and the first A combination of strips 51. As shown in FIG. 4, the combination of the second strip 52 and the first strip 51 overlaps the source electrode 410.
  • the second via hole 4112 can be disposed at both the second tooth portion 411 and the second stem portion 412.
  • the channel width between the drain electrode and the source electrode is further increased, which is advantageous for applying the thin film transistor to high performance and large size. Display device.
  • the combination of the second strip 52 and the first strip 51 may be overlapped with the drain electrode 310.
  • the same technical effect can be achieved by providing the first via hole on each of the 312.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 5 is a schematic view showing the structure of a thin film transistor when viewed along the normal direction of the substrate in the present embodiment.
  • the active layer 50 further includes a third strip 53 which is combined with the first strip 51.
  • the third strip 53 overlaps the drain electrode; when the second strip 52 and the first strip
  • the third strip 53 overlaps with the source electrode, and of course, there are other combinations.
  • the first strip 51, the second strip 52, and the third strip 53 have a common overlap with the source and the drain.
  • the three are now defined as a combination, that is, the first A combination of the three strips 53 and the first strip 51 and the second strip 52.
  • the combination of the third strip 53 and the first strip 51 and the second strip 52 overlaps the drain electrode 310 and the source electrode 410.
  • the third strip 53 and the first strip 51 may have overlapping portions, but this does not affect the function of the thin film transistor.
  • the third strip 53 can be integrated with the first strip 51, that is, the first strip 51, the second strip 52 and the third strip 53 can be an entire surface, and the entire drain electrode 310 and source In the electrode 410, when the first strip portion 51, the second strip portion 52, and the third strip portion 53 are in an integrated structure, such an active layer increases the width of the channel between the source electrode and the drain electrode.
  • the active layer has a simple structure and is convenient to manufacture.
  • a first via 3112 is provided at both the first tooth portion 311 and the first stem portion 312 of the drain electrode 310. This arrangement makes the channel between the drain electrode and the source electrode wavy, and the channel size is further increased, further improving the performance of the thin film transistor.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • FIG. 6 is a schematic cross-sectional view of the thin film transistor of FIG. 5 at 100.
  • the production method is as follows:
  • the metal light shielding layer 61 is then formed using a photolithography technique.
  • the thickness of the metallic light shielding layer 61 herein is preferably about 100 nm.
  • a buffer layer 62 is formed on the entire surface of the substrate 60 by chemical vapor deposition.
  • the material of the buffer layer 62 is preferably an oxide of silicon and has a thickness of about 300 nm.
  • the buffer layer 62 can provide a better interface for subsequent formation of the active layer.
  • the active layer 50 is deposited on the buffer layer 62.
  • the material of the active layer 50 is preferably IGZO, and the pattern of the active layer 50 is formed by photolithography.
  • the active layer 50 has a thickness of about 60 nm.
  • a gate insulating layer 63 is formed on the active layer 50.
  • the material of the gate insulating layer 63 is preferably an oxide of silicon (SiOx) having a thickness of about 150 nm.
  • a gate electrode 40 is formed on the gate insulating layer 63. Then, the active layer 50 is electrically conductive by an automatic adjustment method, that is, the active layer 50 is laser-conducted by using the gate electrode 40 which has been formed as a mask.
  • interlayer dielectric layer (ILD) 64 on the entire surface, and forming a first via hole 3112 and a second via hole 4112 on the interlayer dielectric layer 64, and the active layer 50 is in the first via hole 3112 and the first layer The second via 4112 is exposed.
  • the material of the interlayer dielectric layer 64 is preferably SiOx and has a thickness of about 400 nm.
  • a drain electrode 310 and a source electrode 410 are formed on the interlayer dielectric layer.
  • the drain electrode 310 is connected to the active layer 50 through the first via hole 3112
  • the source electrode 410 is connected to the active layer 50 through the second via hole 4112.
  • the drain electrode 320 has a comb-shaped shape, and the drain electrode 310 includes a plurality of first tooth portions 311 disposed in parallel with each other and a first stem portion 312 that communicates with the first tooth portion 311 at one end of the first tooth portion 311;
  • the source electrode 410 is in the shape of a comb, the source electrode 410 includes a plurality of second teeth 411 disposed in parallel with each other, and a second stem portion 412 that communicates with the second teeth 411 at one end of the second tooth portion 411;
  • the first tooth portion 311 and the second tooth portion 411 are arranged in parallel with each other in parallel, the first dry portion 312 is disposed opposite to the second dry portion 412, and the drain electrode 310 is connected to the active layer 50 through the first via hole 3112, and the source electrode 410 passes through The second via 4112 is connected to the active layer 50.
  • a protective layer 65 is formed on the entire surface.
  • the material of the protective layer 65 is preferably SiOx and has a thickness of about 200 nm.
  • the active layer 50 includes a first strip 51, a second strip 52, and a third strip 53.
  • the drain electrode 310 includes a first tooth portion 311 and a first stem portion 312.
  • the source electrode 410 includes a second tooth portion 411 and a second rod portion 412.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • Fig. 7 is a schematic view showing the structure of a thin film transistor when viewed along the normal direction of the substrate in the present embodiment.
  • the comb-shaped drain electrode 320 includes a plurality of first tooth portions 321 disposed in parallel with each other, and also includes a first stem portion 322 that communicates with each other at the upper end of the first tooth portion 321.
  • the comb-shaped source electrode 420 includes a plurality of second tooth portions 421 disposed in parallel with each other, and further includes a second stem portion 422 that communicates with each other at the lower end of the second tooth portion 421.
  • the first tooth portion 321 and the second tooth portion 421 are sequentially parallel to each other, and the first stem portion 322 and the second stem portion 422 are oppositely disposed.
  • the first stem portion 322 is disposed perpendicular to the first tooth portion 321 and the second stem portion 422 is disposed perpendicular to the second tooth portion 421.
  • the first tooth portion 321 includes a first insertion portion 3211 that is inserted into the second tooth portion 421.
  • the second tooth portion 421 includes a second insertion portion 4211 that is inserted into the first tooth portion 321.
  • the active layer 500 includes a first strip 510 covering the first insertion portion 3211 and the second insertion portion 4211. That is, the first strip 510 overlaps with a portion of the first tooth portion 321 while overlapping a portion of the second tooth portion 421.
  • the orthographic projection of the first strip 510 is a rectangular structure as viewed in the normal direction of the substrate. As shown in FIG. 7, the side of the rectangular structure exceeds the lower end of the first tooth portion 321 and the second tooth portion. The location of the upper end of the 421.
  • the first insertion portion 3211 and the second insertion portion 4211 are the overlapping portions of the first tooth portion 321 and the second tooth portion 421 and the first strip 510, respectively.
  • the orthographic projection of the active layer 500 is located inside the orthographic projection of the gate electrode 41 as viewed in the normal direction of the substrate, so that the gate electrode 41 also overlaps the first insertion portion 3211 and the second insertion portion 4211. .
  • a first via 3212 that is connected to the active layer 500 is preferably disposed at the first insertion portion 3211.
  • a second via hole 4212 that is connected to the active layer 500 is provided at the second insertion portion 4211. Therefore, the drain electrode 320 is connected to the first strip 510 of the active layer 500 through the first via 3212, and the source electrode 420 is connected to the first strip 510 of the active layer 500 through the second via 4212.
  • the layout size of the thin film transistor is reduced, and the channel width between the drain electrode and the source electrode is increased, Conducive to high resolution and high frequency performance.
  • the thin film transistor is applied to a GOA circuit or other circuits, it is advantageous to realize the design of the narrow bezel display panel.
  • the active layer is indium gallium zinc oxide.
  • the electron mobility of indium gallium zinc oxide is several tens of times that of the amorphous silicon layer. Therefore, when indium gallium zinc oxide is used as the active layer, the electron mobility of the active layer can be greatly improved, so that the thin film transistor has more High resolution and high frequency drive performance. It is advantageous to apply the thin film transistor to a high performance, large size display device.
  • FIG. 8 is a schematic view showing the structure of a thin film transistor when viewed along the normal direction of the substrate in the present embodiment.
  • the active layer 500 in this embodiment includes not only the first strip 510 but also the second strip 520, wherein the second strip 520 is different from the fifth embodiment.
  • the two may be a unitary structure.
  • the first strip 510 and the second strip 520 may have overlapping portions, but this does not affect the performance of the thin film transistor.
  • the first strip 510 and the second strip 520 have a mutual overlap with the source or the drain.
  • the two are now defined as a combination, that is, the second strip 520 and the first A combination of strips 510.
  • the combination of the second strip 520 and the first strip 510 overlaps the source electrode 420.
  • the orthographic projection of the active layer 500 is located inside the orthographic projection of the gate electrode 41 as viewed in the normal direction of the substrate. Since the active layer 500 covers the second tooth portion 421 and the second stem portion 422 of the source electrode 420, the second tooth portion 421 and the A second via 4212 is disposed at each of the two stems 422.
  • the second via hole 4212 in this embodiment is disposed along the second tooth portion 421 and the second stem portion 422 of the source electrode 420.
  • the channel between the first tooth portion 321 and the source electrode 420 is "U" shaped, thereby further increasing the channel width between the drain electrode and the source electrode, which is advantageous for applying the thin film transistor to high performance. Large size display device.
  • the combination of the second strip 520 and the first strip 510 may overlap with the drain electrode 320.
  • the same technical effect can be achieved by providing the first via 3212 on both sides 322.
  • Fig. 9 is a schematic view showing the structure of a thin film transistor when viewed along the normal direction of the substrate in the present embodiment.
  • the active layer 500 further includes a third strip 530, which is the first strip 510, the second strip 520, and the third strip 530 in the present invention.
  • the three strips 530 overlap with the source and drain electrodes.
  • the third strip 530 overlaps with the drain electrode;
  • the third strip 530 overlaps with the source electrode, and of course, there are other combinations.
  • the three are now defined as a combination, that is, a combination of the third strip 530 and the first strip 510 and the second strip 520.
  • the combination of the third strip 530 and the first strip 510 and the second strip 520 overlaps the drain electrode and the source electrode.
  • the third strip 530 and the first strip 510 may be a unitary structure, or there may be overlapping portions, but this does not affect the function of the thin film transistor.
  • the first strip 510, the second strip 520, and the third strip 530 are of a unitary structure, such an active layer is based on increasing the width of the channel between the source electrode and the drain electrode.
  • the active layer has a simple structure and is convenient to manufacture.
  • the orthographic projection of the active layer 500 is located inside the orthographic projection of the gate electrode 41 as viewed in the normal direction of the substrate.
  • the first via 3212 is disposed at both the first tooth portion 321 and the first stem portion 322 of the drain electrode.
  • the first via 3212 in this embodiment is disposed along the second tooth portion 321 and the second stem portion 322 of the source electrode. This arrangement makes the channel between the drain electrode and the source electrode wavy, and the channel size is further increased, further improving the performance of the thin film transistor.
  • FIG. 10 is a schematic cross-sectional view of the thin film transistor of FIG. 9 at 200.
  • the production method is as follows:
  • a gate electrode 41 is formed on the substrate 70 by a photolithography technique, and the gate electrode 41 has a thickness of about 400 nm.
  • a gate insulating layer 73 is formed on the entire surface of the substrate 70 by a chemical vapor deposition method.
  • the material of the gate insulating layer 73 is preferably SiOx and has a thickness of about 450 nm.
  • the active layer 500 is formed on the gate insulating layer 73.
  • the material of the active layer 500 is preferably IGZO, and the pattern of the active layer 500 is formed by photolithography.
  • the active layer 500 has a thickness of about 100 nm.
  • ESL etch stop layer
  • the ESL layer 74 can protect the active layer 500 from the metal etching solution in the post process.
  • the first via 3212 and the second via 4212 capable of exposing the active layer 500 are disposed on the ESL layer 74.
  • the material of the ESL layer 74 is preferably SiOx and has a thickness of about 100 nm.
  • a drain electrode 320 and a source electrode 420 are formed on the etch barrier layer 74.
  • the drain electrode 320 is connected to the active layer 500 through the first via 3212
  • the source electrode 420 is connected to the active layer 500 through the second via 4212.
  • the drain electrode 320 has a comb-shaped shape, and the drain electrode 320 includes a plurality of first tooth portions 321 disposed in parallel with each other, and a first stem portion 322 that communicates with the first tooth portion 321 at one end of the first tooth portion 321;
  • the source electrode 420 is in the shape of a comb, the source electrode 420 includes a plurality of second teeth 421 disposed in parallel with each other, and a second stem portion 422 that communicates with the second teeth 421 at one end of the second tooth portion 421;
  • the first tooth portion 321 and the second tooth portion 421 are arranged in parallel with each other in parallel, the first dry portion 322 is disposed opposite to the second dry portion 422, the drain electrode 320 is connected to the active layer 500 through the first via 3212, and the source electrode 420 is passed through The two vias 4212 are connected to the active layer 500.
  • a protective layer 75 is formed on the entire surface.
  • the material of the protective layer 75 is preferably SiOx and has a thickness of about 200 nm.
  • the active layer 500 includes a first strip 510, a second strip 520, and a third strip 530.
  • the drain electrode 320 includes a first tooth portion 321 and a first stem portion 322.
  • the source electrode 420 includes a second tooth portion 421 and a second stem portion 422.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

涉及显示面板技术领域，尤其涉及一种薄膜晶体管及其制作方法。该薄膜晶体管，设置在基板上，其包括漏电极（310）、源电极（410）、栅电极（40）和有源层（50），漏电极（310）和源电极（410）均呈梳齿状，漏电极（310）和源电极（410）分别通过第一过孔（3112）和第二过孔（4112）与有源层（50）连接。这种设置，能够使得漏电极（310）和源电极（410）之间的沟道的宽度增大，同时减少了薄膜晶体管的布局尺寸，达到了节省空间的目的。当将其应用在GOA电路或其他电路时，有利于实现窄边框显示面板的设计。

Description

薄膜晶体管及其制作方法
相关申请的交叉引用
本申请要求享有于2017年05月19日提交的名称为“薄膜晶体管及其制作方法”的中国专利申请CN201710359347.9的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示面板技术领域，尤其涉及一种薄膜晶体管及其制作方法。
背景技术
薄膜晶体管液晶显示器(TFT-LCD，Thin Film Transistor Liquid Crystal Display)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，越来越多地被应用于高性能显示领域当中。随着显示器件尺寸逐渐变大，要求显示器件具有更高分辨率和高频驱动性能。因此，要求TFT具有高迁移率和高性能。为了提高半导体有源层的电子迁移率，通常采用电子迁移率是非晶硅层迁移率几十倍的半导体氧化物材料，如IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)作为TFT的半导体有源层。现有技术中，采用IGZO作为半导体有源层的阵列基板主要有两种，分别为顶栅极IGZO TFT结构和刻蚀阻挡层(ESL)IGZO TFT结构。
如图1a所示，为沿基板的法线方向观测，现有技术中顶栅极IGZO TFT结构的示意图，图1b为图1a中的顶栅极IGZO TFT结构的截面示意图。从图1a中可以看出，栅电极11与IGZO有源层12部分重叠，漏电极13和源电极14也与IGZO有源层12重叠且分别设置于栅电极11的上下两侧，漏电极13和源电极14分别通过甲过孔15、乙过孔16与IGZO有源层12连接。由于栅电极11与漏电极13、源电极14没有重叠，所以其产生的寄生电容就很小，因此，顶栅极IGZO TFT结构在显示面板应用领域有着较大的发展前景。
如图2a所示，为沿基板的法线方向观测，现有技术中ESL IGZO TFT结构的 示意图，图2b为图2a中的ESL IGZO TFT结构的截面示意图。结合图2a和图2b可以看出，IGZO有源层22设置在栅电极21的内部，漏电极23和源电极24分别与IGZO有源层22重叠并依次设置在IGZO有源层22的上部和下部，漏电极23和源电极24分别通过甲过孔25、乙过孔26与IGZO有源层22连接。此种TFT结构中的ESL27用作IGZO的保护层，用来防止IGZO有源层22受到后制程中金属刻蚀液的影响。该TFT结构的电性可以做到非常优秀，所以ESL IGZO TFT结构在显示面板应用领域同样有着较大的发展前景。
但是，无论是现有技术中的顶栅极IGZO TFT结构还是ESL IGZO TFT结构，当将其应用到GOA电路或其他方面时，均需要将TFT沟道的宽度做大，这样就会使得TFT占用较大的空间，不利于实现窄边框显示面板的设计。
发明内容
当将薄膜晶体管的沟道宽度做大并将其应用到GOA电路或其他方面时，为了避免由于薄膜晶体管尺寸过大而影响窄边框显示面板的设计，本发明提出了一种薄膜晶体管及其制作方法。
本发明提出的薄膜晶体管，设置在基板上，其包括漏电极、源电极、栅电极和有源层，其中，所述漏电极呈梳齿状，所述漏电极包括若干条相互平行设置的第一齿部以及在所述第一齿部的一端将所述第一齿部相互连通的第一干部；所述源电极呈梳齿状，所述源电极包括若干条相互平行设置的第二齿部以及在所述第二齿部的一端将所述第二齿部相互连通的第二干部；所述第一齿部与所述第二齿部相互平行依次交叉设置，所述第一干部与所述第二干部相对设置，所述漏电极通过第一过孔与所述有源层连接，所述源电极通过第二过孔与所述有源层连接。
这种薄膜晶体管，由于漏电极和源电极呈交叉设置的梳齿状，从而使得漏电极和源电极之间的沟道的宽度增大，同时减少了薄膜晶体管的布局尺寸，达到了节省空间的目的。当将其应用在GOA电路或其他电路时，有利于实现窄边框显示面板的设计。
作为对薄膜晶体管的进一步改进，所述有源层为铟镓锌氧化物。铟镓锌氧化物的电子迁移率是非晶硅层的几十倍，因此，当使用铟镓锌氧化物作为有源层时，能够大大提高有源层的电子迁移率，使得该薄膜晶体管具有更高分辨率和高频驱动性能。有利于将该薄膜晶体管应用于高性能、大尺寸显示器件。
作为对有源层的进一步改进，当沿所述基板的法线方向观测时，所述有源层包括第一条状，所述第一条状与所述第一齿部的一部分重叠，同时与所述第二齿部的一部分重叠。
这种设置的薄膜晶体管，可以在第一条状与第一齿部的重叠区域设置第一过孔，在第一条状与第二齿部的重叠区域设置第二过孔，从而使第一条状作为漏电极和源电极之间的沟道，这样的沟道宽度大大增加，有利于高分辨率和高频性能，并且有源层的设置并未增大薄膜晶体管的整体尺寸，有利于实现窄边框显示面板的设计。
为了在不改变薄膜晶体管整体尺寸的情况下，进一步增大漏电极和源电极之间的沟道宽度，所述有源层还包括与所述第一条状结合的第二条状，所述第二条状和所述第一条状的结合体与所述源电极或所述漏电极重叠。
当第一条状和第二条状的结合体与源电极重叠时，可以根据需要在源电极的第二齿部和第二干部处均设置第二过孔，从而进一步增大了源电极和漏电极之间沟道的宽度。当第一条状和第二条状的结合体与漏电极重叠时，可以根据需要在漏电极的第一齿部和第一干部处均设置第一过孔，从而进一步增大了源电极和漏电极之间沟道的宽度。
作为对有源层的进一步改进，所述有源层进一步包括与所述第一条状结合的第三条状，所述第三条状与所述第一条状、所述第二条状的结合体与所述漏电极和所述源电极重叠。这样就可以根据需要在漏电极的第一齿部和第一干部处均设置第一过孔，在源电极的第二齿部和第二干部处均设置第二过孔，从而进一步增大了源电极和漏电极之间沟道的宽度。
作为对有源层的进一步改进，当所述第二条状和所述第一条状的结合体与所述源电极重叠时，所述第三条状与所述漏电极重叠；当所述第二条状和所述第一条状的结合体与所述漏电极重叠时，所述第三条状与所述源电极重叠。
作为对该薄膜晶体管的栅电极的进一步改进，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。这样就能进一步减少薄膜晶体管的布局空间，促进了窄边框显示面板的设计。
作为对栅电极的另一种改进，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
本发明同时提出了包含上述特征的薄膜晶体管的制作方法，包括如下步骤：
S11：在基板上制作金属遮光层；
S12：在基板全表面形成缓冲层；
S13：在缓冲层上制作有源层；
S14：在有源层上制作栅极绝缘层；
S15：在栅极绝缘层上制作栅电极；
S16：在基板全表面形成层间介电层，同时在层间介电层上设置有穿过所述层间介电层并将所述有源层暴露出来的第一过孔和第二过孔；
S17：在层间介电层上制作漏电极和源电极，其中，
所述漏电极呈梳齿状，所述漏电极包括若干条相互平行设置的第一齿部以及在所述第一齿部的一端将所述第一齿部相互连通的第一干部；
所述源电极呈梳齿状，所述源电极包括若干条相互平行设置的第二齿部以及在所述第二齿部的一端将所述第二齿部相互连通的第二干部；
所述第一齿部与所述第二齿部相互平行依次交叉设置，所述第一干部与所述第二干部相对设置，所述漏电极通过所述第一过孔与所述有源层连接，所述源电极通过所述第二过孔与所述有源层连接；
S18：在基板全表面制作保护层。
在上述步骤S15中，沿所述基板的法线方向观测，栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
在上述步骤S15中，在制作完成栅电极后，采用自动调整的方法对有源层进行导体化。
本发明同时提出了另一种包含上述特征的薄膜晶体管的制作方法，包括如下步骤：
S21：在基板上制作栅电极；
S22：在基板全表面形成栅绝缘层；
S23：在栅绝缘层上制作有源层；
S24：在基板全表面形成刻蚀阻挡层，同时在刻蚀阻挡层上设置有穿过所述刻蚀阻挡层并将所述有源层暴露出来的第一过孔和第二过孔；
S25：在刻蚀阻挡层上制作漏电极和源电极，其中，
所述漏电极呈梳齿状，所述漏电极包括若干条相互平行设置的第一齿部以及在所述第一齿部的一端将所述第一齿部相互连通的第一干部，
所述源电极呈梳齿状，所述源电极包括若干条相互平行设置的第二齿部以及在所述第二齿部的一端将所述第二齿部相互连通的第二干部，
所述第一齿部与所述第二齿部相互平行依次交叉设置，所述第一干部与所述第二干部相对设置，所述漏电极通过所述第一过孔与所述有源层连接，所述源电极通过所述第二过孔与所述有源层连接；
S26：在基板全表面制作保护层。
在上述步骤S23中，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
综上所述，本发明提出的薄膜晶体管，由于漏电极和源电极呈交叉设置的梳齿状，从而使得漏电极和源电极之间的沟道的宽度增大，同时减少了薄膜晶体管的布局尺寸，达到了节省空间的目的。当将其应用在GOA电路或其他电路时，有利于实现窄边框显示面板的设计。尤其当有源层为铟镓锌氧化物，使得漏电极和源电极之间的沟道的电子迁移率是非晶硅的几十倍，从而使得该薄膜晶体管具有更高分辨率和高频驱动性能。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1a为沿基板的法线方向观测，现有技术中顶栅极IGZO TFT结构的示意
图；图1b为图1a中的顶栅极IGZO TFT结构的截面示意图；
图2a为沿基板的法线方向观测，现有技术中ESL IGZO TFT结构的示意图；
图2b为图2a中的ESL IGZO TFT结构的截面示意图；
图3为实施例一中，沿基板法线方向观测时，薄膜晶体管的结构示意图；
图4为实施例二中，沿基板法线方向观测时，薄膜晶体管的结构示意图；
图5为实施例三中，沿基板法线方向观测时，薄膜晶体管的结构示意图；
图6为图5中薄膜晶体管在100处的截面结构示意图；
图7为实施例五中，沿基板法线方向观测时，薄膜晶体管的结构示意图；
图8为实施例六中，沿基板法线方向观测时，薄膜晶体管的结构示意图；
图9为实施例七中，沿基板法线方向观测时，薄膜晶体管的结构示意图；
图10为图9中薄膜晶体管在200处的截面结构示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
以下将结合附图对本发明的内容作出详细的说明，下文中的“上”“下”“左”“右”均为相对于图示方向，不应理解为对本发明的限制。
实施例一：
图3为本实施例中，沿基板法线方向观测时，薄膜晶体管的结构示意图。从图3中可以看出，呈梳齿状的漏电极310包括若干条相互平行设置的第一齿部311，同时还包括在第一齿部311的上端将其相互连通的第一干部312。呈梳齿状的源电极410包括若干条相互平行设置的第二齿部411，同时还包括在第二齿部411的下端将其相互连通的第二干部412。第一齿部311与第二齿部411相互平行依次交叉，且第一干部312和第二干部412相对设置。优选地，第一干部312垂直于第一齿部311设置，第二干部412垂直于第二齿部411设置。
在图3中，第一齿部311包括插入第二齿部411的第一插入部3111，同理，第二齿部411包括插入第一齿部311的第二插入部4111。有源层50包括覆盖第一插入部3111和第二插入部4111的第一条状51。即第一条状51与第一齿部311的一部分重叠，同时与第二齿部411的一部分重叠。如图3所示，第一齿部311的下端以及第二齿部411的上端与第一条状51重叠；即沿基板的法线方向观测，第一条状51的正投影为矩形结构，其中矩形结构的上边和下边恰好分别与第二齿部411的上端以及第一齿部311的下端平齐。在图3所示的结构中，其中的第一插入部3111和第二插入部4111分别为第一齿部311和第二齿部411和第一条状51的重叠部分。
优选地，薄膜晶体管的栅电极40呈波形状，并设置在漏电极310与源电极410之间的间隙内。在实施例中，由于第一条状51呈条状设置，因此第一条状5与设置在漏电极310与源电极410之间的间隙内的栅电极40也有重叠，如图3所示，所述第一条状51与所述栅电极40的中部有重叠。
在本实施例中，为了使漏电极310、源电极410分别与有源层50连接，优选地，在第一插入部3111处设置有使其与有源层50相连接的第一过孔3112，在第二插入部4111处设置有使其与有源层50相连接的第二过孔4112。因此，漏电极310通过第一过孔3112与有源层50的第一条状51连接，源电极410通过第二过孔4112与有源层50的第一条状51连接。
本实施例中的薄膜晶体管，由于第一齿部311和第二齿部411相互交叉，从而减小了薄膜晶体管的布局尺寸，同时增大了漏电极和源电极之间的沟道宽度，有利于高分辨率和高频性能。当将该薄膜晶体管应用于GOA电路或其他电路时，有利于实现窄边框显示面板的设计。
优选地，有源层为铟镓锌氧化物。铟镓锌氧化物的电子迁移率是非晶硅层的几十倍，因此，当使用铟镓锌氧化物作为有源层时，能够大大提高有源层的电子迁移率，使得该薄膜晶体管具有更高分辨率和高频驱动性能。有利于将该薄膜晶体管应用于高性能、大尺寸显示器件。
实施例二：
图4为本实施例中，沿基板法线方向观测时，薄膜晶体管的结构示意图。从图4中可以看出，本实施例与实施例一不同的是，本实施例中的有源层50不仅包括第一条状51，还包括第二条状52，第二条状52和第一条状51相结合，两者可以为一体结构，当第二条状52和第一条状51为一体结构时，这样的有源层结构简单，制作方便。当然第一条状51和第二条状52有重叠的部分，但这并不影响该薄膜晶体管的性能。本发明中第一条状51和第二条状52两者共同与源极或漏极有重叠的情况，为了方便描述，现将两者定义为一个结合体，即第二条状52和第一条状51的结合体。如图4所示，第二条状52和第一条状51的结合体与源电极410重叠。
如图4所示，由于有源层50覆盖了源电极的第二齿部411和第二干部412，所以能够在第二齿部411和第二干部412处均设置第二过孔4112，此时第一齿部311与源电极之间的沟道呈“U”型，从而进一步增大了漏电极与源电极之间的沟道宽度，有利于将该薄膜晶体管应用于高性能、大尺寸显示器件。
当然，在本实施例中，也可以设置为第二条状52和第一条状51的结合体与漏电极310重叠，此时，只要在漏电极310的第一齿部311和第一干部312上均设置第一过孔就可以达到相同的技术效果。
实施例三：
图5为本实施例中，沿基板法线方向观测时，薄膜晶体管的结构示意图。从图5中可以看出，本实施例相比于实施例二，有源层50进一步包括第三条状53，第三条状53与第一条状51结合，一种情况下，当第二条状52和第一条状51的结合体与源电极重叠时，第三条状53与漏电极重叠；当第二条状52和第一条状 51的结合体与漏电极重叠时，第三条状53与所述源电极重叠，当然也不排除还有其他的组合情况。本发明中第一条状51、第二条状52和第三条状53三者共同与源极和漏极有重叠的情况，为了方便描述，现将三者定义为一个结合体，即第三条状53与第一条状51、第二条状52的结合体。第三条状53与第一条状51、第二条状52的结合体与漏电极310和源电极410重叠。这里的第三条状53与第一条状51也可以存在相互重叠的部分，但这并不影响该薄膜晶体管的功能。当然第三条装53可以与第一条状51为一体结构，即第一条状51、第二条状52和第三条状53可以为一个整个的面，与整个的漏电极310和源电极410，当第一条状部51、第二条状部52和第三条状部53为一体结构时，这样的有源层在增大了源电极和漏电极之间沟道的宽度的基础上，同时该有源层结构简单，制作方便。
在本实施例中，在漏电极310的第一齿部311和第一干部312处均设置有第一过孔3112。这种设置，使得漏电极和源电极之间的沟道呈波状，沟道尺寸进一步增大，进一步提高了该薄膜晶体管的性能。
实施例四：
在本实施例中，将详细介绍实施例一至实施例三中的薄膜晶体管的制作方法。如图6所示，为图5中薄膜晶体管在100处的截面结构示意图。该制作方法如下：
S11：在基板60的全表面上沉积一层金属膜，所用的金属有钼(Mo)、钽(Ta)、钼钽(MoTa)、铝(Al)等。然后利用照相蚀刻技术形成金属遮光层61。这里的金属遮光层61的厚度优选地约100nm。
S12：采用化学气相沉积法在基板60的全表面形成缓冲层62，缓冲层62的材料优选为硅的氧化物，厚度约300nm。缓冲层62能够为后续形成有源层时提供较好的界面。
S13：在缓冲层62上沉积制作有源层50，有源层50的材料优选为IGZO，利用照相蚀刻技术制作有源层50的图案。在这里，有源层50的厚度约为60nm。
S14：在有源层50上制作栅极绝缘层63。在这里，栅极绝缘层63的材料优选为硅的氧化物(SiOx)，厚度约150nm。
S15：在栅极绝缘层63上制作栅电极40。然后采用自动调整的方法对有源层50进行导体化，即采用已经制成的栅电极40作为掩膜板，对有源层50进行激光导体化。
S16：在全表面形成层间介电层(ILD)64，同时在层间介电层64上形成第一过孔3112和第二过孔4112，有源层50在第一过孔3112和第二过孔4112处暴露出来。在这里，层间介电层64的材料优选为SiOx，厚度约400nm。
S17：在层间介电层上制作漏电极310和源电极410，漏电极310通过第一过孔3112与有源层50连接，源电极410通过第二过孔4112与有源层50连接。
其中，
漏电极320呈梳齿状，漏电极310包括若干条相互平行设置的第一齿部311以及在第一齿部311的一端将第一齿部311相互连通的第一干部312；
源电极410呈梳齿状，源电极410包括若干条相互平行设置的第二齿部411以及在第二齿部411的一端将第二齿部411相互连通的第二干部412；
第一齿部311与第二齿部411相互平行依次交叉设置，第一干部312与第二干412部相对设置，漏电极310通过第一过孔3112与有源层50连接，源电极410通过第二过孔4112与有源层50连接。
S18：在全表面制作保护层65。保护层65的材料优选为SiOx，厚度约200nm。
其中，有源层50包括第一条状51、第二条状52和第三条状53。漏电极310包括第一齿部311和第一干部312。源电极410包括第二齿部411和第二杆部412。
实施例五：
图7为本实施例中，沿基板法线方向观测时，薄膜晶体管的结构示意图。从图7中可以看出，呈梳齿状的漏电极320包括若干条相互平行设置的第一齿部321，同时还包括在第一齿部321的上端将其相互连通的第一干部322。呈梳齿状的源电极420包括若干条相互平行设置的第二齿部421，同时还包括在第二齿部421的下端将其相互连通的第二干部422。第一齿部321与第二齿部421相互平行依次交叉，且第一干部322和第二干部422相对设置。优选地，第一干部322垂直于第一齿部321设置，第二干部422垂直于第二齿部421设置。
在图7中，第一齿部321包括插入第二齿部421的第一插入部3211，同理，第二齿部421包括插入第一齿部321的第二插入部4211。有源层500包括覆盖第一插入部3211和第二插入部4211的第一条状510。即第一条状510与第一齿部321的一部分重叠，同时与第二齿部421的一部分重叠。在本实施例中，沿基板的法线方向观测，第一条状510的正投影为矩形结构，如图7所示，矩形结构的边超出了第一齿部321的下端和第二齿部421的上端所在的位置。在图7所示的 结构中，其中的第一插入部3211和第二插入部4211分别为第一齿部321和第二齿部421和第一条状510的重叠部分。
在本实施例中，沿基板的法线方向观测，有源层500的正投影位于栅电极41的正投影的内部，所以，栅电极41也与第一插入部3211和第二插入部4211重叠。
在本实施例中，为了使漏电极320、源电极420分别与有源层500连接，优选地，在第一插入部3211处设置有使其与有源层500相连接的第一过孔3212，在第二插入部4211处设置有使其与有源层500相连接的第二过孔4212。因此，漏电极320通过第一过孔3212与有源层500的第一条状510连接，源电极420通过第二过孔4212与有源层500的第一条状510连接。
本实施例中的薄膜晶体管，由于第一齿部321和第二齿部421相互交叉，从而减小了薄膜晶体管的布局尺寸，同时增大了漏电极和源电极之间的沟道宽度，有利于高分辨率和高频性能。当将该薄膜晶体管应用于GOA电路或其他电路时，有利于实现窄边框显示面板的设计。
优选地，有源层为铟镓锌氧化物。铟镓锌氧化物的电子迁移率是非晶硅层的几十倍，因此，当使用铟镓锌氧化物作为有源层时，能够大大提高有源层的电子迁移率，使得该薄膜晶体管具有更高分辨率和高频驱动性能。有利于将该薄膜晶体管应用于高性能、大尺寸显示器件。
实施例六：
图8为本实施例中，沿基板法线方向观测时，薄膜晶体管的结构示意图。从图8中可以看出，本实施例与实施例五不同的是，本实施例中的有源层500不仅包括第一条状510，还包括第二条状520，其中第二条状520与第一条状510结合，两者可以为一体结构，当第二条状520与第一条状510为一体结构时，这样的有源层结构简单，制作方便。当然第一条状510和第二条状520可以有重叠的部分，但这并不影响该薄膜晶体管的性能。本发明中第一条状510和第二条状520两者共同与源极或漏极有重叠的情况，为了方便描述，现将两者定义为一个结合体，即第二条状520和第一条状510的结合体。如图8所示，第二条状520和第一条状510的结合体与源电极420重叠。同理，本实施例中，沿基板的法线方向观测，有源层500的正投影位于栅电极41的正投影的内部。由于有源层500覆盖了源电极420的第二齿部421和第二干部422，所以能够在第二齿部421和第 二干部422处均设置第二过孔4212。如图8所示，本实施例中的第二过孔4212沿源电极420的第二齿部421和第二干部422通长设置。这样就使得第一齿部321与源电极420之间的沟道呈“U”型，从而进一步增大了漏电极与源电极之间的沟道宽度，有利于将该薄膜晶体管应用于高性能、大尺寸显示器件。
当然，在本实施例中，也可以设置为第二条状520与第一条状510的结合体与漏电极320重叠，此时，只要在漏电极320的第一齿部321和第一干部322上均设置第一过孔3212就可以达到相同的技术效果。
实施例七：
图9为本实施例中，沿基板法线方向观测时，薄膜晶体管的结构示意图。从图9中可以看出，本实施例相比于实施例六，有源层500进一步包括第三条状530，本发明中第一条状510、第二条状520和第三条状530三者共同与源极和漏极有重叠的情况，一种情况下，当第二条状520和第一条状510的结合体与源电极重叠时，第三条状530与漏电极重叠；当第二条状520和第一条状510的结合体与漏电极重叠时，第三条状530与所述源电极重叠，当然也不排除还有其他的组合情况。为了方便描述，现将三者定义为一个结合体，即第三条状530与第一条状510、第二条状520的结合体。第三条状530与第一条状510、第二条状520的结合体与漏电极和源电极重叠。当然这里的第三条状530与第一条状510可以为一体结构，也可以存在相互重叠的部分，但这并不影响该薄膜晶体管的功能。当第一条状部510、第二条状部520和第三条状部530为一体结构时，这样的有源层在增大了源电极和漏电极之间沟道的宽度的基础上，同时该有源层结构简单，制作方便。同理，本实施例中，沿基板的法线方向观测，有源层500的正投影位于栅电极41的正投影的内部。
在本实施例中，在漏电极的第一齿部321和第一干部322处均设置有第一过孔3212。本实施例中的第一过孔3212沿源电极的第二齿部321和第二干部322通长设置。这种设置，使得漏电极和源电极之间的沟道呈波状，沟道尺寸进一步增大，进一步提高了该薄膜晶体管的性能。
实施例八：
在本实施例中，将详细介绍实施例五至实施例七中的薄膜晶体管的制作方法。如图10所示，为图9中薄膜晶体管在200处的截面结构示意图。该制作方法如下：
S21：采用照相蚀刻技术，在基板70上制作栅电极41，栅电极41厚度约400nm。
S22：采用化学气相沉积的方法，在基板70全表面形成栅绝缘层73。栅绝缘层73的材料优选为SiOx，厚度约450nm。
S23：在栅绝缘层73上制作有源层500，有源层500的材料优选为IGZO，利用照相蚀刻技术制作有源层500的图案。在这里，有源层500的厚度约为100nm。
S24：在全表面形成刻蚀阻挡层(ESL)74，ESL层74能够保护有源层500免受在后制程中金属刻蚀液的影响。同时ESL层74上设置能将有源层500暴露出来的第一过孔3212和第二过孔4212。在这里，ESL层74的材料优选为SiOx，厚度约100nm。
S25：在刻蚀阻挡层74上制作漏电极320和源电极420，漏电极320通过第一过孔3212与有源层500连接，源电极420通过第二过孔4212与有源层500连接。
其中，漏电极320呈梳齿状，漏电极320包括若干条相互平行设置的第一齿部321以及在第一齿部321的一端将所述第一齿部321相互连通的第一干部322；
源电极420呈梳齿状，源电极420包括若干条相互平行设置的第二齿部421以及在第二齿部421的一端将第二齿部421相互连通的第二干部422；
第一齿部321与第二齿部421相互平行依次交叉设置，第一干部322与第二干部422相对设置，漏电极320通过第一过孔3212与有源层500连接，源电极420通过第二过孔4212与有源层500连接。
S26：在全表面制作保护层75。保护层75的材料优选为SiOx，厚度约200nm。
其中，有源层500包括第一条状510、第二条状520和第三条状530。漏电极320包括第一齿部321和第一干部322。源电极420包括第二齿部421和第二干部422。
最后说明的是，以上实施例仅用于说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换。尤其是，只要不存在结构上的冲突，各实施例中的特征均可相互结合起来，所形成的组合式特征仍属于本发明的范围内。只要不脱离本发明技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (18)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管设置在基板上，其包括漏电极、源电极、栅电极和有源层，其中，
    所述漏电极呈梳齿状，所述漏电极包括若干条相互平行设置的第一齿部以及在所述第一齿部的一端将所述第一齿部相互连通的第一干部；
    所述源电极呈梳齿状，所述源电极包括若干条相互平行设置的第二齿部以及在所述第二齿部的一端将所述第二齿部相互连通的第二干部；
    所述第一齿部与所述第二齿部相互平行依次交叉设置，所述第一干部与所述第二干部相对设置，所述漏电极通过第一过孔与所述有源层连接，所述源电极通过第二过孔与所述有源层连接。
  2. 根据权利要求1所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
  3. 根据权利要求1所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
  4. 根据权利要求1所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述有源层包括第一条状，所述第一条状与所述第一齿部的一部分重叠，同时与所述第二齿部的一部分重叠。
  5. 根据权利要求4所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
  6. 根据权利要求4所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
  7. 根据权利要求4所述的薄膜晶体管，其中，所述有源层还包括与所述第一条状结合的第二条状，所述第二条状和所述第一条状的结合体与所述源电极或所述漏电极重叠。
  8. 根据权利要求7所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
  9. 根据权利要求7所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
  10. 根据权利要求7所述的薄膜晶体管，其中，所述有源层进一步包括与所 述第一条状结合的第三条状，所述第三条状与所述第一条状、所述第二条状的结合体与所述漏电极和所述源电极重叠。
  11. 根据权利要求10所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
  12. 根据权利要求10所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
  13. 根据权利要求10所述的薄膜晶体管，其中，当所述第二条状和所述第一条状的结合体与所述源电极重叠时，所述第三条状与所述漏电极重叠；当所述第二条状和所述第一条状的结合体与所述漏电极重叠时，所述第三条状与所述源电极重叠。
  14. 根据权利要求13所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
  15. 根据权利要求13所述的薄膜晶体管，其中，沿所述基板的法线方向观测，所述有源层的正投影位于所述栅电极的正投影的内部。
  16. 一种薄膜晶体管的制作方法，其中，所述方法包括如下步骤：
    S11：在基板上制作金属遮光层；
    S12：在基板全表面形成缓冲层；
    S13：在缓冲层上制作有源层；
    S14：在有源层上制作栅极绝缘层；
    S15：在栅极绝缘层上制作栅电极；
    S16：在基板全表面形成层间介电层，同时在层间介电层上设置有穿过所述层间介电层并将所述有源层暴露出来的第一过孔和第二过孔；
    S17：在层间介电层上制作漏电极和源电极，其中，
    所述漏电极呈梳齿状，所述漏电极包括若干条相互平行设置的第一齿部以及在所述第一齿部的一端将所述第一齿部相互连通的第一干部；
    所述源电极呈梳齿状，所述源电极包括若干条相互平行设置的第二齿部以及在所述第二齿部的一端将所述第二齿部相互连通的第二干部；
    所述第一齿部与所述第二齿部相互平行依次交叉设置，所述第一干部与所述第二干部相对设置，所述漏电极通过第一过孔与所述有源层连接，所述源电极通过第二过孔与所述有源层连接。
    S18：在基板全表面制作保护层。
  17. 根据权利要求16所述的薄膜晶体管的制作方法，其中，沿所述基板的法线方向观测，所述栅电极呈波形状，并设置在所述漏电极与所述源电极之间的间隙内。
  18. 一种薄膜晶体管的制作方法，其中，所述方法包括如下步骤：
    S21：在基板上制作栅电极；
    S22：在基板全表面形成栅绝缘层；
    S23：在栅绝缘层上制作有源层；
    S24：在基板全表面形成刻蚀阻挡层，同时在刻蚀阻挡层上设置有穿过所述刻蚀阻挡层并将所述有源层暴露出来的第一过孔和第二过孔；
    S25：在刻蚀阻挡层上制作漏电极和源电极，其中，
    所述漏电极呈梳齿状，所述漏电极包括若干条相互平行设置的第一齿部以及在所述第一齿部的一端将所述第一齿部相互连通的第一干部，
    所述源电极呈梳齿状，所述源电极包括若干条相互平行设置的第二齿部以及在所述第二齿部的一端将所述第二齿部相互连通的第二干部，
    所述第一齿部与所述第二齿部相互平行依次交叉设置，所述第一干部与所述第二干部相对设置，所述漏电极通过第一过孔与所述有源层连接，所述源电极通过第二过孔与所述有源层连接；
    S26：在基板全表面制作保护层。
PCT/CN2017/087368 2017-05-19 2017-06-07 薄膜晶体管及其制作方法 WO2018209736A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/551,637 US10403755B2 (en) 2017-05-19 2017-06-07 Thin film transistor and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710359347.9A CN107204375B (zh) 2017-05-19 2017-05-19 薄膜晶体管及其制作方法
CN201710359347.9 2017-05-19

Publications (1)

Publication Number Publication Date
WO2018209736A1 true WO2018209736A1 (zh) 2018-11-22

Family

ID=59905298

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/087368 WO2018209736A1 (zh) 2017-05-19 2017-06-07 薄膜晶体管及其制作方法

Country Status (3)

Country Link
US (1) US10403755B2 (zh)
CN (1) CN107204375B (zh)
WO (1) WO2018209736A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107121865A (zh) * 2017-06-07 2017-09-01 深圳市华星光电技术有限公司 一种薄膜晶体管、tft基板以及显示面板
US10509279B2 (en) * 2017-06-07 2019-12-17 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd Thin film transistor, TFT substrate, and display panel having source eletrodes and gate electrodes comprising U-shape structures
CN207183274U (zh) 2017-10-13 2018-04-03 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN109309100B (zh) 2018-09-29 2020-12-29 京东方科技集团股份有限公司 薄膜晶体管、栅极驱动电路和显示面板
CN111179765B (zh) * 2018-11-12 2021-09-10 惠科股份有限公司 显示面板及显示装置
CN111312805B (zh) * 2019-11-01 2021-07-06 深圳市华星光电半导体显示技术有限公司 薄膜晶体管结构、goa电路及显示装置
CN210535674U (zh) * 2019-11-29 2020-05-15 合肥鑫晟光电科技有限公司 薄膜晶体管、栅极驱动电路、显示基板和显示装置
CN111312729B (zh) * 2020-02-28 2023-01-24 Tcl华星光电技术有限公司 共享薄膜晶体管及显示面板
CN111463267A (zh) * 2020-04-08 2020-07-28 深圳市华星光电半导体显示技术有限公司 一种显示面板及显示装置
EP3975246A1 (en) * 2020-09-25 2022-03-30 Infineon Technologies Austria AG Semiconductor die and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202142535U (zh) * 2011-07-22 2012-02-08 京东方科技集团股份有限公司 一种薄膜场效应晶体管和液晶显示器
CN102437196A (zh) * 2011-12-15 2012-05-02 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管及其制造方法
US20130252431A1 (en) * 2012-03-22 2013-09-26 Tong-Yu Chen Method of Forming Trench in Semiconductor Substrate
CN105140300A (zh) * 2015-10-20 2015-12-09 重庆京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN106128944A (zh) * 2016-07-13 2016-11-16 深圳市华星光电技术有限公司 金属氧化物薄膜晶体管阵列基板的制作方法

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB856430A (en) * 1956-12-13 1960-12-14 Mullard Ltd Improvements in and relating to semi-conductive devices
JPS466271Y1 (zh) * 1967-08-16 1971-03-05
US3700976A (en) * 1970-11-02 1972-10-24 Hughes Aircraft Co Insulated gate field effect transistor adapted for microwave applications
BE788874A (fr) * 1971-09-17 1973-01-02 Western Electric Co Module de circuit integre
US4462041A (en) * 1981-03-20 1984-07-24 Harris Corporation High speed and current gain insulated gate field effect transistors
FR2585167B1 (fr) * 1985-07-19 1993-05-07 Gen Electric Structures conductrices redondantes pour affichages a cristaux liquides commandes par des transistors a effet de champ en couche mince
US4665374A (en) * 1985-12-20 1987-05-12 Allied Corporation Monolithic programmable signal processor using PI-FET taps
DE69319760T2 (de) * 1992-02-21 1999-02-11 Toshiba Kawasaki Kk Flüssigkristallanzeigevorrichtung
US6348808B1 (en) * 1999-06-25 2002-02-19 Lsi Logic Corporation Mobile ionic contamination detection in manufacture of semiconductor devices
WO2001017029A1 (en) * 1999-08-31 2001-03-08 E Ink Corporation Transistor for an electronically driven display
EP1085320A1 (en) * 1999-09-13 2001-03-21 Interuniversitair Micro-Elektronica Centrum Vzw A device for detecting an analyte in a sample based on organic materials
JP2004538618A (ja) * 1999-10-11 2004-12-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 集積回路
BR0016661B1 (pt) * 1999-12-21 2013-11-26 Métodos para formação de um dispositivo eletrônico, dispositivo eletrônico e dispositivo de exibição
GB2371910A (en) * 2001-01-31 2002-08-07 Seiko Epson Corp Display devices
EP1378015A4 (en) * 2001-04-10 2005-08-03 Sarnoff Corp METHOD AND DEVICE FOR PROVIDING AN ACTIVE MATRIX PIXEL WITH HIGH EFFICIENCY USING ORGANIC THIN FILM TRANSISTORS
CN100367516C (zh) * 2001-10-11 2008-02-06 皇家飞利浦电子股份有限公司 薄膜晶体管器件及其制造方法
US7023503B2 (en) * 2002-02-20 2006-04-04 Planar Systems, Inc. Image sensor with photosensitive thin film transistors
GB2388709A (en) * 2002-05-17 2003-11-19 Seiko Epson Corp Circuit fabrication method
TWI256732B (en) * 2002-08-30 2006-06-11 Sharp Kk Thin film transistor, liquid crystal display apparatus, manufacturing method of thin film transistor, and manufacturing method of liquid crystal display apparatus
KR100918180B1 (ko) * 2003-03-04 2009-09-22 삼성전자주식회사 쉬프트 레지스터
TWI242671B (en) * 2003-03-29 2005-11-01 Lg Philips Lcd Co Ltd Liquid crystal display of horizontal electronic field applying type and fabricating method thereof
US7651957B2 (en) * 2003-05-20 2010-01-26 Polymer Vision Limited Structure for a semiconductor arrangement and a method of manufacturing a semiconductor arrangement
JP2005084416A (ja) * 2003-09-09 2005-03-31 Sharp Corp アクティブマトリクス基板およびそれを用いた表示装置
JP4415653B2 (ja) * 2003-11-19 2010-02-17 セイコーエプソン株式会社 薄膜トランジスタの製造方法
JP4100351B2 (ja) * 2004-02-09 2008-06-11 セイコーエプソン株式会社 薄膜トランジスタの製造方法
US7773139B2 (en) * 2004-04-16 2010-08-10 Apple Inc. Image sensor with photosensitive thin film transistors
KR101002347B1 (ko) * 2004-06-24 2010-12-21 엘지디스플레이 주식회사 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법
KR101186019B1 (ko) * 2004-12-29 2012-09-25 엘지디스플레이 주식회사 박막트랜지스터 기판 및 그 제조 방법
KR101246023B1 (ko) * 2005-01-06 2013-03-26 삼성디스플레이 주식회사 어레이 기판 및 이를 갖는 표시장치
JP4636921B2 (ja) * 2005-03-30 2011-02-23 セイコーエプソン株式会社 表示装置の製造方法、表示装置および電子機器
JP2006303449A (ja) * 2005-04-21 2006-11-02 Samsung Sdi Co Ltd アクティブマトリックス回路基板、この製造方法及びこれを備えたアクティブマトリックスディスプレイ装置
KR100808747B1 (ko) * 2005-05-23 2008-02-29 샤프 가부시키가이샤 액티브 매트릭스 기판, 표시 장치 및 화소 결함 수정 방법
DE102005060794B3 (de) * 2005-12-16 2007-06-14 Siemens Ag Flachbilddetektor
DE102005060795A1 (de) * 2005-12-16 2007-07-12 Siemens Ag Flachbilddetektor
JP2009528254A (ja) * 2006-03-03 2009-08-06 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ 空間的に配列したナノチューブ及びナノチューブアレイの作製方法
TWI358832B (en) * 2007-02-26 2012-02-21 Au Optronics Corp Semiconductor device and manufacturing method ther
FR2913818B1 (fr) * 2007-03-16 2009-04-17 Thales Sa Matrice active d'un ecran electroluminescent organique
US8017940B2 (en) * 2007-05-25 2011-09-13 Panasonic Corporation Organic transistor, method of forming organic transistor and organic EL display with organic transistor
JP5178492B2 (ja) * 2007-12-27 2013-04-10 株式会社半導体エネルギー研究所 表示装置および当該表示装置を具備する電子機器
WO2009104302A1 (ja) * 2008-02-19 2009-08-27 シャープ株式会社 Ｔｆｔ、シフトレジスタ、走査信号線駆動回路、スイッチ回路、および、表示装置
KR101274706B1 (ko) * 2008-05-16 2013-06-12 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
US8604579B2 (en) * 2008-12-05 2013-12-10 Sharp Kabushiki Kaisha Semiconductor device, and method for manufacturing same
US8575713B2 (en) * 2009-02-19 2013-11-05 Sharp Kabushiki Kaisha Semiconductor device and display device
EP2256814B1 (en) * 2009-05-29 2019-01-16 Semiconductor Energy Laboratory Co, Ltd. Oxide semiconductor device and method for manufacturing the same
US7867916B2 (en) * 2009-06-15 2011-01-11 Palo Alto Research Center Incorporated Horizontal coffee-stain method using control structure to pattern self-organized line structures
EP2299492A1 (en) * 2009-09-22 2011-03-23 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO Integrated circuit
US20120200546A1 (en) * 2009-10-16 2012-08-09 Sharp Kabushiki Kaisha Semiconductor device, display device provided with same, and method for manufacturing semiconductor device
JP5148778B2 (ja) * 2010-03-24 2013-02-20 シャープ株式会社 信号分配装置および表示装置
US20130039455A1 (en) * 2010-04-28 2013-02-14 Satoshi Horiuchi Shift register and display device
IT1402406B1 (it) * 2010-10-22 2013-09-04 St Microelectronics Srl Metodo di fabbricazione di un dispositivo sensore di una sostanza gassosa di interesse.
KR101877448B1 (ko) * 2011-06-30 2018-07-12 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판 및 이의 제조 방법
JP2013021165A (ja) * 2011-07-12 2013-01-31 Sony Corp 蒸着用マスク、蒸着用マスクの製造方法、電子素子および電子素子の製造方法
JP5971679B2 (ja) * 2011-11-21 2016-08-17 株式会社ジャパンディスプレイ 液晶表示装置
TWI493724B (zh) * 2012-03-01 2015-07-21 E Ink Holdings Inc 半導體元件
TWI459567B (zh) * 2012-06-08 2014-11-01 Au Optronics Corp 主動元件、驅動電路結構以及顯示面板
CN103383946B (zh) * 2013-07-12 2016-05-25 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
US9343288B2 (en) * 2013-07-31 2016-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN103456795A (zh) 2013-09-02 2013-12-18 合肥京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
GB2521139B (en) * 2013-12-10 2017-11-08 Flexenable Ltd Reducing undesirable capacitive coupling in transistor devices
KR102232258B1 (ko) * 2014-08-27 2021-03-29 삼성디스플레이 주식회사 표시 기판 및 그의 제조방법
TW201622158A (zh) * 2014-12-10 2016-06-16 中華映管股份有限公司 薄膜電晶體以及其製作方法
CN104465787B (zh) * 2014-12-31 2017-10-17 京东方科技集团股份有限公司 一种薄膜晶体管及电路结构
KR101798433B1 (ko) * 2014-12-31 2017-11-17 엘지디스플레이 주식회사 인셀 터치 액정 디스플레이 장치와 이의 제조방법
EP3070741B1 (en) * 2015-03-18 2020-07-29 Emberion Oy An apparatus comprising a sensor arrangemenet and associated fabrication method
US20160379995A1 (en) * 2015-06-29 2016-12-29 Shenzhen China Star Optoelectronics Technology Co., Ltd. Thin-film transistor array substrate and manufacturing method thereof
CN105161045B (zh) * 2015-10-21 2018-06-29 京东方科技集团股份有限公司 栅极集成驱动电路、其修复方法、显示面板及显示装置
CN108292683A (zh) * 2015-11-20 2018-07-17 株式会社半导体能源研究所 半导体装置、包括该半导体装置的显示装置以及包括该半导体装置的电子设备
CN108807672B (zh) * 2017-04-28 2020-03-17 清华大学 有机薄膜晶体管及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202142535U (zh) * 2011-07-22 2012-02-08 京东方科技集团股份有限公司 一种薄膜场效应晶体管和液晶显示器
CN102437196A (zh) * 2011-12-15 2012-05-02 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管及其制造方法
US20130252431A1 (en) * 2012-03-22 2013-09-26 Tong-Yu Chen Method of Forming Trench in Semiconductor Substrate
CN105140300A (zh) * 2015-10-20 2015-12-09 重庆京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN106128944A (zh) * 2016-07-13 2016-11-16 深圳市华星光电技术有限公司 金属氧化物薄膜晶体管阵列基板的制作方法

Also Published As

Publication number Publication date
CN107204375B (zh) 2019-11-26
CN107204375A (zh) 2017-09-26
US20190123209A1 (en) 2019-04-25
US10403755B2 (en) 2019-09-03

Similar Documents

Publication Publication Date Title
WO2018209736A1 (zh) 薄膜晶体管及其制作方法
JP5823686B2 (ja) 薄膜トランジスタ、その製造方法、およびそれを利用した表示基板
US10665616B2 (en) Thin film transistor substrate and method of manufacturing thin film transistor substrate
KR102248645B1 (ko) 금속 산화물 반도체를 포함하는 박막 트랜지스터 기판 및 그 제조 방법
WO2016165187A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2010032425A1 (ja) 半導体素子
US9508750B2 (en) Thin film transistor substrate and method for manufacturing the same
US7462503B2 (en) Liquid crystal display device and fabricating method thereof
US9190564B2 (en) Array substrate and method for fabricating the same
WO2016165185A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2014183422A1 (zh) 薄膜晶体管及其制备方法、阵列基板
KR20100091123A (ko) 표시 장치
US11397359B2 (en) Thin film transistor array substrate, manufacturing method thereof, and display panel
US20180277661A1 (en) Thin film transistor substrate, manufacturing method for thin film transistor substrate, and liquid crystal display
US10403654B2 (en) Mask for manufacturing TFT in 4M production process and TFT array manufacturing method of 4M production process
US20210366942A1 (en) Array substrate and manufacturing method thereof
WO2019210602A1 (zh) 阵列基板及其制造方法、显示面板
US9178024B2 (en) Thin film transistor display panel and manufacturing method thereof
JP6584157B2 (ja) 薄膜トランジスタ、薄膜トランジスタ基板、液晶表示装置及び薄膜トランジスタの製造方法
WO2013163880A1 (zh) 阵列基板及其制造方法和显示装置
TWI518430B (zh) 顯示面板及應用其之顯示裝置
WO2016179877A1 (zh) 共平面型氧化物半导体tft基板结构及其制作方法
WO2023197363A1 (zh) 阵列基板及其制作方法、显示面板
US10741690B2 (en) Thin film transistor, thin film transistor substrate, and liquid crystal display device
JP2020031107A (ja) 薄膜トランジスタ、薄膜トランジスタ基板及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17910251

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17910251

Country of ref document: EP

Kind code of ref document: A1