WO2016033977A1 - 一种斜场板功率器件及斜场板功率器件的制备方法 - Google Patents

一种斜场板功率器件及斜场板功率器件的制备方法 Download PDF

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WO2016033977A1
WO2016033977A1 PCT/CN2015/077305 CN2015077305W WO2016033977A1 WO 2016033977 A1 WO2016033977 A1 WO 2016033977A1 CN 2015077305 W CN2015077305 W CN 2015077305W WO 2016033977 A1 WO2016033977 A1 WO 2016033977A1
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field plate
layer
power device
gate
drain
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PCT/CN2015/077305
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English (en)
French (fr)
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李元
裴轶
刘飞航
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苏州捷芯威半导体有限公司
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Priority to JP2017529122A priority Critical patent/JP6434625B2/ja
Publication of WO2016033977A1 publication Critical patent/WO2016033977A1/zh
Priority to US15/442,644 priority patent/US10068974B2/en
Priority to US16/052,442 priority patent/US10439029B2/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a slant field plate power device and a slant field plate power device.
  • GaN third-generation semiconductor gallium nitride
  • Si first-generation semiconductor silicon
  • GaAs second-generation semiconductor gallium arsenide
  • gallium nitride can form a heterojunction with other III-N compound semiconductors and has a high concentration of two-dimensional electron gas (2DEG) channel. Therefore, the characteristics of high voltage and large current make High Electron Mobility Transistor (HEMT) is especially suitable for manufacturing high-power electronic devices, which has a good application prospect.
  • 2DEG two-dimensional electron gas
  • the HEMT device belongs to a planar channel field effect transistor.
  • the edge of the gate near the drain direction tends to concentrate most of the electric field lines, forming a high electric field peak.
  • the electric field at this point is rapidly increased, causing the gate leakage current to increase.
  • the high electric field in this local region easily causes the device to fail due to avalanche breakdown, thereby reducing the breakdown voltage of the device.
  • the high electric field will also cause degradation and denaturation of the dielectric layer or semiconductor material layer on the surface of the device, which will affect the reliability of the device and reduce the lifetime of the device.
  • FIG. 1 is a prior art A structural diagram of a midfield plate power device, as shown in FIG.
  • the field plate power device includes a substrate 101, a nucleation layer 102 sequentially stacked on the substrate 101, a buffer layer 103, a channel layer 104, and a barrier Layer 105, source 106 on barrier layer 105, drain 107, and gate 108 between source 106 and drain 107, on gate 108 and gate 108 and source 106 and drain 107
  • the connection can generate an additional potential in the gate-drain region, which can effectively suppress the electric field spike near the edge of the drain 107 of the gate 108, thereby improving device breakdown voltage and device reliability.
  • a field plate structure in which a plurality of layers (e.g., three layers) are gradually moved upward is often used to form a gradient distribution of electric potential.
  • the field plate structure of such a gradient distribution must be completed by a combination of multi-step lithography, dielectric deposition, metal deposition, etc., the fabrication process is complicated, and the manufacturing cost of the device is increased.
  • multi-stage field plates do not allow the device surface to be completely evenly distributed, making it difficult to achieve optimal device performance.
  • the embodiments of the present invention provide a method for preparing a slant field plate power device and a slant field plate power device, thereby suppressing a high electric field peak on the surface of the power device, eliminating a breakdown area, improving the withstand voltage of the device, and improving The high frequency characteristics of the device and reduce the complexity and manufacturing cost of the manufacturing process.
  • an embodiment of the present invention provides a slant field plate power device, the device including
  • a source a drain, and a gate between the source and the drain;
  • a dielectric layer on the plurality of semiconductor layers on the gate, between the gate and the source, and between the gate and the drain;
  • the multilayer semiconductor layer includes a nucleation layer on the substrate, a buffer layer on the nucleation layer, a channel layer on the buffer layer, and a barrier layer on the channel layer, wherein The channel layer and the barrier layer form a heterojunction structure, and a two-dimensional electron gas is formed at the hetero interface, and the source and the drain are respectively in contact with the two-dimensional electron gas.
  • the material of the slant field plate structure is a metal material.
  • the slant field plate structure is connected to the source or connected to the gate or connected to a fixed potential or in a floating state.
  • the shape of the slant field plate structure includes any one of a straight shape, a curved shape, a zigzag shape, or a step shape, or a combination of a plurality of shapes.
  • the multilayer semiconductor layer further includes an interposer layer between the channel layer and the barrier layer.
  • the material of the insertion layer is AlN.
  • the multilayer semiconductor layer further includes a back barrier layer between the buffer layer and the channel layer.
  • the material of the back barrier layer is AlGaN.
  • the device further includes a gate dielectric between the plurality of semiconductor layers and the gate.
  • the gate is located on a surface of the barrier layer or at least partially disposed in a recess of the barrier layer.
  • the multilayer semiconductor layer comprises a semiconductor material of a III-V compound.
  • the material of the gate dielectric includes any one of SiN, SiO2, SiON, Al2O3, HfO2, HfAlOx or a combination of any of them.
  • the gate is a T-shaped gate or a slanted grid.
  • an embodiment of the present invention provides a method for fabricating a slant field plate power device according to the first aspect, the method comprising:
  • a slant field plate structure is formed on the inner wall of the groove.
  • forming the multilayer semiconductor layer on the substrate comprises:
  • a barrier layer on the channel layer, wherein the channel layer and the barrier layer form a heterojunction structure, and a two-dimensional electron gas is formed at the hetero interface, the source and the drain respectively Contact with two-dimensional electron gas.
  • a method of forming a groove on the dielectric layer includes dry etching or wet etching.
  • the method of forming the slant field plate structure on the inner wall of the groove includes a metal electron beam evaporation process or a metal sputtering process or a metal chemical vapor deposition process.
  • the slant field plate power device and the slant field plate power device manufacturing method provided by the embodiments of the present invention by forming a groove having a slope on the side of the dielectric layer, depositing a slant field plate structure on the inner wall of the groove, When an applied voltage is applied to the drain of the power device, the slant field plate structure can adjust the electric field distribution on the surface of the device.
  • the slant field plate structure Since the slant field plate structure has an inclination, the electric field peak at the end of the field plate is suppressed, and the entire electric field is The distribution is more uniform, and the electric field peak at the gate close to the drain is also pulled down, so that the surface of the power device no longer generates a distinct high peak electric field, eliminating the easy breakdown region, improving the overall pressure resistance of the power device, and improving The high frequency characteristics of the power device and the complexity and manufacturing cost of the manufacturing process are reduced.
  • FIG. 1 is a structural diagram of a field plate power device in the prior art
  • FIG. 2 is a structural diagram of a slant field plate power device according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic view showing electric field distribution of a device on a surface of a device in a high voltage state in a slant field plate power device according to Embodiment 1 of the present invention
  • 4A-4F are cross-sectional views showing corresponding structures of respective steps of a method for fabricating a slant field plate power device according to Embodiment 1 of the present invention.
  • FIG. 5 is a structural diagram of a slant field plate power device according to a preferred embodiment of the present invention.
  • FIG. 10 is a structural diagram of a slant field plate power device according to Embodiment 2 of the present invention.
  • FIG. 11 is a structural diagram of a slant field plate power device according to Embodiment 3 of the present invention.
  • FIG. 12 is a structural diagram of a slant field plate power device according to Embodiment 4 of the present invention.
  • FIG. 13 is a structural diagram of a slant field plate power device according to Embodiment 5 of the present invention.
  • FIG. 14 is a structural diagram of a slant field plate power device according to Embodiment 6 of the present invention.
  • FIG. 15 is a structural diagram of a slant field plate power device according to Embodiment 7 of the present invention.
  • 16A-16D are cross-sectional views corresponding to the steps of preparing the slant field plate structure in the seventh embodiment of the present invention.
  • 17A-17D are cross-sectional views corresponding to the steps of preparing a slant field plate structure in a preferred embodiment of the seventh embodiment of the present invention.
  • the slant field plate power device includes a substrate 11 and a plurality of semiconductor layers 12 on the substrate 11. a source 13 on the multilayer semiconductor layer 12, a drain 14 and a gate 15 between the source 13 and the drain 14, a gate 15 and a gate 15 and a source 13, and a gate 15 Multilayer semiconductor with drain 14 a dielectric layer 16 on the layer 12, a recess on the dielectric layer 16 between the gate 15 and the drain 14, the side of the recess having an inclination, and a slant field plate on the inner wall of the recess Structure 17.
  • the material of the substrate 11 may be silicon, sapphire, silicon carbide, insulating substrate silicon, gallium nitride, aluminum nitride, zinc oxide or any other material capable of growing a group III nitride.
  • the material of the multilayered semiconductor layer 12 may be a semiconductor material of a III-V compound.
  • the multilayered semiconductor layer 12 may include:
  • nucleation layer 121 on the substrate 11, the nucleation layer 121 affecting the crystal quality, surface morphology, and electrical properties of the heterojunction material thereon to match the substrate material and the heterojunction structure
  • the role of the layer of semiconductor material The role of the layer of semiconductor material.
  • the buffer layer 122 on the nucleation layer 121 can protect the substrate 11 from being invaded by some metal ions, and can bond other semiconductor material layers that need to be grown thereon.
  • the material of the buffer layer 122 can be AlGaN.
  • a group III nitride material such as GaN or AlGaInN.
  • a channel layer 123 on the buffer layer 122, a barrier layer 124 on the channel layer 123, a material of the barrier layer 124 may be AlGaN, and the channel layer 123 and the barrier layer 124 form a heterojunction structure.
  • a 2DEG channel (shown in phantom in FIG. 2) is formed at the hetero interface, wherein the channel layer 123 provides a channel for 2DEG motion and the barrier layer 124 acts as a barrier.
  • the source 13 and the drain 14 on the barrier layer 124 are respectively in contact with the 2DEG, the gate 15 is located between the source 13 and the drain 14, and is located on the barrier layer 124, and the gate 15 may be a T-shaped gate.
  • a suitable bias voltage is applied across the gate 15, current flows between the source 13 and the drain 14 through the 2DEG conductive channel between the interface of the channel layer 123 and the barrier layer 124.
  • the dielectric layer 16 is capable of passivating the surface of the multilayer semiconductor layer in the slant field plate power device.
  • a groove on the dielectric layer 16 between the gate 15 and the drain 14, the side of the groove having an inclination, and an inclined field plate structure 17 is deposited on the inner wall of the groove, the slope
  • the shape of the field plate structure 17 is linear, and the bottom of the groove is further away from the multilayer semiconductor layer 12 during the extension to the drain 14, and when an applied voltage is applied to the drain 14, the oblique
  • the field plate structure 17 can adjust the surface electric field of the power device.
  • FIG. 3 is a slant field plate power device and a prior art field plate in the first embodiment of the present invention. Schematic diagram of the electric field distribution of the device surface under high voltage conditions.
  • the abscissa indicates the electric field distribution position
  • the ordinate indicates the electric field on the surface of the device
  • the solid line indicates the electric field distribution on the surface of the device in the high voltage state in the prior art field plate power device.
  • the schematic diagram and the dashed line show a schematic diagram of the electric field distribution of the device surface under the high voltage state of the slant field plate power device according to the first embodiment of the present invention. It can be seen from the figure that the surface of the field plate and the surface of the device barrier layer are Parallel, while reducing the electric field spike near the edge of the gate, a new small electric field spike is formed near the end of the field plate. This new peak of the electric field spike increases with the length of the field plate, which is easy to cause.
  • the breakdown of the device in the field-terminated terminal region is not solved, and the device is not fully solved.
  • the slant field plate power provided by the first embodiment of the present invention is The surface of the piece no longer produces a distinct high peak electric field, the easy breakdown area is eliminated, the overall pressure resistance of the device is improved, and the parasitic capacitance effect is gradually weakened as the slant field plate is away from the device surface, improving the field plate to the device.
  • FIG. 4A-4F, FIG. 4A to FIG. 4F are cross-sectional views showing corresponding structures of respective steps of a method for preparing a slant field plate power device according to Embodiment 1 of the present invention, and a method for preparing the slant field plate power device is used for preparing as shown in FIG.
  • the slant field plate power device shown in 2 the manufacturing method of the slant field plate power device comprises:
  • Step S11 a semiconductor layer 12 is formed on the substrate 11.
  • a nucleation layer 121, a buffer layer 122, a channel layer 123, and a barrier layer 124 may be sequentially formed on the substrate 11, wherein the channel layer 123 and the barrier layer 124 form a heterojunction Structure, 2DEG is formed at the hetero interface.
  • Step S12 a source electrode 13 and a drain electrode 14 and a gate electrode 15 between the source electrode 13 and the drain electrode 14 are formed on the multilayer semiconductor layer 12.
  • the source 13 and the drain 14 are respectively in contact with the 2DEG at the interface of the heterojunction, and the formation process of the source 13 and the drain 14 may include a high temperature annealing method or a heavy doping method or an ion implantation method or the like.
  • Step S13 a dielectric layer 16 is formed on the gate electrode 15, the gate 15 and the source 13 and the multilayer semiconductor layer 12 between the gate 15 and the drain 14.
  • a dielectric layer 16 is formed over the multilayer semiconductor layer 12, and the dielectric layer 16 acts as a passivation for protecting the surface of the slant field plate power device.
  • step S14 a groove is formed on the dielectric layer 16, and the side surface of the groove has an inclination.
  • a groove may be formed on the dielectric layer 16 by dry etching or wet etching.
  • a positive photoresist 18 is used on the dielectric layer 16 as a photolithography process, and a specially designed mask is used to lithography the slant field plate region, and the density of the shading lattice on the mask is adjusted to make the slant field plate.
  • a mask design in which the region gradually increases the exposure degree and then gradually reduces the exposure degree in the direction away from the gate electrode 15 and away from the gate electrode 15 and close to the drain electrode 14.
  • a groove having a certain inclination is formed on the photoresist.
  • the inclination of the groove is not limited, and the optimum inclination can be set according to the design requirements of the process or the power device.
  • the lithography region is etched by a dry etching process, and the etching selectivity ratio of the photoresist and the dielectric layer 16 is optimized, for example, The etching selectivity ratio of the photoresist and the dielectric layer 16 is 1:1, thereby ensuring that the shape of the recess formed in the dielectric layer 16 after etching is consistent with the shape of the recess on the photoresist, thereby forming on the dielectric layer 16.
  • an etch control layer may be inserted in the dielectric layer 16 to precisely control the etching depth to form a groove satisfying the design conditions.
  • step S15 a slant field plate structure 17 is formed on the inner wall of the groove.
  • the material of the slant field plate structure 17 is metal.
  • the slant field plate structure 17 may be formed on the inner wall of the groove by a metal evaporation process or a metal sputtering process or a metal chemical vapor deposition process.
  • the slanted field plate structure 17 completely covers the grooves on the dielectric layer 16.
  • the length and thickness of the metal slant field plate structure 17 and the distance of the slant field plate structure from the surface of the multilayer semiconductor layer can be adjusted according to the design requirements of the power device.
  • slant field plate structure forming process It should be noted that although the above describes how to form a slant field plate structure by using a specially designed mask lithography, dielectric etching, metal evaporation, etc., it should be understood that the slant field plate structure forming process It can also be formed by other processes known to those skilled in the art, which is not limited herein.
  • the slant field plate power device can be applied to the present invention and can also be applied to any device that needs to use a field plate, including a high voltage laterally diffused metal oxide semiconductor (LDMOS) power device, and a gallium nitride high.
  • LDMOS laterally diffused metal oxide semiconductor
  • the preparation method of the slant field plate power device provided by the embodiment of the invention has simple preparation process and does not need to increase the manufacturing cost of the power device, can uniformly distribute the electric field on the surface of the power device, eliminate the easy breakdown region, and improve the overall power device.
  • the withstand voltage and improved high frequency characteristics of the power device can uniformly distribute the electric field on the surface of the power device, eliminate the easy breakdown region, and improve the overall power device.
  • FIG. 5 is a structural diagram of a slant field plate power device according to a preferred embodiment of the present invention, which is as follows:
  • the multilayer semiconductor layer 12 further includes an interposer layer 125 between the channel layer 123 and the barrier layer 124, and the material of the interposer layer 125 may be AlN, as shown in FIG.
  • the AlN insertion layer 125 also isolates the 2DEG conductive channel from the barrier layer 124, The scattering effect of the barrier layer 124 on the electrons is reduced, thereby increasing the mobility of the electrons and improving the overall characteristics of the device.
  • the multilayer semiconductor layer 12 further includes a back barrier layer 126 between the buffer layer 122 and the channel layer 123, and the material of the back barrier layer 126 may be AlGaN, as shown in FIG.
  • the slant field plate power device further includes a layer between the plurality of semiconductor layers 12 and the gate 15
  • the gate dielectric 18 is as shown in FIG.
  • the gate dielectric 18 can serve as both a passivation layer of the power device and a gate insulating layer, which can effectively reduce the leakage current of the gate 15 and adjust the turn-on voltage.
  • the material of the gate dielectric 18 may include any one of SiN, SiO2, SiON, Al2O3, HfO2, HfAlOx, or a combination of any of them.
  • the gate electrode 15 can be at least partially disposed in the recess of the barrier layer 124.
  • the recess is formed by etching the barrier layer 124, and the metal is further deposited to form the gate electrode 15, which can reduce the gate metal.
  • the surface defects and surface states of the material reduce the leakage and increase the breakdown voltage.
  • the etching depth of the barrier layer 124 needs to be controlled. When the etching depth of the barrier layer is large, the two-dimensional electron gas under the recess may be reduced or disappeared, and the power device may be Implement enhanced device functionality.
  • the gate 15 can be a beveled gate.
  • a bevel groove is formed when the dielectric layer 16 of the gate trench region is etched, and a metal is formed to form a bevel gate, a bevel gate.
  • the technology can reduce the electric field strength of the gate 15 close to the drain 14, and can reduce the leakage current of the gate 15, thereby increasing the breakdown voltage of the device.
  • the inclined gate structure does not introduce excessive parasitic capacitance, and the device has high frequency. The characteristic has little effect, and the improvement of the device characteristics by the slant field plate structure 17 in the embodiment of the present invention is more obvious.
  • the slant field plate power device and the slant field plate power device are prepared according to the first embodiment of the present invention, so that the electric field distribution of the power device is more uniform, and the electric field peak near the drain is also pulled down, and the power device surface is no longer.
  • the formation of a distinct high peak electric field eliminates the breakdown area, improves the overall voltage resistance of the power device, improves the high frequency characteristics of the power device, and reduces the complexity and manufacturing cost of the manufacturing process.
  • FIG. 10 is a structural diagram of a slant field plate power device according to Embodiment 2 of the present invention.
  • the slant field plate power device includes a substrate 21, and a plurality of semiconductor layers 22 on the substrate 21. a source 23, a drain 24, a gate 25 between the source 23 and the drain 24, a gate 25, a gate 25 and a source 23, and a gate 25 on the multilayer semiconductor layer 22.
  • Multi-layer half with drain 24 a dielectric layer 26 on the conductor layer 22, a recess on the dielectric layer 26 between the gate 25 and the drain 24, the side of the recess having an inclination, an oblique field on the inner wall of the recess Plate structure 27.
  • the second embodiment of the present invention is based on the first embodiment, and is different from the first embodiment in that the shape of the slant field plate structure 27 in the second embodiment is linear on the side close to the gate 25, and is close to the drain.
  • One side of the slanting field plate structure 27 has an upward convex curve shape, and the distance from the lower end of the slant field plate structure 27 to the multilayered semiconductor layer 22 is gradually increased in the process of approaching the drain electrode 24.
  • an oblique field plate structure with an upper convex curve shape can be formed, and the electric field distribution is optimized by the inclination angle of the linear oblique field plate, and the curved oblique field plate is optimized.
  • the electric field distribution can be adjusted by the curve arc, and the method of optimizing the electric field distribution is added.
  • the slant field plate structure 27 of the shape can well adjust the electric field of the slant field plate near the end of the drain 24, and can better improve the device characteristics.
  • the slant field plate power device includes a substrate 31, and a plurality of semiconductor layers 32 on the substrate 31.
  • a source 33, a drain 34, and a gate 35 between the source 33 and the drain 34, a gate 35, a gate 35 and a source 33, and a gate 35 are disposed on the multilayer semiconductor layer 32.
  • the third embodiment is based on the above embodiment, and is different from the above embodiment in that the slant field plate structure 37 forms a slant field plate structure with a concave curve shape at an end close to the drain electrode 34, and a slant field of a concave curved shape.
  • the front section of the board is closer to the surface of the power device, which can enhance the modulation of the electric field on the surface of the power device.
  • the shape of the slant field plate structure in the slant field plate power device provided by the third embodiment of the present invention can be realized by designing the density of the light shielding lattice on the mask.
  • the slant field plate power device includes a substrate 41, a plurality of semiconductor layers 42 on the substrate 41, lie in The source 43 and the drain 44 on the multilayer semiconductor layer 42 and the gate 45 between the source 43 and the drain 44, the gate 45, the gate 45 and the source 43 and the gate 45 and a dielectric layer 46 on the multilayer semiconductor layer 42 between the drains 44, a recess on the dielectric layer 46 between the gate 45 and the drain 44, the side of the recess having an inclination, located at The slanted field plate structure 47 on the inner wall of the groove.
  • Embodiment 4 of the present invention is based on the above embodiment, and is different from the above embodiment in that the slant field plate structure 47 forms a linear structure in the first half during the approach to the drain 44, and the partial linear structure
  • the slant field plate is parallel to the multilayer semiconductor layer, and a concave-shaped slant field plate is formed in the second half (ie, a section near the drain 44).
  • the slant field plate structure 47 of the shape can well surface the power device. The electric field distribution is adjusted.
  • the shape of the slant field plate structure in the slant field plate power device of the fourth embodiment of the present invention can be realized by designing the density of the light-shielding lattice on the mask.
  • the slant field plate power device includes a substrate 51, a plurality of semiconductor layers 52 on the substrate 51, a source 53 on the multilayer semiconductor layer 52, a drain 54 and a gate 55 between the source 53 and the drain 54, a gate 55, a gate 55 and a source 53, and a gate 55 a dielectric layer 56 on the multilayer semiconductor layer 52 between the drain 54 and a recess on the dielectric layer 56 between the gate 55 and the drain 54 having a slope on the side of the recess An inclined field plate structure 57 on the inner wall of the groove.
  • the fifth embodiment of the present invention is based on the above embodiment, and is different from the above embodiment in that the shape of the slant field plate structure 57 in the fifth embodiment is zigzag, which can reduce the electric field peak at the end of the field plate and make it The distribution is more uniform, and the size and shape of the zigzag slant field plate is determined by the process and design.
  • the zigzag slant field plate structure 57 can be achieved by designing the density of the shading lattice on the mask.
  • the slant field plate power device includes a substrate 61, a multilayer semiconductor layer 62 on the substrate 61, A source 63, a drain 64, and a gate 65 between the source 63 and the drain 64, a gate 65, a gate 65 and a source 63, and a gate 65 are disposed on the multilayer semiconductor layer 62.
  • Embodiment 6 of the present invention is based on the above embodiment, and is different from the above embodiment in that the slant field plate structure 67 partially covers the groove on the dielectric layer 66 between the gate 65 and the drain 64.
  • the slant field plate structure 67 is directly connected to the gate 65, which can effectively adjust the electric field intensity distribution at the edge of the gate 65 and improve device characteristics.
  • the slant field plate structure 67 may be connected to the source 63 or connected to the gate 65 or connected to a fixed potential or in a floating state.
  • the slant field plate power device provided in Embodiment 6 of the present invention makes the electric field distribution of the power device more uniform, and the electric field peak at the gate close to the drain is also pulled down, and the surface of the power device no longer generates a distinct high peak electric field, eliminating The easy breakdown region improves the overall voltage resistance of the power device and improves the high frequency characteristics of the power device.
  • the slant field plate power device includes a substrate 71, a multilayer semiconductor layer 72 on the substrate 71, A source 73, a drain 74, and a gate 35 between the source 73 and the drain 74, a gate 75, a gate 75 and a source 73, and a gate 75 are disposed on the multilayer semiconductor layer 72.
  • An inclined field plate structure 77 on the inner wall of the groove.
  • the seventh embodiment of the present invention is based on the first embodiment, and is different from the first embodiment in that the slant field plate structure 77 in the seventh embodiment is linear on the side close to the gate 75, and is close to the drain.
  • the shape of one side of the pole 74 is stepped.
  • FIGS. 16A to 16D are cross-sectional views corresponding to the steps of preparing the slant field plate structure 77 in the seventh embodiment of the present invention, and are formed as shown in FIG.
  • the illustrated slant field plate power device, as shown in Figures 16A-16D, is fabricated as follows:
  • a slanted field plate region is photolithographically patterned on a dielectric layer 76 between the gate 75 and the drain 74 using a positive paste to form a recess in the photoresist, followed by a dry method.
  • Etch The etch is performed along the lithographic region to optimize the etch selectivity of the photoresist and dielectric layer 76 to form a recess in the dielectric layer 76 that conforms to the shape of the photoresist.
  • a plurality of SiOxNy structures are deposited in the grooves on the dielectric layer 76 between the gate 75 and the drain 74, and the composition ratio of each layer varies according to design requirements, for example, from top to bottom.
  • the Si component is decremented, and then the polishing process is used to remove the SiOxNy layer outside the slant field plate region.
  • the dielectric layer 76 on the gate electrode 75 is polished together to form a SiOxNy layer in the slant field plate region. A flush structure.
  • a slanted field plate structure 77 is formed by depositing metal in the recess by a metal evaporation process.
  • the slant field plate structure 77 is also stepped in a shape close to the gate 75 and adjacent to the drain 74 (as shown in FIG. 17D).
  • FIGS. 17A-17D are preferred embodiments of the seventh embodiment of the present invention.
  • the stepped slant field plate structure 77 is manufactured as follows:
  • a first photoresist 761 and a second photoresist 762 are sequentially coated on the dielectric layer 76 between the gate 75 and the drain 74, and the first photoresist 761 can be washed away by an organic solvent. After exposure, it is dissolved in the developing solution; the second photoresist 762 is dissolved in the developing solution and the stripping solution, and is insoluble in a general organic solvent.
  • the first photoresist 761 is first exposed and developed.
  • a recess may be formed on the second photoresist 762, and then the first photoresist 761 may be washed away with an organic solvent. Recoating the first photoresist 761, repeating the previous exposure and development process, the width of each exposure window is gradually graded according to design requirements, the development time is changed according to design requirements, and finally forming a step shape on the second photoresist 762. Groove.
  • the lithographic region is etched by a dry etching process to optimize the etching selectivity ratio of the second photoresist 762 and the dielectric layer 76.
  • a groove conforming to the shape of the groove on the second photoresist 762 is formed on the dielectric layer 76.
  • a metal slant field plate structure 77 is formed in the recess by a metal evaporation process.
  • the slant field plate power device provided in Embodiment 7 of the present invention makes the electric field distribution of the power device more uniform, and the electric field peak near the drain of the gate is also pulled down, and the surface of the power device no longer has a significant height.
  • the spike electric field eliminates the breakdown area, improves the overall voltage resistance of the power device, and improves the high frequency characteristics of the power device.

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Abstract

一种斜场板功率器件及斜场板功率器件的制备方法。斜场板功率器件包括衬底（11），位于衬底上的多层半导体层（12），位于多层半导体层上的源极（13）、漏极（14）以及位于源极和漏极之间的栅极（15）；位于栅极上和栅极与源极和漏极之间的多层半导体层上的介质层(16)，介质层上存在凹槽，凹槽的侧面具有倾斜度，位于凹槽内壁上的斜场板结构（17），使得功率器件表面不再产生明显的高尖峰电场，消除了易击穿区域，提高了功率器件整体的耐压性并改善了功率器件的高频特性。

Description

一种斜场板功率器件及斜场板功率器件的制备方法
本专利申请要求于2014年09月01日提交的，申请号为201410440179.2，申请人为苏州捷芯威半导体有限公司，发明名称为“一种斜场板功率器件及斜场板功率器件的制备方法”的中国专利申请的优先权，该申请的全文以引用的方式并入本申请中。
技术领域
本发明涉及半导体技术领域，具体涉及一种斜场板功率器件及斜场板功率器件的制备方法。
背景技术
第三代半导体氮化镓(GaN)材料的击穿电场远高于第一代半导体硅(Si)材料或第二代半导体砷化镓(GaAs)材料，因此基于氮化镓的电子器件能承受更高的工作电压。此外，氮化镓可以与其他III-N族化合物半导体形成异质结，并且具有高浓度的二维电子气(Two-Dimensional Electron Gas，简称2DEG)沟道，因此，高电压大电流的特性使氮化镓高电子迁移率晶体管(High Electron Mobility Transistor，简称HEMT)特别适用于制造大功率电子器件，从而具有很好的应用前景。
HEMT器件属于一种平面沟道场效应晶体管，其栅极靠近漏极方向的边缘往往聚集大部分电场线，形成一个高电场尖峰，当在栅极和漏极之间施加的电压增大时，此处的电场就会迅速增高，使得栅极泄漏电流增大，这种局部区域的高电场很容易引起器件因发生雪崩击穿而失效，从而降低器件的击穿电压。同时，随着工作时间的增加，高电场也会引起器件表面介质层或半导体材料层退化、变性，进而影响器件工作可靠性，降低器件寿命。
现有技术一般在栅极靠近漏极的一侧放置一个场板，以降低器件的栅极附近的强电场，从而提高器件的击穿电压并获得优良的可靠性。图1是现有技术 中场板功率器件的结构图，如图1所示，该场板功率器件包括衬底101、顺次堆叠于衬底101上的成核层102、缓冲层103、沟道层104和势垒层105、位于势垒层105上的源极106、漏极107以及位于源极106和漏极107之间的栅极108、位于栅极108上和栅极108与源极106和漏极107之间的势垒层105上的介质层109，以及位于介质层109上的金属场板结构110，所述金属场板110的底部平行于势垒层105，通常与源极106或栅极108连接，在栅漏区域可以产生一个附加电势，可以有效地平抑栅极108接近漏极107边沿附近的电场尖峰，从而提高器件击穿电压及器件可靠性。由于这种场板的底部与器件势垒层105表面是平行的，因此在减小靠近栅极108边缘的电场尖峰同时，会在场板终端附近形成一个新的较小的电场尖峰，这个新出现的电场尖峰峰值会随着场板长度的增加而增加，容易造成场板终端区域器件击穿或失效，器件击穿问题没有得到根本解决，只是将矛盾从一个地方转移到了另一个地方，而且场板过长会产生较大的寄生电容，影响器件高频功率特性。
为了改善这种状态，现有技术中，往往采用多层(如三层)依次逐渐走高的场板结构，形成电势的梯度分布。这种梯度分布的场板结构必须由多步光刻、介质沉积、金属沉积等工艺配合完成，制作工艺复杂，同时会增加器件的制造成本。而且，这种多级场板不能使器件表面电场完全均匀分布，从而难以实现最佳的器件性能。
发明内容
有鉴于此，本发明实施例提供一种斜场板功率器件及斜场板功率器件的制备方法，以平抑功率器件表面的高电场尖峰、消除易击穿区域、提高器件的耐压性、改善器件的高频特性并降低制造工艺的复杂性和制造成本。
第一方面，本发明实施例提供了一种斜场板功率器件，所述器件包括
衬底；
位于所述衬底上的多层半导体层；
位于所述多层半导体层上的源极、漏极以及位于源极和漏极之间的栅极；
位于所述栅极上、栅极与源极之间和栅极与漏极之间的多层半导体层上的介质层；
位于所述栅极与漏极之间的介质层上的凹槽，所述凹槽的侧面具有倾斜度；
位于所述凹槽内壁上的斜场板结构。
进一步地，所述多层半导体层包括位于衬底上的成核层，位于成核层上的缓冲层，位于缓冲层上的沟道层，位于沟道层上的势垒层，其中，所述沟道层和所述势垒层形成异质结结构，异质界面处形成有二维电子气，所述源极和漏极分别与二维电子气接触。
进一步地，所述斜场板结构的材料为金属材料。
进一步地，所述斜场板结构与所述源极连接或与所述栅极连接或与一固定电位连接或处于浮空状态。
进一步地，所述斜场板结构的形状包括直线形、曲线形、锯齿形或阶梯形中的任意一种形状或多种形状的组合。
进一步地，所述多层半导体层还包括位于所述沟道层和势垒层之间的插入层。
进一步地，所述插入层的材料为AlN。
进一步地，所述多层半导体层还包括位于缓冲层和沟道层之间的背势垒层。
进一步地，所述背势垒层的材料为AlGaN。
进一步地，所述器件还包括位于所述多层半导体层和栅极之间的栅介质。
进一步地，所述栅极位于所述势垒层的表面或至少部分设置于所述势垒层的凹处。
进一步地，所述多层半导体层包括III-V族化合物的半导体材料。
进一步地，所述栅介质的材料包括SiN、SiO2、SiON、Al2O3、HfO2、HfAlOx中的任意一种或任意几种的组合。
进一步地，所述栅极为T形栅或斜面栅。
第二方面，本发明实施例提供了一种如第一方面所述的斜场板功率器件的制备方法，所述方法包括：
在衬底上形成多层半导体层；
在所述多层半导体层上形成源极、漏极以及位于源极和漏极之间的栅极；
在所述栅极上、栅极与源极和栅极与漏极之间的多层半导体层上形成介质层；
在所述栅极与漏极之间的介质层上形成凹槽，所述凹槽的侧面具有倾斜度；
在所述凹槽的内壁上形成斜场板结构。
进一步地，所述在衬底上形成多层半导体层包括：
在所述衬底上形成成核层；
在所述成核层上形成缓冲层；
在所述缓冲层上形成沟道层；
在所述沟道层上形成势垒层，其中，所述沟道层和所述势垒层形成异质结结构，异质界面处形成有二维电子气，所述源极和漏极分别与二维电子气接触。
进一步地，在所述介质层上形成凹槽的方法包括干法刻蚀或湿法腐蚀。
进一步地，在所述凹槽的内壁上形成斜场板结构的方法包括金属电子束蒸发工艺或金属溅射工艺或金属化学气相淀积工艺。
本发明实施例提供的斜场板功率器件及斜场板功率器件的制备方法，通过在介质层上形成侧面具有倾斜度的凹槽，在所述凹槽的内壁上沉积有斜场板结构，当有外加电压加载到功率器件的漏极上时，所述斜场板结构可以对器件表面的电场分布进行调节，由于斜场板结构具有倾斜度，场板终端的电场尖峰被平抑，整个电场分布更加均匀，在栅极接近漏极处的电场尖峰也被拉低，使得功率器件表面不再产生明显的高尖峰电场，消除了易击穿区域，提高了功率器件整体的耐压性、改善了功率器件的高频特性并降低制造工艺的复杂性和制造成本。
附图说明
下面将通过参照附图详细描述本发明的示例性实施例，使本领域的普通技术人员更清楚本发明的上述及其他特征和优点，附图中：
图1是现有技术中场板功率器件的结构图；
图2是本发明实施例一提供的一种斜场板功率器件的结构图；
图3是本发明实施例一中斜场板功率器件与现有技术中场板功率器件在高压状态下器件表面的电场分布示意图；
图4A-图4F是本发明实施例一提供的斜场板功率器件的制备方法各步骤对应结构的剖面图；
图5-图9是本发明实施例一的优选实施例提供的斜场板功率器件的结构图；
图10是本发明实施例二提供的一种斜场板功率器件的结构图；
图11是本发明实施例三提供的一种斜场板功率器件的结构图；
图12是本发明实施例四提供的一种斜场板功率器件的结构图；
图13是本发明实施例五提供的一种斜场板功率器件的结构图；
图14是本发明实施例六提供的一种斜场板功率器件的结构图；
图15是本发明实施例七提供的一种斜场板功率器件的结构图；
图16A-图16D是本发明实施例七中制备斜场板结构的步骤对应的剖面图；
图17A-图17D是本发明实施例七的优选实施例中制备斜场板结构的步骤对应的剖面图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部内容。
实施例一
图2是本发明实施例一提供的一种斜场板功率器件的结构图，如图2所示，该斜场板功率器件包括衬底11、位于衬底11上的多层半导体层12、位于多层半导体层12上的源极13、漏极14以及位于源极13和漏极14之间的栅极15、位于栅极15上和栅极15与源极13之间、栅极15与漏极14之间的多层半导体 层12上的介质层16，位于所述栅极15与漏极14之间的介质层16上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构17。
衬底11的材料可以是硅、蓝宝石、碳化硅、绝缘衬底硅、氮化镓、氮化铝、氧化锌或任何其他能够生长III族氮化物的材料。
多层半导体层12的材料可以是III-V族化合物的半导体材料，具体地，所述多层半导体层12可包括：
位于衬底11上的成核层121，该成核层121影响位于其上的异质结材料的晶体质量、表面形貌以及电学性质等参数，起到匹配衬底材料和异质结结构中半导体材料层的作用。
位于成核层121上的缓冲层122，缓冲层122能够保护衬底11不被一些金属离子侵入，又能够粘合需要生长于其上的其他半导体材料层，缓冲层122的材料可以是AlGaN、GaN或AlGaInN等III族氮化物材料。
位于缓冲层122上的沟道层123，位于沟道层123上的势垒层124，势垒层124的材料可以为AlGaN，所述沟道层123和势垒层124形成异质结结构，异质界面处形成有2DEG沟道(图2中虚线所示)，其中，沟道层123提供了2DEG运动的沟道，势垒层124起势垒作用。
位于势垒层124上的源极13和漏极14分别与2DEG接触，栅极15位于源极13和漏极14之间且位于势垒层124上，栅极15可以是T形栅，当在栅极15上施加适当的偏压时，电流通过沟道层123和势垒层124界面之间的2DEG导电沟道在源极13和漏极14之间流动。
所述介质层16能够对所述斜场板功率器件中多层半导体层的表面进行钝化保护。
位于在所述栅极15与漏极14之间的介质层16上的凹槽，所述凹槽的侧面具有倾斜度，在所述凹槽的内壁上沉积有斜场板结构17，该斜场板结构17的形状为直线形，该凹槽的底部在向漏极14延伸的过程中距离多层半导体层12的距离越来越远，当有外加电压施加到漏极14上时，斜场板结构17可以对功率器件的表面电场进行调节，随着斜场板结构17靠近漏极14的一端距离多层半导体层12越来越远，相对于现有技术中的场板来说，场板终端的电场尖峰也被 平抑，整个电场分布更加均匀，栅极15靠近漏极14的电场尖峰也被拉低，如图3所示，图3是本发明实施例一中斜场板功率器件与现有技术中场板功率器件在高压状态下器件表面的电场分布示意图，图中，横坐标表示电场分布位置，纵坐标表示器件表面的电场，实线表示现有技术中场板功率器件在高压状态下器件表面电场分布示意图，虚线表示本发明实施例一提供的斜场板功率器件在高压状态下器件表面电场分布示意图，从图中可以发现，现有技术中由于这种场板的底部与器件势垒层表面是平行的，在减小靠近栅极边缘的电场尖峰同时，会在场板终端附近形成一个新的较小的电场尖峰，这个新出现的电场尖峰峰值会随着场板长度的增加而增加，容易造成场板终端区域器件击穿或失效，器件击穿问题没有得到根本解决，本发明实施例一提供的斜场板功率器件表面不再产生明显的高尖峰电场，易击穿区域被消除，器件整体耐压性提高，并且随着斜场板远离器件表面，产生的寄生电容效应逐渐减弱，改善了场板对器件高频特性的影响。
下面，对本发明实现上述斜场板半导体器件的制造方法做详细说明。
参见图4A-图4F，图4A-图4F是本发明实施例一提供的斜场板功率器件的制备方法各步骤对应结构的剖面图，该斜场板功率器件的制备方法用于制备如图2所示的斜场板功率器件，该斜场板功率器件的制造方法包括：
步骤S11、在衬底11上形成半导体层12。
参见图4A，具体地，可在衬底11上顺次形成成核层121、缓冲层122、沟道层123和势垒层124，其中，沟道层123和势垒层124形成异质结结构，异质界面处形成有2DEG。
步骤S12、在多层半导体层12上形成源极13、漏极14及位于源极13和漏极14之间的栅极15。
参见图4B，源极13和漏极14分别与异质结界面处的2DEG接触，源极13和漏极14的形成工艺可包括高温退火法或重掺杂法或离子注入法等。
步骤S13、在所述栅极15上、栅极15与源极13之间和栅极15与漏极14之间的多层半导体层12上形成介质层16。
参见图4C，在栅极15上以及栅极15与源极13之间、栅极15与漏极14 之间的多层半导体层12上形成介质层16，介质层16起钝化作用，用于保护斜场板功率器件的表面。
步骤S14，在介质层16上形成凹槽，所述凹槽的侧面具有倾斜度。
具体地，可通过干法刻蚀或湿法腐蚀的方法在介质层16上形成凹槽。
参见图4D，在介质层16上使用正胶18做光刻工艺，采用特殊设计的掩膜板对斜场板区域进行光刻，通过调整掩膜板上遮光点阵的密度，使得斜场板区域在栅极15附近到远离栅极15而靠近漏极14的方向上先逐渐增强曝光度再逐渐降低曝光度的掩膜设计，显影后在光刻胶上形成具有一定倾斜度的凹槽，在本发明中，对凹槽的倾斜度不做限定，最佳倾斜度可根据工艺或功率器件的设计要求来进行设定。
参见图4E，在光刻胶上形成具有一定倾斜度的凹槽以后，采用干法刻蚀工艺，对光刻区域进行刻蚀，通过优化光刻胶和介质层16的刻蚀选择比，例如：光刻胶和介质层16的刻蚀选择比为1∶1，从而保证刻蚀以后介质层16中形成凹槽的形状与光刻胶上凹槽的形状一致，从而在介质层16上形成具有一定倾斜度的凹槽，所述凹槽的底部在向漏极14延伸的过程中距离多层半导体层12的距离逐渐增大。
优选的，为了控制凹槽距离多层半导体层12的距离，可在介质层16内插入刻蚀控制层来精确控制刻蚀深度，形成满足设计条件的凹槽。
需要说明的是，在本步骤中，采用干法刻蚀工艺在介质层16上刻蚀凹槽的过程中，当位于栅极15上介质层16的厚度比较薄时，该部分介质层16被完全刻蚀掉，当位于栅极15上介质层16的厚度比较厚时，该部分介质层16没有被完全刻蚀掉，形成如图4E所示的结构。
步骤S15，在所述凹槽的内壁上形成斜场板结构17。
参见图4F，所述斜场板结构17的材料为金属，具体地，可通过金属蒸发工艺或金属溅射工艺或金属化学气相淀积工艺在所述凹槽的内壁上形成斜场板结构17，所述斜场板结构17完全覆盖了介质层16上的凹槽。
所述金属斜场板结构17的长度、厚度以及斜场板结构距离多层半导体层表面的距离可根据功率器件的设计需求进行调整。
需要说明的是，以上虽然以使用特殊设计的掩膜板光刻、介质刻蚀，金属蒸发等工艺为例描述了如何形成斜场板结构，但是应该理解，所述斜场板结构的形成工艺也可以使用本领域的技术人员公知的其它工艺方法来形成，在此不作限定。
所述斜场板功率器件可应用于本发明也可以应用在任何需要使用场板的器件中，包括高压横向扩散金属氧化物半导体(Laterally Diffused Metal Oxide Semiconductor，简称LDMOS)功率器件、氮化镓高电子迁移率射频器件、电力电子器件、SiC功率器件、GaAs器件或其他半导体器件等。
本发明实施例提供的斜场板功率器件的制备方法，制备工艺简单，且不需要增加功率器件的制造成本，能够使功率器件表面电场分布均匀，消除了易击穿区域，提高了功率器件整体的耐压性并改善了功率器件的高频特性。
图5-图9是本发明实施例一的优选实施例提供的斜场板功率器件的结构图，具体如下：
优选的，多层半导体层12还包括位于沟道层123和势垒层124之间的插入层125，所述插入层125的材料可以为AlN，如图5所示。
由于AlN的禁带宽度非常高，可以更有效地将电子限制在异质结势井中，从而提高2DEG的浓度，此外，AlN插入层125还将2DEG导电沟道与势垒层124隔离开，减小了势垒层124对电子的散射效应，从而提高电子的迁移率，使得器件整体特性得以提高。
优选的，多层半导体层12还包括位于缓冲层122和沟道层123之间的背势垒层126，所述背势垒层126的材料可以为AlGaN，如图6所示。
在一定外加电压下，2DEG导电沟道中的电子会进入缓冲层122，尤其是在短沟道器件中这种现象更为严重，使得栅极15对2DEG导电沟道电子的控制相对变弱，出现短沟道效应；加上缓冲层122材料中的缺陷和杂质比较多，会对沟道中的2DEG产生影响，如产生电流崩塌，通过引入AlGaN背势垒层126可以将2DEG导电沟道电子与缓冲层122隔离开，将2DEG有效地限制在沟道层123中，改善短沟道效应及电流崩塌效应。
优选的，所述斜场板功率器件还包括位于多层半导体层12和栅极15之间 的栅介质18，如图7所示。
该栅介质18既可作为功率器件的钝化层，又可作为栅极绝缘层，可有效降低栅极15的漏电电流，调节开启电压。所述栅介质18的材料可包括SiN、SiO2、SiON、Al2O3、HfO2、HfAlOx中的任意一种或任意几种的组合。
优选的，栅极15可至少部分设置于势垒层124的凹处，如图8所示，通过刻蚀势垒层124形成凹槽，再沉积金属形成栅极15，可以减小栅极金属下材料表面缺陷及表面态的影响，降低漏电，提高击穿电压；同时由于栅极15距离2DEG导电沟道距离更近，对2DEG的控制作用更强，提高了器件的高频特性。需要说明的是，在本实施例中，需要控制对势垒层124的刻蚀深度，当势垒层刻蚀深度较大，凹槽下的二维电子气会降低或消失，该功率器件可实现增强型器件功能。
优选的，栅极15可以为斜面栅，如图9所示，通过优化刻蚀条件，在刻蚀栅槽区域的介质层16时形成斜面凹槽，再沉积金属形成斜面栅极，斜面栅极技术既可以降低栅极15靠近漏极14电场强度，并能够减小栅极15漏电电流，从而提高器件击穿电压，此外，采用斜面栅结构不会引入过大的寄生电容，对器件高频特性影响不大，配合本发明实施例中的斜场板结构17对器件特性的改善更加明显。
本发明实施例一提供的斜场板功率器件及斜场板功率器件的制备方法，使得功率器件整个电场分布更加均匀，栅极接近漏极处的电场尖峰也被拉低，功率器件表面不再产生明显的高尖峰电场，消除了易击穿区域，提高了功率器件整体的耐压性、改善了功率器件的高频特性并降低制造工艺的复杂性和制造成本。
实施例二
图10是本发明实施例二提供的一种斜场板功率器件的结构图，如图10所示，该斜场板功率器件包括衬底21、位于衬底21上的多层半导体层22、位于多层半导体层22上的源极23、漏极24以及位于源极23和漏极24之间的栅极25、位于栅极25上、栅极25与源极23之间和栅极25与漏极24之间的多层半 导体层22上的介质层26，位于所述栅极25与漏极24之间的介质层26上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构27。
本发明实施例二以上述实施例一为基础，与实施例一的不同之处在于，实施例二中斜场板结构27的形状在靠近栅极25的一侧为直线形，在靠近漏极24的一侧为上凸曲线形，该斜场板结构27的最低端在向漏极24靠近的过程中距离多层半导体层22的距离逐渐增加。
在本实施例中，通过设计掩膜板上的遮光点阵密度，可以形成上凸曲线形状的斜场板结构，相比直线形斜场板通过倾斜角度来优化电场分布，曲线形斜场板可以通过曲线弧度来调整电场分布，增加了优化电场分布的方法，该形状的斜场板结构27能够很好地调节斜场板靠近漏极24一端的电场，能够更好的改善器件特性。
实施例三
图11是本发明实施例三提供的一种斜场板功率器件的结构图，如图11所示，该斜场板功率器件包括衬底31、位于衬底31上的多层半导体层32、位于多层半导体层32上的源极33、漏极34以及位于源极33和漏极34之间的栅极35、位于栅极35上、栅极35与源极33之间和栅极35与漏极34之间的多层半导体层32上的介质层36，位于所述栅极35与漏极34之间的介质层36上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构37。
本实施例三以上述实施例为基础，与上述实施例的不同之处在于，斜场板结构37在靠近漏极34一端形成下凹曲线形状的斜场板结构，下凹曲线形状的斜场板前段更加贴近功率器件表面，可以加强对功率器件表面电场的调制作用。本发明实施例三提供的斜场板功率器件中斜场板结构的形状可通过设计掩膜板上的遮光点阵的密度来实现。
实施例四
图12是本发明实施例四提供的一种斜场板功率器件的结构图，如图12所示，该斜场板功率器件包括衬底41、位于衬底41上的多层半导体层42、位于 多层半导体层42上的源极43、漏极44以及位于源极43和漏极44之间的栅极45、位于栅极45上、栅极45与源极43之间和栅极45与漏极44之间的多层半导体层42上的介质层46，位于所述栅极45与漏极44之间的介质层46上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构47。
本发明实施例四以上述实施例为基础，与上述实施例的不同之处在于，斜场板结构47在向漏极44靠近的过程中，在前半段形成直线形结构，该部分直线形结构的斜场板平行于多层半导体层，在后半段(即靠近漏极44的一段)形成下凹形状的斜场板，该形状的斜场板结构47能够很好地对功率器件表面的电场分布进行调节，本发明实施例四的斜场板功率器件中斜场板结构的形状可通过设计掩膜板上的遮光点阵的密度来实现。
实施例五
图13是本发明实施例五提供的一种斜场板功率器件的结构图，如图13所示，该斜场板功率器件包括衬底51、位于衬底51上的多层半导体层52、位于多层半导体层52上的源极53、漏极54以及位于源极53和漏极54之间的栅极55、位于栅极55上、栅极55与源极53之间和栅极55与漏极54之间的多层半导体层52上的介质层56，位于所述栅极55与漏极54之间的介质层56上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构57。
本发明实施例五以上述实施例为基础，与上述实施例的不同之处在于，实施例五中斜场板结构57的形状为锯齿形，这样可以降低场板末端的电场峰值，并使其分布更加均匀，锯齿形斜场板的尺寸和形状由工艺和设计决定，所述锯齿形的斜场板结构57可通过设计掩膜板上的遮光点阵的密度来实现。
实施例六
图14是本发明实施例六提供的一种斜场板功率器件的结构图，如图14所示，该斜场板功率器件包括衬底61、位于衬底61上的多层半导体层62、位于多层半导体层62上的源极63、漏极64以及位于源极63和漏极64之间的栅极65、位于栅极65上、栅极65与源极63之间和栅极65与漏极64之间的多层半 导体层62上的介质层66，位于所述栅极65与漏极64之间的介质层66上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构67。
本发明实施例六以上述实施例为基础，与上述实施例的不同之处在于，所述斜场板结构67部分覆盖位于栅极65与漏极64之间的介质层66上的凹槽，该斜场板结构67直接与栅极65连接，能够有效地调节栅极65边缘电场强度分布，提高器件特性。
需要说明的是，所述斜场板结构67可以与源极63连接或与所述栅极65连接或与一固定电位连接或处于浮空状态。
本发明实施例六提供的斜场板功率器件，使得功率器件整个电场分布更加均匀，在栅极接近漏极处的电场尖峰也被拉低，功率器件表面不再产生明显的高尖峰电场，消除了易击穿区域，提高了功率器件整体的耐压性并改善了功率器件的高频特性。
实施例七
图15是本发明实施例七提供的一种斜场板功率器件的结构图，如图15所示，该斜场板功率器件包括衬底71、位于衬底71上的多层半导体层72、位于多层半导体层72上的源极73、漏极74以及位于源极73和漏极74之间的栅极35、位于栅极75上、栅极75与源极73之间和栅极75与漏极74之间的多层半导体层72上的介质层76，位于栅极75与漏极74之间的介质层76上的凹槽，所述凹槽的侧面具有倾斜度，位于所述凹槽内壁上的斜场板结构77。
本发明实施例七以上述实施例一为基础，与实施例一的不同之处在于，实施例七中的斜场板结构77是在靠近栅极75一侧的形状是直线形，在靠近漏极74一侧的形状是阶梯形。
在本实施例中，与实施例一相同的部分不再重述，图16A-图16D是本发明实施例七中制备斜场板结构77的步骤对应的剖面图，用以形成如图15所示的斜场板功率器件，如图16A-图16D所示，斜场板结构77的制作方法如下：
参见图16A，在栅极75与漏极74之间的介质层76上使用正胶做光刻工艺对斜场板区域进行光刻，从而在光刻胶上形成一个凹槽，之后采用干法刻蚀工 艺，随光刻区域进行刻蚀，通过优化光刻胶和介质层76的刻蚀选择比，从而在介质层76中形成与光刻胶上形状一致的凹槽。
参见图16B，在栅极75与漏极74之间的介质层76上的凹槽中沉积多层SiOxNy结构，每一层的组份比例按照设计要求变化，例如：从上往下每一层Si组份递减，然后使用抛光工艺，去除斜场板区域外的SiOxNy层，在本步骤中，位于栅极75上的介质层76被一起抛光磨平，从而形成与斜场板区域中SiOxNy层表面平齐的结构。
参见图16C，在斜场板区域进行光刻和湿法腐蚀，并利用不同组份SiOxNy腐蚀速率不同的特点，形成符合要求阶梯形凹槽。
参见图16D，通过金属蒸发工艺在所述凹槽中沉积金属形成斜场板结构77。
优选的，斜场板结构77也可在靠近栅极75和靠近漏极74方向的形状都是阶梯形(如图17D所示)，图17A-图17D是本发明实施例七的优选实施例中制备斜场板结构77的步骤对应的剖面图，如图17A-图17D所示，该阶梯形斜场板结构77的制作方法如下：
参见图17A，在栅极75与漏极74之间的介质层76上依次涂覆第一光刻胶761和第二光刻胶762，该第一光刻胶761可以被有机溶剂清洗掉，曝光后溶于显影液；该第二光刻胶762溶于显影液和剥离液，不溶于一般的有机溶剂。
参见图17B，先对第一光刻胶761进行曝光显影，通过控制曝光窗口宽度和显影时间，可以在第二光刻胶762上形成凹槽，然后用有机溶剂清洗掉第一光刻胶761，重新涂覆第一光刻胶761，重复之前的曝光显影工艺，每次曝光窗口的宽度按照设计要求成梯度渐变，显影时间按照设计要求变化，最终在第二光刻胶762上形成阶梯形凹槽。
参见图17C，在第二光刻胶762上形成阶梯形凹槽以后，采用干法刻蚀工艺对光刻区域进行刻蚀，通过优化第二光刻胶762和介质层76的刻蚀选择比，从而在介质层76上形成与第二光刻胶762上的凹槽形状一致的凹槽。
参见图17D，通过金属蒸发工艺在所述凹槽中形成金属斜场板结构77。
本发明实施例七提供的斜场板功率器件，使得功率器件整个电场分布更加均匀，栅极接近漏极处的电场尖峰也被拉低，功率器件表面不再产生明显的高 尖峰电场，消除了易击穿区域，提高了功率器件整体的耐压性并改善了功率器件的高频特性。
以上所述仅为本发明的优选实施例，并不用于限制本发明，对于本领域技术人员而言，本发明可以有各种改动和变化。凡在本发明的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (18)

  1. 一种斜场板功率器件，其特征在于，所述器件包括
    衬底；
    位于所述衬底上的多层半导体层；
    位于所述多层半导体层上的源极、漏极以及位于源极和漏极之间的栅极；
    位于所述栅极上、栅极与源极之间和栅极与漏极之间的多层半导体层上的介质层；
    位于所述栅极与漏极之间的介质层上的凹槽，所述凹槽的侧面具有倾斜度；
    位于所述凹槽内壁上的斜场板结构。
  2. 根据权利要求1所述的斜场板功率器件，其特征在于，所述多层半导体层包括位于衬底上的成核层，位于成核层上的缓冲层，位于缓冲层上的沟道层，位于沟道层上的势垒层，其中，所述沟道层和所述势垒层形成异质结结构，异质界面处形成有二维电子气，所述源极和漏极分别与二维电子气接触。
  3. 根据权利要求1所述的斜场板功率器件，其特征在于，所述斜场板结构的材料为金属材料。
  4. 根据权利要求1所述的斜场板功率器件，其特征在于，所述斜场板结构与所述源极连接或与所述栅极连接或与一固定电位连接或处于浮空状态。
  5. 根据权利要求1所述的斜场板功率器件，其特征在于，所述斜场板结构的形状包括直线形、曲线形、锯齿形或阶梯形中的任意一种形状或多种形状的组合。
  6. 根据权利要求2所述的斜场板功率器件，其特征在于，所述多层半导体层还包括位于所述沟道层和势垒层之间的插入层。
  7. 根据权利要求6所述的斜场板功率器件，其特征在于，所述插入层的材料为AlN。
  8. 根据权利要求2所述的斜场板功率器件，其特征在于，所述多层半导体层还包括位于缓冲层和沟道层之间的背势垒层。
  9. 根据权利要求8所述的斜场板功率器件，其特征在于，所述背势垒层的材料为AlGaN。
  10. 根据权利要求1所述的斜场板功率器件，其特征在于，所述器件还包 括位于所述多层半导体层和栅极之间的栅介质。
  11. 根据权利要求2所述的斜场板功率器件，其特征在于，所述栅极位于所述势垒层的表面或至少部分设置于所述势垒层的凹处。
  12. 根据权利要求2所述的斜场板功率器件，其特征在于，所述多层半导体层包括III-V族化合物的半导体材料。
  13. 根据权利要求10所述的斜场板功率器件，其特征在于，所述栅介质的材料包括SiN、SiO2、SiON、Al2O3、HfO2、HfAlOx中的任意一种或任意几种的组合。
  14. 根据权利要求1所述的斜场板功率器件，其特征在于，所述栅极为T形栅或斜面栅。
  15. 一种如权利要求1所述的斜场板功率器件的制备方法，其特征在于，所述方法包括：
    在衬底上形成多层半导体层；
    在所述多层半导体层上形成源极、漏极以及位于源极和漏极之间的栅极；
    在所述栅极上、栅极与源极之间和栅极与漏极之间的多层半导体层上形成介质层；
    在所述栅极与漏极之间的介质层上形成凹槽，所述凹槽的侧面具有倾斜度；
    在所述凹槽的内壁上形成斜场板结构。
  16. 根据权利要去15所述的斜场板功率器件的制备方法，其特征在于，所述在衬底上形成多层半导体层包括：
    在所述衬底上形成成核层；
    在所述成核层上形成缓冲层；
    在所述缓冲层上形成沟道层；
    在所述沟道层上形成势垒层，其中，所述沟道层和所述势垒层形成异质结结构，异质界面处形成有二维电子气，所述源极和漏极分别与二维电子气接触。
  17. 根据权利要求15所述的斜场板功率器件的制备方法，其特征在于，在所述介质层上形成凹槽的方法包括干法刻蚀或湿法腐蚀。
  18. 根据权利要求15所述的斜场板功率器件的制备方法，其特征在于，在 所述凹槽的内壁上形成斜场板结构的方法包括金属电子束蒸发工艺或金属溅射工艺或金属化学气相淀积工艺。
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