WO2015079294A2 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2015079294A2
WO2015079294A2 PCT/IB2014/002403 IB2014002403W WO2015079294A2 WO 2015079294 A2 WO2015079294 A2 WO 2015079294A2 IB 2014002403 W IB2014002403 W IB 2014002403W WO 2015079294 A2 WO2015079294 A2 WO 2015079294A2
Authority
WO
WIPO (PCT)
Prior art keywords
solder
layer
terminal
wiring layer
semiconductor device
Prior art date
Application number
PCT/IB2014/002403
Other languages
English (en)
Other versions
WO2015079294A8 (fr
WO2015079294A3 (fr
Inventor
Takuya Kadoguchi
Takanori Kawashima
Original Assignee
Toyota Jidosha Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Jidosha Kabushiki Kaisha filed Critical Toyota Jidosha Kabushiki Kaisha
Priority to US15/036,089 priority Critical patent/US9953905B2/en
Priority to KR1020167013533A priority patent/KR101812908B1/ko
Priority to DE112014005420.8T priority patent/DE112014005420B4/de
Priority to CN201480064023.7A priority patent/CN105917463B/zh
Publication of WO2015079294A2 publication Critical patent/WO2015079294A2/fr
Publication of WO2015079294A3 publication Critical patent/WO2015079294A3/fr
Publication of WO2015079294A8 publication Critical patent/WO2015079294A8/fr
Priority to US15/590,572 priority patent/US9824961B2/en

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    • H—ELECTRICITY
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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Definitions

  • the present invention relates to a semiconductor device.
  • a semiconductor device in which a semiconductor element and a terminal are mounted on a substrate for example, a semiconductor device that is mounted on a vehicle and has a function of power control and the like is known.
  • the substrate and the semiconductor element are fixed via a first solder layer and the substrate and the terminal are fixed via a second solder layer.
  • the present invention provides a semiconductor device that can prevent a solder that forms a solder layer from outflowing toward other member.
  • a semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part.
  • the semiconductor element is fixed on one side of the substrate v ia a first solder layer.
  • the terminal is fixed on the one side of the substrate via a second solder layer.
  • the solder outflow prevention part is provided between the semiconductor element and the terminal in the one side of the substrate and is configured to prevent the first solder layer and the second solder layer from outflowing.
  • a distance between the solder outflow prevention part and the semiconductor element is longer than a thickness of the first solder layer.
  • the semiconductor device that can prevent the solder that forms the solder layer from outflowing toward other member can be provided.
  • FIG. 1 is a cross-sectional view that shows a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a plan view that shows the semiconductor device according to the first embodiment
  • FIGs. 3A and 3B are diagrams for describing an amount of a solder and a volume of a groove
  • FIG. 4 is a plan view that shows another example of a shape of the groove
  • FIG. 5 is a cross-sectional view that shows a semiconductor device according to a second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view that shows a semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 is a plan view that shows the semiconductor device according to the third embodiment.
  • FIG. 8 is a cross-sectional view that shows a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 9 is a plan view that shows the semiconductor device according to the fourth embodiment
  • FIG. 10 is a cross-sectional view that shows a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 1 1 is a plan view that shows the semiconductor device according to the fifth embodiment.
  • FIG. 12 is a cross-sectional view that shows a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 1 is a cross-sectional view that shows a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a plan view that shows the semiconductor device according to the first embodiment. However, in FIG. 2, only a part of members shown in FIG. 1 is shown. Further, FIG. 1 shows a cross-section along a I-I line of FIG. 2.
  • a semiconductor device 1 includes a substrate 10, a semiconductor element 20, a sealing resin 30, and terminals 41 and 42.
  • the substrate 10 includes an insulating layer 1 1 , a first wiring layer 12 and a second wiring layer 13.
  • the terminal 41 side is taken as an upper side or one side of the substrate 10
  • a second wiring layer 13 side is taken as a lower side or the other side of the substrate 10.
  • a surface on the terminal 41 side of the respective sites is taken as an upper surface or one surface
  • a surface on the second wiring layer 13 side is taken as a lower surface or the other surface.
  • the semiconductor device 1 can be used in an upside-down state, or can oe disposed at an arbitrary angle.
  • a plan view indicates to see a subject matter from a normal line direction of one surface of the insulating layer 1 1
  • a planar shape indicates a shape when the subject matter is seen from the normal line direction of one surface of the insulating layer 1 1.
  • the insulating layer 1 1 is formed of an insulating material such as ceramics, for example.
  • an insulating material such as ceramics, for example.
  • the insulating layer 1 1 is formed of the ceramics, as a material, for example, silicon nitride (S13N4), aluminum oxide (AI2O3), aluminum nitride (A1N) or the like can be used.
  • the material of the insulating layer 1 1 is not limited to the ceramics, an insulating resin, glass and the like may be used.
  • the planar shape of the insulating layer 11 may be a square, a rectangle or the like having a side of about 30 to 50 mm.
  • a thickness of the insulating layer 11 may be, for example, about 0.2 to 1.5 mm.
  • the first wiring layer 12 is bonded to one surface of the insulating layer 1 1 , by, for example, brazing or the like.
  • the first wiring layer 12 may be disposed over an entire surface of one surface of the insulating layer 1 1 or, for example, may be disposed such that an outer periphery part of one surface of the insulating layer 1 1 is exposed.
  • a thickness of the first wiring layer 12 may be, for example, about 0.2 to 1 mm.
  • the first wiring layer 12 is made of a material having a poor solder wetting property such as aluminum (Al), a surface treatment film (a plating film or the like) such as nickel (Ni) or gold (Au) having an excellent solder wetting property is preferably formed on a surface of the first wiring layer 12.
  • a surface treatment film such as nickel (Ni) or gold (Au) having an excellent solder wetting property is preferably formed on a surface of the first wiring layer 12.
  • a groove 12x (through groove) that exposes one surface of the insulating layer 1 1 is formed.
  • the groove 12x is formed on a terminal 42 side of the semiconductor element 20.
  • the groove 12x is a typical example of a solder outflow prevention part according to the present invention.
  • a planar shape of the groove 12x may be, for example, a U-shape that opens on an opposite side from the semiconductor element 20.
  • a distance d between the groove 12x and the semiconductor element 20 is set longer than a thickness t of a solder layer 51.
  • a thickness t of a solder layer 51 is 0.1 mm
  • the distance d between the groove 12x and the semiconductor element 20 at least about 0.15 mm is necessary.
  • the distance d may be set to any length.
  • the reason why the distance d between the groove 12x and the semiconductor element 20 is set longer than the thickness t of the solder layer 51 is as follows. That is, since a solder fillet usually forms an angle of inclination of about 45° to 90°, a tip of the fillet of the solder layer 51 extends at most only to an extent the same as the thickness t of the solder layer 51 from an end surface of the semiconductor element 20.
  • the fillet of the solder layer 51 can be prevented from reaching the groove 12x and establishing an electrical continuity with a solder layer 53 in the groove 12x.
  • a starting point of the distance d is preferably set to a part closest to the groove 12x of the electrode on the lower surface side of the semiconductor element 20.
  • the distance d between the groove 12x and the semiconductor element 20 is represented by including also such a case.
  • the solder that forms the solder layer 53 is also required not to reach the solder layer 51.
  • a relationship between an amount of the solder (that forms the solder layer 53 after curing) and a volume of the groove 12x is important. This will be described below.
  • the second wiring layer 13 is bonded to the other surface of the insulating layer 11 by, for example, brazing or the like.
  • the second wiring layer 13 may be disposed over an entire surface of the other surface of the insulating layer 1 1 , or, for example, may be disposed such that an outer periphery part of the other surface of the insulating layer 1 1 is exposed.
  • a thickness of the second wiring layer 13 may be set to, for example, about 0.2 to 1 mm.
  • the second wiring layer 13 is made of a material having a poor solder wetting property such as aluminum (Al), a surface treatment film (a plating film or the like) such as nickel (Ni) or gold (Au) having an excellent solder wetting property is preferably formed on a surface of the second wiring layer 13.
  • a surface treatment film such as nickel (Ni) or gold (Au) having an excellent solder wetting property is preferably formed on a surface of the second wiring layer 13.
  • the semiconductor element 20 is mounted in a predetermined element mounting region on the first wiring layer 12 of the substrate 10.
  • An electrode on a lower surface side of the semiconductor element 20 is electrically connected with the first wiring layer 12 via the solder layer 51.
  • the semiconductor element 20 is, for example, a switching element for electric power, which generates heat during operation of an IGBT (Insulated Gate Bipolar Transistor) or the like that constitutes an inverter circuit.
  • the heat that the semiconductor element 20 generates is radiated via the substrate 10.
  • a heat radiation component By disposing a heat radiation component on the second wiring layer 13 side, a heat radiation property may be further improved.
  • the semiconductor device 1 radiates the heat that the semiconductor element 20 generates from one surface side (a lower surface side), the semiconductor device 1 can be called a one-sided cooling module.
  • the sealing resin 30 is formed so as to cover the substrate 10, the semiconductor element 20, and the terminals 41 and 42.
  • the sealing resin 30 can be formed by transfer molding or the like, for example, with an insulting material such as an epoxy resin that contains a filler.
  • an insulting material such as an epoxy resin that contains a filler.
  • the terminal 41 is electrically connected with the semiconductor element
  • the terminal 41 is electrically connected to the first wiring layer 12.
  • a leading end part of one end of the terminal 42 has a connection part 42a.
  • a bent part 42b is formed over from the leading end part of the one end to the other end part.
  • a part from the connection part 42a to the bent part 42b is a connection surface to the first wiring layer 12, and the connection surface is bonded with the first wiring layer 12 via the solder layer 53.
  • the one end of the terminal 42 is fixed above the groove 12x.
  • connection part 42a of the terminal 42 is preferable to be fixed at a position that overlaps with the groove 12x in a plan view. This is because when the connection part 42a of the terminal 42 does not overlap with the groove 12x in a plan view and is located on an outer periphery side of the substrate 10 than the groove 12x, a distance between the superfluous solder and the groove 12x becomes long and it becomes difficult for the superfluous solder to enter into the groove 12x. On the other hand, this is because when the connection part 42a of the terminal 42 does not overlap with the groove 12x in a plan view and is located on a semiconductor element 20 side than the groove 12x, the superfluous solder may outflow from the groove 12x to the semiconductor element 20 side.
  • the other end of the terminal 42 is exposed outside from the sealing resin 30.
  • the terminal 42 is formed by processing a lead frame base material made of, for example, copper (Cu) or the like.
  • the solder layer 53 is formed such that it enters in the groove 12x, extends on the first wiring layer 12 in a direction away from the semiconductor element 20, and further covers a lower surface of the bent part 42b of the terminal 42 (forms a back fillet).
  • the groove 12x is formed like this, when the terminal 42 is soldered to the first wiring layer 12, the superfluous solder enters in the groove 12x even when an amount of melted solder (that becomes the solder layer 53 after curing) is large. Further, a part of the superfluous solder forms a back fillet on the lower surface of the bent part 42b of the termina: 42. Thus, since the superfluous solder does not outftow onto the first wiring layer 12 on the semiconductor element 20 side, the solder layer 53 can be prevented from being connected with the solder layer 51 and the semiconductor element 20. Further, due to the back fillet formed on the lower surface of the bent part 42b of the terminal 42, connection reliability between the terminal 42 and the first wiring layer 12 can be improved.
  • the first wiring layer 12 in which a through hole that becomes the groove 12x is formed in advance may well be brazed to the insulating layer 1 1.
  • a resist in which a portion that becomes the groove 12x is opened is formed on the first wiring layer 12, and by removing the first wiring layer 12 exposed in the resist by etching, the groove 12x may be formed.
  • a first factor is a variance in a bonding area between the terminal 42 side and the first wiring layer 12 side.
  • a second factor is a variance in a bonding thickness between the terminal 42 and the first wiring layer 12 (a thickness of the solder layer 53 between planes of the terminal 42 and the first wiring layer 12 that face with each other).
  • a third factor is a variance in an amount of the solder (that becomes the solder layer 53 after curing).
  • the volume of the groove 12x may be determined such that "the superfluous part of the solder ⁇ a minimum value of the volume of the grove 12x" (a state of FIG. 3 A).
  • a maximum value of the volume of the groove 12x is determined according to a restraint on a dimension or the like, there is no restriction on the maximum value.
  • the bonding area that is the first factor is maximum, the bonding thickness that is the second factor ;s maximum, and the amount of the solder that is the third factor is minimum is considered.
  • a minimum value of the amount of the solder may be determined such that the superfluous solder does not occur (a state shown in FIG. 3B).
  • planar shape of the groove 12x may be a linear shape (I-shape) as shown in FIG. 4, for example.
  • planar shape of the groove 12x may be, for example, a C-shape that opens on an opposite side from the semiconductor element 20 or the like (not shown in the drawing).
  • FIG. 5 is a cross-sectional view that shows a semiconductor device according to a second embodiment.
  • a semiconductor device 1A is different from the semiconductor device 1 in a point that the terminal 42 is substituted with a terminal 43 (see FIG. 1 or the like).
  • FIG. 5 descriptions of the same constituent parts as those of the embodiment described above will be omitted.
  • the terminal 43 is electrically connected to the first wiring layer 12.
  • a leading end part of one end of the terminal 43 has a connection part 43a
  • a bending part 43b is formed over from the leading end part of the one end to the other end part.
  • a part from the connection part 43a (that contains a bent part 43c described below) to the bending part 43b is a connection surface to the first wiring layer 12, and the connection surface is bonded to the first wiring layer 12 via the solder layer 53.
  • the one end of the terminal 43 is fixed above the groove 12x.
  • connection part 43a of the terminal 43 has, at its leading end part, the bent part 43c that bends from a direction substantially parallel with the first wiring layer 12 to a direction substantially vertical to the first wiring layer 12.
  • the bent part 43c is inserted in the groove 12x and a tip surface of the bent part 43c contacts with one surface of the insulating layer 1 1 that is exposed in the groove 12x.
  • the other end of the terminal 43 is exposed outside from the sealing resin 30.
  • the terminal 43 is formed by processing a lead frame base material made of copper (Cu) or the like.
  • the solder layer 53 is formed such that it enters in the groove 12x, extends on the first wiring layer 12 in a direction away from the semiconductor element 20, and further covers a lower surface of the bending part 43 b of the terminal 43 (forms the back fillet).
  • planar shape of the groove 12x may be one shown in FIG. 2, one shown in FIG. 4, or other than those.
  • the second embodiment further exerts the following effect in addition to the effect of the first embodiment. That is, by providing the bent part 43c to the leading part of the connection part 43a of the terminal 43, without using a particular jig, the terminal 43 can be readily positioned with respect to the substrate 10.
  • the thickness of the solder layer 53 is determined by a length L of the bent part 43c. Therefore, accuracy of the thickness of the solder layer 53 can be improved.
  • FIG. 6 is a cross-sectional view that shows a semiconductor device according to a third embodiment.
  • FIG. 7 is a plan view that shows the semiconductor device according to the third embodiment. However, in FIG. 7, only a part of the members shown in FIG. 6 is shown. Further, FIG. 6 shows a cross-section along a VI-VI line of FIG. 7.
  • a semiconductor device I B is different from the semiconductor device 1 in points that the first wiring layer 12 is not provided with the groove 12x and an insulating material 60 is disposed on the first wiring layer 12 (see FIG. 1 and the like).
  • the insulating material 60 is fixed on an upper surface of the first wiring layer 12 by, for example, an insulating adhesive or the like.
  • the insulating material 60 is disposed on the terminal 42 side of the semiconductor element 20.
  • the insulating material 60 is a typical example of the solder outflow prevention part according to the present invention.
  • an insulating resin for example, such as an epoxy resin may be used.
  • the insulating material 60 may be formed by covering a surface of a conductive material such as metal with an insulating film.
  • a planar shape of the insulating material 60 may have a linear shape (I-shape), for example.
  • the U-shape the same as that of FIG. 2, a C-shape (not shown in the drawing) or the like may be used.
  • a distance d between the insulating material 60 and the semiconductor element 20 is being set longer than the thickness t of the solder layer 51.
  • the thickness t of the solder layer 51 is 0.1 mm
  • the distance d between the insulating material 60 and the semiconductor element 20 at least about 0.15 mm is necessary.
  • the distance d may be set to any length.
  • a height of the insulating material 60 is set higher than a value obtained by adding the thickness of the terminal 42 to a height of the solder layer 53.
  • a tip of one end of the terminal 42 contacts with a side surface of the insulating material 60.
  • the insulating material 60 is protruded from the upper surface of the first wiring layer 12, when the terminal 42 is soldered to the first wiring layer 12, the superfluous solder can be stemmed even when an amount of the solder in a molten state (that becomes the solder layer 53 after curing) is large. Further, a part of the superfluous solder forms the back fillet on the lower surface of the bent part 42b of the terminal 42. Thus, since the superfluous solder does not outflow on the first wiring layer 12 on the semiconductor element 20 side, the solder layer 53 can be prevented from being connected with the solder layer 51 and the semiconductor element 20. Further, by the back fillet formed on the lower surface of the bent part 42b of the terminal 42, the connection reliability between the terminal 42 and the first wiring layer 12 can be improved.
  • FIG. 8 is a cross-sectional view that shows a semiconductor device according to a fourth embodiment.
  • FIG. 9 is a plan view that shows the semiconductor device according to the fourth embodiment. However, in FIG. 9, only a part of members shown in FIG. 8 is shown. Further, FIG. 8 shows a cross-section along a VIII-VIII line of FIG. 9.
  • a semiconductor device 1C is different from the semiconductor device 1 in points that the upper surface of the first wiring layer 12 is covered with a surface treatment film 70 and an opening part 70x that exposes the upper surface of the first wiring layer 12 is formed on a part of the surface treatment film 70 (see FIG. 1 and the like).
  • FIG. 8 and FIG. 9 descriptions of the same constituent parts as those of the embodiments described above will be omitted.
  • the first wiring layer 12 is made of a material having a poor solder wetting property such as aluminum (Al) and the upper surface of the first wiring layer 12 is covered with the surface treatment film 70 having an excellent solder wetting property such as nickel (Ni) or gold (Au). Then, by forming the opening part 70x on the terminal 42 side of the semiconductor element 20 of the surface treatment film 70, and the upper surface of the first wiring layer 12 is exposed in the opening part 70x. That is, only a part of the upper surface of the first wiring layer 12 that is exposed in the opening part 70x becomes a non-soldbred region 12y having a poor solder wetting property, and other region becomes a solder region having an excellent solder wetting property.
  • the non-soldered region 12y is a typical example of the solder outflow prevention part according to the present invention.
  • the planar shape of the non-soldered region 12y (opening part 70x) may be, for example, rectangular.
  • the surface treatment film 70 may be divided in two of a region on the terminal 41 side and a region on the terminal 42 side.
  • a distance d between a side on the terminal 42 side of the non-soldered region 12y and the semiconductor element 20 is set longer than the thickness t of the solder layer 51.
  • the thickness t of the solder layer 51 is 0.1 mm
  • the distance d between the side on the terminal 42 side of the non-soldered region 12y and the semiconductor element 20 at least about 0.15 mm is necessary.
  • the distance d may be set to any length.
  • the surface treatment film 70 having the opening part 70x on the upper surface of the first wiring layer 12 is formed, for example, as shown below.
  • the substrate 10 is prepared.
  • the first wiring layer 12 (aluminum or the like) is disposed on one surface of the insulating layer 11 and the second wiring layer 13 is disposed on the other surface.
  • a mask such as a resist film or a masking tape is formed.
  • the surface treatment film 70 such-as nickel (Ni) or gold (Au) is formed, and after that, the mask is removed.
  • the surface treatment film 70 having the opening part 70x on the upper surface of the first wiring layer 12 is formed, and an inside of the opening part 70x becomes the non-soldered region 12y.
  • the non-soldered region 12y is formed like this, when the terminal 42 is soldered to the first wiring layer 12, the superfluous solder neither wets the non-soldered region 12y nor expands thereto and becomes the back fillet on the lower surface of the. bent part 42b of the terminal 42 even when an amount of the solder in a molten state (that becomes the solder layer 53 after curing) is large.
  • the solder layer 53 can be prevented from being connected with the solder layer 51 and the semiconductor element 20.
  • the connection reliability between the terminal 42 and the first wiring layer 12 can be improved.
  • FIG. 10 is a cross-sectional view that shows a semiconductor device according to a fifth embodiment.
  • FIG. 1 1 is a plan view that shows the semiconductor device according to the fifth embodiment. However, in FIG. 1 1 , only a part of the members shown in FIG. 10 is shown. Further, FIG. 10 shows a cross-section along a X-X line of FIG. 1 1.
  • a semiconductor device I D is different from the semiconductor device 1 in a point that the groove 12x is substituted with
  • the grooves 12z that do not penetrate through the first wiring layer 12 are formed.
  • the grooves 12z are formed on the terminal 42 side of the semiconductor element 20.
  • the grooves 12z are a typical example of the solder outflow prevention part according to the present invention.
  • the planar shape of the groove 12z can be set to a case shape (frame shape).
  • Distances d between the grooves 12z and the semiconductor element 20 are set longer than the thickness t of the solder layer 51. For example, when the thickness t of the solder layer 51 is 0.1 mm, in order to prevent the electrical continuity between the semiconductor element 20 and the terminal 42, as the distances d between the grooves 12z and the semiconductor element 20, at least about 0.15 mm is necessary.
  • the distance d may be set to any length.
  • the adjustment between the amount of the solder (that becomes the solder layer 53 after curing) and a volume of the groove 12z is the same as the case of the groove 12x described in the first embodiment.
  • the solder wetting property is excellent in the inside of the grooves 12z. That is, when the first wiring layer 12 is made of a material having excellent solder wetting property such as copper (Cu), the material having the excellent solder wetting property such as copper (Cu) is exposed also in the grooves 12z. Further, when the first wiring layer 12 is made of a material having poor solder wetting property such as aluminum (Al), a surface treatment film having excellent solder wetting property is formed after the grooves 12z are formed. Thus, the surface treatment film having excellent solder wetting property is exposed also in the grooves 12z.
  • a material having excellent solder wetting property such as copper (Cu)
  • Al aluminum
  • the grooves 12z may be formed in the first wiring layer 12, for example, as shown below.
  • the substrate 10 is prepared.
  • the first wiring layer 12 is disposed on one surface of the insulating layer 1 1 and the second wiring layer 13 is disposed on the other surface.
  • the first wiring layer 12 is molded by pressing with a metal mold having projection parts corresponding to shapes of the grooves 12z (at this time, the grooves 12z are controlled so as not to penetrate through the first wiring layer 12).
  • the grooves 12z are formed in the first wiring layer 12.
  • the surface treatment film such as nickel (Ni) or gold (Au) is formed, for example, by plating.
  • the fifth embodiment further exerts the following effect in addition to the effect of the first embodiment. That is, since the inside of the groove 12z is in a state of excellent solder wetting property, when the terminal 42 is soldered to the first wiring layer 12, due to a capillary phenomenon, the solder in a molten state actively enters into the grooves 12z, and the superfluous solder can be readily absorbed.
  • the planar shape of the grooves 12z may not be the case shape (frame shape), may be a shape shown in FIG. 2 or a shape shown in FIG. 4, or may be other than those. In essence, as long as the inside of the groove 12z has an excellent solder wetting property, due to the capillary phenomenon, effects specific to the present embodiment can be obtained.
  • FIG. 12 is a cross-sectional iew that shows a semiconductor device according to a sixth embodiment.
  • a semiconductor device I E is different from the semiconductor device 1 in points that a metal block 80 is disposed on the semiconductor element 20 via the solder layer 52, and the metal block 80 is fixed to the substrate 10A via a solder layer 54 (see FIG. 1 and the like).
  • the substrate 1 OA is imparted with a different mark for convenience sake, it is a substrate having the same structure as the substrate 10.
  • FIG. 12 descriptions of constituent parts the same as those of the embodiments described above will be omitted.
  • Heat generated by the semiconductor element 20 is radiated via the substrates 10 and 10A.
  • the heat radiation property may be further improved.
  • the semiconductor device IE since the heat generated by the semiconductor element 20 is radiated from both surface sides (upper surface side and lower surface side), the semiconductor device IE can be called a double-sided cooling module.
  • the grooves 12z that do not penetrate through the first wiring layer 12 are formed. Since the grooves 12z of the substrate 10A absorb the superfluous solder due to the capillary phenomenon, the solder layer 54 that fixes the metal block 80 to the substrate 10A does not outflow outside the grooves 12z.
  • the grooves 12z may be applied to parts other than the terminal. The situation is the same also in the solder outflow prevention parts shown in the other embodiments such as the groove 12x.
  • the respective embodiments can be properly combined.
  • the insulating material 60 may be disposed on the semiconductor element 20 side of the groove 12x.
  • the superfluous solder can be more surely prevented from outflowing on the first wiring layer 12 on the semiconductor element 20 side.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Cette invention concerne un dispositif à semi-conducteur (1) comprenant un substrat (10), un élément semi-conducteur (20), une borne (42) et une partie de prévention d'écoulement de brasure (12x). Ledit élément semi-conducteur est fixé sur un premier côté du substrat par l'intermédiaire d'une première couche de brasure (51). Ladite borne est fixée sur ledit premier côté du substrat par l'intermédiaire d'une seconde couche de brasure (53). Ladite partie de prévention d'écoulement de brasure est formée entre l'élément semi-conducteur et la borne dans le premier côté du substrat et elle est conçue pour empêcher l'écoulement de la première couche de brasure et de la seconde couche de brasure. Une distance séparant la partie d'écoulement de brasure et l'élément semi-conducteur est supérieure à une épaisseur de la première couche de brasure.
PCT/IB2014/002403 2013-11-26 2014-11-11 Dispositif à semi-conducteur WO2015079294A2 (fr)

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US15/036,089 US9953905B2 (en) 2013-11-26 2014-11-11 Semiconductor device
KR1020167013533A KR101812908B1 (ko) 2013-11-26 2014-11-11 반도체 장치
DE112014005420.8T DE112014005420B4 (de) 2013-11-26 2014-11-11 Halbleitervorrichtung
CN201480064023.7A CN105917463B (zh) 2013-11-26 2014-11-11 半导体装置
US15/590,572 US9824961B2 (en) 2013-11-26 2017-05-09 Semiconductor device

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JP2013244325A JP6086055B2 (ja) 2013-11-26 2013-11-26 半導体装置

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DE112014005420B4 (de) 2021-02-11
CN105917463A (zh) 2016-08-31
WO2015079294A8 (fr) 2016-06-16
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US9824961B2 (en) 2017-11-21
TW201526168A (zh) 2015-07-01
US20160293561A1 (en) 2016-10-06
KR20160075649A (ko) 2016-06-29
WO2015079294A3 (fr) 2015-07-23
JP6086055B2 (ja) 2017-03-01
US9953905B2 (en) 2018-04-24
DE112014005420T5 (de) 2016-08-25
US20170243812A1 (en) 2017-08-24
CN105917463B (zh) 2018-09-14
JP2015103713A (ja) 2015-06-04
TWI543306B (zh) 2016-07-21

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