WO2011131130A1 - 移位寄存器、液晶显示器栅极驱动装置和数据线驱动装置 - Google Patents

移位寄存器、液晶显示器栅极驱动装置和数据线驱动装置 Download PDF

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Publication number
WO2011131130A1
WO2011131130A1 PCT/CN2011/073079 CN2011073079W WO2011131130A1 WO 2011131130 A1 WO2011131130 A1 WO 2011131130A1 CN 2011073079 W CN2011073079 W CN 2011073079W WO 2011131130 A1 WO2011131130 A1 WO 2011131130A1
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Prior art keywords
thin film
film transistor
signal
shift register
driving
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PCT/CN2011/073079
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English (en)
French (fr)
Inventor
韩承佑
商广良
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北京京东方光电科技有限公司
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Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Priority to KR1020117030591A priority Critical patent/KR101365233B1/ko
Priority to JP2013505323A priority patent/JP6114183B2/ja
Priority to EP11771583.9A priority patent/EP2562761B1/en
Priority to US13/380,994 priority patent/US8736537B2/en
Publication of WO2011131130A1 publication Critical patent/WO2011131130A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to a shift register, a liquid crystal display gate driving device, and a data line driving device. Background technique
  • a prior art shift register unit includes a signal output for outputting a drive signal.
  • the shift register unit controls a row of thin film transistors to be turned on; when the driving signal is low, the shift register unit controls a row of thin film transistors to be turned off.
  • the liquid crystal display usually adopts a progressive scan mode.
  • the corresponding shift register unit When scanning a certain row or a column, the corresponding shift register unit outputs a high level driving signal, and the remaining shift registers output a low level driving signal, which is visible.
  • the drive signal For a shift register unit, the drive signal is low for most of the time.
  • the shift register unit typically includes a reduced signal thin film transistor for pulling the drive signal low during the drive signal being low.
  • the junction control coupled to the gate of the reduced signal thin film transistor reduces the conduction of the signal thin film transistor, thereby enabling the level of the gate drive signal at the signal output to be pulled low.
  • a problem with the prior art shift register unit is that the node that is normally connected to the gate of the reduced signal thin film transistor remains at a high level for most of the time, so that the signal thin film transistor remains turned on most of the time, thereby reducing the signal.
  • the threshold voltage of the thin film transistor produces a large offset. If the threshold voltage of the reduced signal thin film transistor is continuously increased, the signal thin film transistor cannot be turned on, thereby suppressing the noise and affecting the performance of the entire shift register.
  • Embodiments of the present invention provide a shift register, including: at least two shift register units, wherein one shift register unit includes:
  • Raising the signal thin film transistor which receives the first clock signal and inputs to the output terminal in an on state Output a high voltage signal
  • Elevating driving the first thin film transistor which receives the frame start signal or the output signal of the other shift register unit turns on the boost signal thin film transistor;
  • the first thin film transistor receives a reset signal or an output signal of another shift register, and outputs a low voltage signal to the output terminal in an on state;
  • Decreasing a signal third thin film transistor which receives an output signal that reduces driving of the first thin film transistor, and reduces an output signal of the output terminal in an on state;
  • the boost signal thin film transistor of the other shift register unit, the lower driving first thin film transistor, and the lower driving second thin film transistor respectively receive the fourth clock signal, the fifth clock signal, and the sixth clock signal.
  • Figure la is a schematic structural diagram of a shift register unit of the present invention
  • Figure lb is a timing diagram of input and output of the shift register unit shown in Figure 1;
  • 2a is a schematic structural diagram of another shift register unit of the present invention.
  • Figure 2b is a timing diagram showing the input and output of another shift register unit shown in Figure 3. detailed description
  • Embodiments of the present invention disclose a shift register that includes at least two shift register units.
  • At least one shift register unit of the shift register of the embodiment of the present invention includes: a boost signal thin film transistor T3 that receives the first clock signal CLK and outputs a high voltage signal to the output terminal in an on state. Raising the driving of the first thin film transistor T1, which receives the frame start signal or the output signal of the last shift register unit turns on the boost signal thin film transistor T3; boosts the driving of the second thin film transistor T2, which receives the next shift The output signal of the register is turned on to raise the signal thin film transistor T3; the signal lowering the first thin film transistor T4, which receives the output signal of the next shift register, outputs a low voltage signal to the output terminal in the on state; lowers the driving of the first film
  • the transistor ⁇ 5 receives the second clock signal CLKB1 to turn on the lowering signal second thin film transistor T10 and the lowering signal third thin film transistor T11; lowers driving the second thin film transistor T5-1, and receives the third clock signal CLKB2 to turn on the lowering signal
  • the boost signal thin film transistor t3 of another shift register unit of the shift register according to the embodiment of the present invention, the driving of the first thin film transistor t5, and the driving of the second thin film transistor t5-l are respectively received.
  • the second clock signal and the third clock signal received by the shift register unit provided by the embodiment of the present invention are clock output clock signals separated by a frame.
  • the fifth clock signal and the sixth clock signal received by the shift register unit provided by the embodiment of the present invention are clock output clock signals separated by a frame.
  • the drain and the source are interchangeable, so the source of the thin film transistor mentioned in the embodiment of the present invention may be the drain of the thin film transistor.
  • the drain of the thin film transistor can also be the source of the thin film transistor.
  • the input signal (INPUT) signal is the frame start signal (STV) is high, and the first film is driven up.
  • the transistor T1 is turned on, the voltage of the PU node is raised; the driving of the first thin film transistor T6 is turned off, and the driving of the second thin film transistor T6-1 is turned off, so that the voltage of the PD1 and PD2 nodes is low, thereby lowering the signal of the second thin film transistor T10.
  • the signal of the third thin film transistor Til is turned off; the auxiliary thin film transistors T8 and T8-1 are turned on, the release lowers the driving of the first thin film transistor ⁇ 5, and the lowering of the driving of the second thin film transistor T5-1; the rising signal thin film transistor ⁇ 3 is turned on.
  • the first clock signal CLK is at a high level, so the signal output terminal (OUT) output signal (OUTPUT) is at a high level, and the reset signal input terminal (RESETIN) input signal (RESET) is at a low level, and the driving is increased.
  • the second thin film transistor T2, the lowering signal, the first thin film transistor ⁇ 4 is turned off.
  • the input signal (INPUT) signal is low, the driving of the first thin film transistor T1 is turned off; the reset signal (RESET) is high level, the driving of the second thin film transistor T2 is raised, and the first film of the signal is lowered.
  • the transistor ⁇ 4 is turned on, the PU node discharges the charge, and becomes a low level, and the signal output terminal (OUT) output signal (OUTPUT) becomes a low level under the pull-down effect of the lowering of the first thin film transistor T4;
  • the second clock signal (CLKB1) is high level, lowering driving of the first thin film transistor T5 to be turned on, the PD1 node is raised, causing the lowering of the second thin film transistor T10, the lowering signal, the third thin film transistor T11 to be turned on, and the signal output end (OUT) output signal (OUTPUT) becomes a low level under the pull-down effect of the lowering signal second thin film transistor T10 and the lowering signal third thin film transistor T11, thereby lowering the duty ratio of the driving thin film transistor than the conventionally reducing the duty ratio of the driving thin film transistor , can effectively prevent the deviation of the driving thin film transistor. That is, the signal lowering the first thin film transistor ⁇ 4, lowering the signal, the second thin film transistor ⁇ 10
  • the input signal (INPUT) signal is the frame start signal (STV) is high, and the first film is driven up.
  • the transistor T1 is turned on, the voltage of the PU node is raised; the driving of the first thin film transistor T6 is turned off, and the driving of the second thin film transistor T6-1 is turned off, so that the voltage of the PD1 and PD2 nodes is low, thereby lowering the signal of the second thin film transistor T10.
  • the third thin film transistor Til is turned off; the auxiliary thin film transistors T8 and T8-1 are turned on, releasing the charge of driving the first thin film transistor T5 and the low driving second thin film transistor T5-1; and raising the signal thin film transistor T3 to turn on
  • the first clock signal CLK is at a high level, so the signal output terminal (OUT) output signal (OUTPUT) is at a high level, and the reset signal input terminal (RESETIN) input signal (RESET) is at a low level, and the driving is increased.
  • the second thin film transistor T2, the lowering signal, the first thin film transistor ⁇ 4 is turned off.
  • the input signal (INPUT) signal is low, the driving of the first thin film transistor T1 is turned off; the reset signal (RESET) is high level, the driving of the second thin film transistor T2 is raised, and the first film of the signal is lowered.
  • the transistor ⁇ 4 is turned on, the PU node discharges the charge, and becomes a low level, and the signal output terminal (OUT) output signal (OUTPUT) becomes a low level under the pull-down effect of the lowering of the first thin film transistor T4;
  • the third clock signal (CLKB1) is at a high level, lowering driving of the second thin film transistor T5-1 to be turned on, the PD2 node is raised, causing the lowering of the fourth thin film transistor T10-1, the lowering signal, the fifth thin film transistor T11-1 to be turned on, and the signal output
  • the output signal (OUTPUT) of the terminal (OUTPUT) becomes a low level under the pull-down effect of the fourth thin film transistor T10-1 for lowering the signal and the fifth thin film transistor T11-1 for lowering the signal, thereby lowering the duty ratio of the driving thin film transistor
  • the first thin film transistor ⁇ 8 and the auxiliary second thin film transistor T8-1 are respectively assisted in the operation of the shift register, respectively receiving an output signal for driving up the first thin film transistor T1, and releasing the lower driving first film in the on state.
  • the transistor ⁇ 5 and the charge for driving the second thin film transistor T5-1 are lowered;
  • the auxiliary third thin film transistor ⁇ 7, the auxiliary fourth thin film transistor ⁇ 9 and the auxiliary fifth thin film transistor T9-1 receive the first clock signal CLK and the second clock signal, respectively.
  • CLKB1 and the third clock signal CLKB2 in the on state, reduce the rising signal thin film transistor T3, and lower the driving of the first film
  • the transistor T5 and the biasing effect of driving the second thin film transistor T5-1 are lowered.
  • the gate of ⁇ 3 is connected to the signal output terminal (OUT).
  • the level of the signal at the PU node can rise to a higher level due to the coupling of the first capacitor C1.
  • FIG. 2a is a schematic structural diagram of another shift register unit according to an embodiment of the present invention.
  • FIG. 2b is a timing chart of input and output of another shift register unit shown in FIG. 3.
  • the embodiment of the invention further provides a gate driving device and a data line driving device (not shown) of the liquid crystal display including the shift register, and the gate driving device and the data line driving device can be disposed on the display of the liquid crystal display On the panel.
  • the shift register provided by the embodiment of the invention reduces the duty ratio of the driving thin film transistor, effectively prevents the deviation of the driving thin film transistor, thereby ensuring the testability of the shift register unit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Description

移位寄存器、 液晶显示器栅极驱动装置和数据线驱动装置 技术领域
本发明涉及一种移位寄存器、 液晶显示器栅极驱动装置和数据线驱动装 置。 背景技术
现有技术中的移位寄存器单元， 包括用于输出驱动信号的信号输出端。 驱动信号为高电平时， 移位寄存器单元控制一行薄膜晶体管导通； 驱动信号 为低电平时， 移位寄存器单元控制一行薄膜晶体管截止。
液晶显示器通常采用逐行扫描的方式， 当扫描到某一行或某一列时， 相 应的移位寄存器单元输出高电平的驱动信号， 其余的移位寄存器输出低电平 的驱动信号， 可见， 对于一个移位寄存器单元来说， 大部分时间驱动信号为 低电平。
在驱动信号为低电平期间， 驱动信号很容易受到输入的时钟信号的千扰 而产生噪声。 为了抑制噪声， 移位寄存器单元通常包括用于在驱动信号为低 电平期间将驱动信号拉低的降低信号薄膜晶体管。 与降低信号薄膜晶体管的 栅极连接的结点控制降低信号薄膜晶体管导通， 从而能够拉低信号输出端的 栅极驱动信号的电平。
现有技术中的移位寄存器单元存在的问题是： 通常与降低信号薄膜晶体 管的栅极连接的节点大部分时间保持高电平， 这样大部分时间降低信号薄膜 晶体管保持导通， 从而使得降低信号薄膜晶体管的阈值电压产生较大偏移。 如果降低信号薄膜晶体管的阈值电压不断升高， 会导致降低信号薄膜晶体管 无法导通， 从而无法起到抑制噪声的作用， 影响整个移位寄存器的性能。 发明内容
本发明的实施例提供一种移位寄存器， 包括： 至少两个移位寄存器单元， 其中一个移位寄存器单元包括：
升高信号薄膜晶体管， 其接收第一时钟信号， 在导通状态下向输出端输 出高电压信号；
升高驱动第一薄膜晶体管， 其接收帧起始信号或者另一个移位寄存器单 元的输出信号导通升高信号薄膜晶体管；
升高驱动第二薄膜晶体管， 其接收复位信号或者另一个移位寄存器的输 出信号导通升高信号薄膜晶体管；
降低信号第一薄膜晶体管， 其接收复位信号或者另一个移位寄存器的输 出信号， 在导通状态下向输出端输出低电压信号；
降低驱动第一薄膜晶体管， 其接收第二时钟信号导通降低信号薄膜晶体 管；
降低驱动第二薄膜晶体管， 其接收第三时钟信号导通降低信号薄膜晶体 管；
降低信号第二薄膜晶体管 ,其接收降低驱动第一薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
降低信号第三薄膜晶体管，其接收降低驱动第一薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
关闭驱动第一薄膜晶体管，其接收升高驱动第一薄膜晶体管的输出信号， 在导通状态下截止降低信号第二薄膜晶体管和降低信号第三薄膜晶体管； 降低信号第四薄膜晶体管，其接收降低驱动第二薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
降低信号第五薄膜晶体管，其接收降低驱动第二薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
关闭驱动第二薄膜晶体管，在接收升高驱动第一薄膜晶体管的输出信号， 在导通状态下截止降低信号第四薄膜晶体管和降低信号第五薄膜晶体管， 并且与上述移位寄存器单元相邻的另一个移位寄存器单元的升高信号薄 膜晶体管、 降低驱动第一薄膜晶体管、 降低驱动第二薄膜晶体管分别接收第 四时钟信号、 第五时钟信号、 第六时钟信号。
下面通过具体实施例并结合附图对本发明故进一步的详细描述。 附图说明
图 la所示为本发明移位寄存器单元结构示意图; 图 lb所示为图 1所示的移位寄存器单元的输入输出时序图；
图 2a所示为本发明另一移位寄存器单元结构示意图；
图 2b所示为图 3所示的另一移位寄存器单元的输入输出时序图。 具体实施方式
本发明的实施例公开了一种移位寄存器， 该移位寄存器包括至少两个移 位寄存器单元。
如图 la所示，本发明实施例的移位寄存器的至少一个移位寄存器单元包 括： 升高信号薄膜晶体管 T3 , 其接收第一时钟信号 CLK, 在导通状态下向 输出端输出高电压信号； 升高驱动第一薄膜晶体管 T1 , 其接收帧起始信号或 者上一个移位寄存器单元的输出信号导通升高信号薄膜晶体管 T3;升高驱动 第二薄膜晶体管 T2,其接收下一个移位寄存器的输出信号导通升高信号薄膜 晶体管 T3; 降低信号第一薄膜晶体管 T4， 其接收下一个移位寄存器的输出 信号，在导通状态下向输出端输出低电压信号；降低驱动第一薄膜晶体管 Τ5, 其接收第二时钟信号 CLKB1导通降低信号第二薄膜晶体管 T10和降低信号 第三薄膜晶体管 T11 ; 降低驱动第二薄膜晶体管 T5-1 , 其接收第三时钟信号 CLKB2 导通降低信号第四薄膜晶体管 T10-1 和降低信号第五薄膜晶体管 T11-1 ; 降低信号第二薄膜晶体管 T10, 其接收降低驱动第一薄膜晶体管 Τ5 的输出信号， 在导通状态下降低输出端的输出信号； 降低信号第三薄膜晶体 管 T11 ,其接收降低驱动第一薄膜晶体管 Τ5的输出信号，在导通状态下降低 输出端的输出信号； 降低信号第四薄膜晶体管 T10-1,其接收降低驱动第二薄 膜晶体管 T5-1的输出信号，在导通状态下降低输出端得输出信号； 关闭驱动 第一薄膜晶体管 Τ6， 其接收升高驱动第一薄膜晶体管 T1的输出信号， 在导 通状态下截止降低信号第二薄膜晶体管 T10 和降低信号第三薄膜晶体管 T11 ; 关闭驱动第二薄膜晶体管 T6-l， 在接收升高驱动第一薄膜晶体管 T1 的输出信号， 在导通状态下截止降低信号第四薄膜晶体管 T10-1和降低信号 第五薄膜晶体管 Tl l-1。
如图 2a所示，本发明实施例的移位寄存器的另一移位寄存器单元的升高 信号薄膜晶体管 t3、 降低驱动第一薄膜晶体管 t5、 降低驱动第二薄膜晶体管 t5-l 分别接收第四时钟信号 CLKB、 第五时钟信号 CLK1、 第六时钟信号 CLK2. 本发明实施例的提供的移位寄存器单元接收的第二时钟信号、 第三时钟 信号是隔一帧轮流输出时钟信号。
本发明实施例提供的移位寄存器单元接收的第五时钟信号、 第六时钟信 号是隔一帧轮流输出时钟信号。
需要说明的是， 对于液晶显示领域的所使用的薄膜晶体管来说， 漏极和 源极可以互换， 所以本发明实施例中所提到的薄膜晶体管的源极可以为薄膜 晶体管的漏极， 薄膜晶体管的漏极也可以为薄膜晶体管的源极。
下面结合图 la和图 lb, 来说明本发明实施例的移位寄存器单元的工作 原理。
选择图 lb所示时序图的第一帧一部分并选择其中前 2个阶段，在第一阶 段， 输入信号 (INPUT)信号为帧起始信号 （STV )是高电平， 升高驱动第一 薄膜晶体管 T1导通， PU节点电压升高； 关闭驱动第一薄膜晶体管 T6、 关 闭驱动第二薄膜晶体管 T6-1导通， 使 PD1、 PD2节点电压为低电平， 因此 降低信号第二薄膜晶体管 T10、 降低信号第三薄膜晶体管 Til截止； 辅助薄 膜晶体管 T8、 T8-1导通， 释放降低驱动第一薄膜晶体管 Τ5、 降低驱动第二 薄膜晶体管 T5-1的电荷； 升高信号薄膜晶体管 Τ3导通， 此时第一时钟信号 CLK为高电平， 因此信号输出端 （OUT )输出信号 （OUTPUT ) 为高电平， 复位信号输入端 （RESETIN )输入信号（RESET )为低电平， 升高驱动第二 薄膜晶体管 T2、 降低信号第一薄膜晶体管 Τ4截止。
在第二阶段， 输入信号 (INPUT)信号为低电平， 升高驱动第一薄膜晶体 管 T1截止； 复位信号 （RESET ) 为高电平， 升高驱动第二薄膜晶体管 T2、 降低信号第一薄膜晶体管 Τ4导通， PU节点释放电荷， 变为低电平， 信号输 出端 （OUT )输出信号 （OUTPUT )在降低信号第一薄膜晶体管 T4 的拉低 作用下变为低电平； 第二时钟信号（CLKB1 )为高电平， 降低驱动第一薄膜 晶体管 T5导通， PD1节点升高， 使降低信号第二薄膜晶体管 T10、 降低信 号第三薄膜晶体管 T11导通， 信号输出端 （OUT )输出信号 （OUTPUT )在 降低信号第二薄膜晶体管 T10、 降低信号第三薄膜晶体管 T11的拉低作用下 变为低电平， 因此降低驱动薄膜晶体管的占空比比现有降低驱动薄膜晶体管 的占空比降低， 能有效防止降低驱动薄膜晶体管的偏执作用。 即使得降低信 号第一薄膜晶体管 Τ4、 降低信号第二薄膜晶体管 Τ10、 降低信号第三薄膜晶 体管 Ti l能够起到抑制噪声的作用， 保证移位寄存器单元的可靠性。
选择图 lb所示时序图的第二帧一部分并选择其中前 2个阶段，在第一阶 段， 输入信号 (INPUT)信号为帧起始信号 （STV )是高电平， 升高驱动第一 薄膜晶体管 T1导通， PU节点电压升高； 关闭驱动第一薄膜晶体管 T6、 关 闭驱动第二薄膜晶体管 T6-1导通， 使 PD1、 PD2节点电压为低电平， 因此 降低信号第二薄膜晶体管 T10、 降低信号第三薄膜晶体管 Til截止； 辅助薄 膜晶体管 T8、 T8-1导通， 释放降低驱动第一薄膜晶体管 T5、 低驱动第二 薄膜晶体管 T5-1的电荷； 升高信号薄膜晶体管 T3导通， 此时第一时钟信号 CLK为高电平， 因此信号输出端 （OUT )输出信号 （OUTPUT ) 为高电平， 复位信号输入端 （RESETIN )输入信号（RESET )为低电平， 升高驱动第二 薄膜晶体管 T2、 降低信号第一薄膜晶体管 Τ4截止。
在第二阶段， 输入信号 (INPUT)信号为低电平， 升高驱动第一薄膜晶体 管 T1截止； 复位信号 （RESET ) 为高电平， 升高驱动第二薄膜晶体管 T2、 降低信号第一薄膜晶体管 Τ4导通， PU节点释放电荷， 变为低电平， 信号输 出端 （OUT )输出信号 （OUTPUT )在降低信号第一薄膜晶体管 T4 的拉低 作用下变为低电平； 第三时钟信号（CLKB1 )为高电平， 降低驱动第二薄膜 晶体管 T5-1导通， PD2节点升高， 使降低信号第四薄膜晶体管 T10-l、 降低 信号第五薄膜晶体管 T11-1导通， 信号输出端（OUT )输出信号（OUTPUT ) 在降低信号第四薄膜晶体管 T10-l、 降低信号第五薄膜晶体管 T11-1 的拉低 作用下变为低电平， 因此降低驱动薄膜晶体管的占空比比现有降低驱动薄膜 晶体管的占空比降低， 能有效防止降低驱动薄膜晶体管的偏执作用。 即使得 降低信号第一薄膜晶体管 Τ4、 降低信号第四薄膜晶体管 T10-l、 降低信号第 五薄膜晶体管 T11-1能够起到抑制噪声的作用， 保证移位寄存器单元的可靠 性。
在上述移位寄存器的工作过程中辅助第一薄膜晶体管 Τ8和辅助第二薄 膜晶体管 T8-1 , 分别接收升高驱动第一薄膜晶体管 T1的输出信号， 在导通 状态下释放降低驱动第一薄膜晶体管 Τ5和降低驱动第二薄膜晶体管 T5-1的 电荷;辅助第三薄膜晶体管 Τ7、辅助第四薄膜晶体管 Τ9和辅助第五薄膜晶体 管 T9-1 , 分别接收第一时钟信号 CLK、 第二时钟信号 CLKB1和第三时钟信 号 CLKB2, 在导通状态下减少升高信号薄膜晶体管 T3、 降低驱动第一薄膜 晶体管 T5和降低驱动第二薄膜晶体管 T5-1的偏执作用。
在上述移位寄存器单元中的电容 C1 的两端分别与升高信号薄膜晶体管
Τ3的栅极和信号输出端 （OUT )连接， 在移位寄存器单元工作时， PU结点 处的信号的电平， 由于第一电容 C1的耦合作用， 可以升到较高的高电平。
图 2a所示为本发明实施例的另一移位寄存器单元结构示意图； 图 2b所示为图 3所示的另一移位寄存器单元的输入输出时序图。
如图 2a、2b所示的另一移位寄存器的工作原理与上述移位寄存器的工作 原理类似， 此处不再赘述。
本发明实施例还提供了一种包括上述移位寄存器的液晶显示器的栅驱动 装置及数据线驱动装置 （此部分未画出） ， 该栅驱动装置及数据线驱动装置 可设置在液晶显示器的显示面板上。
本发明实施例提供的移位寄存器是降低驱动薄膜晶体管的占空比， 有效 防止降低驱动薄膜晶体管的偏执作用， 从而保证移位寄存器单元的可考性。
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其 限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术 人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或 者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种移位寄存器， 包括至少两个移位寄存器单元， 并且其中一个移位 寄存器单元包括：
升高信号薄膜晶体管， 其接收第一时钟信号， 在导通状态下向输出端输 出高电压信号；
升高驱动第一薄膜晶体管， 其接收帧起始信号或者另一个移位寄存器单 元的输出信号导通升高信号薄膜晶体管；
升高驱动第二薄膜晶体管， 其接收复位信号或者另一个移位寄存器的输 出信号导通升高信号薄膜晶体管；
降低信号第一薄膜晶体管， 其接收复位信号或者另一个移位寄存器的输 出信号， 在导通状态下向输出端输出低电压信号；
降低驱动第一薄膜晶体管， 其接收第二时钟信号导通降低信号薄膜晶体 管；
降低驱动第二薄膜晶体管， 其接收第三时钟信号导通降低信号薄膜晶体 管；
降低信号第二薄膜晶体管，其接收降低驱动第一薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
降低信号第三薄膜晶体管，其接收降低驱动第一薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
关闭驱动第一薄膜晶体管，其接收升高驱动第一薄膜晶体管的输出信号， 在导通状态下截止降低信号第二薄膜晶体管和降低信号第三薄膜晶体管； 降低信号第四薄膜晶体管，其接收降低驱动第二薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
降低信号第五薄膜晶体管，其接收降低驱动第二薄膜晶体管的输出信号， 在导通状态下降低输出端的输出信号；
关闭驱动第二薄膜晶体管，在接收升高驱动第一薄膜晶体管的输出信号， 在导通状态下截止降低信号第四薄膜晶体管和降低信号第五薄膜晶体管， 并且与所述移位寄存器单元相邻的另一个移位寄存器单元的升高信号薄 膜晶体管、 降低驱动第一薄膜晶体管、 降低驱动第二薄膜晶体管分别接收第 四时钟信号、 第五时钟信号、 第六时钟信号。
2、根据权利要求 1所述的移位寄存器， 其中， 所述移位寄存器单元还包 括辅助第一薄膜晶体管和辅助第二薄膜晶体管， 分别接收升高驱动第一薄膜 晶体管的输出信号， 在导通状态下释放降低驱动第一薄膜晶体管和降低驱动 第二薄膜晶体管的电荷。
3、根据权利要求 1所述的移位寄存器， 其中， 所述移位寄存器单元还包 括辅助第三薄膜晶体管、 辅助第四薄膜晶体管和辅助第五薄膜晶体管， 分别 接收第一时钟信号、 第二时钟信号和第三时钟信号， 在导通状态下减少升高 信号薄膜晶体管、 降低驱动第一薄膜晶体管和降低驱动第二薄膜晶体管的偏 执作用。
4、根据权利要求 1所述的移位寄存器， 其中， 所述移位寄存器单元还包 括一电容，其两端分别与所述升高驱动第一薄膜晶体管的漏极和输出端连接。
5、根据权利要求 1所述的移位寄存器， 其中， 所述移位寄存器单元接收 的第二时钟信号、 第三时钟信号是隔一帧轮流输出时钟信号。
6、根据权利要求 1所述的移位寄存器， 其中， 所述移位寄存器单元接收 的第五时钟信号、 第六时钟信号是隔一帧轮流输出时钟信号。
7、 包括根据权利要求 1所述的移位寄存器的液晶显示器栅极驱动装置。
8、 包括根据权利要求 1 所述的移位寄存器的液晶显示器数据线驱动装 置。
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