WO2008095405A1 - Élément microélectronique et procédé de fabrication correspondant - Google Patents

Élément microélectronique et procédé de fabrication correspondant Download PDF

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Publication number
WO2008095405A1
WO2008095405A1 PCT/CN2008/000226 CN2008000226W WO2008095405A1 WO 2008095405 A1 WO2008095405 A1 WO 2008095405A1 CN 2008000226 W CN2008000226 W CN 2008000226W WO 2008095405 A1 WO2008095405 A1 WO 2008095405A1
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WIPO (PCT)
Prior art keywords
conductive layer
conductive
metal
layer
bump
Prior art date
Application number
PCT/CN2008/000226
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English (en)
French (fr)
Inventor
Lei Jia
Zhiping Wang
Han Ding
Zhenhua Xiong
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Shanghai Jiaotong University
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Application filed by Shanghai Jiaotong University filed Critical Shanghai Jiaotong University
Publication of WO2008095405A1 publication Critical patent/WO2008095405A1/zh

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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1345—Conductors connecting electrodes to cell terminals
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Definitions

  • the present invention relates to the field of microelectronics, and in particular to a microelectronic component, including a package structure of the microelectronic component, a liquid crystal display device, and a method of fabricating the microelectronic component. Background technique
  • FC flip chip
  • ACF anisotropic conductive film
  • the widely used ACF manufacturing processes mainly include: a manufacturing method (COG, ie, chip on glass) for directly mounting a driver chip on a glass substrate with a circuit; and packaging the driver chip in a flexible circuit
  • COB, ie, chip on board) for packaging a driver chip on a general printed circuit board.
  • COG technology and COF technology are two key technologies for manufacturing liquid crystal display devices.
  • a glass substrate, a flexible circuit board, a printed circuit board, or other circuit board member in the above manufacturing method is represented by a circuit board, and the circuit board includes a substrate, and a circuit is formed on a surface or an inside thereof, and a connection terminal formed on the surface of the substrate (pad), the connection terminal is electrically connected to a circuit on the substrate;
  • the driver chip is composed of a semiconductor chip having an integrated circuit therein and a conductive bump formed on the surface of the semiconductor chip with a certain thickness.
  • the ACF is placed between the driver chip and the circuit board, and the conductive bumps on the driver chip and the corresponding connection terminals on the substrate are aligned with each other.
  • the driving chip and the circuit board with the substrate are heated and pressurized, and the polymer in the ACF is cured by heat, and the driving chip and the circuit board are bonded and fixed together, and at the same time, the polymer is partially dispersed in the polymer polymerization. Conductive particles in the object are captured in the phase
  • the conductive particles are trapped between the conductive bumps and the connecting terminals through the conductive metal material wrapped around the surface. Electrical connection.
  • the inner core of the conductive particles that is, the resin particles have a certain elasticity, and thus a certain elastic deformation occurs when being pressed, and when the distance between the conductive bump and the connection terminal is changed by the external environmental change, this The elastic deformation can maintain a reliable electrical connection between the conductive bumps and the connection terminals through the conductive particles. It can be seen that the flip chip connection is performed by using the ACF, and the mechanical fixing and electrical connection between the driving chip and the circuit board are completed at the same time, and the conductive particles ensure the reliability of the interconnection.
  • connection resistance between the conductive bump and the connection terminal mainly depends on the conductive current captured therebetween.
  • the number of particles One problem with this is that the number of conductive particles between the conductive bumps and the connection terminals becomes too small due to the escape of the conductive particles during the packaging process, thereby increasing the connection resistance and even causing an open circuit.
  • the cured polymer between the conductive bumps of the driving chip and the connecting terminal with the circuit substrate is filled with the cured polymer to keep the insulation, but some untrapped conductive particles will also be Scattered in between.
  • Another problem with this is that too many conductive particles are concentrated between adjacent conductive bumps, forming a lateral electrical connection, i.e., shorting adjacent conductive bumps and adjacent connection terminals.
  • the object of the present invention is to provide a microelectronic component that does not need to use an anisotropic conductive film during the packaging process, and the obtained package structure or liquid crystal display device and anisotropic conductive adhesive are used for the defects of the prior art.
  • the package structure of the film or the liquid crystal display device has a lower connection resistance while avoiding the occurrence of a short circuit.
  • the present invention also provides a method of fabricating the microelectronic device, and a package structure and liquid crystal display device including the microelectronic device.
  • the present invention provides an electronic component including a semiconductor chip and disposed thereon 6
  • the conductive bump on the surface solder pad of the semiconductor chip comprises a conductive layer and an elastic conductive layer, the conductive layer is electrically connected with the surface pad of the semiconductor chip, and the elastic conductive layer is metallurgically connected with the conductive layer.
  • the conductive layer is a metal layer composed of at least one metal selected from the group consisting of Au, Cu, Al, Ni, Sn, Pb, Bi, Ag, In, Sb, Cd, Zn, Ga or an alloy of these metals.
  • the thickness of the conductive layer is not less than about 5 ⁇ m.
  • the elastic conductive layer is composed of conductive particles.
  • the conductive particles are metal particles or metal coated metal particles.
  • an under bump metallurgy may be included between the pad and the conductive bump of the semiconductor chip.
  • the present invention provides a microelectronic component comprising a circuit component and a conductive bump disposed on the circuit component, the conductive bump comprising a conductive layer and an elastic conductive layer, the conductive layer and the circuit on the circuit component Electrically connected, the elastic conductive layer is metallurgically connected to the conductive layer.
  • the conductive layer is a metal layer composed of at least one metal selected from the group consisting of Au, Cu, Al, M, Sn, Pb, Bi, Ag, In, Sb, Cd, Zn, Ga or an alloy of these metals.
  • the thickness of the conductive layer is not less than about 5 ⁇ m.
  • the elastic conductive layer is composed of conductive particles.
  • the conductive particles are metal particles or metal coated metal particles.
  • the present invention provides a package structure including any of the above microelectronic components, wherein the microelectronic component is bonded to a circuit board, and the conductive bumps of the microelectronic component are placed opposite to the connection terminals of the circuit substrate. And electrically connected.
  • the bonding of the microelectronic component to the circuit board with the substrate is achieved by an insulating adhesive which does not contain any conductive material.
  • the invention provides a liquid crystal display device comprising any of the above microelectronic components, the microelectronic component being bonded to the liquid crystal display panel assembly, the conductive bump of the microelectronic component being connected to the liquid crystal display panel assembly
  • the terminals are placed opposite each other and electrically connected.
  • the bonding of the microelectronic component to the liquid crystal display panel assembly is achieved by an insulating adhesive that does not contain any conductive material.
  • the present invention provides a method of fabricating a microelectronic component, comprising the steps of: (a) providing a semiconductor chip having a pad on its surface, depositing a conductive layer on the semiconductor chip (b) forming an elastic conductive layer over the conductive layer, the elastic conductive layer being metallurgically connected to the conductive layer to obtain a microelectronic component.
  • the conductive layer is a metal layer formed by an electroplating method.
  • the formation of the conductive layer comprises the following two steps: (1) depositing a first metal material, the metal material being at least one metal selected from the group consisting of Au, Cu, Ni, A1 or an alloy of these metals; (2) depositing a first Two metal materials, the metal material being at least one metal selected from the group consisting of Au, Cu, Al, Ni, Sn, Pb, Bi, Ag, In>Sb, Cd, Zn, Ga or an alloy of these metals, wherein The melting point of the second metal material is lower than the melting point of the first metal material.
  • the elastic conductive layer is formed by metallurgically connecting the conductive particles to the conductive layer.
  • the conductive particles are metal particles or resin particles coated with metal.
  • the metallurgical connection of the elastic conductive layer to the conductive layer is formed by heat or by heat and pressure.
  • the present invention provides a method of fabricating a microelectronic component, comprising the steps of: a) providing a semiconductor chip, the surface of the semiconductor chip comprising a solder pad, forming a bump bottom metal layer on the surface of the semiconductor chip a substrate (b) forming a non-conductive layer on the bottom metal layer of the bump and the surface of the semiconductor chip, and patterning the non-conductive layer to form at least one opening, the opening exposing the bottom metal layer of the bump; (cc) Forming a conductive layer in the opening; (dd) forming an elastic conductive layer on the conductive layer, the elastic conductive layer being metallurgically connected to the conductive layer; (ee) removing the non-conductive layer to obtain a microelectronic component.
  • the conductive layer is a metal layer formed by an electroplating method.
  • the formation of the conductive layer comprises the following two steps: (1) depositing a first metal material, the metal material being at least one metal selected from the group consisting of Au, Cu, Ni, A1 or an alloy of these metals; (2) depositing a layer Two metal materials, the metal material being at least one metal selected from the group consisting of Au, Cu, Al, Ni, Sn, Pb>Bi, Ag, In, Sb, Cd, Zn, Ga or an alloy of these metals, wherein The melting point of the second metal material is lower than the melting point of the first metal material.
  • the elastic conductive layer is formed by metallurgically connecting the conductive particles to the conductive layer.
  • the conductive particles are metal particles or resin particles coated with metal.
  • the metallurgical connection of the elastic conductive layer to the conductive layer is formed by heating, or by heat and pressure.
  • the invention in another aspect, relates to a method of fabricating an electronic component, which is also applicable to a circuit component, comprising the steps of: aa) providing a circuit component, depositing a conductive layer on the circuit component Surfacely, the conductive layer is electrically connected to the circuit on the circuit component; (bbb) forming an elastic conductive layer on the conductive layer, and the elastic conductive layer and the conductive layer are metallurgically connected to obtain a microelectronic component.
  • the deposition of the conductive layer is formed by the same method and the same material as the circuit on the circuit component.
  • the deposition of the conductive layer is formed using at least one metal selected from the group consisting of Au, Cu Al, Ni, Sn, Pb, Bi, Ag, In, Sb, Cd, Zn, Ga or an alloy of these metals.
  • the elastic conductive layer is formed by metallurgically connecting the conductive particles to the conductive layer.
  • the conductive particles are metal particles or resin particles coated with metal.
  • the metallurgical connection of the elastic conductive layer to the conductive layer is formed by heating, or by heat and pressure.
  • the microelectronic component provided by the invention does not need to use an anisotropic conductive adhesive film in the packaging process, and the obtained package structure or liquid crystal display device is compared with a package structure or a liquid crystal display device using an anisotropic conductive adhesive film, on the one hand, by elasticity
  • the number of conductive particles provided by the conductive layer is more stable than the number of conductive particles captured in the prior ACF packaging process, and the connection resistance of the individual conductive bumps and the connection terminals due to too little trapped conductive particles is avoided. Open circuit.
  • FIG. 1 is a schematic structural view of a driving chip according to an embodiment of the invention.
  • FIGS. 2 to 4 are schematic views of a method of manufacturing a driving chip according to an embodiment of the present invention.
  • 5 to 11 are views showing another method of manufacturing a driving chip according to an embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing another manufacturing method of an elastic conductive layer for driving a conductive bump of a chip according to an embodiment of the present invention
  • 6 is a schematic view showing the application of a driving chip in a package structure according to an embodiment of the present invention
  • FIG. 14 is a schematic diagram of a liquid crystal display device assembly in which a driving according to an embodiment of the present invention is installed in a COG and COF package form. Chip; specific implementation
  • a liquid crystal display driving chip hereinafter simply referred to as a driving chip
  • a driving chip as a microelectronic element
  • FIG. 1 is a schematic structural view of a driving chip according to an embodiment of the present invention.
  • an embodiment of the present invention provides a driver chip 1 including a semiconductor chip 2 and a pad 3 disposed on the surface of the semiconductor chip.
  • the conductive bump 4 includes a conductive layer 5 and an elastic conductive layer 6, wherein the conductive layer 5 is electrically connected to the surface pad 3 of the semiconductor chip 2, and the elastic conductive layer 6 is metallurgically connected to the conductive layer 5.
  • the conductive layer 5 is a metal layer having a shape similar to that of a "straight wall" conductive bump on a current driving chip, and at least one selected from the group consisting of Sn, Au, Cu, Pb, Bi, and Ag.
  • the metal of In, Al, M, Sb, Cd, Zn, Ga or an alloy composition of these metals is preferably composed of Au and an Au-Sn alloy plating layer on the surface thereof.
  • the elastic conductive layer 6 is composed of conductive particles 7 which are metal particles or metal coated metal particles, or a mixture of two kinds of particles. Generally, both the metal particles and the resin particles have a certain elasticity, but the elastic deformation ability of the resin particles is superior to that of the metal particles.
  • the substrate is glass, and the texture is hard and difficult.
  • the deformation therefore, requires the conductive bumps 4 to have a large elastic deformation range to satisfy the reliability requirements of the package structure.
  • the conductive particles 7 are metal-coated resin particles.
  • the surface of the conductive particles 7 is coated with at least one metal selected from the group consisting of Sn, Au, Cu, Pb, Bi, Ag, In, Al, Ni, Sb, Cd, Zn, Ga.
  • the driver chip 1 has some process features of a flip chip currently using ACF as an interconnect medium, and its packaging process is similar to that of using ACF, but ACF is no longer needed, and can be utilized.
  • the polymer chip 1 and the circuit board to be packaged are bonded to each other by heat curing, and the conductive bumps 4 of the driving chip 1 and the connection terminals with the circuit board are placed opposite each other.
  • the pressing contact forms an electrical connection, so that the mechanical fixing and electrical connection between the driving chip 1 and the circuit board are completed simultaneously, and the conductive particles 7 in the elastic conductive layer 6 are elastically deformed during the extrusion process, replacing the original ACF.
  • the function of the conductive particles captured during the encapsulation ensures the reliability of the electrical connection between the conductive bumps 4 and the connection terminals.
  • the package structure of the driving chip 1 is, on the one hand, the number of conductive particles 7 provided by the elastic conductive layer 6 is more stable than the number of conductive particles captured in the prior ACF packaging process, and at the same time It can be artificially controlled, and therefore, the connection resistance of the individual conductive bumps 4 and the connection terminals due to too little trapped conductive particles is prevented from being excessively high or even broken.
  • the adjacent conductive bumps 4 and the connection terminals are filled with the cured polymer, and there is no dispersion of the conductive particles, the probability of occurrence of the short circuit is greatly reduced. With the gradual increase in the density of microelectronic packages, the advantages of the above two aspects will be more obvious.
  • the thickness of the conductive layer 5 is not less than about 5 ⁇ m in order to prevent the dust particles in the air from causing a decrease in yield during the process of encapsulating the driving chip 1. This is especially important for applications such as liquid crystal display packages, because if the height of the conductive bumps is too low, glass particles floating in the air with a diameter of a few micrometers can cause mechanical damage to the chip or increase the resistance of the interconnects or even Turn on.
  • the driving chip 1 further includes a bump bottom metal layer between the bonding pad 3 and the conductive bumps 4 (not shown).
  • the bump bottom metal layer has the connection strength of the reinforcing pad 3 and the conductive bump 4, and prevents the mutual diffusion of the pad 3 and the conductive bump 4, and the specific embodiment thereof will be in the following manufacturing method embodiment. Do a detailed description.
  • FIGS. 2 through 4 are cross-sectional views showing a method of fabricating a driving chip in accordance with an embodiment of the present invention.
  • FIG. 2 shows a semiconductor chip 2 having a semiconductor integrated circuit (not shown) formed therein.
  • a pad 3 for forming a conductive bump is formed on the surface, and the pad 3 is electrically connected to an integrated circuit in the semiconductor chip 2 for inputting and outputting driving and function signals.
  • the deposition process comprises two steps, that is, first depositing a first metal material 5a, the first metal material 5a being composed of at least one metal selected from the group consisting of Au, Cu, Ni, and A1 or The composition of these metals is preferably Au; next, a second metal material 5b is deposited, and the two metal materials 5b are made of at least one selected from the group consisting of Au, Cu, Al, Ni, Sn, Pb, Bi, A metal of Ag, In, Sb, Cd, Zn, Ga or an alloy of these metals, and having a melting point ⁇ in the first metal material 5a, preferably a Sn or Au-Sn alloy.
  • the thickness of the conductive layer 5 is not less than about 5 ⁇ i, wherein a preferred thickness of the first metal material 5a is 5 micrometers to 20, and a preferred thickness of the second metal material 5b is 0.5. Micron to 2 microns.
  • an elastic conductive layer 6 is formed on the surface of the conductive layer 5, as shown in Fig. 4, whereby a driving chip 1 according to an embodiment of the present invention is obtained.
  • the elastic conductive layer 6 is formed by metallurgically connecting the conductive particles 7 to the conductive layer 5.
  • the conductive particles 7 are metal particles or metal coated metal particles, or two kinds of particles.
  • the conductive particles 7 are preferably surface-coated with metal resin particles.
  • the metal material coated on the surface of the conductive particles 7 is made of at least one metal selected from the group consisting of Sn, Au, Cu, Pb, Bi, Ag, In, Al, Ni, Sb, Cd, Zn, Ga or these according to an embodiment of the present invention.
  • Metal alloy composition From the viewpoint of electrical conductivity, Au is preferable, and eutectic welding is easily formed with the Sn or Au-Sn alloy constituting the second metal material 5b.
  • the metallurgical connection of the conductive layer 5 to the elastic conductive layer 6 is accomplished by heating, and the preferred heating temperature is from 278 ⁇ to 320 ° C according to the Au-Sn eutectic phase diagram.
  • the conductive particles 7 are usually between 1 ⁇ m and 20 ⁇ m in diameter, and preferably have a diameter of 3 ⁇ m to 5 ⁇ m.
  • the metallurgical connection of the conductive layer 5 to the elastic conductive layer 6 can also be accomplished by heating and pressurization.
  • 5 to 11 are cross-sectional views showing another method of manufacturing a driving chip according to an embodiment of the present invention.
  • FIG. 5 shows a semiconductor chip 2 having a semiconductor integrated circuit (not shown) formed therein.
  • a solder pad 3 for forming a conductive bump is formed on the surface, and the pad 3 is electrically connected to an integrated circuit in the semiconductor chip 2 for inputting and outputting driving and function signals.
  • the pad 3 may be formed of a conductive material such as metal, and preferably, the pad 3 is formed of A1 or Cu.
  • a passivation layer 8 for protecting the semiconductor chip 2 and exposing the pad 3 is formed on the semiconductor chip 2. To achieve electrical contact of the pad 3 with the outside, it is preferable that the passivation layer 8 has a predetermined portion on the upper portion of the pad 3. Opening.
  • the opening of the passivation layer 8 can be formed by a photolithographic etching process using a mask.
  • a bump bottom metal layer 9 is formed on the semiconductor chip 2 on which the passivation layer 8 is formed, and covers the exposed portion of the pad 3.
  • the metal layer 9 at the bottom of the bump can strengthen the connection strength of the A1 or Cu pad 3 to the conductive bump.
  • the bump bottom metal layer 9 can function to prevent interdiffusion between the pad 3 and the conductive bump interconnect. Therefore, it is preferable that the bump bottom metal layer 9 has good adhesion to the pad 3 and the passivation layer 8, thereby minimizing the stress acting on the semiconductor chip 2 and serving as a diffusion barrier. Further, a low resistance between the bump bottom metal layer 9 and the pad 3 is preferable.
  • the bump bottom metal layer 9 uses Ti, Cr, W, Ni, Au, Cu, Cao, NiV, Pd, Cr/Cu, Xiao/Cu, TiW/Au, NiV. At least one of /Cu is formed, preferably by sputtering or evaporation.
  • the present invention is not limited thereto, and the bump bottom metal layer 9 can be made of various materials by various manufacturing processes.
  • the non-conductive layer 10 is formed on the bump bottom metal layer 9.
  • Any insulating material having the following function can be used as the non-conductive layer 10. That is, in the subsequent plating process for forming the conductive bumps (see FIG. 9), by blocking current flow to the bump bottom metal layer 9, the insulating material prevents the formation of conductive bumps in the metal layer 9 except the bump bottom. Part of the area is plated on the remaining area of the bump bottom metal layer 9.
  • a photoresist be used as the non-conductive layer 10.
  • the non-conductive layer 10 can be formed by electroless plating, sputtering, evaporation, spin coating, roll-coating, slit-or slot-die, or the like.
  • a positive or negative photoresist can be used as the non-conductive layer 10.
  • the photoresist is cured in a hot plate by a soft bake process to remove the solvent.
  • the exposure process is selectively performed on the cured photoresist using an exposure source and a mask having a pattern formed thereon.
  • the photoresist is thermally cured in a hot furnace, thereby The area where the light is not illuminated and the area where the light is not illuminated.
  • the non-conductive layer 10 is patterned by a photolithography etching process.
  • the non-conductive layer pattern 10a is formed while defining a region where the conductive bumps (refer to reference numeral 4 of Fig. 10) are formed. As shown in Fig. 8, it is preferable that the conductive bump region is over the pad 3.
  • a conductive bump 4 is formed on the region of the bottom metal layer 9 of the bump exposed by the non-conductive layer pattern 10a.
  • the formation of the conductive layer 5 is performed by a plating method to form a metal layer on a region where the bump bottom metal layer 9 is exposed through the non-conductive layer pattern 10a, of course, not limited to the plating method.
  • the formation process of the conductive layer 5 further comprises two steps, that is, first depositing a first metal material 5a, the first metal material 5a being at least one selected from the group consisting of Au, Cu, Ni, A metal of A1 or an alloy composition of these metals, preferably Au; followed by deposition of a second metal material 5b consisting of at least one selected from the group consisting of Au, Cu, Al, Ni, Sn, Pb a metal of Bi, Ag, In, Sb, Cd, Zn, Ga or an alloy of these metals, and having a lower melting point than the first metal material 5a, preferably a Sn or Au-Sn alloy.
  • the conductive layer 5 has a thickness of not less than about 5 ⁇ m, wherein the first metal material 5a has a preferred thickness of 5 ⁇ m to 20 ⁇ m, and the second metal material 5b has a preferred thickness of 0.5. Micron to 2 microns.
  • an elastic conductive layer 6 is formed on the surface of the conductive layer 5.
  • the elastic conductive layer 6 is formed by metallurgically connecting the conductive particles 7 to the conductive layer 5.
  • the conductive particles 7 are metal particles or metal coated metal particles, or two kinds of particles.
  • the conductive particles 7 are metal-coated resin particles.
  • the metal material coated on the surface of the conductive particles 7 is made of at least one metal selected from the group consisting of Sn, Au, Cu, Pb, Bi, Ag, In, Al, Ni, Sb, Cd, Zn, Ga or these according to an embodiment of the present invention.
  • Metal alloy composition From the viewpoint of electrical conductivity, Au is preferably formed into a eutectic weld with a Sn or Au-Sn alloy constituting the second metal material 5b.
  • the metallurgical connection of the conductive layer 5 to the elastic conductive layer 6 is accomplished by heating, and the preferred heating temperature is from 278 ° C to 320 ° C according to the Au-Sn eutectic phase diagram.
  • the conductive particles 7 are typically between 1 and 20 microns in diameter, preferably between 3 and 5 microns in diameter.
  • the conductive layer 5 and the elastic conductive layer 6 The gold connection can also be done by heating and pressurization.
  • the non-conductive layer pattern 10a is removed by an ashing and stripping process.
  • the bump bottom metal layer 9 is etched according to the shape of the conductive bump 4, thereby obtaining the driving chip 1 according to an embodiment of the present invention.
  • the semiconductor chip 2 is diced, so that the driving chip 1 is divided into a plurality of individual driving chips.
  • the individual driver chips obtained are packaged using methods such as COG or COF, eliminating the need to use ACF as an interconnect medium.
  • Figure 12 is a cross-sectional view showing another method of fabricating an elastic conductive layer for driving a chip conductive bump in accordance with an embodiment of the present invention.
  • the conductive particles 7 are uniformly disposed on the surface of a flat substrate 11, which requires a hard texture and a high heat-resistant temperature, preferably a glass substrate or a ceramic substrate.
  • the semiconductor chip 2 on which the conductive layer 5 has been formed on the pad 3 is reversely disposed on the conductive particles 7, and the semiconductor chip 2 and the substrate 11 are pressurized while being heated, thereby accelerating metallurgy between the conductive layer 5 and the conductive particles 7.
  • the formation of the connection is described in this specification.
  • the range of the pressure should be determined according to the type and number of the conductive particles 7, and the pressed conductive particles 7 are more, and the pressure can be selected to be larger, and conversely, the applied pressure is reduced.
  • the applied pressure should be such that most of the conductive particles 7 do not undergo large plastic deformation, and for metal coated resin particles, the applied pressure should be less than that of the conductive particles.
  • the semiconductor chip 2 in this embodiment may be an uncut wafer or a single chip after cutting, preferably a single chip.
  • the structure of the conductive bump according to the embodiment of the present invention can be applied to various chips.
  • the structure of the conductive bumps according to the present invention can be advantageously applied to chips associated with products such as flat panel displays, RFID, electronic tags, and the like.
  • various chips that need to be interconnected by ACF or Non-Conductive Film (NCF) can be interconnected by adopting a structure of a conductive bump according to an embodiment of the present invention. Performance improvement.
  • microelectronic components according to the present invention can also be applied to a variety of other circuit components, such as printed circuit boards (PCBs), flexible circuit boards (FPCs), and surface mount components (SMT Components). , MEMS Components, etc.
  • the conductive bumps disposed on the circuit components comprise a conductive layer and an elastic conductive layer, wherein The electrical layer is electrically coupled to circuitry on the circuit component, and the resilient conductive layer is metallurgically coupled to the conductive layer.
  • the conductive layer is a metal layer composed of at least one metal selected from the group consisting of Sn, Au, Cu, Pb, Bi, Ag, In, Al, M, Sb, Cd, Zn, Ga or these
  • the alloy composition of the metal is preferably a surface plating of Cu and Cu, wherein the surface plating layer is composed of at least one of Au, Ni/Au, Sn, Sn/Au or Sn/Ag/Cu.
  • the conductive layer is part of a pad on the circuit component for interconnecting with the outside world, or a plating is applied to the surface of the pad, substantially consistent with the material and thickness of the circuitry on the circuit component.
  • the manufacturing process of the conductive bump formed on the circuit component is similar to the manufacturing process example of the conductive bump of the driving chip described above, but the forming process and method of the conductive layer may vary according to the circuit component to be applied to the liquid crystal.
  • a flexible circuit board needs to be connected to a liquid crystal display panel assembly through an ACF.
  • the flexible circuit board according to an embodiment of the present invention can be directly bonded to the liquid crystal display panel assembly.
  • the formation of the conductive layer of the conductive bumps on the flexible circuit board is formed by the same method and the same material, preferably by electroplating or calendering, in accordance with an embodiment of the present invention and the circuit on the surface of the flexible circuit board.
  • the driving chips according to various embodiments of the present invention described in Figs. 1 through 12 can be mounted on various structures in accordance with various mounting methods.
  • the driving chip is directly packaged on a glass substrate with a circuit by a COG method; the driving chip is packaged on a flexible circuit board by a COF method; and the driving chip is packaged on a general printed circuit board by a COB method.
  • a common insulating adhesive is required as an interconnecting medium between the driving chip and the various substrates to support, bond and protect.
  • FIG. 13 is a schematic diagram of the application of a driving chip in a package structure according to an embodiment of the present invention.
  • the driving chip 1 and the circuit-coated substrate 12 are bonded by an insulating adhesive 14, wherein the conductive bumps 4 on the driving chip 1 are placed opposite to and electrically connected to the connecting terminals 13 on the circuit board 12.
  • the insulating adhesive 14 is disposed between the driving chip 1 and the circuit board 12, and the conductive bumps 4 are opposed to the corresponding connection terminals 13 thereof.
  • the insulating adhesive 14 has thermosetting properties, and the packaging process is completed by heating and pressurizing the driving chip 1 and the circuit board 12 .
  • the insulating adhesive 14 has photo-curability, and in this case, the circuit-coated substrate 12 is preferably a transparent substrate.
  • the packaging process passes through the pair of driving chip 1 and the circuit board 12 is pressurized, and illumination is completed by the circuit board 12 .
  • the insulating adhesive 14 has a compressive property, and the packaging process is completed by pressurizing the driving chip 1 and the circuit board 12.
  • the insulating adhesive 14 may be a strip adhesive, preferably a non-conductive film (NCF). During the packaging process, the NCF is first applied to the circuit board 12, and then The drive chip 1 and the circuit board 12 are heated and pressurized.
  • NCF non-conductive film
  • the insulating adhesive 14 may be a paste-like adhesive, preferably a non-conductive adhesive (NCP).
  • NCP non-conductive adhesive
  • the NCP is first sprayed on the circuit board 12 with a circuit.
  • the driving chip 1 and the circuit board 12 are heated and pressurized.
  • the present invention is not limited thereto. Obviously, the package structure of the above various circuit components according to the present invention can also be used.
  • FIG 14 is a schematic illustration of a liquid crystal display device assembly in which a driver chip in accordance with an embodiment of the present invention is mounted in the form of a COG and COF package.
  • the liquid crystal display panel 15 of the present invention comprises a lower substrate 16 and an upper substrate 17, and a protruding portion of the lower substrate 16 has a transparent electrode 18 formed of indium tin oxide (ITO) for connecting the external driving circuit and the pixels of the display panel. Circuit.
  • ITO indium tin oxide
  • the driving chip 1 according to an embodiment of the present invention is directly packaged on the lower substrate 16 of the liquid crystal display panel 15 by the insulating adhesive 14 by the COG method, and the conductive bumps 4 are placed opposite to the ITO transparent electrodes 18 and electrically connected together.
  • a flexible circuit board member 19 including a flexible film 20 and a connection terminal 21 formed on the flexible film 20 is mounted on the lower substrate 16.
  • the driving chip 1 according to an embodiment of the present invention is packaged on the flexible circuit board member 19 by the insulating adhesive 14 by the COF method, and the conductive bumps 4 are placed opposite to the connection terminals 21 and electrically connected together.
  • the insulating adhesive 14 has thermosetting properties, preferably an insulating adhesive having a curing temperature lower than the curing temperature of the high molecular polymer in the current ACF, which helps to improve production efficiency while reducing the liquid crystal display device. Warpage caused by different thermal expansion coefficients of different materials during the manufacturing process improves reliability.
  • the insulating adhesive 14 has photo-curability, and since the lower substrate 16 and the flexible circuit board component 19 are transparent themselves, the insulating adhesive 14 is cured by illumination, and the liquid crystal display device due to heating can be avoided.
  • the insulating adhesive 14 has a compressive property, and the packaging process is completed by pressurizing the driving chip 1 and the lower substrate 16, or the driving chip 1 and the flexible circuit board member 19.
  • the insulating adhesive 14 may be a strip adhesive, preferably NCF.
  • the NCF is first applied to the lower substrate 16 or the flexible circuit board member 19, and then to the driving chip 1 and the lower substrate 16, or the driving chip 1 and the flexible
  • the board component 19 is heated and pressurized.
  • the insulating adhesive 14 may be a paste adhesive, preferably NCP.
  • the NCP is first sprayed on the lower substrate 16 or the flexible circuit board component 19, and then the driving chip 1 and the lower substrate 16 are applied. , or the driving chip 1 and the flexible circuit board component 19 are heated and pressurized.
  • the liquid crystal display panel 15 in which the driving chip 1 is mounted in the form of a COG and COF package is described in the present embodiment, the present invention is not limited thereto. It is apparent that, as shown in FIG. 14, the connection of the flexible circuit board member 19 to the liquid crystal display panel 15 can be replaced with the connection of the flexible circuit board according to the present invention to the liquid crystal display panel 15 by the above-described method.
  • the microelectronic element according to the present invention does not need to use an anisotropic conductive film in the packaging process, and the obtained package structure or liquid crystal display device has a package structure or a liquid crystal display device using an anisotropic conductive film. Lower connection resistance while avoiding short circuits.

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Description

微电子元件及其制造方法 技术领域
本发明涉及微电子技术领域， 具体提供了一种微电子元件， 包括该微 电子元件的封装结构和液晶显示装置， 以及该微电子元件的制造方法。 背景技术
在现有的微电子制造技术当中， 以各向异性导电胶膜 （Anisotropic Conductive Film, ACF ) 为互联介质的倒装芯片（Flip Chip, FC)技术扮演着 十分重要的角色。以目前常用的一种 ACF为例，它由高分子聚合物和均匀 在其中的导电颗粒组成， 典型的导电颗粒的直径大约为 3~5 米， 通 常是一种表面包裹导电性金属材料的树脂颗粒。
在现有的倒装芯片技术当中， 广泛使用 ACF的制造工艺主要包括： 将 驱动芯片直接封装在带电路的玻璃基板上的制造方法（COG， 即 chip on glass );将驱动芯片封装在柔性电路板（FPC )上的制造方法（COF， 即 chip on FPC ); 以及将驱动芯片封装于一般的印刷电路板上的制造方法（COB， 即 chip on board )。 其中， COG技术和 COF技术是制造液晶显示装置的两 个关键技术。
ACF在倒装芯片技术当中的应用描述如下。 以带电路基板表示上述制 造方法中的玻璃基板、 柔性电路板、 印刷电路板或者其他电路板件， 该带 电路基板包含基板， 通常其表面或内部形成有电路， 以及形成在基板表面 的连接端子（pad ), 该连接端子与基板上的电路电连接； 另一方面， 驱动 芯片由内部有集成电路的半导体芯片和形成在该半导体芯片表面具有一 定厚度的导电凸块（bump )组成。 在封装过程中， 将 ACF置于驱动芯片 和带电路基板之间， 并使该驱动芯片上的导电凸块和基板上与之相对应的 连接端子相互对准。然后对该驱动芯片和带电路基板进行加热及加压， ACF 中的高分子聚合物受热后固化， 将驱动芯片和带电路基板粘结固定在一 起， 与此同时， 部分均匀分散在高分子聚合物当中的导电颗粒被捕捉在相
确 认 本 对突出的导电凸块和连接端子之间， 并在外力条件下受到挤压， 这样， 通 过其表面包裹的导电性金属材料， 被捕捉的导电颗粒便在导电凸块与连接 端子之间建立了电连接。 其中， 导电颗粒的内核， 即树脂颗粒具有一定的 弹性， 因此在受到挤压时会发生一定的弹性变形， 当导电凸块和连接端子 之间的距离受到外部环境变化影响而发生变化时， 这种弹性变形可以使导 电凸块和连接端子之间通过导电颗粒始终保持可靠的电连接。 由此可见， 使用 ACF进行倒装芯片互联，驱动芯片与带电路基板之间的机械固定和电 气连接同时完成， 而导电颗粒保证了互联的可靠性。
应用 ACF进行倒装芯片互联时， 由于驱动芯片和带电路基板之间的电 路导通通过导电颗粒实现， 因此导电凸块和连接端子之间的连接电阻主要 取决于被捕捉于其之间的导电颗粒的数目。 这样带来的一个问题是： 导电 凸块和连接端子之间的导电颗粒数目由于在封装过程中导电颗粒的四处 逸散而变得太少， 从而使其连接电阻增加， 甚至造成断路。
另一方面， 应用 ACF进行的封装完成后， 驱动芯片的导电凸块之间以 及带电路基板的连接端子之间充满了固化后的聚合物， 保持绝缘， 但一些 未被捕捉的导电颗粒也会散布于其间。 这样带来的另一个问题是： 太多的 导电颗粒集中于相邻的导电凸块之间， 形成侧向的电连接， 即对相邻的导 电凸块和相邻的连接端子造成短路。
随着^ t电子产品功能的日渐增加， 封装密度逐步提高， 芯片表面单位 面积上的导电凸块的数量也成倍增长， 这就造成导电凸块的表面积和相邻 间距同时减小， 上述两方面的问题将越来越容易发生。 发明内容
本发明的目的在于针对现有技术的不足， 提供一种微电子元件， 该微 电子元件在封装过程中无需使用各向异性导电胶膜， 所得封装结构或液晶 显示装置与使用各向异性导电胶膜的封装结构或液晶显示装置相比， 具有 更低的连接电阻， 同时避免短路发生。 本发明还提供了该微电子元件的制 造方法， 以及包含该微电子元件的封装结构和液晶显示装置。
一方面， 本发明提供了一种 电子元件， 包括半导体芯片和设置于该 6
3 半导体芯片表面焊垫上的导电凸块， 导电凸块包括一导电层和一弹性导电 层，导电层与半导体芯片表面焊垫电连接，弹性导电层与导电层冶金连接。
其中， 导电层是金属层， 由至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金组成。 导电层 的厚度不低于约 5微米。
此外， 弹性导电层由导电颗粒组成。 导电颗粒是金属颗粒或是表面涂 覆金属的树脂颗粒。
另外， 在上述 电子元件中， 半导体芯片的焊垫和导电凸块之间还可 以包含一凸块底部金属层 (under bump metallurgy, UBM)。
另一方面， 本发明提供了一种微电子元件， 包括电路组件和设置于该 电路組件上的导电凸块， 导电凸块包括一导电层和一弹性导电层， 导电层 与电路组件上的电路电连接， 弹性导电层与导电层冶金连接。
其中， 导电层是金属层， 由至少一种选自 Au、 Cu、 Al、 M、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金组成。 导电层 的厚度不低于约 5微米。
此外， 弹性导电层由导电颗粒组成。 导电颗粒是金属颗粒或是表面涂 覆金属的树脂颗粒。
另一方面， 本发明提供了一种包含上述任一项微电子元件的封装结构， 微电子元件与带电路基板粘结， 该微电子元件的导电凸块与该带电路基板 的连接端子相对放置并电连接。
其中， 微电子元件与带电路基板的粘结通过绝缘粘胶实现， 该绝缘粘 胶不包含任何导电性物质。
另一方面， 牟发明提供了一种包含上述任一项微电子元件的液晶显示 装置， 微电子元件与液晶显示面板组件粘结， 该微电子元件的导电凸块与 该液晶显示面板组件的连接端子相对放置并电连接。
其中， 微电子元件与液晶显示面板组件的粘结通过绝缘粘胶实现， 该 绝缘粘胶不包含任何导电性物质。
另一方面， 本发明提供了一种微电子元件的制造方法， 包括以下步驟： ( a )提供一表面具有焊垫的半导体芯片，沉积一导电层于该半导体芯片表 面的焊垫上； （b )形成一弹性导电层于该导电层之上， 该弹性导电层与该 导电层冶金连接， 得到微电子元件。
其中， 导电层是通过电镀方法形成的金属层。 导电层的形成包括下列 两步： （1 )沉积一第一种金属材料， 该金属材料是至少一种选自 Au、 Cu、 Ni、 A1的金属或者这些金属的合金； （2 )沉积一第二种金属材料， 该金属 材料是至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In> Sb、 Cd、 Zn、 Ga 的金属或者这些金属的合金， 其中， 该第二种金属材料的熔点低 于该第一种金属材料的熔点。
此外， 弹性导电层的形成是将导电颗粒冶金连接到该导电层。 导电颗 粒是金属颗粒或是表面涂覆金属的树脂颗粒。 弹性导电层与导电层的冶金 连接是通 Ρ热形成， 或加热及加压形成。
另一方面， 本发明提供了一种微电子元件的制造方法， 包括以下步骤： a )提供一半导体芯片， 该半导体芯片表面包括焊垫， 形成一凸块底部 金属层于该半导体芯片表面的焊垫上； （bb )形成一非导电层于该凸块底 部金属层及半导体芯片表面上，并图案化该非导电层，以形成至少一开口， 该开口暴露该凸块底部金属层； （cc )在开口中形成一导电层； （dd )在导 电层上形成一弹性导电层，该弹性导电层与该导电层冶金连接； （ee )去除 非导电层， 得到微电子元件。
其中， 导电层是通过电镀方法形成的金属层。 导电层的形成包括下列 两步： （1 )沉积一第一种金属材料， 该金属材料是至少一种选自 Au、 Cu、 Ni、 A1的金属或者这些金属的合金； （2 )沉积一笫二种金属材料， 该金属 材料是至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb> Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga 的金属或者这些金属的合金， 其中， 该第二种金属材料的熔点低 于该第一种金属材料的熔点。
此外， 弹性导电层的形成是将导电颗粒冶金连接到该导电层。 导电颗 粒是金属颗粒或是表面涂覆金属的树脂颗粒。 弹性导电层与导电层的冶金 连接是通过加热形成， 或力热及加压形成。
另一方面， 本发明涉及的一种 电子元件的制造方法也适用于电路组 件， 包括以下步骤： aa )提供一电路组件， 沉积一导电层于该电路组件 表面上， 并使该导电层与该电路组件上的电路电连接； （bbb )形成一弹性 导电层于该导电层上， 该弹性导电层和该导电层冶金连接， 得到微电子元 件。
其中， 导电层的沉积是与电路组件上的电路同时， 用同样的方法和同 样的材料形成。 导电层的沉积是利用至少一种选自 Au、 Cu Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金形成的。
此外， 弹性导电层的形成是将导电颗粒冶金连接到该导电层。 导电颗 粒是金属颗粒或是表面涂覆金属的树脂颗粒。 弹性导电层与导电层的冶金 连接是通过加热形成， 或力 p热及加压形成。
本发明提供的微电子元件在封装过程中无需使用各向异性导电胶膜， 所得封装结构或液晶显示装置与使用各向异性导电胶膜的封装结构或液 晶显示装置相比， 一方面， 由弹性导电层所提供的导电颗粒的数目比现有 ACF封装过程中被捕捉的导电颗粒的数目更加稳定，避免了个别导电凸块 和连接端子由于所捕捉导电颗粒过少而造成的连接电阻过高甚至断路。 另 一方面， 相邻的导电凸块之间和连接端子之间没有散布的导电颗粒， 短路 的出现几率也会大大降低。 随着目前微电子封装密度的逐步提高， 上述两 方面的优势将会更加明显。 附图说明
读者在参照附图阅读了本发明的具体实施例以后， 将会清楚地了解 本发明的各个方面及其优点。
其中，
图 1是根据本发明一实施例的驱动芯片的结构示意图；
图 2至图 4是一种制造根据本发明一实施例的驱动芯片的方法的示意 图；
图 5至图 11是另一种制造根据本发明一实施例的驱动芯片的方法的示 意图；
图 12是 _据本发明一实施例的驱动芯片导电凸块的弹性导电层的另一 种制造方法的剖面图； 6 图 13是^^据本发明一实施例的驱动芯片在封装结构中应用的示意图； 图 14是液晶显示装置组件的示意图，其中以 COG和 COF封装的形式 安装了根据本发明实施例的驱动芯片； 具体实施方式
以下将参照附图更充分地描述本发明， 附图中示出了本发明的优选实 施例。
实施例将参照作为微电子元件的液晶显示器驱动芯片 （以下简称为驱 动芯片）给出说明， 其特性将通过示例的方式描述。
图 1是根据本发明一实施例的驱动芯片的结构示意图。
鉴于上文描述的对于目前使用 ACF进行倒装互联的封装结构所面临的 问题， 本发明的一实施例提供了一种驱动芯片 1, 包括半导体芯片 2和设 置于该半导体芯片表面焊垫 3上的导电凸块 4。 导电凸块 4包括一导电层 5和一弹性导电层 6， 其中， 导电层 5与半导体芯片 2表面焊垫 3电连接， 弹性导电层 6与导电层 5冶金连接。
在本发明的一实施例中， 导电层 5是金属层， 外形与目前驱动芯片上 的 "直墙式"导电凸块类似， 由至少一种选自 Sn、 Au、 Cu、 Pb、 Bi、 Ag、 In、 Al、 M、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金组成， 优选地， 由 Au和其表面的 Au-Sn合金镀层组成。 而弹性导电层 6由导电颗粒 Ί组 成， 导电颗粒 7是金属颗粒或是表面涂覆金属的树脂颗粒， 或者是两种颗 粒的混合。 通常情况下， 金属颗粒和树脂颗粒都具有一定的弹性， 但树脂 颗粒的弹性变形能力优于金属颗粒， 由于驱动芯片 1将用于封装在液晶显 示器面板上， 基板为玻璃， 质地较硬， 不易变形， 因此， 需要导电凸块 4 具有较大的弹性变形范围， 满足封装结构的可靠性要求， 优选地， 导电颗 粒 7是表面涂覆金属的树脂颗粒。 在本发明的一实施例中， 导电颗粒 7表 面涂覆的金属材料由至少一种选自 Sn、 Au、 Cu、 Pb、 Bi、 Ag、 In、 Al、 Ni、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金组成， 从导电性能来看， 优选 Au，而表面为 Au的导电颗粒 Ί与导电层 5表面的 Au-Sn合金在其对 应的组分的液相温度或以上时可以形成冶金连接。 6 由此可以看出， 这种驱动芯片 1具备了目前以 ACF为互联介质的倒装 芯片的一些工艺特点，它的封装过程与使用 ACF的封装过程类似，但不再 需要 ACF, 而可以利用类似于組成 ACF的高分子聚合物通过加热固化， 将需要封装起来的驱动芯片 1和带电路基板相互粘结， 同时， 驱动芯片 1 的导电凸块 4和带电路基板的连接端子相对放置并相互挤压接触形成电连 接，这样，驱动芯片 1和带电路基板之间的机械固定和电气连接同时完成， 而弹性导电层 6 中的导电颗粒 7 在挤压过程中发生弹性变形， 替代原有 ACF封装过程中被捕捉的导电颗粒的作用，保证了导电凸块 4和连接端子 之间电连接的可靠性。
这种驱动芯片 1的封装结构与现有技术相比，一方面， 由弹性导电层 6 所提供的导电颗粒 7的数目比现有 ACF封装过程中被捕捉的导电颗粒的数 目更加稳定， 同时又可以人为控制， 因此， 避免了个别导电凸块 4和连接 端子由于所捕捉导电颗粒过少而造成的连接电阻过高甚至断路。 另一方 面， 由于相邻的导电凸块 4之间和连接端子之间充满了固化的高分子聚合 物， 没有导电颗粒的散布， 短路的出现几率也会大大降低。 随着目前微电 子封装密度的逐步提高， 上述两方面的优势将会更加明显。
在本发明的一实施例中， 上述导电层 5的厚度不低于约 5微米， 这是 为了避免在封装该驱动芯片 1的过程中， 空气中的灰尘颗粒造成良率的下 降。 这一点对液晶显示封装等方面的应用特别重要， 因为如果导电凸块的 高度太低， 漂浮在空气中的直径为几微米的玻璃颗粒会对芯片造成机械损 伤或导致互联的电阻增大甚至不导通。
此外， 参照图 1所示的驱动芯片 1 , 在本发明的一实施例中， 上述驱动 芯片 1还包括介于焊垫 3和导电凸块 4之间的一凸块底部金属层（未示出）, 该凸块底部金属层具有增强焊垫 3和导电凸块 4的连接强度， 防止焊垫 3 和导电凸块 4的相互扩散的作用， 其具体实施方式将在后面的制造方法实 施例中做详细描述。
图 2至图 4为剖面图， 示出了一种制造根据本发明一实施例的驱动芯 片的方法。
图 2示出一半导体芯片 2， 其内部形成有半导体集成电路（未示出）， 08 000226
8
表面形成有用于制作导电凸块的焊垫 3, 该焊垫 3与半导体芯片 2中的集 成电路电连接， 用以输入和输出驱动和功能信号。
然后， 在焊垫 3表面沉积一导电层 5， 如图 3所示， 该导电层 5的沉积 是通过电镀方法形成一金属层， 当然不限于电镀方法。 在本发明的一实施 例中， 该沉积过程包括两步， 即先沉积一第一种金属材料 5a， 该第一种金 属材料 5a由至少一种选自 Au、 Cu、 Ni、 A1的金属或者这些金属的 ^^组 成， 优选的是 Au; 接下来沉积一第二种金属材料 5b, 该笫二种金属材料 5b由至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金組成， 且熔点氐于第一种金属材料 5a, 优 选的是 Sn或 Au-Sn合金。 在本发明的一实施例中， 导电层 5的厚度不低 于约 5 ^i, 其中， 第一种金属材料 5a的优选厚度为 5微米到 20 ， 第二种金属材料 5b的优选厚度为 0.5微米到 2微米。
接下来，在导电层 5表面形成弹性导电层 6, 如图 4所示， 由此得到根 据本发明一实施例的驱动芯片 1。 该弹性导电层 6的形成是将导电颗粒 7 冶金连接到该导电层 5, 在本发明一实施例中， 导电颗粒 7是金属颗粒或 是表面涂覆金属的树脂颗粒， 或者是两种颗粒的混合， 为使导电凸块 4具 有较大的弹性变形范围， 满足封装结构的可靠性要求， 导电颗粒 7优选表 面涂覆金属的树脂颗粒。 导电颗粒 7表面涂覆的金属材料根据本发明一实 施例由至少一种选自 Sn、 Au、 Cu、 Pb、 Bi、 Ag、 In、 Al、 Ni、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金组成。从导电性能来看，优选的是 Au, 与組成第二种金属材料 5b的 Sn或 Au-Sn合金易形成共晶（ eutectic )焊接。 根据本发明的一实施例， 导电层 5与弹性导电层 6的冶金连接是通过加热 完成的， 根据 Au-Sn共晶相图， 优选的加热温度为 278Ό到 320°C。 导电 颗粒 7的直径通常在 1微米到 20微米之间，优选的直径大小为 3微米到 5 微米。 当然， 导电层 5与弹性导电层 6的冶金连接也可以通过加热及加压 完成。
图 5至图 11为剖面图， 示出了另一种制造 居本发明一实施例的驱动 芯片的方法。
图 5示出一半导体芯片 2, 其内部形成有半导体集成电路（未示出）， 表面形成有用于制作导电凸块的焊垫 3 , 该焊垫 3与半导体芯片 2中的集 成电路电连接， 用以输入和输出驱动和功能信号。 焊垫 3可由诸如金属的 导电材料形成， 优选地， 焊垫 3由 A1或 Cu形成。 保护半导体芯片 2并暴 露焊垫 3的钝化层 8形成在半导体芯片 2上， 为实现焊垫 3与外界的电接 触， 优选的是， 钝化层 8在焊垫 3的上面部分上具有预定开口。 钝化层 8 的开口可利用掩模通过光刻烛刻工艺 （ photolithographic etching process ) 形成。
然后， 如图 6所示， 在形成有钝化层 8的半导体芯片 2上形成凸块底 部金属层 9， 并覆盖焊垫 3暴露的部分。 凸块底部金属层 9 可以加强 A1 或 Cu焊垫 3与导电凸块的连接强度。 另外， 凸块底部金属层 9能在防止 焊垫 3与导电凸块互联之间的相互扩散中起作用。 因此， 优选的是， 凸块 底部金属层 9与焊垫 3和钝化层 8具有良好附着， 从而最小化作用到半导 体芯片 2上的应力并用作扩散阻挡层。 此外， 凸块底部金属层 9与焊垫 3 之间的低电阻是优选的。 因此， 在本发明的一实施例中， 凸块底部金属层 9使用 Ti、 Cr、、 W、 Ni、 Au、 Cu、曹、 NiV、 Pd、 Cr/Cu、蕭 /Cu、 TiW/Au, NiV/Cu中至少一种形成， 优选通过溅射或蒸镀完成。 然而， 本发明不限于 此， 凸块底部金属层 9可通过各种制造工艺由各种材料制成。
然后， 如图 7所示， 非导电层 10形成在凸块底部金属层 9上。 任何具 有下述功能的绝缘材料可用作非导电层 10。 即， 在后续用于形成导电凸块 的电镀工艺 （参见图 9 ) 中， 通过阻挡电流流至凸块底部金属层 9, 该绝 缘材料防止在除了凸块底部金属层 9的将形成导电凸块的部分区域之夕卜的 凸块底部金属层 9的其余区域上被电镀。 考虑到非导电层 10与凸块底部 金属层 9之间的附着及构图非导电层 10的方便性， 优选的是， 光致抗蚀 剂被用作非导电层 10。 非导电层 10可利用化学镀、 溅射、 蒸镀、 旋涂、 辊涂（roll-coating )、 狭缝或狭槽模（ slit- or slot-die )、 或类 4以的方法形成。 正或负光致抗蚀剂可用作非导电层 10。在沉积光致抗蚀剂之后， 光致抗蚀 剂通过软烘烤工艺在热炉 （hot plate ) 中固化， 从而去除溶剂。 利用曝光 源和其上形成有图案的掩模， 在固化了的光致抗蚀剂上选棒性地进行曝光 工艺。 然后， 通过硬烘烤工艺， 该光致抗蚀剂在热炉中被热固化， 从而区 别光照射的区域与光未照射的区域。
参照图 8, 当在凸块底部金属层 9上形成非导电层 10后， 非导电层 10 通过光刻蚀刻工艺构图。 结果， 形成非导电层图案 10a, 同时限定了形成 导电凸块（参照图 10的附图标记 4 )的区域。 如图 8所示， 优选的是， 导 电凸块区域在焊垫 3之上。
参照图 9和 10, 导电凸块 4形成在非导电层图案 10a暴露的凸块底部 金属层 9区域上。 首先， 如图 9所示， 导电层 5的形成是通过电镀方法在 凸块底部金属层 9通过非导电层图案 10a暴露的区域上形成一金属层， 当 然不限于电镀方法。 这里， 根据本发明一实施例， 导电层 5的形成过程又 包括两步， 即先沉积一第一种金属材料 5a， 该第一种金属材料 5a由至少 一种选自 Au、 Cu、 Ni、 A1的金属或者这些金属的合金组成，优选的是 Au; 接下来沉积一第二种金属材料 5b， 该第二种金属材料 5b由至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这 些金属的合金组成，且熔点低于第一种金属材料 5a,优选的是 Sn或 Au-Sn 合金。 在本发明的一实施例中， 导电层 5的厚度不低于约 5微米， 其中， 第一种金属材料 5a的优选厚度为 5微米到 20微米， 第二种金属材料 5b 的优选厚度为 0.5微米到 2微米。
随后， 如图 10所示， 在导电层 5表面形成弹性导电层 6。 该弹性导电 层 6的形成是将导电颗粒 7冶金连接到该导电层 5，在本发明一实施例中， 导电颗粒 7是金属颗粒或是表面涂覆金属的树脂颗粒， 或者是两种颗粒的 混合， 为使导电凸块 4具有较大的弹性变形范围， 满足封装结构的可靠性 要求， 优选地， 导电颗粒 7是表面涂覆金属的树脂颗粒。 导电颗粒 7表面 涂覆的金属材料根据本发明一实施例由至少一种选自 Sn、 Au、 Cu、 Pb、 Bi、 Ag、 In、 Al、 Ni、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金组成。 从导电性能来看， 优选 Au, 与组成第二种金属材料 5b的 Sn或 Au-Sn合 金易形成共晶 （eutectic )焊接。 根据本发明的一实施例， 导电层 5与弹性 导电层 6的冶金连接是通过加热完成的， 根据 Au-Sn共晶相图， 优选的加 热温度为 278°C到 320 °C。导电颗粒 7的直径通常在 1微米到 20微米之间， 优选的直径大小为 3微米到 5微米。 当然， 导电层 5与弹性导电层 6的冶 金连接也可以通过加热及加压完成。
然后， 如图 11所示， 非导电层图案 10a通过灰化和剥离工艺去除。 凸 块底部金属层 9根据导电凸块 4的形状被蚀刻， 由此得到根据本发明一实 施例的驱动芯片 1。
其后， 半导体芯片 2 皮切割， 从而驱动芯片 1被分割成若干单独的驱 动芯片。所获得的单独的驱动芯片利用诸如 COG或 COF等方法进行封装， 无需再使用 ACF作为互联介质。
图 12是根据本发明一实施例的驱动芯片导电凸块的弹性导电层的另一 种制造方法的剖面图。 首先， 将导电颗粒 7均匀设置在一平整基板 11的 表面上， 基板 11 需要较硬的质地和较高的耐热温度， 优选玻璃基板或陶 瓷基板。 将焊垫 3上已形成有导电层 5的半导体芯片 2倒扣设置在导电颗 粒 7上， 在加热的同时对半导体芯片 2和基板 11加压， 从而加速导电层 5 和导电颗粒 7之间冶金连接的形成。 其中， 压力的范围应根据导电颗粒 7 的种类和个数来确定， 受压的导电颗粒 7较多，压力可以选裤较大， 反之， 则要减小施加的压力。 对于金属颗粒， 所施加的压力应使大部分导电颗粒 7不发生较大的塑性变形， 而对于表面涂覆金属的树脂颗粒， 所施加的压 力应小于导电颗粒 Ί 在表面金属层不被破坏的条件下所能承受压力的上 限。 本实施例中的半导体芯片 2可以是未切割的晶圆， 也可以是切割后的 单个芯片， 优选的是单个芯片。
尽管在上述实施例中给出了对液晶显示器驱动芯片例子的描述， 但是 显然， 根据本发明实施例的导电凸块的结构可应用于各种芯片。 例如， 根 据本发明的导电凸块的结构可以有益地应用于与平板显示器、 RFID、 电子 标签等产品相关的芯片上。 通常， 在目前的微电子领域当中， 需要通过 ACF或者非导电胶膜 ( Non-Conductive Film, NCF ) 进行互联的各种芯片， 通过采用根据本发明实施例的导电凸块的结构均可得到互联性能的改善。
根据本发明的微电子元件除在芯片领域的应用之外， 还可以应用于多 种其他电路组件当中， 如印刷电路板（PCB )、 柔性电路板（FPC )、 表面 贴装元件（ SMT Components )、微机电系统元件（ MEMS Components )等。 设置于这些电路组件上的导电凸块包括一导电层和一弹性导电层， 其中导 电层与该电路組件上的电路电连接， 弹性导电层与导电层冶金连接。 在本 发明的一实施例中， 导电层是金属层， 由至少一种选自 Sn、 Au、 Cu、 Pb、 Bi、 Ag、 In、 Al、 M、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金組成， 优选 Cu及 Cu的表面镀层， 其中， 表面镀层由 Au、 Ni/Au、 Sn、 Sn/Au或 Sn/Ag/Cu中的至少一种组成。在本发明的一实施例中， 导电层是电路组件 上用于与外界互连的焊盘的一部分， 或在焊盘表面施加一镀层， 与该电路 組件上的电路的材料和厚度基本一致。
上述形成在电路組件上的导电凸块的制造过程与前面描述的驱动芯片 的导电凸块的制造过程示例相似， 但导电层的形成过程和方法会根据电路 组件的不同而变化， 以应用在液晶显示装置当中的柔性电路板为例， 在现 有技术领域里，柔性电路板需要通过 ACF与液晶显示面板组件相连。根据 本发明一实施例的柔性电路板可以直接粘结在液晶显示面板组件上。 该柔 性电路板上导电凸块的导电层的形成根据本发明一实施例与柔性电路板 表面的电路同时， 用同样的方法和同样的材料形成， 优选通过电镀或压延 完成。
图 1至 12描述的根据本发明各种实施例的驱动芯片可以根据各种安装 方法安装在各种结构上。 例如， 通过 COG的方法将驱动芯片直接封装在 带电路的玻璃基板上； 通过 COF的方法将驱动芯片封装在柔性电路板上； 以及通过 COB 的方法将驱动芯片封装于一般的印刷电路板上。 在这些方 法中， 驱动芯片与各种基板之间只需要普通的绝缘粘胶作为互联介质， 起 到支撑， 粘结和保护的作用。
图 13是^据本发明一实施例的驱动芯片在封装结构中应用的示意图。 驱动芯片 1与带电路基板 12通过绝缘粘胶 14粘结起来， 其中驱动芯片 1 上的导电凸块 4与带电路基板 12上的连接端子 13相对放置并电连接。 在 封装过程中，需要将绝缘粘胶 14设置在驱动芯片 1和带电路基板 12之间， 并使导电凸块 4和与之相对应的连接端子 13相对。 在本发明一实施例中， 绝缘粘胶 14具有热固性， 封装过程通过对驱动芯片 1和带电路基板 12加 热及加压完成。 在本发明一实施例中， 绝缘粘胶 14具有光固性， 此时， 带电路基板 12优选透明基板。 封装过程通过对驱动芯片 1和带电路基板 12加压， 以及透过带电路基板 12进行光照完成。 在本发明一实施例中， 绝缘粘胶 14具有压固性， 封装过程通过对驱动芯片 1和带电路基板 12加 压即可完成。 在本发明一实施例中， 绝缘粘胶 14可以采用带状粘胶， 优 选非导电胶膜 ( Non-Conductive Film, NCF ), 封装过程中 , 首先将 NCF贴 敷在带电路基板 12上， 然后对驱动芯片 1和带电路基板 12进行加热及加 压。 在本发明一实施例中， 绝缘粘胶 14 可以采用膏状粘胶， 优选非导电 胶（膏）（ Non-Conductive Paste, NCP )， 封装过程中， 首先将 NCP喷涂在 带电路基板 12上， 然后对驱动芯片 1和带电路基板 12进行加热及加压。 虽然本实施例中描述了根据本发明的驱动芯片在封装结构中的应用， 但本 发明不限于此。 显然， 根据本发明的各种电路组件的封装同样可以使用上 述的封装结构。
图 14为液晶显示装置組件的示意图，其中以 COG和 COF封装的形式 安装了根据本发明实施例的驱动芯片。 本发明的液晶显示面板 15 包括下 基板 16和上基板 17, 下基板 16的伸出部分有铟锡氧化物 （ ITO )形成的 透明电极 18,用于连接外部驱动电路和显示面板各像素的连接电路。其中， 根据本发明一实施例的驱动芯片 1利用 COG方法通过绝缘粘胶 14直接封 装在液晶显示面板 15的下基板 16上， 导电凸块 4与 ITO透明电极 18相 对放置并电连接在一起。 另外， 下基板 16上还安装有柔性电路板元件 19， 其包括柔性膜 20和形成在柔性膜 20上的连接端子 21。根据本发明一实施 例的驱动芯片 1利用 COF方法通过绝缘粘胶 14封装在柔性电路板元件 19 上， 导电凸块 4与连接端子 21相对放置并电连接在一起。 在本发明一实 施例中， 绝缘粘胶 14具有热固性， 优选固化温度低于目前 ACF中高分子 聚合物的固化温度的绝缘粘胶， 这样有助于提高生产效率， 同时还能降低 液晶显示装置在制造过程中由于不同材料的热膨胀系数不同而造成的翘 曲， 提高可靠性。 在本发明一实施例中， 绝缘粘胶 14具有光固性， 由于 下基板 16和柔性电路板元件 19本身透明， 透过光照使绝缘粘胶 14固化， 可以避免由于加热而造成的液晶显示装置中的翘曲， 在本发明一实施例 中， 绝缘粘胶 14具有压固性， 封装过程通过对驱动芯片 1和下基板 16, 或驱动芯片 1和柔性电路板元件 19加压即可完成。 在本发明一实施例中， 绝缘粘胶 14可以采用带状粘胶， 优选 NCF, 封装过程中， 首先将 NCF贴 敷在下基板 16或柔性电路板元件 19上， 然后对驱动芯片 1和下基板 16, 或驱动芯片 1和柔性电路板元件 19进行加热及加压。 在本发明一实施例 中，绝缘粘胶 14可以采用膏状粘胶，优选 NCP，封装过程中，首先将 NCP 喷涂在下基板 16或柔性电路板元件 19上，然后对驱动芯片 1和下基板 16, 或驱动芯片 1和柔性电路板元件 19进行加热及加压。 虽然本实施例中描 述了其中以 COG和 COF封装的形式安装驱动芯片 1的液晶显示面板 15, 但本发明不限于此。 显然， 如图 14所示， 柔性电路板元件 19与液晶显示 面板 15 的连接， 可以替换为根据本发明的柔性电路板通过上述的方法与 液晶显示面板 15的连接。
如上所述， 根据本发明的微电子元件在封装过程中无需使用各向异性 导电胶膜， 所得封装结构或液晶显示装置与使用各向异性导电胶膜的封装 结构或液晶显示装置相比， 具有更低的连接电阻， 同时避免短路发生。
本领域技术人员理解， 在不偏离本发明的原理的情况下， 可以对优选 实施例进行多种变化和修改， 因此， 所公开的本发明的优选实施例只在一 般的和描述的意义上得以使用， 而不用于限制的目的。

Claims

权 利 要 求
1、 一种微电子元件， 包括半导体芯片和设置于所述半导体芯片表面焊 垫上的导电凸块， 其中所述导电凸块包括一导电层和一弹性导电层， 所述 导电层与所述半导体芯片表面焊垫电连接， 所述弹性导电层与所述导电层 冶金连接。
2、 一种微电子元件， 包括电路組件和设置于所述电路組件上的导电凸 块， 其中所述导电凸块包括一导电层和一弹性导电层， 所述导电层与所述 电路组件上的电路电连接， 所述弹性导电层与所述导电层冶金连接。
3、 根据权利要求 1或 2的微电子元件， 其中所述导电层是金属层， 由 至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga 的金属或者这些金属的合金组成。
4、 根据权利要求 1或 2的微电子元件， 其中所述导电层的厚度不低于 约 5微米。
5、 根据权利要求 1或 2的微电子元件， 其中所述弹性导电层由导电颗 粒组成。
6、 根据权利要求 5的微电子元件， 其中所述导电颗粒是金属颗粒或是 表面涂覆金属的树脂颗粒。
7、 根据权利要求 1的微电子元件， 其中所述半导体芯片的焊垫和所述 导电凸块之间有凸块底部金属层。
8、 一种封装结构， 包含微电子元件， 所述微电子元件包括半导体芯片 和设置于所述半导体芯片表面焊垫上的导电凸块， 其中所述导电凸块包括 一导电层和一弹性导电层， 所述导电层与所述半导体芯片表面焊垫电连 接， 所述弹性导电层与所述导电层冶金连接， 所述 电子元件与带电路基 板粘结， 微电子元件的导电凸块与带电路基板的连接端子相对放置并电连 接。
9、 一种封装结构， 包含微电子元件， 所述微电子元件包括电路組件和 设置于所述电路組件上的导电凸块， 其中所述导电凸块包括一导电层和一 弹性导电层， 所述导电层与所述电路組件上的电路电连接， 所述弹性导电 层与所述导电层冶金连接。 所述微电子元件与带电路基板粘结， 微电子元 件的导电凸块与带电路基板的连接端子相对放置并电连接。
10、 根据权利要求 8或 9的封装结构， 其中所述导电层是金属层， 由 至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga 的金属或者这些金属的合金組成。
11、 根据权利要求 8或 9的封装结构， 其中所述导电层的厚度不低于 约 5 «t。
12、 根椐权利要求 8或 9的封装结构， 其中所述弹性导电层由导电颗 粒組成。
13、 根据权利要求 12的封装结构， 其中所述导电颗粒是金属颗粒或是 表面涂覆金属的树脂颗粒。
14、 根据权利要求 8的封装结构， 其中所述半导体芯片的焊垫和所述 导电凸块之间有凸块底部金属层。
15、 一种液晶显示装置， 包含 电子元件， 所述^：电子元件包括半导 体芯片和设置于所述半导体芯片表面悍垫上的导电凸块， 其中所述导电凸 块包括一导电层和一弹性导电层， 所述导电层与所述半导体芯片表面焊垫 电连接， 所述弹性导电层与所述导电层冶金连接， 所述微电子元件与液晶 显示面板组件粘结， 微电子元件的导电凸块与液晶显示面板组件的连接端 子相对放置并电连接。
16、 一种液晶显示装置， 包含 电子元件， 所述微电子元件包括电路 组件和设置于所述电路组件上的导电凸块， 其中所述导电凸块包括一导电 层和一弹性导电层， 所述导电层与所述电路組件上的电路电连接， 所述弹 性导电层与所述导电层冶金连接， 所述微电子元件与液晶显示面板组件粘 结， 微电子元件的导电凸块与液晶显示面板组件的连接端子相对放置并电 连接。
17、 根据权利要求 15或 16的液晶显示装置， 其中所述导电层是金属 层， 由至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的合金組成。
18、 根据权利要求 15或 16的液晶显示装置， 其中所述导电层的厚度 不低于约 5微米。
19、 根据权利要求 15或 16的液晶显示装置， 其中所述弹性导电层由 导电颗粒組成。
20、根据权利要求 19的液晶显示装置， 其中所述导电颗粒是金属颗粒 或是表面涂覆金属的树脂颗粒。
21、根据权利要求 15的液晶显示装置， 其中所述半导体芯片的焊埜和 所述导电凸块之间有凸块底部金属层。
22、 一种微电子元件的制造方法， 其中包括以下步骤：
(a)提供一表面具有焊垫的半导体芯片， 沉积一导电层于该半导体芯 片表面的焊垫上；
(b)形成一弹性导电层于该导电层之上， 该弹性导电层与该导电层冶 金连接， 得到所述微电子元件。
23、 一种微电子元件的制造方法， 其中包括以下步骤：
(aa)提供一半导体芯片， 该半导体芯片表面包括焊垫， 形成一凸块 底部金属层于该半导体芯片表面的焊垫上；
(bb) 形成一非导电层于该凸块底部金属层及半导体芯片表面上， 并 图案化该非导电层， 以形成至少一开口， 该开口暴露该凸块底部金属层；
(cc)在所述开口中形成一导电层；
(dd)在所述导电层上形成一弹性导电层， 该弹性导电层与该导电层 冶金连接；
(ee)去除所述非导电层， 得到所述微电子元件。
24、 一种微电子元件的制造方法， 其中包括以下步骤：
(aaa)提供一电路组件， 沉积一导电层于该电路组件表面上， 并使该 导电层与该电路组件上的电路电连接；
(bbb)形成一弹性导电层于该导电层上， 该弹性导电层和该导电层冶 金连接， 得到所述微电子元件。
25、 根据权利要求 22或 23的制造方法， 其中所述导电层的形成是通 过电镀方法形成一金属层。
26、 ^^据权利要求 22或 23的制造方法， 其中所述导电层的形成包括 下歹 ij两步：
( 1 )沉积一第一种金属材料， 该金属材料是至少一种选自 Au、 Cu、 Ni、 A1的金属或者这些金属的合金；
( 2 )沉积一第二种金属材料， 该金属材料是至少一种选自 Au、 Cu、 Al、 Ni、 Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的金属或者这些金属的 合金， 其中， 该第二种金属材料的熔点低于该笫一种金属材料的熔点。
27、 根据权利要求 24的制造方法， 其中所述导电层的沉积是与电路组 件上的电路同时， 用同样的方法和同样的材料形成。
28、 根据权利要求 24的制造方法， 其中所述导电层的沉积是利用至少 一种选自 Au、 Cu、 Al、 Ni Sn、 Pb、 Bi、 Ag、 In、 Sb、 Cd、 Zn、 Ga的 金属或者这些金属的合金形成的。
29、 根据权利要求 22、 23或 24的制造方法， 其中所述弹性导电层的 形成是将导电颗粒冶金连接到该导电层。
30、 根据权利要求 22、 23或 24的制造方法， 其中所述弹性导电层与 导电层的冶金连接是通过加热形成， 或加热及加压形成。
31、 根据权利要求 29的制造方法， 其中所述导电颗粒是金属颗粒或是 表面涂覆金属的树脂颗粒。
PCT/CN2008/000226 2007-02-01 2008-01-30 Élément microélectronique et procédé de fabrication correspondant WO2008095405A1 (fr)

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