US8576368B2 - Driving circuit for a liquid crystal display device, method of manufacturing the same and display device having the same - Google Patents

Driving circuit for a liquid crystal display device, method of manufacturing the same and display device having the same Download PDF

Info

Publication number
US8576368B2
US8576368B2 US11/986,594 US98659407A US8576368B2 US 8576368 B2 US8576368 B2 US 8576368B2 US 98659407 A US98659407 A US 98659407A US 8576368 B2 US8576368 B2 US 8576368B2
Authority
US
United States
Prior art keywords
driving circuit
conductive
bump
layer
conductive particle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/986,594
Other versions
US20080180376A1 (en
Inventor
Yun-Hee Kim
Ho-Min Kang
Jong-Sig HYUN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HYUN, JONG-SIG, KANG, HO-MIN, KIM, YUN-HEE
Publication of US20080180376A1 publication Critical patent/US20080180376A1/en
Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG ELECTRONICS CO., LTD.
Application granted granted Critical
Publication of US8576368B2 publication Critical patent/US8576368B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11332Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/2939Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29399Coating material
    • H01L2224/294Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/29698Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29798Fillers
    • H01L2224/29799Base material
    • H01L2224/2989Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01059Praseodymium [Pr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/102Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by bonding of conductive powder, i.e. metallic powder

Definitions

  • the present invention relates to a driving circuit for a liquid crystal display (LCD) device. More particularly, the present invention relates to a driving circuit for an LCD device, a method of manufacturing the driving circuit and a display device having the driving circuit.
  • LCD liquid crystal display
  • a liquid crystal display (LCD) device has advantageous characteristics such as reduced thickness, light weight, low power consumption, and has good resolution, color reproducibility, and display quality.
  • the LCD device which is a type of flat panel display device, is being widely used and intensively researched.
  • the LCD device typically includes an LCD panel having a thin-film transistor (TFT) array substrate, a color filter substrate, a liquid crystal layer located between the TFT array substrate and the color filter substrate, a backlight assembly disposed under the LCD panel to serve as a light source, and a driving circuit part disposed at a peripheral portion of the LCD panel to drive the LCD panel.
  • the LCD panel includes two glass substrates (the TFT array substrate and the color filter substrate mentioned above), a plurality of pixels disposed between the two glass substrates and arranged in a matrix shape on the thin-film transistor (TFT) array substrate and for each pixel a switching element such as a TFT for controlling signals provided to the pixel.
  • the driving circuit part includes a printed circuit board (PCB) on which parts for generating various signals such as a control signal, a clock signal, and a data signal, are mounted.
  • a driving circuit that is an LCD driver integrated circuit (IC) (LDI) is connected to the LCD panel and the PCB to apply a signal to wirings formed on the LCD panel.
  • the LCD driver integrated circuit includes a set of bonding pads with each bonding pad including a metal bump.
  • the surface to which the driver integrated circuit is to be mounted is provided with a matching set of pads.
  • the driver integrated circuit is mounted on the surface by bonding the set of bonding pads to the matching set of pads.
  • Examples of LDI mounting methods include chip-on-glass (COG), tape carrier package (TCP), and chip-on-film (COF).
  • COG chip-on-glass
  • TCP tape carrier package
  • COF chip-on-film
  • the LDI mounting methods require fine pad pitch bonding, an easy bonding process and high reliability, especially with the increasing complexity of an LDI chip arising from, for example increases in the number of pixels and high resolution.
  • a method of forming a bump and a method of fine pad pitch bonding are key technologies.
  • the driving circuit and the LCD panel are electrically connected to each other through the conventional ACF.
  • the AFC comprises electrically conductive particles dispersed in a non-conductive film.
  • the ACF is adhered to the glass TFT array substrate and the driver IC is bonded to the ACF. Thereafter, in a final bonding process, a plurality of conductive particles flows in the ACF and some of the conductive particles are captured between the bumps and the pads on the TFT array substrate, thereby electrically connecting the driving circuit to the pads and to wiring on the TFT array substrate.
  • the pitch of a COG chip becomes finer as an LCD device becomes smaller, lighter and thinner, and the pitch of an outer lead bonding (OLB) or a film-on-glass (FOG) bonding also becomes finer.
  • OLB outer lead bonding
  • FOG film-on-glass
  • an agglomeration of the conductive particles may extend from one bump to an adjacent bump, thus forming an electrical connection between the bumps to cause an electrical short defect.
  • the area of the bumps decreases the number of conductive particles trapped between a pad and a bump decreases. Indeed, the number of captured conductive particles may be zero, the lack of the conductive particles causing an electrical open defect after the COG bonding.
  • the above-mentioned defects may be found during manufacture of an LCD or they may be found by end users of a LCD device after some time has elapsed. Thus, yield and reliability may be degraded.
  • the present invention provides a driving circuit for a liquid crystal display (LCD) device capable of easily being electrically connected to the LCD device through bonding pads in which conductive particles are disposed on a bump.
  • LCD liquid crystal display
  • the present invention further provides a method of manufacturing the driving circuit.
  • the present invention still further provides an LCD device having the driving circuit.
  • a driving circuit includes a resin layer formed on a bump on an integrated circuit (IC) pad electrode, and a conductive particle deposited on and coupled to the resin layer.
  • the resin layer is electrically conductive and the conductive particle adheres to the resin layer.
  • the conductive particle may have, for example, a spherical shape, a hexahedron shape, a tetrahedron shape or any suitable shape.
  • the conductive particle includes an outer portion comprising an electrically conductive material and an inner portion comprising an elastic material such as an elastic polymer.
  • the elastic material may be compressed during bonding so as to prevent an electrical connection defect due to height differences between individual bumps in a plurality of bumps.
  • a driving circuit for an LCD device includes an integrated circuit IC, an electrode pad, a bump and a conductive particle.
  • the IC generates a signal.
  • the electrode pad is formed on the IC to externally transmit the signal.
  • the bump is formed on the electrode pad to receive the signal.
  • the conductive particle is disposed on the bump to electrically connect the bump to an external electronic device.
  • the driving circuit may further include a resin layer between the bump and the conductive particle.
  • the resin layer is electrically conductive.
  • the conductive particle may include an outer layer including an electrically conductive material and an inner portion including an elastic polymer material.
  • the electrically conductive material may include at least one of the metals gold (Au) and nickel (Ni).
  • a method of manufacturing a driving circuit for an LCD device is provided as follows.
  • An electrode pad is formed on an integrated circuit chip portion of a wafer.
  • a first passivation layer is formed on the chip.
  • An opening is provided in the passivation layer to expose a portion of the pad.
  • a second passivation layer is formed on the first passivation layer.
  • An opening in the second passivation layer is provided to again expose the portion of the pad.
  • a metal layer is formed on the second passivation layer and on the exposed portion of the pad.
  • a photoresist pattern having an opening corresponding to the pad is formed. The opening is filled with metal to form a bump.
  • a resin layer having electrical conductivity is formed on the bump and the photoresist pattern. Conductive particles are sprayed onto the resin layer. The photoresist pattern is removed such that the conductive particles remain only on the bump.
  • the conductive particles may be sprayed onto the resin layer by using an ink jet or a fine nozzle.
  • Each of the conductive particles may include an outer layer including an electrical conductive material and an inner portion including an elastic polymer material.
  • an LCD device in another exemplary embodiment, includes a driving circuit, a thin-film transistor (TFT) array substrate, a color filter substrate and a liquid crystal layer.
  • the driving circuit includes an IC, an electrode pad, a bump and a conductive particle.
  • the IC generates a signal.
  • the electrode pad is formed on the IC to externally transmit the signal.
  • the bump is formed on the electrode pad to receive the signal.
  • the conductive particle is disposed on the bump.
  • the TFT array substrate includes a pad electrically connected to the bump of the driving circuit through the conductive particle of the driving circuit.
  • the color filter substrate faces the TFT array substrate.
  • the liquid crystal layer is disposed between the TFT array substrate and the color filter substrate.
  • the driving circuit may include a plurality of bumps electrically insulated from each other.
  • the LCD device may further include a non-conductive adhesive configured to adhere the bump of the driving circuit to the TFT array substrate.
  • the non-conductive adhesive may include one of a non-conductive film, a non-conductive paste, an ultraviolet adhesive and an epoxy group adhesive.
  • the conductive particle may include an outer layer including an electrically conductive material and an inner portion including an elastic polymer material.
  • the electrically conductive material may include at least one metal selected from the group consisting of gold and nickel.
  • FIG. 1 is an exploded perspective view illustrating a liquid crystal display (LCD) panel according to an exemplary embodiment of the present invention
  • FIG. 2 is a cross-sectional view illustrating a conventional driving circuit for an LCD device
  • FIG. 3 is a photomicrograph illustrating an electrical open defect that is generated at a bump when the conventional driving circuit is mounted on an LCD panel;
  • FIG. 4 is a photomicrograph illustrating an electrical short defect that is generated at a bump when the conventional driving circuit is mounted on the LCD panel;
  • FIGS. 5 to 10 are cross-sectional views illustrating a method of manufacturing a driving circuit according to an exemplary embodiment of the present invention.
  • FIG. 10 also shows in cross-section a driving circuit in accordance with an exemplary embodiment of the present invention
  • FIGS. 11A and 11B are cross-sectional views illustrating conductive particles used in a driving circuit according to an exemplary embodiment of the present invention.
  • FIG. 12 is a cross-sectional view illustrating a method of mounting a conventional driving circuit on an LCD device by using an anisotropic conductive film (ACF);
  • ACF anisotropic conductive film
  • FIG. 13 is a cross-sectional view illustrating a structure of the conventional driving circuit on an LCD device by using the ACF;
  • FIG. 14 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive film (NCF);
  • NCF non-conductive film
  • FIG. 15 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive paste (NCP); and
  • FIG. 16 is a cross-sectional view illustrating a structure in which a driving circuit is attached to an LCD device according to an embodiment of the present invention.
  • first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • FIG. 1 is an exploded perspective view illustrating a liquid crystal display (LCD) panel according to an exemplary embodiment of the present invention.
  • LCD liquid crystal display
  • an LCD device includes a color filter substrate 7 , a thin-film transistor (TFT) array substrate 1 and a liquid crystal layer 5 interposed between the color filter substrate 7 and the TFT array substrate 1 .
  • TFT thin-film transistor
  • the color filter substrate 7 includes a color filter layer having red, green and blue color filters 9 , a black matrix 8 dividing the color filters and blocking light passing through the liquid crystal layer 5 , and a transparent common electrode 6 for applying a voltage to the liquid crystal layer 5 .
  • Gate lines and data lines are horizontally and vertically formed on the TFT array substrate 1 . Pixel areas are defined between the intersections of gate and data lines on the TFT array substrate 1 .
  • a TFT switching element is formed in each pixel area. The TFT switching elements are located adjacent to intersections between the gate lines 2 and the data lines 3 .
  • a pixel electrode is also formed in each pixel area. Each TFT switching element controls the application of a data voltage to its associated pixel electrode.
  • Each pixel area corresponds to one of the color filters 9 of the color filter substrate 7 .
  • a full color image may be obtained by combining red, green and blue colors.
  • the color filters 9 are arranged in groups of three including red, green and blue to produce full color images.
  • FIG. 2 is a cross-sectional view illustrating a conventional driving circuit that is used in an LCD device.
  • Electrodes 23 are formed on the driving circuit 21 .
  • a bump 25 is formed on each of the electrodes 23 .
  • the bumps are to be directly electrically connected to pads provided on a TFT array substrate in an LCD device.
  • FIG. 3 is a photomicrograph showing an electrical open circuit defect that occurred at a bump when a conventional driving circuit was mounted on an LCD device.
  • FIG. 4 is a photomicrograph showing a cross-sectional view of an electrical short circuit defect that occurred between two bumps when a conventional driving circuit was mounted on an LCD device.
  • an agglomeration of the conductive particles 35 may form an electrical connection between adjacent bumps 25 to cause an electrical short circuit defect (refer to FIG. 4 ).
  • conductive particles 35 are present on all the bumps 25 but are absent from bump 25 a . The reduction of the areas of the bumps 25 leads to a lack of the conductive particles 35 and an electrical open circuit defect after the COG bonding.
  • FIGS. 5 to 10 are cross-sectional views illustrating a method of manufacturing a driving circuit according to an exemplary embodiment of the present invention.
  • FIGS. 5-10 show cross sections of the driving circuit that is part of a wafer (not shown) containing many such driving circuits, the wafer being later divided into individual driving circuits like the one shown in FIGS. 5-10 .
  • a chip 41 contains circuits (not shown) that are required to provide the functions of a driving circuit.
  • the chip 41 may be referred to as an integrated circuit 41 .
  • Electrode pads 43 are formed on the chip 41 . These electrode pads 43 provide electrical connections to chip 41 , with some of electrode pads dedicated to receiving signals, other electrode pads dedicated to outputting signals and others providing power and ground connections.
  • a passivation layer 45 is formed on chip 41 and on the electrode pads 43 . Openings are provided in the passivation layer 45 to expose a portion of each electrode pad 43 .
  • a layer of electrically insulating material such as a polyimide layer 47 is formed on the passivation layer 45 . Openings are provided in the polyimide layer 47 so that the open portion of each electrode pad 43 is again exposed.
  • the layer 47 may hereinafter be referred to as a second insulating layer 47 .
  • an under bump metallurgy (UBM) layer 49 is formed on the chip 41 having the passivation layer 45 and the polyimide layer 47 .
  • the under bump metallurgy layer 49 is optional.
  • a photoresist pattern 51 is formed on the UBM layer 49 .
  • the photoresist pattern 51 has openings A corresponding to the electrode pads 43 .
  • the photoresist pattern 51 may be obtained by using a positive type photoresist material. Alternatively, the photoresist pattern 51 may be obtained by using a negative type photoresist material.
  • an electroplating operation is performed so that the openings in the photoresist pattern 51 are filled with metal, to thereby form bumps 53 .
  • metals suitable for forming the bumps 53 include gold (Au) and nickel (Ni) and may include other suitable metals. These metals may be used alone or in a combination thereof.
  • an adhesive material is coated on the photoresist pattern 51 and on the bumps 53 to form an adhesive layer 60 .
  • the adhesive material may comprise a resin material and the adhesive layer 60 may hereinafter be referred to as a resin layer 60 .
  • the adhesive material includes an electrically conductive material so that conductive particles 30 deposited on the bumps 53 are in good electrical contact with the electrode pads 43 . Examples of the electrically conductive material used in the adhesive layer 60 may include silver paste.
  • each of the conductive particles 30 includes an outer portion including at least one layer of metal, and an inner portion comprising an elastic material such as an elastic polymer.
  • the outer portion may include a single metal layer, or may include a first metal layer and a second metal layer that are different in composition from each other. Examples of the metal forming the outer portion may include gold (Au), nickel (Ni), or copper (Cu). These metals may be used alone or in a combination thereof.
  • An ink jet or fine nozzle or other suitable device may be used to uniformly apply the conductive particles 30 to the adhesive layer 60 , thereby increasing uniformity of the distribution of the conductive particles 30 .
  • the photoresist pattern 51 is removed, and the UBM layer 49 (if present) is etched so that the UBM layer 49 remains only under the bump 53 .
  • the driving circuit 40 comprises an integrated circuit 41 , electrode pads 43 formed on the integrated circuit 41 , bumps 53 formed on the electrode pads 43 , a conductive adhesive layer 60 formed on the bumps 53 and conductive particles 30 deposited on the adhesive layer 60 .
  • FIGS. 11A and 11B are cross-sectional views illustrating a conductive particle as used in a driving circuit according to an exemplary embodiment of the present invention.
  • FIGS. 11A and 11B illustrate shapes and structures of the conductive particles 30 .
  • a conductive particle 30 a includes an outer portion comprising a layer 31 including an electrically conductive material such as a metal.
  • the conductive particle 30 a also includes an inner portion 34 a including an elastic material such as an elastic polymer.
  • a conductive particle 30 b includes an outer portion including a first metal layer 31 and a second metal layer 32 that are different from each other in their composition, and an inner portion 34 b comprising an elastic material such as an elastic polymer.
  • the metal forming the outer portion may include gold (Au), nickel (Ni), and copper (Cu). These may be used alone or in a combination thereof. Alternatively, other metal materials having excellent electrical conductivity may be employed in the metal layers.
  • FIG. 12 is a cross-sectional view illustrating a method of mounting a conventional driving circuit on an LCD device by using an anisotropic conductive film (ACF).
  • FIG. 13 is a cross-sectional view illustrating a structure of the conventional driving circuit on the LCD device by using the ACF.
  • a driving circuit 70 and an LCD panel are electrically connected to each other through an ACF 90 .
  • the ACF 90 is adhered to the TFT array substrate 81 , which may be a glass substrate, and the driving circuit 70 is bonded to the ACF 90 .
  • a plurality of conductive particles 35 flows in the ACF 90 and some of the particles are captured between a bump 75 and a pad 83 on the TFT array substrate 81 , thereby electrically connecting the driving circuit 70 to the pad 83 on the TFT array substrate 81 .
  • FIG. 14 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive film (NCF).
  • FIG. 15 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive paste (NCP).
  • FIG. 16 is a cross-sectional view illustrating a structure of the driving circuit according to an exemplary embodiment of the present invention on an LCD device.
  • the driving circuit 40 having the conductive particles 30 formed on the bump 53 is mounted on a TFT array substrate 81 of an LCD panel.
  • the TFT array substrate 81 is cleaned so that foreign substances may not be present on the TFT array substrate 81 .
  • an NCF 70 or an NCP 75 is bonded on a pad 83 formed on the TFT array substrate 81 .
  • the NCF 70 and the NCP 75 are adhesive and non-conductive.
  • the non-conductive adhesive may include a non-conductive film, a non-conductive paste, an ultra-violet curable adhesive or an epoxy group adhesive.
  • the bump 53 on the driving circuit is bonded on the pad 83 on which the NCF 70 or the NCP 75 is bonded.
  • the conductive particles 30 electrically connect the bump 53 and the pad 83 to each other in response to the application of pressure during the final bonding as shown in FIG. 16 .
  • the inner elastic portions 34 a and 34 b may compensate for the irregularity, thereby maintaining a stable electrical connection.
  • a conductive particle is disposed on a bump of a driving circuit for an LCD device to improve electrical contact between an LCD panel and the driving circuit.
  • the conductive particle includes an inner portion comprising an elastic material, the conductive particle including the elastic polymer inner portion may compensate the irregularity between bumps, although the distance between the bumps is irregular.
  • the driving circuit is mounted on the LCD panel, a stable electrical connection may be obtained to reduce electrical connection resistance and prevent reliability defects.
  • the conductive particles are not disposed between the bumps and thus electrical short circuits between bumps are precluded.
  • the bump may be electrically connected to the pad of the LCD panel through the conductive particle by the compression of the conductive particles to prevent an electrical open defect.
  • the bumps may have a fine pitch, so that chip size may be reduced to increase the number of net dies per wafer, thereby reducing manufacturing cost.
  • the driving circuit may be applied to an LCD display IC (LDI) having a fine pitch.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Wire Bonding (AREA)

Abstract

A driving circuit for a liquid crystal display, the driving circuit being an integrated circuit having electrode pads disposed on a surface of the integrated circuit, bumps formed on the electrode pads, a conductive adhesive layer formed on the bumps and conductive particles having an outer conductive layer and an elastic polymer inner portion deposited on the conductive adhesive layer. The driving circuit is mounted on a TFT array substrate and bonded to pads provided on the substrate. The conductive particles reduce electrical connection resistance that would otherwise arise due to height differences between bumps in a plurality of bumps, and prevents electrical open defects and an electrical short defects.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims the benefit of priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2006-115743, filed on Nov. 22, 2006 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving circuit for a liquid crystal display (LCD) device. More particularly, the present invention relates to a driving circuit for an LCD device, a method of manufacturing the driving circuit and a display device having the driving circuit.
2. Description of the Related Art
A liquid crystal display (LCD) device has advantageous characteristics such as reduced thickness, light weight, low power consumption, and has good resolution, color reproducibility, and display quality. Thus, the LCD device, which is a type of flat panel display device, is being widely used and intensively researched.
The LCD device typically includes an LCD panel having a thin-film transistor (TFT) array substrate, a color filter substrate, a liquid crystal layer located between the TFT array substrate and the color filter substrate, a backlight assembly disposed under the LCD panel to serve as a light source, and a driving circuit part disposed at a peripheral portion of the LCD panel to drive the LCD panel. The LCD panel includes two glass substrates (the TFT array substrate and the color filter substrate mentioned above), a plurality of pixels disposed between the two glass substrates and arranged in a matrix shape on the thin-film transistor (TFT) array substrate and for each pixel a switching element such as a TFT for controlling signals provided to the pixel.
The driving circuit part includes a printed circuit board (PCB) on which parts for generating various signals such as a control signal, a clock signal, and a data signal, are mounted. A driving circuit that is an LCD driver integrated circuit (IC) (LDI) is connected to the LCD panel and the PCB to apply a signal to wirings formed on the LCD panel. The LCD driver integrated circuit includes a set of bonding pads with each bonding pad including a metal bump. The surface to which the driver integrated circuit is to be mounted is provided with a matching set of pads. The driver integrated circuit is mounted on the surface by bonding the set of bonding pads to the matching set of pads.
Examples of LDI mounting methods include chip-on-glass (COG), tape carrier package (TCP), and chip-on-film (COF). The LDI mounting methods require fine pad pitch bonding, an easy bonding process and high reliability, especially with the increasing complexity of an LDI chip arising from, for example increases in the number of pixels and high resolution. Thus, a method of forming a bump and a method of fine pad pitch bonding are key technologies.
When a conventional driving circuit is mounted on an LCD panel by using an anisotropic conductive film (ACF), the driving circuit and the LCD panel are electrically connected to each other through the conventional ACF. The AFC comprises electrically conductive particles dispersed in a non-conductive film. In the connection through the conventional ACF, the ACF is adhered to the glass TFT array substrate and the driver IC is bonded to the ACF. Thereafter, in a final bonding process, a plurality of conductive particles flows in the ACF and some of the conductive particles are captured between the bumps and the pads on the TFT array substrate, thereby electrically connecting the driving circuit to the pads and to wiring on the TFT array substrate. However, only about 10 to 30 percent of an original amount of the conductive particles are captured in the manner described, and thus much of the conductive particles are wasted. In addition, as the area of the bumps is made smaller, the number of conductive particles trapped between the bumps and the pads becomes smaller and thereby increases the resistance of the electrical connections between the bumps and the pads.
The pitch of a COG chip becomes finer as an LCD device becomes smaller, lighter and thinner, and the pitch of an outer lead bonding (OLB) or a film-on-glass (FOG) bonding also becomes finer.
When an interval between bumps of a COG chip is less than or equal to about 15 μm, an agglomeration of the conductive particles may extend from one bump to an adjacent bump, thus forming an electrical connection between the bumps to cause an electrical short defect. As noted above, as the area of the bumps decreases the number of conductive particles trapped between a pad and a bump decreases. Indeed, the number of captured conductive particles may be zero, the lack of the conductive particles causing an electrical open defect after the COG bonding.
The above-mentioned defects may be found during manufacture of an LCD or they may be found by end users of a LCD device after some time has elapsed. Thus, yield and reliability may be degraded.
SUMMARY OF THE INVENTION
The present invention provides a driving circuit for a liquid crystal display (LCD) device capable of easily being electrically connected to the LCD device through bonding pads in which conductive particles are disposed on a bump.
The present invention further provides a method of manufacturing the driving circuit.
The present invention still further provides an LCD device having the driving circuit.
In one aspect of the present invention, a driving circuit includes a resin layer formed on a bump on an integrated circuit (IC) pad electrode, and a conductive particle deposited on and coupled to the resin layer. The resin layer is electrically conductive and the conductive particle adheres to the resin layer.
The conductive particle may have, for example, a spherical shape, a hexahedron shape, a tetrahedron shape or any suitable shape. The conductive particle includes an outer portion comprising an electrically conductive material and an inner portion comprising an elastic material such as an elastic polymer. The elastic material may be compressed during bonding so as to prevent an electrical connection defect due to height differences between individual bumps in a plurality of bumps.
In a first exemplary embodiment, a driving circuit for an LCD device includes an integrated circuit IC, an electrode pad, a bump and a conductive particle. The IC generates a signal. The electrode pad is formed on the IC to externally transmit the signal. The bump is formed on the electrode pad to receive the signal. The conductive particle is disposed on the bump to electrically connect the bump to an external electronic device.
The driving circuit may further include a resin layer between the bump and the conductive particle. The resin layer is electrically conductive.
The conductive particle may include an outer layer including an electrically conductive material and an inner portion including an elastic polymer material.
The electrically conductive material may include at least one of the metals gold (Au) and nickel (Ni).
In another embodiment of the invention, a method of manufacturing a driving circuit for an LCD device is provided as follows. An electrode pad is formed on an integrated circuit chip portion of a wafer. A first passivation layer is formed on the chip. An opening is provided in the passivation layer to expose a portion of the pad. A second passivation layer is formed on the first passivation layer. An opening in the second passivation layer is provided to again expose the portion of the pad. A metal layer is formed on the second passivation layer and on the exposed portion of the pad. A photoresist pattern having an opening corresponding to the pad is formed. The opening is filled with metal to form a bump. A resin layer having electrical conductivity is formed on the bump and the photoresist pattern. Conductive particles are sprayed onto the resin layer. The photoresist pattern is removed such that the conductive particles remain only on the bump.
The conductive particles may be sprayed onto the resin layer by using an ink jet or a fine nozzle.
Each of the conductive particles may include an outer layer including an electrical conductive material and an inner portion including an elastic polymer material.
In another exemplary embodiment, an LCD device includes a driving circuit, a thin-film transistor (TFT) array substrate, a color filter substrate and a liquid crystal layer. The driving circuit includes an IC, an electrode pad, a bump and a conductive particle. The IC generates a signal. The electrode pad is formed on the IC to externally transmit the signal. The bump is formed on the electrode pad to receive the signal. The conductive particle is disposed on the bump. The TFT array substrate includes a pad electrically connected to the bump of the driving circuit through the conductive particle of the driving circuit. The color filter substrate faces the TFT array substrate. The liquid crystal layer is disposed between the TFT array substrate and the color filter substrate.
The driving circuit may include a plurality of bumps electrically insulated from each other.
The LCD device may further include a non-conductive adhesive configured to adhere the bump of the driving circuit to the TFT array substrate.
The non-conductive adhesive may include one of a non-conductive film, a non-conductive paste, an ultraviolet adhesive and an epoxy group adhesive.
The conductive particle may include an outer layer including an electrically conductive material and an inner portion including an elastic polymer material.
The electrically conductive material may include at least one metal selected from the group consisting of gold and nickel.
BRIEF DESCRIPTION OF THE DRAWINGS
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the U.S. Patent and Trademark Office upon request and payment of the necessary fee.
The above and other features and advantages of the present invention will become more apparent based on the following detailed description of exemplary embodiments thereof, taken with reference to the accompanying drawings, in which:
FIG. 1 is an exploded perspective view illustrating a liquid crystal display (LCD) panel according to an exemplary embodiment of the present invention;
FIG. 2 is a cross-sectional view illustrating a conventional driving circuit for an LCD device;
FIG. 3 is a photomicrograph illustrating an electrical open defect that is generated at a bump when the conventional driving circuit is mounted on an LCD panel;
FIG. 4 is a photomicrograph illustrating an electrical short defect that is generated at a bump when the conventional driving circuit is mounted on the LCD panel;
FIGS. 5 to 10 are cross-sectional views illustrating a method of manufacturing a driving circuit according to an exemplary embodiment of the present invention. FIG. 10 also shows in cross-section a driving circuit in accordance with an exemplary embodiment of the present invention;
FIGS. 11A and 11B are cross-sectional views illustrating conductive particles used in a driving circuit according to an exemplary embodiment of the present invention;
FIG. 12 is a cross-sectional view illustrating a method of mounting a conventional driving circuit on an LCD device by using an anisotropic conductive film (ACF);
FIG. 13 is a cross-sectional view illustrating a structure of the conventional driving circuit on an LCD device by using the ACF;
FIG. 14 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive film (NCF);
FIG. 15 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive paste (NCP); and
FIG. 16 is a cross-sectional view illustrating a structure in which a driving circuit is attached to an LCD device according to an embodiment of the present invention.
DESCRIPTION OF THE EMBODIMENTS
The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is an exploded perspective view illustrating a liquid crystal display (LCD) panel according to an exemplary embodiment of the present invention.
As shown in FIG. 1, an LCD device includes a color filter substrate 7, a thin-film transistor (TFT) array substrate 1 and a liquid crystal layer 5 interposed between the color filter substrate 7 and the TFT array substrate 1.
The color filter substrate 7 includes a color filter layer having red, green and blue color filters 9, a black matrix 8 dividing the color filters and blocking light passing through the liquid crystal layer 5, and a transparent common electrode 6 for applying a voltage to the liquid crystal layer 5.
Gate lines and data lines are horizontally and vertically formed on the TFT array substrate 1. Pixel areas are defined between the intersections of gate and data lines on the TFT array substrate 1. A TFT switching element is formed in each pixel area. The TFT switching elements are located adjacent to intersections between the gate lines 2 and the data lines 3. A pixel electrode is also formed in each pixel area. Each TFT switching element controls the application of a data voltage to its associated pixel electrode.
Each pixel area corresponds to one of the color filters 9 of the color filter substrate 7. A full color image may be obtained by combining red, green and blue colors. On the color filter substrate, the color filters 9 are arranged in groups of three including red, green and blue to produce full color images.
FIG. 2 is a cross-sectional view illustrating a conventional driving circuit that is used in an LCD device.
Electrodes 23 are formed on the driving circuit 21. A bump 25 is formed on each of the electrodes 23. The bumps are to be directly electrically connected to pads provided on a TFT array substrate in an LCD device.
FIG. 3 is a photomicrograph showing an electrical open circuit defect that occurred at a bump when a conventional driving circuit was mounted on an LCD device.
FIG. 4 is a photomicrograph showing a cross-sectional view of an electrical short circuit defect that occurred between two bumps when a conventional driving circuit was mounted on an LCD device.
Referring to FIGS. 3 and 4, two types of defects are apparent. When an interval between bumps 25 on a COG chip is less than or equal to about 15 μm, an agglomeration of the conductive particles 35 may form an electrical connection between adjacent bumps 25 to cause an electrical short circuit defect (refer to FIG. 4). As shown in FIG. 3, conductive particles 35 are present on all the bumps 25 but are absent from bump 25 a. The reduction of the areas of the bumps 25 leads to a lack of the conductive particles 35 and an electrical open circuit defect after the COG bonding.
Hereinafter, a method of manufacturing a driving circuit for an LCD having a conductive particles disposed on bumps will be described with reference to FIGS. 5 through 10.
FIGS. 5 to 10 are cross-sectional views illustrating a method of manufacturing a driving circuit according to an exemplary embodiment of the present invention. For convenience, FIGS. 5-10 show cross sections of the driving circuit that is part of a wafer (not shown) containing many such driving circuits, the wafer being later divided into individual driving circuits like the one shown in FIGS. 5-10.
Referring to FIG. 5, a chip 41 contains circuits (not shown) that are required to provide the functions of a driving circuit. Hereinafter the chip 41 may be referred to as an integrated circuit 41. Electrode pads 43 are formed on the chip 41. These electrode pads 43 provide electrical connections to chip 41, with some of electrode pads dedicated to receiving signals, other electrode pads dedicated to outputting signals and others providing power and ground connections. A passivation layer 45 is formed on chip 41 and on the electrode pads 43. Openings are provided in the passivation layer 45 to expose a portion of each electrode pad 43. A layer of electrically insulating material such as a polyimide layer 47 is formed on the passivation layer 45. Openings are provided in the polyimide layer 47 so that the open portion of each electrode pad 43 is again exposed. The layer 47 may hereinafter be referred to as a second insulating layer 47.
Referring to FIG. 6, an under bump metallurgy (UBM) layer 49 is formed on the chip 41 having the passivation layer 45 and the polyimide layer 47. The under bump metallurgy layer 49 is optional. Thereafter, a photoresist pattern 51 is formed on the UBM layer 49. The photoresist pattern 51 has openings A corresponding to the electrode pads 43. The photoresist pattern 51 may be obtained by using a positive type photoresist material. Alternatively, the photoresist pattern 51 may be obtained by using a negative type photoresist material.
Referring to FIG. 7, an electroplating operation is performed so that the openings in the photoresist pattern 51 are filled with metal, to thereby form bumps 53. Examples of metals suitable for forming the bumps 53 include gold (Au) and nickel (Ni) and may include other suitable metals. These metals may be used alone or in a combination thereof.
Referring to FIG. 8, after the bumps 53 are formed, instead of immediately stripping the photoresist pattern 51, an adhesive material is coated on the photoresist pattern 51 and on the bumps 53 to form an adhesive layer 60. The adhesive material may comprise a resin material and the adhesive layer 60 may hereinafter be referred to as a resin layer 60. The adhesive material includes an electrically conductive material so that conductive particles 30 deposited on the bumps 53 are in good electrical contact with the electrode pads 43. Examples of the electrically conductive material used in the adhesive layer 60 may include silver paste.
Referring to FIG. 9, electrically conductive particles 30 are uniformly sprayed onto the adhesive layer 60. Each of the conductive particles 30 includes an outer portion including at least one layer of metal, and an inner portion comprising an elastic material such as an elastic polymer. The outer portion may include a single metal layer, or may include a first metal layer and a second metal layer that are different in composition from each other. Examples of the metal forming the outer portion may include gold (Au), nickel (Ni), or copper (Cu). These metals may be used alone or in a combination thereof.
An ink jet or fine nozzle or other suitable device may be used to uniformly apply the conductive particles 30 to the adhesive layer 60, thereby increasing uniformity of the distribution of the conductive particles 30.
After the conductive particles 30 are adhered to the adhesive layer 60, the photoresist pattern 51 is removed, and the UBM layer 49 (if present) is etched so that the UBM layer 49 remains only under the bump 53.
Referring to FIG. 10, through the above-described processes, a driving circuit for an LCD device having conductive particles 30 that are attached to the bumps 53 is finally completed. The driving circuit 40 comprises an integrated circuit 41, electrode pads 43 formed on the integrated circuit 41, bumps 53 formed on the electrode pads 43, a conductive adhesive layer 60 formed on the bumps 53 and conductive particles 30 deposited on the adhesive layer 60.
FIGS. 11A and 11B are cross-sectional views illustrating a conductive particle as used in a driving circuit according to an exemplary embodiment of the present invention. FIGS. 11A and 11B illustrate shapes and structures of the conductive particles 30.
Referring to FIGS. 11A and 11B, the conductive particles 30 uniformly electrically connect the bump 53 and an LCD panel to each other to reduce electrical connection resistance. In FIG. 11A, a conductive particle 30 a includes an outer portion comprising a layer 31 including an electrically conductive material such as a metal. The conductive particle 30 a also includes an inner portion 34 a including an elastic material such as an elastic polymer. In FIG. 11B, a conductive particle 30 b includes an outer portion including a first metal layer 31 and a second metal layer 32 that are different from each other in their composition, and an inner portion 34 b comprising an elastic material such as an elastic polymer. Examples of the metal forming the outer portion may include gold (Au), nickel (Ni), and copper (Cu). These may be used alone or in a combination thereof. Alternatively, other metal materials having excellent electrical conductivity may be employed in the metal layers.
FIG. 12 is a cross-sectional view illustrating a method of mounting a conventional driving circuit on an LCD device by using an anisotropic conductive film (ACF). FIG. 13 is a cross-sectional view illustrating a structure of the conventional driving circuit on the LCD device by using the ACF.
Referring to FIGS. 12 and 13, a driving circuit 70 and an LCD panel are electrically connected to each other through an ACF 90. In the connection through the ACF 90, the ACF 90 is adhered to the TFT array substrate 81, which may be a glass substrate, and the driving circuit 70 is bonded to the ACF 90. Thereafter, in a final bonding process, a plurality of conductive particles 35 flows in the ACF 90 and some of the particles are captured between a bump 75 and a pad 83 on the TFT array substrate 81, thereby electrically connecting the driving circuit 70 to the pad 83 on the TFT array substrate 81. However, only about 10 to 30 percent of the conductive particles 35 are involved in making the electrical connections, and thus much of the conductive particles 35 are wasted. In addition, as the area of the bump 75 is decreased, the number of the conductive particles that can be captured on the bump 75 becomes smaller and this causes an increase the resistance of the electrical connection. Further, as discussed with regard to FIGS. 3 and 4, open circuit and short circuit failures may occur in this conventional arrangement.
FIG. 14 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive film (NCF). FIG. 15 is a cross-sectional view illustrating a method of mounting a driving circuit according to an exemplary embodiment of the present invention on an LCD device by using a non-conductive paste (NCP). FIG. 16 is a cross-sectional view illustrating a structure of the driving circuit according to an exemplary embodiment of the present invention on an LCD device.
Referring to FIGS. 14 and 15, the driving circuit 40 having the conductive particles 30 formed on the bump 53 is mounted on a TFT array substrate 81 of an LCD panel.
The TFT array substrate 81 is cleaned so that foreign substances may not be present on the TFT array substrate 81. Then, an NCF 70 or an NCP 75 is bonded on a pad 83 formed on the TFT array substrate 81. The NCF 70 and the NCP 75 are adhesive and non-conductive. The non-conductive adhesive may include a non-conductive film, a non-conductive paste, an ultra-violet curable adhesive or an epoxy group adhesive. Thereafter, the bump 53 on the driving circuit is bonded on the pad 83 on which the NCF 70 or the NCP 75 is bonded. When final bonding is performed, the conductive particles 30 electrically connect the bump 53 and the pad 83 to each other in response to the application of pressure during the final bonding as shown in FIG. 16.
Although the distance between bumps 53 is irregular, the inner elastic portions 34 a and 34 b may compensate for the irregularity, thereby maintaining a stable electrical connection.
According to the present invention, a conductive particle is disposed on a bump of a driving circuit for an LCD device to improve electrical contact between an LCD panel and the driving circuit. The conductive particle includes an inner portion comprising an elastic material, the conductive particle including the elastic polymer inner portion may compensate the irregularity between bumps, although the distance between the bumps is irregular. Thus, after the driving circuit is mounted on the LCD panel, a stable electrical connection may be obtained to reduce electrical connection resistance and prevent reliability defects. In addition, the conductive particles are not disposed between the bumps and thus electrical short circuits between bumps are precluded. Also, even when intervals between the bumps and the pads of the LCD panel are various, the bump may be electrically connected to the pad of the LCD panel through the conductive particle by the compression of the conductive particles to prevent an electrical open defect. Further, the bumps may have a fine pitch, so that chip size may be reduced to increase the number of net dies per wafer, thereby reducing manufacturing cost. Thus, the driving circuit may be applied to an LCD display IC (LDI) having a fine pitch.
Although exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.

Claims (17)

What is claimed is:
1. A driving circuit for a liquid crystal display (LCD) device comprising:
an integrated circuit (IC) that generates a signal;
an electrode pad formed on the IC to transmit the signal;
a bump formed on the electrode pad to receive the signal;
a conductive particle formed on the bump to electrically connect the bump to an external electronic device; and
a conductive layer disposed between the bump and the conductive particle,
wherein the conductive particle includes a first electrically conductive material, the conductive layer includes a second electrically conductive material and the conductive layer electrically connects the bump and the conductive particle.
2. The driving circuit of claim 1, wherein the conductive particle comprises an outer layer including the first electrically conductive material and an inner portion including an elastic polymer material.
3. The driving circuit of claim 2, wherein the first electrically conductive material comprises at least one metal selected from the group consisting of gold (Au) and nickel (Ni).
4. An LCD device comprising:
a driving circuit comprising:
an integrated circuit (IC) that generates a signal;
an electrode pad formed on the IC to transmit the signal;
a bump formed on the electrode pad to receive the signal;
a conductive particle formed on the bump; and
a conductive layer disposed between the bump and the conductive particle, wherein the conductive particle includes a first electrically conductive material, the conductive layer includes a second electrically conductive material and the conductive layer electrically connects the bump and the conductive particle;
a thin-film transistor (TFT) array substrate comprising a pad electrically connected to the bump of the driving circuit through the conductive particle of the driving circuit;
a color filter substrate facing the TFT array substrate; and
a liquid crystal layer disposed between the TFT array substrate and the color filter substrate.
5. The LCD device of claim 4, wherein the driving circuit comprises a plurality of bumps electrically insulated from each other.
6. The LCD device of claim 4, further comprising a non-conductive adhesive configured to adhere the bump of the driving circuit to the TFT array substrate.
7. The LCD device of claim 6, wherein the non-conductive adhesive comprises at least one selected from the group consisting of a non-conductive film, a non-conductive paste, an ultraviolet adhesive and an epoxy group adhesive.
8. The LCD device of claim 4, wherein the conductive particle comprises an outer layer including the first electrically conductive material and an inner portion including an elastic polymer material.
9. The LCD device of claim 8, wherein the first electrically conductive material comprises at least one metal selected from the group consisting of gold (Au) and nickel (Ni).
10. The driving circuit of claim 1, wherein the conductive layer absorbs a stress between the bump and the conductive particle.
11. A driving circuit for use in a liquid crystal display device, the driving circuit comprising:
an integrated circuit that generates a signal;
an electrode pad formed on the integrated circuit to transmit the signal;
a passivation layer having a contact hole exposing the electrode pad;
a bump formed on the electrode pad to receive the signal;
a conductive particle disposed on the bump; and
a conductive layer disposed between the bump and the conductive particle,
wherein the conductive layer electrically connects the bump and the conductive particle.
12. The driving circuit of claim 11, wherein a portion of the electrode pad is disposed between the passivation layer and the integrated circuit.
13. The driving circuit of claim 11, wherein the bump is disposed between the passivation layer and the conductive particle.
14. The driving circuit of claim 11 further comprising a metal layer, wherein a portion of the metal layer is disposed between the bump and the passivation layer.
15. The driving circuit of claim 11 further comprising an insulating layer, wherein a portion of the insulating layer is disposed between the bump and the integrated circuit.
16. The driving circuit of claim 15, wherein the insulating layer is disposed between the passivation layer and the conductive particle.
17. The driving circuit of claim 15 further comprising a metal layer, wherein a portion of the metal layer is disposed between the bump and the insulating layer.
US11/986,594 2006-11-22 2007-11-21 Driving circuit for a liquid crystal display device, method of manufacturing the same and display device having the same Expired - Fee Related US8576368B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2006-0115743 2006-11-22
KR20060115743A KR101309319B1 (en) 2006-11-22 2006-11-22 Driving circuit, method of manufacturing thereof and liquid crystal display apparatus having the same

Publications (2)

Publication Number Publication Date
US20080180376A1 US20080180376A1 (en) 2008-07-31
US8576368B2 true US8576368B2 (en) 2013-11-05

Family

ID=39390406

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/986,594 Expired - Fee Related US8576368B2 (en) 2006-11-22 2007-11-21 Driving circuit for a liquid crystal display device, method of manufacturing the same and display device having the same

Country Status (6)

Country Link
US (1) US8576368B2 (en)
EP (1) EP1942365A3 (en)
JP (1) JP2008129595A (en)
KR (1) KR101309319B1 (en)
CN (1) CN101188219B (en)
TW (1) TW200834155A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9773755B2 (en) 2010-05-20 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US9966346B2 (en) 2012-09-18 2018-05-08 Taiwan Semiconductor Manufacturing Company Bump structure and method of forming same
US9991224B2 (en) 2012-04-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect having varying widths and methods of forming same
US10056345B2 (en) 2012-04-17 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US11419216B2 (en) 2020-03-30 2022-08-16 Samsung Display Co., Ltd. Display device and method of manufacturing the same

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090095026A (en) * 2008-03-04 2009-09-09 삼성전자주식회사 Method of manufacturing for display device
CN102237329B (en) * 2010-04-27 2013-08-21 瑞鼎科技股份有限公司 Chip structure, chip bonding structure and manufacturing methods for chip structure and chip bonding structure
TWI451372B (en) * 2010-07-26 2014-09-01 Au Optronics Corp Method for repairing circuit
TWI419095B (en) * 2010-10-25 2013-12-11 Au Optronics Corp Display device
CN102122481B (en) * 2010-11-01 2014-09-03 友达光电股份有限公司 Display
JP2014026042A (en) * 2012-07-25 2014-02-06 Japan Display Inc Display device
TWI457890B (en) * 2012-08-17 2014-10-21 Macroblock Inc Display structure and display
KR101476686B1 (en) * 2013-04-01 2014-12-26 엘지전자 주식회사 Display device using semiconductor light emitting device
KR102417804B1 (en) * 2015-07-01 2022-07-06 엘지디스플레이 주식회사 Display Device
KR20180070774A (en) * 2016-12-16 2018-06-27 삼성디스플레이 주식회사 Substrate, electronic device and display device having the same
TWI742163B (en) * 2017-09-25 2021-10-11 優顯科技股份有限公司 A method of forming a pre-conductive array on a target circuit substrate, a process of applying the aforementioned method to form a conductive structure on a target circuit substrate, a pre-conductive array of the target circuit substrate, and a conductive structure array of the target circuit substrate
CN109801888A (en) 2017-11-16 2019-05-24 群创光电股份有限公司 First electronic component and display equipment comprising the first electronic component
US11119616B2 (en) 2018-11-01 2021-09-14 Apple Inc. Trace transfer techniques for touch sensor panels with flex circuits
US11853515B2 (en) 2018-12-19 2023-12-26 Apple Inc. Ultra-thin touch sensors
KR102448823B1 (en) * 2022-01-12 2022-09-29 주식회사 엠시스 Pre-coated COF manufacturing method and COF structure produced by the method

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4606962A (en) * 1983-06-13 1986-08-19 Minnesota Mining And Manufacturing Company Electrically and thermally conductive adhesive transfer tape
US5034245A (en) * 1989-03-01 1991-07-23 Sharp Kabushiki Kaisha Method of producing connection electrodes
US5332869A (en) 1989-10-27 1994-07-26 W. R. Grace & Co.-Conn. Printed circuit board, a method of its fabrication and a method of attaching electronic parts thereto
JPH06331999A (en) 1993-05-21 1994-12-02 Optrex Corp Electrooptical device and its production
EP1018761A1 (en) 1997-08-21 2000-07-12 Citizen Watch Co., Ltd. Semiconductor device and method of fabricating the same
US20030027379A1 (en) 2001-08-06 2003-02-06 Hermen Liu Laser repair operation
JP2003309255A (en) 2002-04-16 2003-10-31 Canon Inc Semiconductor device
US20040065949A1 (en) 2002-10-08 2004-04-08 William Tze-You Chen [solder bump]
US20040134974A1 (en) 2003-01-10 2004-07-15 Se-Yong Oh Solder bump structure and method for forming a solder bump
CN1532905A (en) 2003-03-26 2004-09-29 精工爱普生株式会社 Method for producing electronic part, electronic part, mounting method for electronic part and electronic device
US20050041189A1 (en) * 2003-08-22 2005-02-24 Lg.Philips Lcd Co., Ltd. Liquid crystal display device preventing electronic corosion and method of fabricating the same
JP2005108992A (en) 2003-09-29 2005-04-21 Seiko Epson Corp Method for packaging semiconductor device, electro-optical device and manufacturing method thereof, and electronic equipment
JP2005229044A (en) 2004-02-16 2005-08-25 Seiko Epson Corp Electronic component, manufacturing method thereof, and electronic equipment
US20050184389A1 (en) * 2004-02-19 2005-08-25 Hui-Chang Chen Thin film transistor substrate and manufacturing method thereof
US6937314B2 (en) * 2001-02-07 2005-08-30 Samsung Electronics Co., Ltd. Liquid crystal display having terminals arranged for securing connection to driving circuit
JP2005302870A (en) 2004-04-08 2005-10-27 Seiko Epson Corp Electronic parts, method for manufacturing the same, optoelectronics device and electronic apparatus
US20060038298A1 (en) * 2004-08-23 2006-02-23 Hee-Bum Park Tape circuit substrate, semiconductor chip package including the same, and liquid crystal display device including the semiconductor chip package
US20060055037A1 (en) * 2004-09-15 2006-03-16 Samsung Electronics Co., Ltd. Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip
US7109058B2 (en) * 2001-02-19 2006-09-19 Sony Chemicals Corp. Bumpless semiconductor device
US20060211232A1 (en) * 2005-03-16 2006-09-21 Mei-Jen Liu Method for Manufacturing Gold Bumps
US20070080453A1 (en) * 2005-10-06 2007-04-12 Samsung Electronics Co., Ltd. Semiconductor chip having a bump with conductive particles and method of manufacturing the same
US20070252274A1 (en) * 2006-04-26 2007-11-01 Daubenspeck Timothy H Method for forming c4 connections on integrated circuit chips and the resulting devices
US20070267745A1 (en) * 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
US20070298603A1 (en) * 2006-06-27 2007-12-27 Kenneth Rebibis Die configurations and methods of manufacture
WO2008095405A1 (en) 2007-02-01 2008-08-14 Shanghai Jiaotong University Microelectronic element and method of manufacturing the same
US20090283903A1 (en) * 2005-12-02 2009-11-19 Nepes Corporation Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11135925A (en) * 1997-10-30 1999-05-21 Toshiba Corp Mounting method of electronic component and transferring method of conductive particle
JP2006237412A (en) 2005-02-28 2006-09-07 Seiko Instruments Inc Method for manufacturing semiconductor device and for electronic apparatus

Patent Citations (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4606962A (en) * 1983-06-13 1986-08-19 Minnesota Mining And Manufacturing Company Electrically and thermally conductive adhesive transfer tape
US5034245A (en) * 1989-03-01 1991-07-23 Sharp Kabushiki Kaisha Method of producing connection electrodes
US5332869A (en) 1989-10-27 1994-07-26 W. R. Grace & Co.-Conn. Printed circuit board, a method of its fabrication and a method of attaching electronic parts thereto
JPH06331999A (en) 1993-05-21 1994-12-02 Optrex Corp Electrooptical device and its production
EP1018761A1 (en) 1997-08-21 2000-07-12 Citizen Watch Co., Ltd. Semiconductor device and method of fabricating the same
US6937314B2 (en) * 2001-02-07 2005-08-30 Samsung Electronics Co., Ltd. Liquid crystal display having terminals arranged for securing connection to driving circuit
US7109058B2 (en) * 2001-02-19 2006-09-19 Sony Chemicals Corp. Bumpless semiconductor device
US20030027379A1 (en) 2001-08-06 2003-02-06 Hermen Liu Laser repair operation
JP2003309255A (en) 2002-04-16 2003-10-31 Canon Inc Semiconductor device
US20040065949A1 (en) 2002-10-08 2004-04-08 William Tze-You Chen [solder bump]
US20040134974A1 (en) 2003-01-10 2004-07-15 Se-Yong Oh Solder bump structure and method for forming a solder bump
CN1532905A (en) 2003-03-26 2004-09-29 精工爱普生株式会社 Method for producing electronic part, electronic part, mounting method for electronic part and electronic device
US20040224441A1 (en) * 2003-03-26 2004-11-11 Seiko Epson Corporation Method of manufacturing electronic part, electronic part, method of mounting electronic part, and electronic apparatus
US20050041189A1 (en) * 2003-08-22 2005-02-24 Lg.Philips Lcd Co., Ltd. Liquid crystal display device preventing electronic corosion and method of fabricating the same
JP2005108992A (en) 2003-09-29 2005-04-21 Seiko Epson Corp Method for packaging semiconductor device, electro-optical device and manufacturing method thereof, and electronic equipment
JP2005229044A (en) 2004-02-16 2005-08-25 Seiko Epson Corp Electronic component, manufacturing method thereof, and electronic equipment
US20050184389A1 (en) * 2004-02-19 2005-08-25 Hui-Chang Chen Thin film transistor substrate and manufacturing method thereof
JP2005302870A (en) 2004-04-08 2005-10-27 Seiko Epson Corp Electronic parts, method for manufacturing the same, optoelectronics device and electronic apparatus
US20060038298A1 (en) * 2004-08-23 2006-02-23 Hee-Bum Park Tape circuit substrate, semiconductor chip package including the same, and liquid crystal display device including the semiconductor chip package
US20060055037A1 (en) * 2004-09-15 2006-03-16 Samsung Electronics Co., Ltd. Microelectronic device chip including hybrid Au bump, package of the same, LCD apparatus including microelectronic device chip and method of fabricating microelectronic device chip
US20060211232A1 (en) * 2005-03-16 2006-09-21 Mei-Jen Liu Method for Manufacturing Gold Bumps
US20070080453A1 (en) * 2005-10-06 2007-04-12 Samsung Electronics Co., Ltd. Semiconductor chip having a bump with conductive particles and method of manufacturing the same
US20090283903A1 (en) * 2005-12-02 2009-11-19 Nepes Corporation Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
US20070252274A1 (en) * 2006-04-26 2007-11-01 Daubenspeck Timothy H Method for forming c4 connections on integrated circuit chips and the resulting devices
US20070267745A1 (en) * 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
US20070298603A1 (en) * 2006-06-27 2007-12-27 Kenneth Rebibis Die configurations and methods of manufacture
WO2008095405A1 (en) 2007-02-01 2008-08-14 Shanghai Jiaotong University Microelectronic element and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
European Search Report, Application No. EP 07022442, Jun. 2, 2009, 10 pp.

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9773755B2 (en) 2010-05-20 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US10056345B2 (en) 2012-04-17 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US11315896B2 (en) 2012-04-17 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9991224B2 (en) 2012-04-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect having varying widths and methods of forming same
US10510710B2 (en) 2012-04-18 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US10847493B2 (en) 2012-04-18 2020-11-24 Taiwan Semiconductor Manufacturing, Ltd. Bump-on-trace interconnect
US11682651B2 (en) 2012-04-18 2023-06-20 Taiwan Semiconductor Manufacturing Company Bump-on-trace interconnect
US9966346B2 (en) 2012-09-18 2018-05-08 Taiwan Semiconductor Manufacturing Company Bump structure and method of forming same
US10008459B2 (en) 2012-09-18 2018-06-26 Taiwan Semiconductor Manufacturing Company Structures having a tapering curved profile and methods of making same
US11043462B2 (en) 2012-09-18 2021-06-22 Taiwan Semiconductor Manufacturing Company Solderless interconnection structure and method of forming same
US11961810B2 (en) 2012-09-18 2024-04-16 Taiwan Semiconductor Manufacturing Company Solderless interconnection structure and method of forming same
US11419216B2 (en) 2020-03-30 2022-08-16 Samsung Display Co., Ltd. Display device and method of manufacturing the same

Also Published As

Publication number Publication date
EP1942365A3 (en) 2009-07-01
EP1942365A2 (en) 2008-07-09
US20080180376A1 (en) 2008-07-31
TW200834155A (en) 2008-08-16
KR20080046371A (en) 2008-05-27
JP2008129595A (en) 2008-06-05
CN101188219A (en) 2008-05-28
CN101188219B (en) 2012-01-25
KR101309319B1 (en) 2013-09-13

Similar Documents

Publication Publication Date Title
US8576368B2 (en) Driving circuit for a liquid crystal display device, method of manufacturing the same and display device having the same
KR101134168B1 (en) Semiconductor chip and manufacturing method thereof, display panel using the same and manufacturing method thereof
US7454831B2 (en) Method for mounting an electronic element on a wiring board
US6617521B1 (en) Circuit board and display device using the same and electronic equipment
US8211788B2 (en) Method of fabricating bonding structure
US7265449B2 (en) Tape circuit substrate, semiconductor chip package including the same, and liquid crystal display device including the semiconductor chip package
US20030008133A1 (en) Anisotropic conductive film and method of fabricating the same for ultra-fine pitch COG application
US7403256B2 (en) Flat panel display and drive chip thereof
TWI390310B (en) Liquid crystal display device and fabricating method thereof
US5844314A (en) Bump comprising protuberances and a method of forming the same
US20060202334A1 (en) Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same
US20030164919A1 (en) Displaying substrate and liquid crystal display device having the same
US20040224441A1 (en) Method of manufacturing electronic part, electronic part, method of mounting electronic part, and electronic apparatus
EP0662256B1 (en) An electrical connecting structure and a method for electrically connecting terminals to each other
DE102005045661A1 (en) Microelectronic device chip and manufacturing process, package and LCD device
JP2008135468A (en) Semiconductor device and display apparatus with semiconductor device
US5995188A (en) Liquid crystal display device using stacked layers
KR101499120B1 (en) Display device and method of manufacturing the same
US20050185127A1 (en) Method of manufacturing liquid crystal display
US20050184389A1 (en) Thin film transistor substrate and manufacturing method thereof
US20040094846A1 (en) Semiconductor device mounting method, semiconductor device mounting structure, ellectro-optical device, electro-optical device manufacturing method and electronic device
JP4103835B2 (en) Manufacturing method of electronic parts
JPH09146110A (en) Liquid crystal display device
KR20080053593A (en) Display panel and method of fabricatingthe same
JPH06224256A (en) Semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, YUN-HEE;KANG, HO-MIN;HYUN, JONG-SIG;REEL/FRAME:020193/0166

Effective date: 20071115

AS Assignment

Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG ELECTRONICS CO., LTD.;REEL/FRAME:029008/0271

Effective date: 20120904

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20211105