JPH11135925A - Mounting method of electronic component and transferring method of conductive particle - Google Patents

Mounting method of electronic component and transferring method of conductive particle

Info

Publication number
JPH11135925A
JPH11135925A JP29875597A JP29875597A JPH11135925A JP H11135925 A JPH11135925 A JP H11135925A JP 29875597 A JP29875597 A JP 29875597A JP 29875597 A JP29875597 A JP 29875597A JP H11135925 A JPH11135925 A JP H11135925A
Authority
JP
Japan
Prior art keywords
electronic component
mounting
conductive particles
electrode
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29875597A
Other languages
Japanese (ja)
Inventor
Kuniaki Takahashi
邦明 高橋
Itsukou Murakami
壱皇 村上
Shusuke Tanaka
秀典 田中
Kuniyasu Hosoda
邦康 細田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Computer Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Computer Engineering Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Computer Engineering Corp filed Critical Toshiba Corp
Priority to JP29875597A priority Critical patent/JPH11135925A/en
Publication of JPH11135925A publication Critical patent/JPH11135925A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/102Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by bonding of conductive powder, i.e. metallic powder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component mounting method and a conductive particle transfer method, wherein an electronic component is reliably mounted on a board surely interposing conductive particles between the bump of a chip electrode and the joint of a board electrode to surely and electrically connect these electrodes together and improving the adjacent terminals in insulating properties between them an electronic component such as a bare chip of fine pitch and the like is mounted on a wiring board through a flip chip mounting method. SOLUTION: Conductive adhesive agent 13 is applied to a bump 12 formed on the chip electrode 11 of a semiconductor bare chip 10, conductive particles 14 are attached to the bump 12, and the semiconductor base chip 10 is bonded to the bare chip mounting part of a wiring board 20 by thermocompression. At this thermocompression bonding, the conductive particles 14 attached to the joint surface of the bump 12 by applying the conductive adhesive agent 13 to the bump 12 are buried in both the bump 12 and the pad 21 biting into them.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば半導体ベア
チップ等、狭ピッチ多電極構造の電子部品を配線基板に
実装する際に適用して好適な電子部品の実装方法及び導
電粒子の転写方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting electronic components and a method for transferring conductive particles which are suitable for mounting electronic components having a narrow-pitch multi-electrode structure such as a semiconductor bare chip on a wiring board.

【0002】[0002]

【従来の技術】半導体チップ等の多電極電子部品を配線
基板に実装するための電子部品実装技術として、ACF
(Anisotropic Conductive Film )と称される異方導電
膜を用いた回路(電極)接合手段が存在する。
2. Description of the Related Art As an electronic component mounting technology for mounting a multi-electrode electronic component such as a semiconductor chip on a wiring board, ACF is known.
There is a circuit (electrode) joining means using an anisotropic conductive film called (Anisotropic Conductive Film).

【0003】しかしながら、この種ACFに於いては異
方性導電シートに導電粒子がランダムに分散しており、
シートの場所によって導電粒子の密度にばらつきがある
ことから、異方性導電シートに含まれる導電粒子が、実
装時に於ける、加熱、加圧時に、電子部品の電極と配線
基板の電極との接合部間から外れることがあり、電気的
に高い信頼性を得ることができないという問題があっ
た。この不具合は、特に半導体ベアチップ等、狭ピッチ
多電極構造の電子部品実装に於いて、より顕著であっ
た。
[0003] However, in this type of ACF, conductive particles are randomly dispersed in an anisotropic conductive sheet.
Since the density of the conductive particles varies depending on the position of the sheet, the conductive particles contained in the anisotropic conductive sheet are bonded to the electrodes of the electronic component and the electrodes of the wiring board during heating and pressing during mounting. There is a problem in that it may come off from the part, and high electrical reliability cannot be obtained. This problem was more remarkable particularly in the mounting of electronic components having a narrow pitch multi-electrode structure such as a semiconductor bare chip.

【0004】この一例を図9に示す。ここでは配線基板
93と電子部品91との間に導電シート95を介在させ
て、熱圧着により、配線基板93に電子部品91を実装
する際、加圧により、導電シート95内の導電粒子96
が基板電極94と部品電極92との接合面から逃げてし
まい、基板電極94と部品電極92との間に、導電シー
ト95内の導電粒子96が咬合状態で埋設されないこと
から、電極間が確実に電気的結合されず、接合部の電気
抵抗の低下並びに回路不安定等による信頼性の低下を招
くとともに、隣接する電極間に多くの不要な導電粒子が
介在することから電気的絶縁性の低下を招くという問題
があった。尚、図中、97は導電シート95内の絶縁性
接着剤である。
FIG. 9 shows an example of this. Here, a conductive sheet 95 is interposed between the wiring board 93 and the electronic component 91, and when the electronic component 91 is mounted on the wiring board 93 by thermocompression bonding, the conductive particles 96 in the conductive sheet 95 are pressed by pressure.
Escapes from the joint surface between the substrate electrode 94 and the component electrode 92, and the conductive particles 96 in the conductive sheet 95 are not embedded between the substrate electrode 94 and the component electrode 92 in an occlusal state. Not electrically coupled to each other, causing a decrease in electrical resistance at the junction and a decrease in reliability due to circuit instability, etc., and a decrease in electrical insulation due to the presence of many unnecessary conductive particles between adjacent electrodes. There was a problem of inviting. In the drawing, reference numeral 97 denotes an insulating adhesive in the conductive sheet 95.

【0005】[0005]

【発明が解決しようとする課題】上述したように従来技
術に於けるACFに於いては、異方性導電シートに導電
粒子がランダムに分散しており、シートの場所によって
導電粒子の密度にばらつきがあることから、異方性導電
シートに含まれる導電粒子が、実装時に於ける、加熱、
加圧時に、電子部品の電極と配線基板の電極との接合部
間から外れることがあり、従って接合部の電気抵抗の低
下並びに回路不安定等による信頼性の低下、並びに隣接
する電極間に多くの不要な導電粒子が介在することによ
る電気的絶縁性の低下を招き、電気的に高い信頼性を得
ることができないという問題があった。この不具合は、
特に半導体ベアチップ等、狭ピッチ多電極構造の電子部
品実装に於いて、より顕著であった。
As described above, in the conventional ACF, the conductive particles are randomly dispersed in the anisotropic conductive sheet, and the density of the conductive particles varies depending on the position of the sheet. Therefore, the conductive particles contained in the anisotropic conductive sheet, during mounting, heating,
At the time of pressurization, it may come off from the joint between the electrode of the electronic component and the electrode of the wiring board. Therefore, the electric resistance of the joint decreases, the reliability decreases due to circuit instability, etc. However, the presence of unnecessary conductive particles causes a decrease in electrical insulation, and there is a problem that high electrical reliability cannot be obtained. This bug is
In particular, in the mounting of electronic parts having a narrow pitch multi-electrode structure, such as a semiconductor bare chip, it was more remarkable.

【0006】本発明は上記実情に鑑みなされたもので、
特に、微細ピッチとなる、例えばフリップチップ法によ
るベアチップ等の電子部品実装時に、チップ電極側バン
プと基板電極の接合部に確実に導電粒子を介在せしめ
て、電極間を確実に電気的結合し、かつ隣接端子間の電
気的な絶縁性を向上せしめて、信頼性の高い電子部品の
実装を可能にした電子部品の実装方法及び導電粒子の転
写方法を提供することを目的とする。
The present invention has been made in view of the above circumstances,
In particular, when mounting electronic components such as bare chips by a flip chip method, which has a fine pitch, for example, by reliably interposing conductive particles at the junction between the chip electrode side bump and the substrate electrode, the electrical connection between the electrodes is ensured, It is another object of the present invention to provide a method for mounting an electronic component and a method for transferring conductive particles, which make it possible to mount a highly reliable electronic component by improving electrical insulation between adjacent terminals.

【0007】[0007]

【課題を解決するための手段】本発明は、特に微細ピッ
チとなるフリップチップ法によるベアチップ等の電子部
品実装時に、チップ電極側バンプと基板電極の接合部か
ら導電粒子を逃げないようにするため、予めバンプ先端
部にのみ導電粒子を転写させ、又は付着させて、その後
に、エポキシ樹脂、硬化剤等を主成分とする絶縁性の樹
脂でバンプと基板電極間を接着、封止することで、導電
粒子を逃げないようにすること、また隣接端子間の不要
な導電粒子を無くすことで、電極間を確実に電気的結合
し、かつ隣接端子間の電気的な絶縁性を向上せしめて、
信頼性の高い電子部品の実装を可能にしたことを特徴と
する。
SUMMARY OF THE INVENTION The present invention is intended to prevent conductive particles from escaping from a junction between a chip electrode-side bump and a substrate electrode, particularly when mounting electronic components such as bare chips by a flip chip method with a fine pitch. By transferring or attaching the conductive particles only to the tip of the bump in advance, and then bonding and sealing the bump and the substrate electrode with an insulating resin mainly composed of an epoxy resin, a curing agent, or the like. By preventing the conductive particles from escaping, and by eliminating unnecessary conductive particles between adjacent terminals, the electrical connection between the electrodes is ensured, and the electrical insulation between the adjacent terminals is improved.
It is characterized by enabling mounting of highly reliable electronic components.

【0008】即ち、本発明は、例えば半導体ベアチップ
等、狭ピッチ多電極構造の電子部品を配線基板に実装す
る電子部品の実装方法であって、前記電子部品の電極上
にバンプを形成し、当該バンプの先端部に導電粒子を付
着させる工程Aと、前記配線基板の電子部品実装面に熱
硬化性フィルムを貼り付ける工程Bと、前記工程Aを経
た電子部品を前記工程Bを経た配線基板に熱圧着により
実装する工程Cとにより電子部品を配線基板に実装する
ことを特徴とする。
That is, the present invention relates to a method of mounting an electronic component having a narrow-pitch multi-electrode structure, such as a semiconductor bare chip, on a wiring board, wherein a bump is formed on an electrode of the electronic component. A step A of attaching conductive particles to the tip of the bump; a step B of attaching a thermosetting film to an electronic component mounting surface of the wiring board; and an electronic component passing through the step A on the wiring board passing through the step B. The electronic component is mounted on the wiring board by the step C of mounting by thermocompression bonding.

【0009】又、本発明は、半導体ベアチップの実装方
法に於いて、半導体ベアチップの電極上に形成されたバ
ンプの先端部に導電粒子を付着させる工程Aと、前記半
導体ベアチップが実装される配線基板の実装面に熱硬化
性フィルムを貼り付ける工程Bと、前記工程Aを経た半
導体ベアチップを前記工程Bを経た配線基板に熱圧着に
より実装する工程Cとにより、半導体ベアチップを配線
基板に実装することを特徴とする。
The present invention also relates to a method for mounting a semiconductor bare chip, a step A of attaching conductive particles to tips of bumps formed on electrodes of the semiconductor bare chip, and a wiring board on which the semiconductor bare chip is mounted. Mounting a semiconductor bare chip on a wiring board by performing a step B of attaching a thermosetting film to the mounting surface of step A and a step C of mounting the semiconductor bare chip having undergone step A on the wiring board having undergone step B by thermocompression bonding. It is characterized by.

【0010】又、本発明は、導電粒子の転写方法に於い
て、粒径3μm以下の細粒導電粒子を埋め込んだ薄膜状
異方性導電フィルムを、電子部品の電極上に形成された
バンプに加圧または熱圧着して、バンプ先端の面上にの
み薄膜状異方性導電フィルムを転写させることを特徴と
する。
Further, the present invention provides a method for transferring conductive particles, wherein a thin film-like anisotropic conductive film in which fine conductive particles having a particle size of 3 μm or less are embedded is formed on a bump formed on an electrode of an electronic component. The method is characterized in that the thin-film anisotropic conductive film is transferred only to the surface of the tip of the bump by pressing or thermocompression bonding.

【0011】又、本発明は、導電粒子の転写方法に於い
て、粒径3μm以下の細粒導電粒子をグリコール系など
の高沸点溶剤を溶媒にペースト状にして、スキージング
により厚さ10μm以下に薄膜コントロールした後、そ
の上部より、電子部品の電極上に形成されたバンプを押
し付け、加熱することにより、電子部品の電極上に形成
されたバンプ先端部にのみ導電粒子を転写することを特
徴とする。
The present invention also relates to a method for transferring conductive particles, wherein fine conductive particles having a particle size of 3 μm or less are pasted in a solvent such as a glycol-based high-boiling solvent and the thickness is reduced to 10 μm or less by squeezing. After controlling the thin film, the bumps formed on the electrodes of the electronic component are pressed from above, and the conductive particles are transferred only to the tips of the bumps formed on the electrodes of the electronic component by heating. And

【0012】又、本発明は、例えば半導体ベアチップ
等、狭ピッチ多電極構造の電子部品を配線基板に実装す
る電子部品の実装方法であって、粒径3μm以下の細粒
導電粒子を埋め込んだ薄膜状異方性導電フィルム上に、
電子部品の電極上に形成されたバンプを加圧または熱圧
着して、バンプ先端の面上にのみ薄膜状異方性導電フィ
ルムを転写し、当該フィルムを介し電子部品を配線基板
に熱圧着により実装することを特徴とする。
The present invention also relates to a method for mounting an electronic component having a narrow-pitch multi-electrode structure, such as a semiconductor bare chip, on a wiring board, comprising a thin film having fine conductive particles having a particle size of 3 μm or less embedded therein. On the anisotropic conductive film,
The bump formed on the electrode of the electronic component is pressed or thermocompressed, the thin anisotropic conductive film is transferred only on the surface of the bump tip, and the electronic component is thermocompressed to the wiring board via the film. It is characterized by implementation.

【0013】又、本発明は、例えば半導体ベアチップ
等、狭ピッチ多電極構造の電子部品を配線基板に実装す
る電子部品の実装方法であって、粒径3μm以下の細粒
導電粒子を高沸点溶剤を溶媒にペースト状にして、スキ
ージングにより厚さ10μm以下に薄膜コントロール
し、その上部より、電子部品の電極上に形成されたバン
プを押し付けて、ペースト状細粒導電粒子をバンプに転
写して後、電子部品を配線基板に熱圧着により実装する
ことを特徴とする。
The present invention also relates to a method for mounting an electronic component having a narrow-pitch multi-electrode structure, such as a semiconductor bare chip, on a wiring board. Into a paste in a solvent, and control the thin film to a thickness of 10 μm or less by squeezing, press the bump formed on the electrode of the electronic component from above, and transfer the paste-like fine conductive particles to the bump. Thereafter, the electronic component is mounted on the wiring board by thermocompression bonding.

【0014】又、本発明は、上記した電子部品の実装方
法に於いて、電子部品の電極上に形成されたバンプと配
線基板の電極部間に、エポキシ樹脂、硬化剤を主成分と
する絶縁性の樹脂を塗布することにより、又は絶縁性の
樹脂フィルムを介し電極間を熱圧着することにより、転
写された導電粒子による接合部の補強及び隣接電極間の
絶縁性を保持することを特徴とする。
According to the present invention, there is provided the electronic component mounting method as described above, wherein between the bump formed on the electrode of the electronic component and the electrode portion of the wiring board, an insulating resin mainly composed of an epoxy resin and a curing agent is provided. By applying a conductive resin, or by thermocompression bonding between electrodes through an insulating resin film, the transferred conductive particles reinforce the joint and maintain the insulation between adjacent electrodes. I do.

【0015】上記した本発明の方法によれば、先ず電子
部品の電極側先端部にのみ導電粒子を転写又は塗布等に
より付着させて、その後に、絶縁性樹脂により、接着、
封止を行なうことで、電極接合部からの導電粒子の流れ
出しを防止し、電極間の電気的接続を確実にする。ま
た、電極側先端部にのみ導電粒子を付着させ圧着するこ
とから、隣接する電極間に存在する不要導電粒子を減少
させて、隣接電極間の高い絶縁性を保持する。これによ
り電気的に安定した信頼性の高い電子部品の実装が可能
となる。
According to the above-described method of the present invention, first, conductive particles are adhered only to the electrode-side tip portion of the electronic component by transfer or coating, and then, adhered by an insulating resin.
By performing the sealing, it is possible to prevent the conductive particles from flowing out from the electrode joint portion, and to ensure the electrical connection between the electrodes. In addition, since the conductive particles are adhered only to the electrode-side tip and pressure-bonded, unnecessary conductive particles existing between adjacent electrodes are reduced, and high insulation between adjacent electrodes is maintained. This makes it possible to mount electrically stable and highly reliable electronic components.

【0016】[0016]

【発明の実施の形態】以下図面を参照して本発明の実施
形態を説明する。図1乃至図4はそれぞれ本発明の第1
実施形態を説明するための図であり、図1は実装対象と
なる半導体ベアチップの前工程を示す図、図2は図1
(d)に示す工程の具体例を示す図、図3は図1に示す
半導体ベアチップが実装される配線基板の前工程を示す
図、図4は図1に示す工程を経た半導体ベアチップを図
3に示す工程を経た配線基板に実装(熱圧着)する工程
と、その実装後に於ける要部の状態を示す図である。
Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 show the first embodiment of the present invention, respectively.
FIG. 1 is a view for explaining an embodiment, FIG. 1 is a view showing a pre-process of a semiconductor bare chip to be mounted, and FIG.
FIG. 3 is a diagram showing a specific example of the process shown in FIG. 3D, FIG. 3 is a diagram showing a pre-process of a wiring board on which the semiconductor bare chip shown in FIG. 1 is mounted, and FIG. FIG. 7 is a diagram showing a process of mounting (thermocompression bonding) on the wiring board after the process shown in FIG. 5 and a state of a main part after the mounting.

【0017】図1乃至図4に於いて、10は実装対象と
なる狭ピッチ多電極構造の電子部品であり、ここでは半
導体ベアチップを実装対象とする。11は半導体ベアチ
ップ10に設けられた電極(チップ電極)であり、実際
には多数配列されるが、ここでは省略して2個のみ示し
ている。12はチップ電極11上に形成された、例えば
Au、Ni、半田合金等でなるバンプである。13はバ
ンプ12の基板電極接合面上に付けられた(例えば塗布
された)ペースト状の導電性接着剤である。
In FIGS. 1 to 4, reference numeral 10 denotes an electronic component having a narrow-pitch multi-electrode structure to be mounted. Here, a semiconductor bare chip is mounted. Reference numeral 11 denotes electrodes (chip electrodes) provided on the semiconductor bare chip 10, which are actually arranged in large numbers, but are omitted here and only two are shown. Reference numeral 12 denotes a bump formed on the chip electrode 11 and made of, for example, Au, Ni, a solder alloy, or the like. Reference numeral 13 denotes a paste-like conductive adhesive applied (for example, applied) on the substrate electrode bonding surface of the bump 12.

【0018】14は半導体ベアチップ10と配線基板と
の電極間を回路結合するための、例えばニッケル等の堅
い微細金属粒でなる導電粒子であり、バンプ12に塗布
された導電性接着剤13によりバンプ12の接合面上に
付着し、熱圧着時の加圧によりバンプ12と基板電極と
の間に咬合状態で埋設される。
Reference numeral 14 denotes conductive particles made of hard fine metal particles such as nickel, for example, for connecting the circuit between the electrodes of the semiconductor bare chip 10 and the wiring board, and the bumps are formed by the conductive adhesive 13 applied to the bumps 12. 12 are buried in a state of being engaged between the bump 12 and the substrate electrode by pressure during thermocompression bonding.

【0019】15は半導体ベアチップ10のチップ電極
11上に形成したバンプ12のそれぞれに複数個の導電
粒子14を付着させるための転写ステージであり、導電
性接着剤13が塗られたバンプ12各々の先端部にそれ
ぞれ複数個の導電粒子14を付着させる。
Reference numeral 15 denotes a transfer stage for adhering a plurality of conductive particles 14 to each of the bumps 12 formed on the chip electrodes 11 of the semiconductor bare chip 10. Each of the transfer stages 15 has a conductive adhesive 13 applied thereto. A plurality of conductive particles 14 are attached to the tips, respectively.

【0020】20はチップ電極11上にバンプ12を形
成した半導体ベアチップ10が実装される配線基板であ
る。21は配線基板20上のベアチップ実装面に設けら
れたパッド(基板電極)である。
Reference numeral 20 denotes a wiring board on which the semiconductor bare chip 10 having the bumps 12 formed on the chip electrodes 11 is mounted. Reference numeral 21 denotes pads (substrate electrodes) provided on the bare chip mounting surface on the wiring board 20.

【0021】30は配線基板20の部品実装面上に張ら
れる熱硬化性フィルムであり、熱圧着工程の際に溶融し
半導体ベアチップ10と配線基板20との隙間を埋めて
半導体ベアチップ10を配線基板20に固着する。ここ
では溶解導電粒子を除外したACFと同等のものを用い
ることができる。
Reference numeral 30 denotes a thermosetting film stretched on the component mounting surface of the wiring board 20, which is melted during the thermocompression bonding step and fills a gap between the semiconductor bare chip 10 and the wiring board 20 so that the semiconductor bare chip 10 is bonded to the wiring board 20. 20. Here, a material equivalent to an ACF excluding dissolved conductive particles can be used.

【0022】ここで上記図1乃至図4を参照して本発明
の第1実施形態による導電粒子の転写並びに半導体ベア
チップ実装方法を説明する。先ず図1を参照して実装対
象となる半導体ベアチップ10の前工程について説明す
る。
A method of transferring conductive particles and mounting a semiconductor bare chip according to the first embodiment of the present invention will now be described with reference to FIGS. First, with reference to FIG. 1, the pre-process of the semiconductor bare chip 10 to be mounted will be described.

【0023】この前工程では、チップ電極11上にバン
プ12を形成した後、当該バンプ12に導電性接着剤1
3を塗布して、当該導電性接着剤13によりバンプ12
の先端部に複数個の導電粒子14を付着させる。
In this pre-process, after the bumps 12 are formed on the chip electrodes 11, the conductive adhesive 1 is applied to the bumps 12.
3 and apply the conductive adhesive 13 to the bumps 12.
A plurality of conductive particles 14 are adhered to the tip of.

【0024】即ち、図1(a)に示す半導体ベアチップ
10のチップ電極11上に、同図(b)に示すように、
バンプ12を形成する。次に、このバンプ12の基板電
極接合面に、図1(c)に示すように、導電性接着剤1
3を塗布する。その後、導電性接着剤13を塗布したバ
ンプ12の基板電極接合面に、図1(d)に示すよう
に、複数個の導電粒子14を付着させる。
That is, as shown in FIG. 1B, on the chip electrode 11 of the semiconductor bare chip 10 shown in FIG.
The bump 12 is formed. Next, as shown in FIG. 1C, the conductive adhesive 1
3 is applied. Thereafter, as shown in FIG. 1D, a plurality of conductive particles 14 are attached to the substrate electrode bonding surface of the bump 12 to which the conductive adhesive 13 has been applied.

【0025】この際の導電粒子付着工程の一例を図2に
示している。ここでは、図2(a)乃至(c)に示すよ
うに、チップ電極11上に形成されたバンプ12に導電
性接着剤13が塗布された半導体ベアチップ10を転写
ステージ15に供給し、多数の導電粒子14を一様に撒
いた転写ステージ15にて、各バンプ12に導電粒子1
4を付着させる。これによりチップ電極11上に形成さ
れたバンプ12各々に、それぞれ複数個の導電粒子14
が導電性接着剤13により付着される。
FIG. 2 shows an example of the conductive particle attaching step at this time. Here, as shown in FIGS. 2A to 2C, a semiconductor bare chip 10 in which a conductive adhesive 13 is applied to a bump 12 formed on a chip electrode 11 is supplied to a transfer stage 15, and a large number of semiconductor bare chips 10 are provided. On the transfer stage 15 in which the conductive particles 14 are uniformly dispersed, the conductive particles 1
4 is deposited. As a result, a plurality of conductive particles 14 are provided on each of the bumps 12 formed on the chip electrode 11.
Is adhered by the conductive adhesive 13.

【0026】このような半導体ベアチップ10の前工程
とは別に図3に示すような配線基板20の前工程を行な
う。ここでは、図3(a),(b)に示すように、配線
基板20のベアチップ実装面に熱硬化性フィルム30を
貼り付ける。
A pre-process for the wiring board 20 as shown in FIG. 3 is performed separately from the pre-process for the semiconductor bare chip 10. Here, as shown in FIGS. 3A and 3B, the thermosetting film 30 is attached to the bare chip mounting surface of the wiring board 20.

【0027】上記したように半導体ベアチップ10及び
配線基板20のそれぞれに前工程を施した後、図4
(a)に示すように、半導体ベアチップ10を配線基板
20のベアチップのベアチップ実装部に熱圧着する。
After performing the pre-process on each of the semiconductor bare chip 10 and the wiring board 20 as described above,
As shown in (a), the semiconductor bare chip 10 is thermocompression-bonded to the bare chip mounting portion of the bare chip of the wiring board 20.

【0028】この熱圧着の際の加圧で、図4(b)に示
すように、バンプ12に塗布された導電性接着剤13に
よりバンプ12の接合面上に付着された複数個の導電粒
子14がバンプ12とパッド21との間に咬合状態で埋
設される。
As shown in FIG. 4B, a plurality of conductive particles adhered on the bonding surface of the bump 12 by the conductive adhesive 13 applied to the bump 12 by the pressure during the thermocompression bonding. 14 is embedded between the bump 12 and the pad 21 in an occlusal state.

【0029】更にこの際、配線基板20の部品実装面上
に張られた熱硬化性フィルム30が溶融し半導体ベアチ
ップ10と配線基板20との隙間を埋めて半導体ベアチ
ップ10を配線基板20に固着する。
Further, at this time, the thermosetting film 30 stretched on the component mounting surface of the wiring board 20 melts and fills the gap between the semiconductor bare chip 10 and the wiring board 20 to fix the semiconductor bare chip 10 to the wiring board 20. .

【0030】このように、導電粒子14をバンプ12に
導電性接着剤13で直接固定することにより、半導体ベ
アチップ10を実装したときに、バンプ12と配線基板
20のパッド21との間に導電粒子14が存在しないこ
とによる、電極間接合部の電気抵抗の低下並びに回路不
安定等の不都合を確実に回避して、安定した信頼性の高
い部品実装が可能となる。また、従来技術によるACF
のように導電粒子がランダムに分散していないため、A
CFの欠点である、回路接続すべき電極間に導電粒子が
存在せず、隣接する電極間に多くの不要な導電粒子が介
在することによる電気的絶縁性の低下を確実に回避し
て、電気的に高い信頼性を確保できる。
As described above, by directly fixing the conductive particles 14 to the bumps 12 with the conductive adhesive 13, when the semiconductor bare chip 10 is mounted, the conductive particles 14 are located between the bumps 12 and the pads 21 of the wiring board 20. Inconveniences such as a decrease in electric resistance of the inter-electrode junction and instability of the circuit due to the absence of 14 can be reliably avoided, and stable and reliable component mounting becomes possible. ACF according to the prior art
Since the conductive particles are not randomly dispersed as in
As a drawback of CF, there is no conductive particles between electrodes to be connected to a circuit, and it is possible to reliably avoid a decrease in electrical insulation due to the presence of many unnecessary conductive particles between adjacent electrodes. High reliability can be ensured.

【0031】次に、図5及び図6を参照して本発明の第
2実施形態を説明する。ここではフリップチップ法によ
るベアチップの実装方法を示している。図5及び図6に
於いて、40は実装対象となる狭ピッチ多電極構造の電
子部品であり、ここでは半導体ベアチップを実装対象と
する。41は半導体ベアチップ40に設けられた電極
(チップ電極)であり、実際には多数配列されるが、こ
こでは省略して2個のみ示している。42はチップ電極
41上に形成された、例えばAu、Ni、半田合金等で
なるバンプである。
Next, a second embodiment of the present invention will be described with reference to FIGS. Here, a method of mounting a bare chip by a flip chip method is shown. 5 and 6, reference numeral 40 denotes an electronic component having a narrow pitch multi-electrode structure to be mounted, and here, a semiconductor bare chip is to be mounted. Reference numeral 41 denotes electrodes (chip electrodes) provided on the semiconductor bare chip 40, which are actually arranged in large numbers, but are omitted here and only two are shown. Reference numeral 42 denotes a bump formed on the chip electrode 41 and made of, for example, Au, Ni, a solder alloy, or the like.

【0032】50は半導体ベアチップ40と配線基板と
の電極間を回路結合するための粒径2〜3μm程度の堅
い微細金属粒でなる導電粒子51を多数埋め込んだ厚さ
5μm程度の薄膜状異方性導電フィルムであり、バンプ
42の電極接合面に例えば熱圧着により貼着される。
Reference numeral 50 denotes a thin film anisotropic member having a thickness of about 5 μm in which a large number of conductive particles 51 made of hard fine metal particles having a particle diameter of about 2 to 3 μm are embedded for circuit coupling between the electrodes of the semiconductor bare chip 40 and the wiring board. A conductive film that is adhered to the electrode joining surface of the bump 42 by, for example, thermocompression bonding.

【0033】ここでは、導電粒子51の粒径をバンプ4
2先端部(電極接合面部42a)の高さ(h)より小さ
くしている。また、異方性導電フィルム50の厚さを導
電粒子51の粒径にできるだけ近づけることによって、
バンプ42の先端部(電極接合面部42a)を押し付け
た際の導電粒子51の逃げを無くすようにしている。
Here, the particle size of the conductive particles 51 is
(2) The height is smaller than the height (h) of the tip portion (electrode joining surface portion 42a). Also, by making the thickness of the anisotropic conductive film 50 as close as possible to the particle size of the conductive particles 51,
The escape of the conductive particles 51 when pressing the tip of the bump 42 (the electrode joining surface 42a) is prevented.

【0034】60はチップ電極41上にバンプ42を形
成した半導体ベアチップ40が実装される配線基板であ
る。61は配線基板60上のベアチップ実装面に設けら
れたパッド(基板電極)である。
Reference numeral 60 denotes a wiring board on which the semiconductor bare chip 40 having the bumps 42 formed on the chip electrodes 41 is mounted. Reference numeral 61 denotes a pad (substrate electrode) provided on the bare chip mounting surface on the wiring substrate 60.

【0035】63は配線基板60のベアチップ実装面上
に設けられる、エポキシ樹脂、硬化剤等を主成分とする
絶縁性の樹脂フィルムであり、熱圧着することで接合部
を補強するとともに隣接電極間の絶縁性を保持する。
Reference numeral 63 denotes an insulating resin film provided on the bare chip mounting surface of the wiring board 60 and containing an epoxy resin, a curing agent, or the like as a main component. Maintain the insulation properties of

【0036】ここで上記図5及び図6を参照して本発明
の第2実施形態に於けるベアチップの実装方法を説明す
る。先ず半導体ベアチップ40のチップ電極41上に形
成されたバンプ42の電極接合面部に、粒径2〜3μm
程度の導電粒子51を埋め込んだ5μm厚程度の薄膜状
異方性導電フィルム50を転写させる。この際の実装対
象となる半導体ベアチップ40を図5(a)に示し、半
導体ベアチップ40のバンプ42に異方性導電フィルム
50を転写した状態を図5(b)に示している。
Here, a method for mounting a bare chip according to the second embodiment of the present invention will be described with reference to FIGS. First, a particle diameter of 2 to 3 μm is applied to the electrode joining surface of the bump 42 formed on the chip electrode 41 of the semiconductor bare chip 40.
A thin film-like anisotropic conductive film 50 having a thickness of about 5 μm in which conductive particles 51 of about 5 μm are embedded is transferred. FIG. 5A shows a semiconductor bare chip 40 to be mounted at this time, and FIG. 5B shows a state where the anisotropic conductive film 50 is transferred to the bumps 42 of the semiconductor bare chip 40.

【0037】その後、半導体ベアチップ40のチップ電
極41上に形成されたバンプ42と配線基板60の基板
電極61との間に、絶縁性の樹脂フィルム63を介在さ
せ、半導体ベアチップ40を配線基板60のベアチップ
実装面部に熱圧着する。これにより電極接合部の補強、
及び隣接電極間の絶縁性保持を実現する。この際の半導
体ベアチップ40のチップ電極41上に形成されたバン
プ42と配線基板60の基板電極61との間に絶縁性の
樹脂フィルム63を介在させた状態を図6(a)に示
し、熱圧着した状態を図6(b)に示している。
Thereafter, an insulating resin film 63 is interposed between the bump 42 formed on the chip electrode 41 of the semiconductor bare chip 40 and the substrate electrode 61 of the wiring board 60, and the semiconductor bare chip 40 is Thermocompression bonding to bare chip mounting surface. This strengthens the electrode joint,
In addition, insulation between adjacent electrodes is maintained. FIG. 6A shows a state in which an insulating resin film 63 is interposed between the bumps 42 formed on the chip electrodes 41 of the semiconductor bare chip 40 and the substrate electrodes 61 of the wiring board 60 at this time. FIG. 6B shows a state in which the pressure is applied.

【0038】尚、絶縁性の樹脂フィルム63に代わり、
ペースト状の熱硬化性絶縁樹脂材料を塗布してもよい。
このようにバンプ42の先端部(電極接合面部42a)
に導電粒子51を異方性導電フィルム50を用いて付着
させることにより、半導体ベアチップ40を配線基板6
0に実装したときに、バンプ42と配線基板60のパッ
ド61との間に、複数個の導電粒子が確実に確保され、
電極接合部間の電気抵抗の安定化及び長期信頼性の向上
が図れる。
In place of the insulating resin film 63,
A paste-like thermosetting insulating resin material may be applied.
As described above, the tip portion of the bump 42 (the electrode joining surface portion 42a)
The semiconductor bare chip 40 is attached to the wiring board 6 by attaching conductive particles 51 to the
0, a plurality of conductive particles are reliably secured between the bump 42 and the pad 61 of the wiring board 60,
Stabilization of the electrical resistance between the electrode junctions and improvement of long-term reliability can be achieved.

【0039】又、バンプの先端部(電極接合面部42
a)のみに確実に導電粒子51を転写することができる
ので、半導体ベアチップ40のチップ電極41に形成さ
れたバンプ42と配線基板60との間から導電粒子51
が流れ出す不都合を回避して、複数個の導電粒子を確実
に電極接合部間に埋め込むことができるとともに、隣接
する電極間の不要な導電粒子の介在を排除できることか
ら、電極接合部間の電気的接続が確実に行なえるととも
に、隣接する電極間の絶縁性を向上できる。
Also, the tip of the bump (electrode bonding surface 42)
Since the conductive particles 51 can be reliably transferred only to a), the conductive particles 51 can be transferred from between the bumps 42 formed on the chip electrodes 41 of the semiconductor bare chip 40 and the wiring board 60.
In addition to avoiding the disadvantage of flowing out, a plurality of conductive particles can be reliably embedded between the electrode joints, and unnecessary conductive particles between adjacent electrodes can be eliminated. Connection can be reliably performed, and insulation between adjacent electrodes can be improved.

【0040】次に、図7及び図8を参照して本発明の第
3実施形態を説明する。ここではフリップチップ法によ
るベアチップの実装方法を示し、上記した図5及び図6
に示す第2実施形態と同一部分には同一符号を付して、
その説明を省略する。
Next, a third embodiment of the present invention will be described with reference to FIGS. Here, a method of mounting a bare chip by a flip chip method is shown, and FIGS.
The same reference numerals are given to the same parts as the second embodiment shown in FIG.
The description is omitted.

【0041】この第3実施形態では、粒径2〜3μm程
度の導電粒子71をグリコール系などの高沸点溶剤70
を溶媒としてペースト状にし、スキージングにより厚さ
5〜10μm程度に薄膜コントロールした後、半導体ベ
アチップ40のチップ電極41上に形成されたバンプ4
2の電極接合面部42aにペースト状の導電粒子71を
複数個付着させることによって、バンプ42の電極接合
面部に複数個の導電粒子71を転写する。この際の電極
接合面部42aにペースト状の導電粒子71を付着させ
る際の状態を図7(a)に示し、バンプ42の電極接合
面部42aに導電粒子71が付着された状態を図7
(b)に示している。尚、この第3実施形態に於いても
導電粒子71の粒径をバンプ42先端部(電極接合面部
42a)の高さ(h)より小さくしている。また、スキ
ージングの際の厚さを導電粒子71の粒径にできるだけ
近い厚さにすることで、バンプ42の先端部(電極接合
面部42a)を押し付けた際の導電粒子71の逃げを無
くすようにしている。
In the third embodiment, conductive particles 71 having a particle size of about 2 to 3 μm are mixed with a high boiling solvent 70 such as a glycol-based solvent.
Is used as a solvent to form a paste, the thin film is controlled to a thickness of about 5 to 10 μm by squeezing, and then the bumps 4 formed on the chip electrodes 41 of the semiconductor bare chip 40 are formed.
By attaching a plurality of paste-like conductive particles 71 to the second electrode bonding surface 42a, the plurality of conductive particles 71 are transferred to the electrode bonding surface of the bump 42. FIG. 7A shows a state in which the paste-like conductive particles 71 are attached to the electrode joining surface 42a at this time, and FIG. 7 shows a state in which the conductive particles 71 are attached to the electrode joining surface 42a of the bump 42.
This is shown in FIG. In the third embodiment as well, the particle size of the conductive particles 71 is smaller than the height (h) of the tip of the bump 42 (the electrode joining surface 42a). In addition, by making the thickness at the time of squeezing as close as possible to the particle size of the conductive particles 71, the escape of the conductive particles 71 when pressing the tip portion (electrode bonding surface portion 42a) of the bump 42 is prevented. I have to.

【0042】又、この実施形態では導電粒子71をペー
スト状にするために高沸点溶剤70を使用していること
から、常温での揮発は少なく、かつバンプ42への熱圧
着時の加熱により残渣を無くすことができる。
Further, in this embodiment, since the high-boiling solvent 70 is used to make the conductive particles 71 into a paste, volatilization at room temperature is small, and residue is generated by heating at the time of thermocompression bonding to the bumps 42. Can be eliminated.

【0043】その後、配線基板60のベアチップ実装面
部に、エポキシ樹脂、硬化剤等を主成分とする絶縁性を
有するペースト状の樹脂80を塗布し、半導体ベアチッ
プ40のチップ電極41上に形成されたバンプ42と配
線基板60のパッド(基板電極)61との間を熱圧着す
る。これにより電極接合部の補強、及び隣接電極間の絶
縁性保持を実現する。この際の熱圧着前の状態を図8
(a)に示し、熱圧着後の状態を図8(b)に示してい
る。
Thereafter, a paste-like resin 80 having an insulating property mainly composed of an epoxy resin, a curing agent and the like is applied to the bare chip mounting surface of the wiring board 60, and is formed on the chip electrodes 41 of the semiconductor bare chip 40. Thermocompression bonding is performed between the bump 42 and the pad (substrate electrode) 61 of the wiring board 60. This achieves reinforcement of the electrode joint and retention of insulation between adjacent electrodes. The state before the thermocompression bonding at this time is shown in FIG.
FIG. 8A shows the state after thermocompression bonding, and FIG.

【0044】尚、上記したペースト状の樹脂80に代わ
って、樹脂フィルムを用いることも可能である。このよ
うにバンプ42の先端部(電極接合面部42a)に導電
粒子71を直接固定することにより、半導体ベアチップ
40を配線基板60に実装したときに、バンプ42と配
線基板60のパッド61との間に、複数個の導電粒子が
確実に確保され、これにより電極接合部間の電気抵抗の
安定化及び長期信頼性の向上が図れる。
It should be noted that a resin film can be used instead of the above-mentioned paste-like resin 80. By directly fixing the conductive particles 71 to the tip portions (electrode bonding surface portions 42a) of the bumps 42, when the semiconductor bare chip 40 is mounted on the wiring board 60, the gap between the bumps 42 and the pads 61 of the wiring board 60 is reduced. In addition, a plurality of conductive particles are reliably ensured, thereby stabilizing the electrical resistance between the electrode joints and improving long-term reliability.

【0045】又、バンプの先端部(電極接合面部42
a)のみに確実に導電粒子71を転写することができる
ので、半導体ベアチップ40のチップ電極41に形成さ
れたバンプ42と配線基板60との間から導電粒子71
が流れ出す不都合を回避して、複数個の導電粒子を確実
に電極接合部間に埋め込むことができるとともに、隣接
する電極間の不要な導電粒子の介在を排除できることか
ら、電極接合部間の電気的接続が確実に行なえるととも
に、隣接する電極間の絶縁性を向上できる。
Further, the tip portion of the bump (electrode bonding surface portion 42)
Since the conductive particles 71 can be reliably transferred only to a), the conductive particles 71 can be transferred between the bumps 42 formed on the chip electrodes 41 of the semiconductor bare chip 40 and the wiring board 60.
In addition to avoiding the disadvantage of flowing out, a plurality of conductive particles can be reliably embedded between the electrode joints, and unnecessary conductive particles between adjacent electrodes can be eliminated. Connection can be reliably performed, and insulation between adjacent electrodes can be improved.

【0046】[0046]

【発明の効果】以上詳記したように本発明によれば、特
に、微細ピッチとなる、例えばフリップチップ法による
ベアチップ等の電子部品実装時に、チップ電極側バンプ
と基板電極の接合部に確実に導電粒子を介在せしめて、
電極間を確実に電気的結合し、かつ隣接端子間の電気的
な絶縁性を向上せしめて、信頼性の高い電子部品の実装
を可能にした電子部品の実装方法及び導電粒子の転写方
法が提供できる。
As described above in detail, according to the present invention, especially when electronic components such as bare chips are mounted at a fine pitch, for example, by a flip chip method, the bonding between the bumps on the chip electrode side and the substrate electrodes is surely performed. With conductive particles interposed,
Provided are a method for mounting an electronic component and a method for transferring conductive particles, which make it possible to reliably mount an electronic component by reliably and electrically connecting electrodes and improving electrical insulation between adjacent terminals. it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態に於ける、半導体ベアチ
ップの前工程を示す図。
FIG. 1 is a view showing a pre-process of a semiconductor bare chip in a first embodiment of the present invention.

【図2】本発明の第1実施形態に於ける、図1(d)に
示す工程の具体例を示す図。
FIG. 2 is a view showing a specific example of the step shown in FIG. 1D in the first embodiment of the present invention.

【図3】本発明の第1実施形態に於ける、配線基板の前
工程を示す図。
FIG. 3 is a diagram showing a pre-process of a wiring board in the first embodiment of the present invention.

【図4】本発明の第1実施形態に於ける、半導体ベアチ
ップを配線基板に実装(熱圧着)する工程と、その実装
後に於ける要部の状態を示す図。
FIG. 4 is a diagram showing a process of mounting (thermocompression bonding) a semiconductor bare chip on a wiring board and a state of a main part after the mounting in the first embodiment of the present invention.

【図5】本発明の第2実施形態に於ける、半導体ベアチ
ップの前工程を示す図。
FIG. 5 is a diagram showing a pre-process of a semiconductor bare chip in a second embodiment of the present invention.

【図6】本発明の第2実施形態に於ける、半導体ベアチ
ップを配線基板に実装(熱圧着)する工程と、その実装
後に於ける要部の状態を示す図。
FIG. 6 is a view showing a process of mounting (thermocompression bonding) a semiconductor bare chip on a wiring board and a state of a main part after the mounting in the second embodiment of the present invention.

【図7】本発明の第3実施形態に於ける、半導体ベアチ
ップの前工程を示す図。
FIG. 7 is a view showing a pre-process of a semiconductor bare chip in a third embodiment of the present invention.

【図8】本発明の第3実施形態に於ける、半導体ベアチ
ップを配線基板に実装(熱圧着)する工程と、その実装
後に於ける要部の状態を示す図。
FIG. 8 is a diagram illustrating a process of mounting (thermocompression bonding) a semiconductor bare chip on a wiring board and a state of a main part after the mounting according to the third embodiment of the present invention.

【図9】従来のACF技術による部品実装方法を説明す
るための図。
FIG. 9 is a view for explaining a component mounting method using a conventional ACF technique.

【符号の説明】[Explanation of symbols]

10…狭ピッチ多電極構造の電子部品(半導体ベアチッ
プ)、 11…半導体ベアチップ10に設けられた電極(チップ
電極)、 12…チップ電極11上に形成されたバンプ、 13…ペースト状の導電性接着剤、 14…導電粒子、 15…転写ステージ、 20…配線基板、 21…パッド(基板電極)、 30…熱硬化性フィルム、 40…狭ピッチ多電極構造の電子部品(半導体ベアチッ
プ)、 41…半導体ベアチップ40に設けられた電極(チップ
電極)、 42…チップ電極41上に形成されたバンプ、 42a…電極接合面部、 50…薄膜状異方性導電フィルム、 51…導電粒子、 60…配線基板、 61…パッド(基板電極)、 63…絶縁性の樹脂フィルム、 70…導電粒子71をペースト状にするための高沸点溶
剤、 71…導電粒子、 80…ペースト状の樹脂。
DESCRIPTION OF SYMBOLS 10 ... Electronic component (semiconductor bare chip) of a narrow pitch multi-electrode structure, 11 ... Electrode (chip electrode) provided on semiconductor bare chip 10, 12 ... Bump formed on chip electrode 11, 13 ... Paste-like conductive adhesive 14 ... conductive particles, 15 ... transfer stage, 20 ... wiring board, 21 ... pad (substrate electrode), 30 ... thermosetting film, 40 ... electronic component (semiconductor bare chip) with narrow pitch multi-electrode structure, 41 ... semiconductor An electrode (chip electrode) provided on the bare chip 40; 42, a bump formed on the chip electrode 41; 42a, an electrode bonding surface; 50, a thin anisotropic conductive film; 51, conductive particles; 61: Pad (substrate electrode) 63: Insulating resin film 70: High boiling point solvent for forming conductive particles 71 into paste, 71: Conductive particles 80: Paste resin.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 村上 壱皇 東京都青梅市末広町2丁目9番地 株式会 社東芝青梅工場内 (72)発明者 田中 秀典 東京都青梅市新町1381番地1 東芝コンピ ュータエンジニアリング株式会社内 (72)発明者 細田 邦康 東京都青梅市新町1381番地1 東芝コンピ ュータエンジニアリング株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ichi Murakami 2-9-9 Suehirocho, Ome-shi, Tokyo Inside the Toshiba Ome Plant (72) Inventor Hidenori Tanaka 1381-1, Shinmachi, Ome-shi, Tokyo Toshiba Computer Data Engineering Co., Ltd. (72) Inventor Kuniyasu Hosoda 1381 Shinmachi, Ome-shi, Tokyo Toshiba Computer Engineering Co., Ltd.

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 狭ピッチ多電極構造の電子部品を配線基
板に実装する電子部品の実装方法であって、 前記電子部品の電極上にバンプを形成し、当該バンプの
先端部に導電粒子を付着させる工程Aと、 前記配線基板の電子部品実装面に熱硬化性フィルムを貼
り付ける工程Bと、 前記工程Aを経た電子部品を前記工程Bを経た配線基板
に熱圧着により実装する工程Cとにより電子部品を配線
基板に実装することを特徴とする電子部品の実装方法。
An electronic component mounting method for mounting an electronic component having a narrow-pitch multi-electrode structure on a wiring board, wherein a bump is formed on an electrode of the electronic component, and conductive particles are attached to a tip of the bump. A step A of bonding, a step B of attaching a thermosetting film to an electronic component mounting surface of the wiring board, and a step C of mounting the electronic component having undergone the step A on the wiring board having undergone the step B by thermocompression bonding. A method for mounting an electronic component, comprising mounting the electronic component on a wiring board.
【請求項2】 半導体ベアチップの電極上に形成された
バンプの先端部に導電粒子を付着させる工程Aと、 前記半導体ベアチップが実装される配線基板の実装面に
熱硬化性フィルムを貼り付ける工程Bと、 前記工程Aを経た半導体ベアチップを前記工程Bを経た
配線基板に熱圧着により実装する工程Cとにより、半導
体ベアチップを配線基板に実装することを特徴とする半
導体ベアチップの実装方法。
2. A step of attaching conductive particles to the tip of a bump formed on an electrode of a semiconductor bare chip, and a B step of attaching a thermosetting film to a mounting surface of a wiring board on which the semiconductor bare chip is mounted. A method for mounting a semiconductor bare chip on a wiring board, comprising: a step C of mounting the semiconductor bare chip after the step A on the wiring board after the step B by thermocompression bonding.
【請求項3】 粒径3μm以下の細粒導電粒子を埋め込
んだ薄膜状異方性導電フィルムを、電子部品の電極上に
形成されたバンプに加圧または熱圧着して、バンプ先端
の面上にのみ薄膜状異方性導電フィルムを転写させるこ
とを特徴とする導電粒子の転写方法。
3. A pressure-sensitive or thermocompression-bonded thin film-like anisotropic conductive film in which fine conductive particles having a particle size of 3 μm or less are embedded is pressed onto a bump formed on an electrode of an electronic component, and the surface of the tip of the bump is pressed. A method for transferring conductive particles, comprising transferring a thin-film anisotropic conductive film only to the conductive particles.
【請求項4】 粒径3μm以下の細粒導電粒子をグリコ
ール系などの高沸点溶剤を溶媒にペースト状にして、ス
キージングにより厚さ10μm以下に薄膜コントロール
した後、その上部より、電子部品の電極上に形成された
バンプを押し付け、加熱することにより、電子部品の電
極上に形成されたバンプ先端部にのみ導電粒子を転写す
ることを特徴とする導電粒子の転写方法。
4. A method in which fine conductive particles having a particle size of 3 μm or less are made into a paste in a solvent such as a glycol-based high-boiling solvent and thinned to a thickness of 10 μm or less by squeezing. A method for transferring conductive particles, wherein a conductive particle is transferred only to a tip portion of a bump formed on an electrode of an electronic component by pressing and heating a bump formed on the electrode.
【請求項5】 狭ピッチ多電極構造の電子部品を配線基
板に実装する電子部品の実装方法であって、 粒径3μm以下の細粒導電粒子を埋め込んだ薄膜状異方
性導電フィルム上に、電子部品の電極上に形成されたバ
ンプを加圧または熱圧着して、バンプ先端の面上にのみ
薄膜状異方性導電フィルムを転写し、当該フィルムを介
し電子部品を配線基板に熱圧着により実装することを特
徴とする電子部品の実装方法。
5. An electronic component mounting method for mounting an electronic component having a narrow pitch multi-electrode structure on a wiring board, comprising: a thin film-like anisotropic conductive film in which fine conductive particles having a particle size of 3 μm or less are embedded; The bump formed on the electrode of the electronic component is pressed or thermocompressed, the thin anisotropic conductive film is transferred only on the surface of the bump tip, and the electronic component is thermocompressed to the wiring board via the film. An electronic component mounting method characterized by mounting.
【請求項6】 狭ピッチ多電極構造の電子部品を配線基
板に実装する電子部品の実装方法であって、 粒径3μm以下の細粒導電粒子を高沸点溶剤を溶媒にペ
ースト状にして、スキージングにより厚さ10μm以下
に薄膜コントロールし、その上部より、電子部品の電極
上に形成されたバンプを押し付けて、ペースト状細粒導
電粒子をバンプに転写して後、電子部品を配線基板に熱
圧着により実装することを特徴とする電子部品の実装方
法。
6. A method of mounting an electronic component having a narrow-pitch multi-electrode structure on a wiring board, comprising: forming fine conductive particles having a particle size of 3 μm or less into a paste using a high-boiling solvent as a solvent; The thin film is controlled to a thickness of 10 μm or less by zing, and the bumps formed on the electrodes of the electronic component are pressed from above to transfer the fine paste conductive particles to the bumps. An electronic component mounting method characterized by mounting by crimping.
【請求項7】 電子部品の電極上に形成されたバンプと
配線基板の電極部間に、エポキシ樹脂、硬化剤を主成分
とする絶縁性の樹脂を塗布することにより、又は絶縁性
の樹脂フィルムを介し電極間を熱圧着することにより、
転写された導電粒子による接合部の補強及び隣接電極間
の絶縁性を保持する請求項5又は6記載の電子部品の実
装方法。
7. An insulating resin film containing an epoxy resin or a hardening agent as a main component is applied between a bump formed on an electrode of an electronic component and an electrode portion of a wiring board. By thermocompression between the electrodes via
7. The method of mounting an electronic component according to claim 5, wherein the transferred conductive particles reinforce the joint and maintain insulation between adjacent electrodes.
【請求項8】 電子部品として半導体ベアチップを用い
た請求項5又は6又は7記載の電子部品の実装方法。
8. The method for mounting an electronic component according to claim 5, wherein a semiconductor bare chip is used as the electronic component.
JP29875597A 1997-10-30 1997-10-30 Mounting method of electronic component and transferring method of conductive particle Pending JPH11135925A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29875597A JPH11135925A (en) 1997-10-30 1997-10-30 Mounting method of electronic component and transferring method of conductive particle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29875597A JPH11135925A (en) 1997-10-30 1997-10-30 Mounting method of electronic component and transferring method of conductive particle

Publications (1)

Publication Number Publication Date
JPH11135925A true JPH11135925A (en) 1999-05-21

Family

ID=17863821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29875597A Pending JPH11135925A (en) 1997-10-30 1997-10-30 Mounting method of electronic component and transferring method of conductive particle

Country Status (1)

Country Link
JP (1) JPH11135925A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003003798A1 (en) * 2001-06-29 2003-01-09 Toray Engineering Co., Ltd. Joining method using anisotropic conductive adhesive
JP2011146557A (en) * 2010-01-15 2011-07-28 Panasonic Corp Method for soldering electronic component
KR101309319B1 (en) * 2006-11-22 2013-09-13 삼성디스플레이 주식회사 Driving circuit, method of manufacturing thereof and liquid crystal display apparatus having the same
CN111799241A (en) * 2020-06-24 2020-10-20 霸州市云谷电子科技有限公司 Bonding structure, manufacturing method thereof and display panel

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003003798A1 (en) * 2001-06-29 2003-01-09 Toray Engineering Co., Ltd. Joining method using anisotropic conductive adhesive
KR101309319B1 (en) * 2006-11-22 2013-09-13 삼성디스플레이 주식회사 Driving circuit, method of manufacturing thereof and liquid crystal display apparatus having the same
JP2011146557A (en) * 2010-01-15 2011-07-28 Panasonic Corp Method for soldering electronic component
CN111799241A (en) * 2020-06-24 2020-10-20 霸州市云谷电子科技有限公司 Bonding structure, manufacturing method thereof and display panel

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