US20060202334A1 - Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same - Google Patents

Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same Download PDF

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Publication number
US20060202334A1
US20060202334A1 US11/421,680 US42168006A US2006202334A1 US 20060202334 A1 US20060202334 A1 US 20060202334A1 US 42168006 A US42168006 A US 42168006A US 2006202334 A1 US2006202334 A1 US 2006202334A1
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Prior art keywords
bump
semiconductor chip
pad
metal line
redistribution metal
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US11/421,680
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Yong-hwan Kwon
Sa-Yoon Kang
Chung-Sun Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to US11/421,680 priority Critical patent/US20060202334A1/en
Publication of US20060202334A1 publication Critical patent/US20060202334A1/en
Abandoned legal-status Critical Current

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Definitions

  • the present invention relates to a semiconductor chip and a mount structure, and more particularly, to a liquid crystal display drive IC (LDI) chip and the mount structure in which the chip is connected to an external electronic device by a bump.
  • LDM liquid crystal display drive IC
  • a liquid crystal display is a flat-panel display having the excellent characteristics of thinness, light-weight, and low power consumption.
  • the LCD also has such characteristics of high resolution, high color display, and high definition.
  • the LCD is made up of a liquid crystal panel (LCP) having liquid crystal injected between two substrates (an array and color filter substrate), a back light in a lower portion of the LCP, and a drive unit at an outer ring of the LCP to drive the LCP.
  • the LCP consists of pixels in a matrix shape between two glass substrates with a switching device for controlling signals respectively supplied to the pixels, like a thin-film transistor.
  • the drive unit includes a printed circuit board (PCB), comprising hardware to generate control and data signals, and a liquid crystal display drive IC (LDI) which connects to the LCP and PCB to signal a LCP wire.
  • PCB printed circuit board
  • LCI liquid crystal display drive IC
  • Mount structures for an LDI chip include chip on glass (COG), tape carrier package (TCP), chip on film (COF), etc.
  • LDI chip mounting requires a fine pitch connection, an easy connecting process, and high reliability to meet a trend in a complicated structure of the LDI chip, an increase in the number of pixels, and obtain high resolution.
  • An exemplary technology for meeting this trend is a method of forming an Au bump and bonding a fine pad pitch.
  • FIGS. 1 through 4 show a manufacturing method of a conventional Au bump used in mounting a LDI chip.
  • FIG. 1 illustrates coating a chip in a wafer-state 1 with a passivation film 5 and covering an open Al pad 3 with polyimide and patterning to expose the Al pad 3 .
  • FIG. 2 illustrates forming an under bump metallurgy (UBM) layer 9 by sputtering in an upper portion of the intermediate structure obtained in FIG. 1 , and forming a photoresist pattern 11 having a hole A in a corresponding location to the Al pad 3 on the UBM layer 9 .
  • UBM under bump metallurgy
  • a bump 13 is formed by filling the hole A with Au layers via Au electroplating as shown in FIG. 3 , and photoresist pattern 11 is removed via stripping as illustrated in FIG. 4 .
  • an etching process of the UBM layer 9 is performed so that the UBM layer 9 remains in a lower portion of the bump 13 .
  • the remaining UBM layer is indicated as 9 a in FIG. 4 .
  • the bump 13 is conventionally formed on the Al pad 3 , thus exposing the passivation film 5 on the lower portion of the bump.
  • the exposed passivation film 5 on the lower portion of the bump 13 makes it difficult to overcome step difference and, furthermore, causes the step difference in an upper portion of the bump 13 .
  • the rough upper portion of the bump hampers the bonding process, and chip size is inevitably big due to the formation of the bump 13 on the Al pad 3 .
  • the size of bump 13 and the space between bumps 13 can be large. It is also difficult to embody the fine pad pitch since the Al pad 3 is disposed in a circumferential pad area separated from a cell (or circuit) area.
  • FIG. 5 displays a conventional redistribution bump 28 .
  • the upper portion of the bump 28 may be rough and an edge of the bump 28 may have protrusions as the bump 28 is formed by leaving the UBM layer 26 as a via for electrical connection in a bump formation location, and protecting a remaining area via the passivation film 27 after forming the redistribution metal wire 25 .
  • Reference numerals 21 , 22 , 23 , and 24 indicate a chip in a wafer-state, an Al pad, and first and second passivation films, respectively.
  • the present invention provides a method of forming a bump to simplify an assembly of a semiconductor chip and to minimize a pad area inside the chip.
  • the present invention also provides a semiconductor chip that is easy to assemble using the method above and a reliable chip mount structure.
  • a method of forming a redistribution bump includes: forming a first passivation film partially exposing an upper portion of a pad on the upper portion of a wafer-state chip in which the pad is formed; forming a second passivation film to expose the upper portion of the pad and a circumferential first passivation film; forming a redistribution metal layer along a surface in which the second passivation film is formed; forming a bump adjoining the redistribution metal layer on the second passivation film in a substantially flat location detached from a location of the pad; etching the redistribution metal layer to leave only a metal line having a predetermined width under the bump; and forming a third passivation film protecting the redistribution metal line and exposing the bump.
  • a semiconductor chip including: a bump used in an electrical connection between the semiconductor chip pad and the external electronic device, wherein the bump having a substantially flat upper surface is formed in a substantially flat location beyond a location of a pad and is connected to the pad via a redistribution metal line.
  • the pad and the bump may have at least one layered substantially flat passivation film formed therebetween and the bump may be made of one of gold and a gold alloy.
  • the redistribution metal line covering the upper portion of the pad can be extended under the bump.
  • the redistribution metal line and the bump may have an additional redistribution metal line formed therebetween and the additional redistribution metal line may be made of Au, an Au alloy, or Ni/Au.
  • a semiconductor chip including: a first passivation film covering a pad formed on an upper portion of the chip and partially exposing the upper portion of the pad; a second passivation film formed on the first passivation film to expose the upper portion of the pad and a circumferential first passivation film; a bump having a substantially flat surface that is formed on the upper portion of the second passivation film in a substantially flat location detached from a location of the pad; a redistribution metal line extended from the upper portion of the pad to a lower portion of the bump for an electrical connection between the pad and the bump; and a third passivation film exposing the bump and protecting the redistribution metal line.
  • the semiconductor chip mounted on a liquid crystal panel has a mount structure in which the bump and an electrode of the LCP are connected.
  • FIGS. 1 through 4 are drawings illustrating a method of manufacturing a conventional Au bump used in mounting a liquid crystal display drive IC (LDI) chip;
  • LDD liquid crystal display drive IC
  • FIG. 5 displays a conventional redistribution bump
  • FIGS. 6 through 12 are cross-sections illustrating a method of forming a redistribution bump according to an embodiment of the present invention
  • FIGS. 13 through 16 are cross-sections illustrating a method of forming a redistribution bump according to another embodiment of the present invention.
  • FIGS. 17 through 21 are cross-sections illustrating a method of forming a redistribution bump according to still another embodiment of the present invention.
  • FIGS. 22 through 25 are cross-sections illustrating various examples of mount structures using a semiconductor chip structure according to embodiments of the present invention.
  • a method of forming a redistribution bump according to a first embodiment of the present invention will be explained with reference to FIGS. 6 through 12 .
  • a first passivation film 35 is applied onto an upper portion of a wafer-state chip 31 in which a plurality of semiconductor devices are formed.
  • the upper portion of an Al pad 33 to transmit signals between the semiconductor device and an external electronic device, is exposed by partially etching the first passivation film 35 .
  • the first passivation film 35 may comprise a silicon oxide and nitride film.
  • the Al pad 33 may be exposed by a photolithography and etching process.
  • a second passivation film 37 such as polyimide, may be formed over the first passivation film 35 and the Al pad 33 via spin coating.
  • the second passivation film 37 is patterned to expose a portion of the Al pad 33 .
  • the second passivation film 37 may comprise, for example, polyetherimide, epoxy, or silicon resin.
  • a metal layer 39 is formed over the intermediate structure obtained in FIG. 6 .
  • the metal layer 39 may be formed, for example, by evaporation, sputtering, or plating.
  • the plating method may include electronic and electroless plating.
  • the manufacturing process of the metal layer 39 may comprise a redistribution process for shifting locations, forming an external terminal or a bump in a subsequent process.
  • the metal layer 39 can function as an under bump metallurgy (UBM) layer for forming the bump in the subsequent process.
  • UBM under bump metallurgy
  • the metal layer 39 may be layered by a compound material made out of TiW, Au, Cr, Cu, Ti, Ni, NiV, and Pd, combinations thereof, etc., to enhance connection reliability between the bump and the Al pad 33 .
  • a photoresist is applied and a first photoresist pattern 41 is formed by leaving an opening H in a location where the bump for a connection will be formed.
  • the opening H is made on a flat surface and is detached from the Al pad 33 , unlike the conventional method.
  • a bump 43 may be formed by filling the opening H with one of gold and a gold alloy via electroplating.
  • the opening H may be formed in a flat location, and thus the bump 43 formed inside the opening H may have a flat upper surface without step difference.
  • Other bump formation methods such as evaporation and sputtering may be used instead of the plating method.
  • a mask is used and an exposure E is performed on the first photoresist pattern 41 to set away from the opening of the first passivation film 35 in the Al pad 33 to the bump 43 .
  • the second photoresist pattern 41 a is formed covering the opening of the first passivation film 35 in the Al pad 33 and the bump 43 and partially exposing the metal layer 39 .
  • a reference numeral 39 a indicates a remaining redistribution metal line.
  • a third passivation film 47 is formed to protect the remaining exposed redistribution metal line 39 a after removing the second photoresist pattern 41 a in FIG. 11 and leaving a portion of the bump 43 .
  • the third passivation film 47 can be made of polyimide, polyetherimide, epoxy, and silicon resin, for example.
  • a method of forming the third passivation film 47 may be one of spin coating and patterning. After dicing the wafer, a process of separating the semiconductor chip from the wafer piece by piece is performed, and then the separated semiconductor chip is mounted.
  • the separated chip C 1 can be formed to be a mount structure such as a chip on glass (COG), a tape carrier package (TCP), a chip on film (COF), etc.
  • the bump 43 is formed on the second passivation film 37 and placed in a flat location slightly detached from an area of the Al pad 33 rather than being directly on the Al pad 33 .
  • An electrical connection between the Al pad 33 and the bump 43 is made by the redistribution metal line 39 a.
  • a flat surface of an upper portion of the bump without any step difference can be obtained in a final chip structure C 1 , and thereby simplifying the bonding process and increasing reliability of connected parts.
  • chip size need not change despite a bigger bump size.
  • Bump 43 may be enlarged even though the Al pad 33 is embodied in a fine pitch.
  • the pitch of the Al pad 33 can be minimized to reduce chip size because the Al pad 33 made with a fine pitch does not influence the size of the bump 43 .
  • a semiconductor chip C 1 with the bump 43 formed by the aforementioned method includes the first passivation film 35 covering and partially exposing the pad 33 formed on an upper portion of the chip.
  • the second passivation film 37 is formed on the first passivation film 35 exposing the upper portion of the pad 33 and the nearby first passivation film 35 .
  • the bump 43 has a flat upper surface since it is formed on the second passivation film 37 in a flat location detached from the pad location.
  • the electrical connection is performed by the redistribution metal line 39 a extended from the upper portion of the pad to a lower portion of the bump 43 .
  • the bump 43 is exposed and the redistribution metal line 39 a is protected by the third passivation film 47 .
  • this semiconductor chip has a simple bonding process and an enhanced reliability of connected parts since a substantially flat surface can be obtained without an occurrence of step difference on the upper portion of the bump 43 .
  • FIGS. 13 through 16 are cross-sections illustrating a method of forming a redistribution bump according to a second embodiment of the present invention. Identical reference numerals have been used to designate identical elements throughout FIGS. 6 to 12 . Overlapping explanations with the first embodiment are omitted.
  • the first photoresist pattern 41 used in forming the bump 43 is removed by ashing and stripping as shown in FIG. 13 .
  • a new photoresist pattern 44 is formed a predetermined width from an opening of the first passivation film 35 in the Al pad 33 to the bump 43 .
  • the redistribution metal line 39 a remains as presented in FIG. 15 by etching the metal layer 39 while using the photoresist pattern 44 as an etching mask.
  • a chip structure C 2 is obtained as shown in FIG. 16 by forming the third passivation film 47 as explained in FIG. 12 .
  • the second photoresist pattern 41 a is formed by additionally exposing the first photoresist pattern 41 in the first embodiment
  • the new photoresist pattern 44 is formed after removing the first photoresist pattern 41 in the present embodiment.
  • the new photoresist pattern 44 is capable of coating the upper portion of the bump 43 and can protect the bump 43 from damage when etching the lower portion of metal layer 39 .
  • FIGS. 17 through 21 are cross-sections illustrating a method of forming a redistribution bump according to a third embodiment of the present invention. Overlapping explanations of the first and second embodiment will be omitted.
  • an upper portion of an Al pad 53 is exposed by applying and patterning a first passivation film 55 on an upper portion of a wafer-state chip 51 .
  • a second passivation film 57 After applying and patterning a second passivation film 57 , a portion of the Al pad 53 is exposed.
  • a metal layer 59 may be formed over the resulting structure including the second passivation film 57 .
  • Example metal layers 59 include TiW, Au, Cr, Cu, Ti, Ni, NiV, Pd, and a layered film may be made of combinations of these eight materials.
  • a first photoresist pattern 61 is formed on the metal layer 59 .
  • the first photoresist pattern 61 has an opening O at a location where an additional redistribution metal line for the electrical connection will be formed.
  • the additional redistribution metal layer 63 is formed in the opening O using electroplating.
  • One of Au, an Au alloy, and Ni/Au with a thickness of 0.1 um ⁇ 20 um may be used for the additional redistribution metal layer 63 .
  • the first photoresist pattern 61 is removed by stripping, as shown in FIG. 18 .
  • a second photoresist pattern 65 is formed over the metal layer 59 .
  • the second photoresist pattern 65 has an opening R in which a bump can be formed.
  • a bump 67 may be formed, for example, by filling gold or a gold alloy inside the opening R via electroplating.
  • the second photoresist pattern 65 used in forming the bump 67 is removed. Thereafter, a third photoresist pattern 69 is formed to set a predetermined width away from the opening of the first passivation film 55 in the Al pad 53 to the bump 67 .
  • the third photoresist pattern 69 may be formed by additionally exposing and developing the second photoresist pattern 65 , instead of removing it. Using the third photoresist pattern 69 as an etching mask, the metal layer 59 is etched, and the metal line 59 a is left as shown in FIG. 21 . Then, after removing the third photoresist pattern 69 , a final chip structure C 3 is obtained by forming a third passivation film 71 so as to expose the bump 67 .
  • the upper portion of the bump 67 is substantially flat, and thus simplifying a bonding process.
  • the additional redistribution metal line 63 prevents a short circuit and enhances the reliability of the present embodiment.
  • FIGS. 22 through 25 are cross-sections illustrating various examples of mount structures with a high reliability using a semiconductor chip structure according to a fourth embodiment of the present invention. For convenience, examples of mounting the chip C 1 in the first embodiment are illustrated.
  • a chip on glass (COG) mount structure in which the chip C 1 is mounted on a liquid crystal panel (LCP) 100 is illustrated in an embodiment shown in FIG. 22 .
  • the chip C 1 having the bump 43 according to an embodiment of the present invention is thermally pressured using an anisotropic conductive film (ACF) 110 and is mounted on the LCP 100 .
  • the ACF 110 has a small conductive particle 107 in a thermosetting resin film 105 . After the ACF is adhered to an electrode 102 (or a pad) of the LCP 100 in which conductive adhesion is performed and the bump 43 is attached to the electrode 102 , the electrical connection is made vertically through a thermal pressure process.
  • the conductive particle 107 may be a polymer or a glass ball coated by gold, silver, or nickel.
  • a reference numeral 103 is an insulation film.
  • a COG mount structure in which the chip C 1 is mounted on the LCP 100 is illustrated in the embodiment in FIG. 23 .
  • the chip C 1 having the bump 43 according to an embodiment of the present invention is thermally pressured using a non-conductive paste (NCP) 120 and is mounted on a LCP 100 .
  • NCP non-conductive paste
  • FIGS. 24 and 25 are cross-sections of a chip on film (COF) and a tape carrier package (TCP) mount structure, respectively. While the COG mount structure as described in FIGS. 22 and 23 has a bigger-sized LCD from mounting the chip on the LCP, the COF and TCP structures may be compact since the chip is mounted using an extra film, and thus the film having the chip can be bent toward a rear side of the LCP.
  • COF chip on film
  • TCP tape carrier package
  • first and second signal wires (or copper lead) 140 and 145 are plurally formed on a base film 130 formed of a material such as polyimide and a solder resist 150 is formed on the first and second signal wires 140 and 145 , respectively.
  • the solder resist 150 also exposes a portion of the first and second signal wires 140 and 145 , respectively.
  • a chip is disposed so that each bump 34 contacts with the first and second signal wires 140 and 145 .
  • the chip and the first and second signal wires 140 and 145 are connected via the bump 43 .
  • a resin 155 is formed on both ends of the chip and covers the solder resist 150 , the first and second signal wires 140 and 145 , and the bump 43 .
  • the TCP mount structure in FIG. 25 is similar with the mount structure in FIG. 24 , except that the former has the base film 130 with a hollow center portion.
  • the mount structure including a semiconductor chip with a redistribution bump as presented in the present invention has excellent connection reliability since the mount structure uses a substantially flat bump.
  • the bump having the flat upper surface and is capable of expanding an area within the same pitch can be formed according to embodiments of the present invention.
  • manufacturing costs can be lowered by increasing the number of net dies and decreasing the chip size. This feature is very useful for LDI fine pitch products.
  • the flat upper surface of the bump can simplify the assembling process and obtain tolerance and can reduce defects in the assembly, a manufacturing process of the circuit thin film is simplified, therefore reducing processing costs.

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Abstract

Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.

Description

  • This application is a Divisional of U.S. patent application Ser. No. 10/898,445, filed on Jul. 22, 2004, now pending, which claims the priority of Korean Patent Application No. 2003-50496, filed on Jul. 23, 2003 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor chip and a mount structure, and more particularly, to a liquid crystal display drive IC (LDI) chip and the mount structure in which the chip is connected to an external electronic device by a bump.
  • 2. Description of the Related Art
  • A liquid crystal display (LCD) is a flat-panel display having the excellent characteristics of thinness, light-weight, and low power consumption. In addition, the LCD also has such characteristics of high resolution, high color display, and high definition.
  • As is well known, the LCD is made up of a liquid crystal panel (LCP) having liquid crystal injected between two substrates (an array and color filter substrate), a back light in a lower portion of the LCP, and a drive unit at an outer ring of the LCP to drive the LCP. The LCP consists of pixels in a matrix shape between two glass substrates with a switching device for controlling signals respectively supplied to the pixels, like a thin-film transistor.
  • The drive unit includes a printed circuit board (PCB), comprising hardware to generate control and data signals, and a liquid crystal display drive IC (LDI) which connects to the LCP and PCB to signal a LCP wire. Mount structures for an LDI chip include chip on glass (COG), tape carrier package (TCP), chip on film (COF), etc. LDI chip mounting requires a fine pitch connection, an easy connecting process, and high reliability to meet a trend in a complicated structure of the LDI chip, an increase in the number of pixels, and obtain high resolution. An exemplary technology for meeting this trend is a method of forming an Au bump and bonding a fine pad pitch.
  • FIGS. 1 through 4 show a manufacturing method of a conventional Au bump used in mounting a LDI chip.
  • FIG. 1 illustrates coating a chip in a wafer-state 1 with a passivation film 5 and covering an open Al pad 3 with polyimide and patterning to expose the Al pad 3.
  • FIG. 2 illustrates forming an under bump metallurgy (UBM) layer 9 by sputtering in an upper portion of the intermediate structure obtained in FIG. 1, and forming a photoresist pattern 11 having a hole A in a corresponding location to the Al pad 3 on the UBM layer 9.
  • A bump 13 is formed by filling the hole A with Au layers via Au electroplating as shown in FIG. 3, and photoresist pattern 11 is removed via stripping as illustrated in FIG. 4. Next, an etching process of the UBM layer 9 is performed so that the UBM layer 9 remains in a lower portion of the bump 13. The remaining UBM layer is indicated as 9 a in FIG. 4.
  • The bump 13 is conventionally formed on the Al pad 3, thus exposing the passivation film 5 on the lower portion of the bump. The exposed passivation film 5 on the lower portion of the bump 13 makes it difficult to overcome step difference and, furthermore, causes the step difference in an upper portion of the bump 13. Additionally, the rough upper portion of the bump hampers the bonding process, and chip size is inevitably big due to the formation of the bump 13 on the Al pad 3. To simplify manufacturing, the size of bump 13 and the space between bumps 13 can be large. It is also difficult to embody the fine pad pitch since the Al pad 3 is disposed in a circumferential pad area separated from a cell (or circuit) area.
  • FIG. 5 displays a conventional redistribution bump 28. The upper portion of the bump 28 may be rough and an edge of the bump 28 may have protrusions as the bump 28 is formed by leaving the UBM layer 26 as a via for electrical connection in a bump formation location, and protecting a remaining area via the passivation film 27 after forming the redistribution metal wire 25. Reference numerals 21, 22, 23, and 24 indicate a chip in a wafer-state, an Al pad, and first and second passivation films, respectively.
    • SUMMARY OF THE INVENTION
  • The present invention provides a method of forming a bump to simplify an assembly of a semiconductor chip and to minimize a pad area inside the chip. In addition, the present invention also provides a semiconductor chip that is easy to assemble using the method above and a reliable chip mount structure.
  • According to an aspect of the present invention, there is provided a method of forming a redistribution bump. The method includes: forming a first passivation film partially exposing an upper portion of a pad on the upper portion of a wafer-state chip in which the pad is formed; forming a second passivation film to expose the upper portion of the pad and a circumferential first passivation film; forming a redistribution metal layer along a surface in which the second passivation film is formed; forming a bump adjoining the redistribution metal layer on the second passivation film in a substantially flat location detached from a location of the pad; etching the redistribution metal layer to leave only a metal line having a predetermined width under the bump; and forming a third passivation film protecting the redistribution metal line and exposing the bump.
  • According to another aspect of the present invention, there is provided a semiconductor chip including: a bump used in an electrical connection between the semiconductor chip pad and the external electronic device, wherein the bump having a substantially flat upper surface is formed in a substantially flat location beyond a location of a pad and is connected to the pad via a redistribution metal line.
  • The pad and the bump may have at least one layered substantially flat passivation film formed therebetween and the bump may be made of one of gold and a gold alloy. In addition, the redistribution metal line covering the upper portion of the pad can be extended under the bump. Furthermore, the redistribution metal line and the bump may have an additional redistribution metal line formed therebetween and the additional redistribution metal line may be made of Au, an Au alloy, or Ni/Au.
  • According to still another aspect of the present invention, there is provided a semiconductor chip including: a first passivation film covering a pad formed on an upper portion of the chip and partially exposing the upper portion of the pad; a second passivation film formed on the first passivation film to expose the upper portion of the pad and a circumferential first passivation film; a bump having a substantially flat surface that is formed on the upper portion of the second passivation film in a substantially flat location detached from a location of the pad; a redistribution metal line extended from the upper portion of the pad to a lower portion of the bump for an electrical connection between the pad and the bump; and a third passivation film exposing the bump and protecting the redistribution metal line.
  • The semiconductor chip mounted on a liquid crystal panel has a mount structure in which the bump and an electrode of the LCP are connected.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
  • FIGS. 1 through 4 are drawings illustrating a method of manufacturing a conventional Au bump used in mounting a liquid crystal display drive IC (LDI) chip;
  • FIG. 5 displays a conventional redistribution bump;
  • FIGS. 6 through 12 are cross-sections illustrating a method of forming a redistribution bump according to an embodiment of the present invention;
  • FIGS. 13 through 16 are cross-sections illustrating a method of forming a redistribution bump according to another embodiment of the present invention;
  • FIGS. 17 through 21 are cross-sections illustrating a method of forming a redistribution bump according to still another embodiment of the present invention; and
  • FIGS. 22 through 25 are cross-sections illustrating various examples of mount structures using a semiconductor chip structure according to embodiments of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention will now be described more fully with reference to the attached drawings, in which exemplary embodiments thereof are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the forms of the elements are exaggerated for clarity. To facilitate understanding, identical reference numerals have been used to designate identical elements that are common to the figures.
  • A method of forming a redistribution bump according to a first embodiment of the present invention will be explained with reference to FIGS. 6 through 12.
  • Referring to FIG. 6, a first passivation film 35 is applied onto an upper portion of a wafer-state chip 31 in which a plurality of semiconductor devices are formed. The upper portion of an Al pad 33, to transmit signals between the semiconductor device and an external electronic device, is exposed by partially etching the first passivation film 35. The first passivation film 35 may comprise a silicon oxide and nitride film. The Al pad 33 may be exposed by a photolithography and etching process. A second passivation film 37, such as polyimide, may be formed over the first passivation film 35 and the Al pad 33 via spin coating. The second passivation film 37 is patterned to expose a portion of the Al pad 33. The second passivation film 37 may comprise, for example, polyetherimide, epoxy, or silicon resin.
  • In the embodiment in FIG. 7, a metal layer 39 is formed over the intermediate structure obtained in FIG. 6. The metal layer 39 may be formed, for example, by evaporation, sputtering, or plating. The plating method may include electronic and electroless plating. The manufacturing process of the metal layer 39 may comprise a redistribution process for shifting locations, forming an external terminal or a bump in a subsequent process. According to an embodiment of the present invention, the metal layer 39 can function as an under bump metallurgy (UBM) layer for forming the bump in the subsequent process. Accordingly, the metal layer 39 may be layered by a compound material made out of TiW, Au, Cr, Cu, Ti, Ni, NiV, and Pd, combinations thereof, etc., to enhance connection reliability between the bump and the Al pad 33.
  • After forming the metal layer 39, a photoresist is applied and a first photoresist pattern 41 is formed by leaving an opening H in a location where the bump for a connection will be formed. The opening H is made on a flat surface and is detached from the Al pad 33, unlike the conventional method.
  • Referring to FIG. 8, a bump 43 may be formed by filling the opening H with one of gold and a gold alloy via electroplating. The opening H may be formed in a flat location, and thus the bump 43 formed inside the opening H may have a flat upper surface without step difference. Other bump formation methods such as evaporation and sputtering may be used instead of the plating method.
  • In the embodiment in FIG. 9, a mask is used and an exposure E is performed on the first photoresist pattern 41 to set away from the opening of the first passivation film 35 in the Al pad 33 to the bump 43. After developing the first photoresist pattern 41, as illustrated in FIG. 10, the second photoresist pattern 41 a is formed covering the opening of the first passivation film 35 in the Al pad 33 and the bump 43 and partially exposing the metal layer 39.
  • Then, referring to FIG. 11, the metal line 39 exposed under the second photoresist pattern 41 a is removed by etching. A reference numeral 39 a indicates a remaining redistribution metal line.
  • Referring to FIG. 12, a third passivation film 47 is formed to protect the remaining exposed redistribution metal line 39 a after removing the second photoresist pattern 41 a in FIG. 11 and leaving a portion of the bump 43. The third passivation film 47 can be made of polyimide, polyetherimide, epoxy, and silicon resin, for example. A method of forming the third passivation film 47 may be one of spin coating and patterning. After dicing the wafer, a process of separating the semiconductor chip from the wafer piece by piece is performed, and then the separated semiconductor chip is mounted. The separated chip C1 can be formed to be a mount structure such as a chip on glass (COG), a tape carrier package (TCP), a chip on film (COF), etc.
  • As described above, the bump 43 is formed on the second passivation film 37 and placed in a flat location slightly detached from an area of the Al pad 33 rather than being directly on the Al pad 33. An electrical connection between the Al pad 33 and the bump 43 is made by the redistribution metal line 39 a. Thus, a flat surface of an upper portion of the bump without any step difference can be obtained in a final chip structure C1, and thereby simplifying the bonding process and increasing reliability of connected parts. Furthermore, chip size need not change despite a bigger bump size. Bump 43 may be enlarged even though the Al pad 33 is embodied in a fine pitch. In addition, the pitch of the Al pad 33 can be minimized to reduce chip size because the Al pad 33 made with a fine pitch does not influence the size of the bump 43.
  • As illustrated in FIG. 12, a semiconductor chip C1 with the bump 43 formed by the aforementioned method includes the first passivation film 35 covering and partially exposing the pad 33 formed on an upper portion of the chip. The second passivation film 37 is formed on the first passivation film 35 exposing the upper portion of the pad 33 and the nearby first passivation film 35. The bump 43 has a flat upper surface since it is formed on the second passivation film 37 in a flat location detached from the pad location. The electrical connection is performed by the redistribution metal line 39 a extended from the upper portion of the pad to a lower portion of the bump 43. The bump 43 is exposed and the redistribution metal line 39 a is protected by the third passivation film 47.
  • As described above, this semiconductor chip has a simple bonding process and an enhanced reliability of connected parts since a substantially flat surface can be obtained without an occurrence of step difference on the upper portion of the bump 43.
  • FIGS. 13 through 16 are cross-sections illustrating a method of forming a redistribution bump according to a second embodiment of the present invention. Identical reference numerals have been used to designate identical elements throughout FIGS. 6 to 12. Overlapping explanations with the first embodiment are omitted.
  • An explanation on the second embodiment will follow one on bump formation in FIGS. 6 through 8. In one embodiment of the present embodiment, the first photoresist pattern 41 used in forming the bump 43 is removed by ashing and stripping as shown in FIG. 13.
  • Referring to FIG. 14, a new photoresist pattern 44 is formed a predetermined width from an opening of the first passivation film 35 in the Al pad 33 to the bump 43. The redistribution metal line 39 a remains as presented in FIG. 15 by etching the metal layer 39 while using the photoresist pattern 44 as an etching mask.
  • After removing the photoresist pattern 44, a chip structure C2 is obtained as shown in FIG. 16 by forming the third passivation film 47 as explained in FIG. 12.
  • Although the second photoresist pattern 41 a is formed by additionally exposing the first photoresist pattern 41 in the first embodiment, the new photoresist pattern 44 is formed after removing the first photoresist pattern 41 in the present embodiment. The new photoresist pattern 44 is capable of coating the upper portion of the bump 43 and can protect the bump 43 from damage when etching the lower portion of metal layer 39.
  • FIGS. 17 through 21 are cross-sections illustrating a method of forming a redistribution bump according to a third embodiment of the present invention. Overlapping explanations of the first and second embodiment will be omitted.
  • Referring to FIG. 17, an upper portion of an Al pad 53 is exposed by applying and patterning a first passivation film 55 on an upper portion of a wafer-state chip 51. After applying and patterning a second passivation film 57, a portion of the Al pad 53 is exposed.
  • A metal layer 59 may be formed over the resulting structure including the second passivation film 57. Example metal layers 59 include TiW, Au, Cr, Cu, Ti, Ni, NiV, Pd, and a layered film may be made of combinations of these eight materials. Then, a first photoresist pattern 61 is formed on the metal layer 59. The first photoresist pattern 61 has an opening O at a location where an additional redistribution metal line for the electrical connection will be formed. The additional redistribution metal layer 63 is formed in the opening O using electroplating. One of Au, an Au alloy, and Ni/Au with a thickness of 0.1 um˜20 um may be used for the additional redistribution metal layer 63.
  • Thereafter, the first photoresist pattern 61 is removed by stripping, as shown in FIG. 18.
  • Referring to FIG. 19, a second photoresist pattern 65 is formed over the metal layer 59. The second photoresist pattern 65 has an opening R in which a bump can be formed. A bump 67 may be formed, for example, by filling gold or a gold alloy inside the opening R via electroplating.
  • Referring to FIG. 20, the second photoresist pattern 65 used in forming the bump 67 is removed. Thereafter, a third photoresist pattern 69 is formed to set a predetermined width away from the opening of the first passivation film 55 in the Al pad 53 to the bump 67. The third photoresist pattern 69 may be formed by additionally exposing and developing the second photoresist pattern 65, instead of removing it. Using the third photoresist pattern 69 as an etching mask, the metal layer 59 is etched, and the metal line 59 a is left as shown in FIG. 21. Then, after removing the third photoresist pattern 69, a final chip structure C3 is obtained by forming a third passivation film 71 so as to expose the bump 67.
  • In the embodiments of the present embodiment, like the first and second embodiment, the upper portion of the bump 67 is substantially flat, and thus simplifying a bonding process. However, unlike the first and second embodiment, the additional redistribution metal line 63 prevents a short circuit and enhances the reliability of the present embodiment.
  • A bump having a flat upper surface is obtained as described in FIGS. 12 and 21, based on the aforementioned method. Various mount structures are possible according to a method of mounting a chip structure having such a bump. FIGS. 22 through 25 are cross-sections illustrating various examples of mount structures with a high reliability using a semiconductor chip structure according to a fourth embodiment of the present invention. For convenience, examples of mounting the chip C1 in the first embodiment are illustrated.
  • A chip on glass (COG) mount structure in which the chip C1 is mounted on a liquid crystal panel (LCP) 100 is illustrated in an embodiment shown in FIG. 22. Specifically, the chip C1 having the bump 43 according to an embodiment of the present invention is thermally pressured using an anisotropic conductive film (ACF) 110 and is mounted on the LCP 100. The ACF 110 has a small conductive particle 107 in a thermosetting resin film 105. After the ACF is adhered to an electrode 102 (or a pad) of the LCP 100 in which conductive adhesion is performed and the bump 43 is attached to the electrode 102, the electrical connection is made vertically through a thermal pressure process. The conductive particle 107 may be a polymer or a glass ball coated by gold, silver, or nickel. A reference numeral 103 is an insulation film.
  • A COG mount structure in which the chip C1 is mounted on the LCP 100 is illustrated in the embodiment in FIG. 23. Particularly, the chip C1 having the bump 43 according to an embodiment of the present invention is thermally pressured using a non-conductive paste (NCP) 120 and is mounted on a LCP 100.
  • FIGS. 24 and 25 are cross-sections of a chip on film (COF) and a tape carrier package (TCP) mount structure, respectively. While the COG mount structure as described in FIGS. 22 and 23 has a bigger-sized LCD from mounting the chip on the LCP, the COF and TCP structures may be compact since the chip is mounted using an extra film, and thus the film having the chip can be bent toward a rear side of the LCP.
  • Referring to FIGS. 24 and 25, mutually corresponding first and second signal wires (or copper lead) 140 and 145 are plurally formed on a base film 130 formed of a material such as polyimide and a solder resist 150 is formed on the first and second signal wires 140 and 145, respectively. The solder resist 150 also exposes a portion of the first and second signal wires 140 and 145, respectively. Then, a chip is disposed so that each bump 34 contacts with the first and second signal wires 140 and 145. The chip and the first and second signal wires 140 and 145 are connected via the bump 43. In addition, a resin 155 is formed on both ends of the chip and covers the solder resist 150, the first and second signal wires 140 and 145, and the bump 43.
  • The TCP mount structure in FIG. 25 is similar with the mount structure in FIG. 24, except that the former has the base film 130 with a hollow center portion.
  • The mount structure including a semiconductor chip with a redistribution bump as presented in the present invention has excellent connection reliability since the mount structure uses a substantially flat bump.
  • As described above, the bump having the flat upper surface and is capable of expanding an area within the same pitch can be formed according to embodiments of the present invention. In addition, it is not necessary for such a bump to increase the pad area inside the chip. Thus, manufacturing costs can be lowered by increasing the number of net dies and decreasing the chip size. This feature is very useful for LDI fine pitch products.
  • Furthermore, since the flat upper surface of the bump can simplify the assembling process and obtain tolerance and can reduce defects in the assembly, a manufacturing process of the circuit thin film is simplified, therefore reducing processing costs.
  • While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as defined by the following claims.

Claims (16)

1. A semiconductor chip mounted on an external electronic device, the semiconductor chip comprising:
a bump coupled between a semiconductor chip pad and an external electronic device,
wherein the bump having a substantially flat upper surface is formed in a substantially flat location beyond a location of a pad and is connected to the pad via a redistribution metal line.
2. The semiconductor chip of claim 1, wherein the pad and the bump have at least one layered substantially flat passivation film formed therebetween.
3. The semiconductor chip of claim 1, wherein the bump is made of one of gold and a gold alloy.
4. The semiconductor chip of claim 1, wherein the redistribution metal line covering the upper portion of the pad is extended under the bump.
5. The semiconductor chip of claim 1, wherein the redistribution metal line is made by layering one selected from the group consisting of TiW, Au, Cr, Cu, Ti, Ni, NiV, Pd, or a compound line made of at least two of the eight materials.
6. The semiconductor chip of claim 1, wherein the redistribution metal line and the bump have an additional redistribution metal line formed therebetween.
7. The semiconductor chip of claim 6, wherein the additional redistribution metal line is made of one selected from the group consisting of Au, an Au alloy, and Ni/Au.
8. A semiconductor chip comprising:
a substrate having a pad formed thereon;
a first passivation film overlying the chip and partially exposing an upper portion of the pad;
a second passivation film formed on the first passivation film to expose the upper portion of the pad and a portion of the first passivation film;
a bump having a substantially flat surface on the upper portion of the second passivation film in a substantially flat location detached from a location of the pad;
a redistribution metal line extending from the upper portion of the pad to a lower portion of the bump for an electrical connection between the pad and the bump; and
a third passivation film exposing the bump and protecting the redistribution metal line.
9. The semiconductor chip of claim 8, wherein the bump is made of one of gold and a gold alloy.
10. The semiconductor chip of claim 8, wherein the redistribution metal line is made by layering one selected from the group consisting of TiW, Au, Cr, Cu, Ti, Ni, NiV, Pd, or a compound line made of at least two of the eight materials.
11. The semiconductor chip of claim 8, wherein the redistribution metal line and bump have an additional redistribution metal line formed therebetween.
12. The semiconductor chip of claim 11, wherein the additional redistribution metal line is made of one selected from the group consisting of Au, an Au alloy, and Ni/Au.
13. A mount structure comprising the semiconductor chip of claim 8 mounted on a liquid crystal panel (LCP), in which the bump and an electrode of the LCP are connected.
14. The mount structure of claim 13, wherein the semiconductor chip and the LCP are attached together with an anisotropic conductive film or non-conductive adhesive.
15. A mount structure comprising the semiconductor chip of claim 8 mounted on a film in which a circuit pattern is made and including the circuit pattern in which the bump and the circuit pattern of the film are connected.
16. A system comprising:
a liquid crystal panel (LCP) having an electrode; and
a semiconductor chip having a semiconductor chip pad, the semiconductor chip including a bump coupled between a semiconductor chip pad and the electrode of the LCP, wherein the bump having a substantially flat upper surface is formed in a substantially flat location beyond a location of the pad and is connected to the pad via a redistribution metal line.
US11/421,680 2003-07-23 2006-06-01 Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same Abandoned US20060202334A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120295404A1 (en) * 2009-11-12 2012-11-22 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing semiconductor package
US20170236795A1 (en) * 2014-02-03 2017-08-17 Dexerials Corporation Connection body

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
TWI254395B (en) * 2005-02-03 2006-05-01 Advanced Semiconductor Eng Chip structure and wafer structure
JP2006310530A (en) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd Circuit device and its manufacturing process
CN100405548C (en) * 2005-05-10 2008-07-23 义隆电子股份有限公司 Technique and structure for making convex
TWI305951B (en) 2005-07-22 2009-02-01 Megica Corp Method for forming a double embossing structure
KR100721163B1 (en) * 2005-09-27 2007-05-23 삼성전기주식회사 Image sensor module and camera module using the same and manufacturing method of the camera module
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
KR100652443B1 (en) 2005-11-17 2006-12-01 삼성전자주식회사 Redistribution interconnection structure of wafer level package and the method for manufacturing thereof
JP4343177B2 (en) * 2006-02-06 2009-10-14 富士通マイクロエレクトロニクス株式会社 Semiconductor device
TWI310983B (en) * 2006-10-24 2009-06-11 Au Optronics Corp Integrated circuit structure, display module, and inspection method thereof
CN101226889B (en) * 2007-01-15 2010-05-19 百慕达南茂科技股份有限公司 Reconfiguration line structure and manufacturing method thereof
JP5018155B2 (en) * 2007-03-16 2012-09-05 富士通セミコンダクター株式会社 Wiring board, electronic component mounting structure, and semiconductor device
US7858438B2 (en) * 2007-06-13 2010-12-28 Himax Technologies Limited Semiconductor device, chip package and method of fabricating the same
CN101355066B (en) * 2008-05-26 2011-05-18 苏州晶方半导体科技股份有限公司 Packaging structure and manufacturing method thereof
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
JP5693375B2 (en) * 2010-05-28 2015-04-01 シチズンホールディングス株式会社 Semiconductor light emitting device
US9202713B2 (en) * 2010-07-26 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch
US9281234B2 (en) * 2013-03-12 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. WLCSP interconnect apparatus and method
US9041215B2 (en) 2013-03-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Single mask package apparatus and method
US9698079B2 (en) 2014-01-03 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures between external electrical connectors
TWI641094B (en) * 2014-09-17 2018-11-11 矽品精密工業股份有限公司 Substrate structure and method of manufacture
JP6628031B2 (en) * 2015-11-04 2020-01-08 ローム株式会社 Electronic components
TWI610410B (en) * 2016-11-23 2018-01-01 南茂科技股份有限公司 Re-distribution layer structure and manufacturing method thereof
KR102422460B1 (en) 2017-08-22 2022-07-19 삼성전자주식회사 A semiconductor device
KR102019355B1 (en) * 2017-11-01 2019-09-09 삼성전자주식회사 Semiconductor package
CN110797372A (en) * 2018-08-01 2020-02-14 创王光电股份有限公司 Flexible display
US11817406B2 (en) * 2021-09-23 2023-11-14 Qualcomm Incorporated Semiconductor die employing repurposed seed layer for forming additional signal paths to back end-of-line (BEOL) structure, and related integrated circuit (IC) packages and fabrication methods

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5607877A (en) * 1993-12-28 1997-03-04 Fujitsu Limited Projection-electrode fabrication method
US5834844A (en) * 1995-03-24 1998-11-10 Shinko Electric Industries Co., Ltd. Semiconductor device having an element with circuit pattern thereon
US5925931A (en) * 1996-10-31 1999-07-20 Casio Computer Co., Ltd. Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US6329608B1 (en) * 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
US20020043723A1 (en) * 2000-10-16 2002-04-18 Hironobu Shimizu Semiconductor device and manufacturing method thereof
US6914332B2 (en) * 2002-01-25 2005-07-05 Texas Instruments Incorporated Flip-chip without bumps and polymer for board assembly
US6967399B2 (en) * 2000-12-12 2005-11-22 Fujitsu Limited Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal
US7057283B2 (en) * 1999-10-29 2006-06-06 Hitachi, Ltd. Semiconductor device and method for producing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3685429B2 (en) * 1996-08-06 2005-08-17 シャープ株式会社 Schottky junction analysis method, semiconductor wafer evaluation method, insulating film evaluation method, and Schottky junction analysis device
JP2000340593A (en) * 1999-05-28 2000-12-08 Sony Corp Manufacture of semiconductor device
KR100298827B1 (en) 1999-07-09 2001-11-01 윤종용 Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate
JP2001237261A (en) * 1999-12-15 2001-08-31 Seiko Epson Corp Semiconductor, device and method for manufacturing the same
JP2001284387A (en) * 2000-04-04 2001-10-12 Citizen Watch Co Ltd Semiconductor device and method of manufacture, and mounting structure of the semiconductor device
JP3848080B2 (en) * 2000-12-19 2006-11-22 富士通株式会社 Manufacturing method of semiconductor device
JP2002231749A (en) * 2001-02-01 2002-08-16 Casio Comput Co Ltd Semiconductor device and its bonding structure
JP2003017530A (en) * 2001-06-28 2003-01-17 Hitachi Ltd Semiconductor device and its mounting method
JP3940891B2 (en) * 2001-11-21 2007-07-04 セイコーエプソン株式会社 Bump forming method and flip chip manufacturing method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5607877A (en) * 1993-12-28 1997-03-04 Fujitsu Limited Projection-electrode fabrication method
US5834844A (en) * 1995-03-24 1998-11-10 Shinko Electric Industries Co., Ltd. Semiconductor device having an element with circuit pattern thereon
US6329608B1 (en) * 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US5925931A (en) * 1996-10-31 1999-07-20 Casio Computer Co., Ltd. Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer
US7057283B2 (en) * 1999-10-29 2006-06-06 Hitachi, Ltd. Semiconductor device and method for producing the same
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
US20020043723A1 (en) * 2000-10-16 2002-04-18 Hironobu Shimizu Semiconductor device and manufacturing method thereof
US6967399B2 (en) * 2000-12-12 2005-11-22 Fujitsu Limited Semiconductor device manufacturing method having a step of applying a copper foil on a substrate as a part of a wiring connecting an electrode pad to a mounting terminal
US6914332B2 (en) * 2002-01-25 2005-07-05 Texas Instruments Incorporated Flip-chip without bumps and polymer for board assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120295404A1 (en) * 2009-11-12 2012-11-22 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing semiconductor package
US20170236795A1 (en) * 2014-02-03 2017-08-17 Dexerials Corporation Connection body
US9960138B2 (en) * 2014-02-03 2018-05-01 Dexerials Corporation Connection body
TWI645480B (en) * 2014-02-03 2018-12-21 日商迪睿合股份有限公司 Connector, method of manufacturing the connector, electronic device

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KR20050011404A (en) 2005-01-29

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