JP2001284387A - Semiconductor device and method of manufacture, and mounting structure of the semiconductor device - Google Patents

Semiconductor device and method of manufacture, and mounting structure of the semiconductor device

Info

Publication number
JP2001284387A
JP2001284387A JP2000101816A JP2000101816A JP2001284387A JP 2001284387 A JP2001284387 A JP 2001284387A JP 2000101816 A JP2000101816 A JP 2000101816A JP 2000101816 A JP2000101816 A JP 2000101816A JP 2001284387 A JP2001284387 A JP 2001284387A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor substrate
film
semiconductor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000101816A
Other languages
Japanese (ja)
Inventor
Koichi Ueda
光一 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2000101816A priority Critical patent/JP2001284387A/en
Publication of JP2001284387A publication Critical patent/JP2001284387A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a connection which causes no defective conduction, e.g. short circuit or open circuit, or unstable connection stably and inexpensively, even if the area is limited due to high density and fine pitch of transparent electrode pads on a glass substrate and bump electrodes on a semiconductor chip. SOLUTION: The semiconductor device comprises I/O terminals, i.e., electrode pads 16 provided on a semiconductor substrate 2, an insulation film 6 provided on the semiconductor substrate 2 to expose the electrode pads 16, lower electrodes having at least aluminum provided on the electrode pads 16, and bump electrodes 4 provided on the lower electrodes where acicular bumps 42 are provided on the surface of the lower electrodes and protrusions and recesses corresponding to the acicular bumps 42 on the surface of the lower electrodes are provided on the top of the bump electrode.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子の形成
面側を下向きに実装する半導体チップのフェースダウン
ボンディング技術にかんし、電気的および機械的に接続
するための半導体チップ上の突起電極の構造およびその
製造方法とフェースダウンボンディングによる半導体装
置の実装構造にかんする。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a face-down bonding technique for a semiconductor chip in which a semiconductor element forming surface is mounted downward, and a structure of a protruding electrode on the semiconductor chip for electrical and mechanical connection. And a manufacturing method thereof and a semiconductor device mounting structure by face-down bonding.

【0002】[0002]

【従来の技術】近年、半導体チップの高密度化にともな
い、電極間ピッチが極端に小さくなってきており、回路
基板と半導体チップの実装接続面積、すなわち接続する
際の電極面積が狭くなる傾向にある。
2. Description of the Related Art In recent years, the pitch between electrodes has become extremely small with the increase in the density of semiconductor chips, and the mounting connection area between a circuit board and a semiconductor chip, that is, the electrode area at the time of connection, has become narrow. is there.

【0003】その代表的なものとして、図10を用いて
COG(チップ・オン・グラス)ペースト実装法の実装
構造を説明する。
As a representative example, a mounting structure of a COG (chip-on-glass) mounting method will be described with reference to FIG.

【0004】以下、図11から図19を用いて製造方法
を説明する。
Hereinafter, a manufacturing method will be described with reference to FIGS.

【0005】液晶表示装置を構成するガラスからなる基
板の周辺部を拡張し、この拡張した領域に、液晶表示装
置を駆動する複数の半導体チップを搭載した従来技術と
してチップオングラス(以下COGと称す)ペースト実
装がある。
[0005] A chip-on-glass (hereinafter referred to as COG) is a conventional technique in which a peripheral portion of a glass substrate constituting a liquid crystal display device is extended and a plurality of semiconductor chips for driving the liquid crystal display device are mounted in the extended region. ) There is paste mounting.

【0006】図10に示すように、二枚のガラス基板2
4間の空隙に液晶48を封入し、印刷法で形成するシー
ル材54によってなる液晶表示装置38のガラス基板2
4上に真空蒸着法もしくはスパッタリング法を用いて形
成された、酸化インジウムスズ(以下ITOと称す)等
の透明電極46によって画素パターンを形成すると同時
に、ガラス基板24の周辺部を拡張し、この拡張した領
域にITO等の透明電極46を引き回し、この配線上に
液晶表示装置38を駆動する複数の半導体チップ8を実
装する。
As shown in FIG. 10, two glass substrates 2
The liquid crystal 48 is sealed in the gap between the four, and the glass substrate 2 of the liquid crystal display device 38 is formed by a sealing material 54 formed by a printing method.
At the same time, a pixel pattern is formed by a transparent electrode 46 made of indium tin oxide (hereinafter referred to as ITO) or the like formed on the substrate 4 by using a vacuum deposition method or a sputtering method. A transparent electrode 46 of ITO or the like is routed in the region thus formed, and a plurality of semiconductor chips 8 for driving the liquid crystal display device 38 are mounted on the wiring.

【0007】図10は、液晶表示装置に半導体チップの
実装を行った状態を示す断面図である。
FIG. 10 is a cross-sectional view showing a state where a semiconductor chip is mounted on a liquid crystal display device.

【0008】5μm〜50μmの高さの銅(Cu)や金
(Au)からなる突起電極4を有する半導体チップ8
と、ガラス基板24上にITOで形成された透明電極4
6パッドとを機械的および電気的に導電性接着剤44で
接続する。
Semiconductor chip 8 having protruding electrodes 4 made of copper (Cu) or gold (Au) having a height of 5 μm to 50 μm.
And a transparent electrode 4 formed of ITO on a glass substrate 24.
The six pads are mechanically and electrically connected with a conductive adhesive 44.

【0009】そして、半導体チップ8とガラス基板24
の隙間を封止樹脂で充填する構造になっている。
Then, the semiconductor chip 8 and the glass substrate 24
Is filled with a sealing resin.

【0010】液晶表示装置38上の入力側の透明電極配
線は、さらにフレキシブル基板32(以下FPCと称
す)の配線とFPC用の異方性導電膜36を介して電気
的機械的に接続している。
The input-side transparent electrode wiring on the liquid crystal display device 38 is further electrically and mechanically connected to the wiring of the flexible substrate 32 (hereinafter, referred to as FPC) via an anisotropic conductive film 36 for FPC. I have.

【0011】つぎに従来技術における前述に構造を形成
するための製造方法について図面を用いて説明する。
Next, a manufacturing method for forming the above-described structure in the prior art will be described with reference to the drawings.

【0012】図11で示すように、半導体基板2は、ア
ルミ配線12以外は、窒化シリコン膜(SiN)などの
絶縁膜6で覆われ外部とは電気的に絶縁されている。
As shown in FIG. 11, except for the aluminum wiring 12, the semiconductor substrate 2 is covered with an insulating film 6 such as a silicon nitride film (SiN) and is electrically insulated from the outside.

【0013】半導体基板2のアルミ配線12上に真空蒸
着法やスパッタリング法を用いて、金属拡散を防止する
バリヤメタル層でもあり電解メッキを行なうための電極
となる共通電極膜14を形成する。
A common electrode film 14, which is also a barrier metal layer for preventing metal diffusion and serves as an electrode for electrolytic plating, is formed on the aluminum wiring 12 of the semiconductor substrate 2 by using a vacuum evaporation method or a sputtering method.

【0014】つぎに、図12に示すようにレジスト膜2
6を形成し、選択的に突起電極を形成する箇所に電解メ
ッキを行なうために、アルミ配線12上部の必要箇所を
選択的に開口する。
Next, as shown in FIG.
6 is formed, and a necessary portion above the aluminum wiring 12 is selectively opened in order to perform electrolytic plating on a portion where a protruding electrode is to be selectively formed.

【0015】その後、図13に示すように、共通電極膜
14上に銅(Cu)を電解メッキ法で形成し、その後、
金(Au)を電解メッキ法を用いて形成することによっ
て、マッシュルーム状の突起電極4を形成する。
Thereafter, as shown in FIG. 13, copper (Cu) is formed on the common electrode film 14 by an electrolytic plating method.
The mushroom-shaped protruding electrode 4 is formed by forming gold (Au) using an electrolytic plating method.

【0016】その後、図14に示すようにレジスト膜2
6を除去し、図15に示すように、突起電極以外の共通
電極膜をエッチング液で除去する。
Thereafter, as shown in FIG.
6 is removed, and as shown in FIG. 15, the common electrode film other than the protruding electrodes is removed with an etchant.

【0017】最後に、半導体基板2内の隣接する半導体
チップの境界部を切断(以下ダイシングと称す)処理す
ることにより、半導体基板2を単個の半導体チップ8に
切り分ける。
Finally, the semiconductor substrate 2 is cut into single semiconductor chips 8 by cutting (hereinafter referred to as dicing) the boundary between adjacent semiconductor chips in the semiconductor substrate 2.

【0018】つぎに、図16に示すように、半導体チッ
プ8上の突起電極4に銀(Ag)、または銀(Ag)と
パラジウム(Pd)の合金膜などの導電性粒子を混入し
たエポキシ系の導電性接着剤44を転写法を用いて、塗
布し、図17に示すように、突起電極4に導電性接着剤
44塗布後の半導体チップ8とガラス基板24に形成さ
れた突起電極4に対応した透明電極46をアライメント
後、図18に示すようにフェースダウンボンディング実
装を行ない、熱硬化を行ない電気的および機械的に接続
する。
Next, as shown in FIG. 16, an epoxy-based material in which conductive particles such as silver (Ag) or an alloy film of silver (Ag) and palladium (Pd) are mixed into the bump electrodes 4 on the semiconductor chip 8. As shown in FIG. 17, the conductive adhesive 44 is applied to the semiconductor chip 8 and the projecting electrode 4 formed on the glass substrate 24 after applying the conductive adhesive 44 to the projecting electrode 4 as shown in FIG. After the alignment of the corresponding transparent electrodes 46, face-down bonding mounting is performed as shown in FIG. 18, heat curing is performed, and electrical and mechanical connections are made.

【0019】導電性接着剤44は、通常、エポキシ系接
着剤を使用するため、硬化は80℃〜120℃程度で熱
硬化を行ない、ガラス基板24上の透明電極46と半導
体チップ8上の突起電極4を接着し、電気的および機械
的に接続する。
Since the conductive adhesive 44 is usually an epoxy-based adhesive, it is hardened at about 80 ° C. to 120 ° C., so that the transparent electrode 46 on the glass substrate 24 and the projections on the semiconductor chip 8 are hardened. The electrodes 4 are bonded and electrically and mechanically connected.

【0020】最後に、図19に示したように、半導体チ
ップ8とガラス基板24の隙間に封止樹脂22を充填
し、硬化させることによって、さらに信頼性を高めてい
る。
Finally, as shown in FIG. 19, the gap between the semiconductor chip 8 and the glass substrate 24 is filled with a sealing resin 22 and cured to further improve the reliability.

【0021】また、図10で右方に形成されている、ガ
ラス基板24上の透明電極46上には、導電性粒子が混
在されているFPC用異方性導電膜36を介在させてF
PC基板32を配置し、そのFPC基板32に対しても
加熱した状態で加圧し、熱圧着を行なう。
On the transparent electrode 46 on the glass substrate 24 formed on the right side in FIG. 10, an FPC anisotropic conductive film 36 containing conductive particles is interposed.
The PC board 32 is arranged, and pressure is applied to the FPC board 32 in a heated state to perform thermocompression bonding.

【0022】FPC基板32は、半導体チップ8に給電
したり入力信号を与えるためにポリイミドシート上に銅
(Cu)配線電極がパターンニングされているフィルム
であり、接続ピッチは、80〜100μm程度である。
The FPC board 32 is a film in which copper (Cu) wiring electrodes are patterned on a polyimide sheet in order to supply power to the semiconductor chip 8 and to provide an input signal. The connection pitch is about 80 to 100 μm. is there.

【0023】[0023]

【発明が解決しようとする課題】従来技術では、安定し
て接続可能な電極間ピッチは150μm程度であり、こ
れより電極間ピッチが狭くなると、半導体チップ上の突
起電極への導電性接着剤の転写の際に転写ダレ現象が発
生して、隣接電極間のショートが発生する。
In the prior art, the pitch between the electrodes which can be stably connected is about 150 μm, and when the pitch between the electrodes becomes narrower than this, the conductive adhesive is applied to the protruding electrodes on the semiconductor chip. A transfer sagging phenomenon occurs during transfer, and a short circuit between adjacent electrodes occurs.

【0024】さらに、導電性接着剤の転写ばらつきによ
り、半導体チップ上の突起電極に導電性接着剤が転写さ
れない箇所が多数発生し、オープン不良になる。
Further, due to the variation in the transfer of the conductive adhesive, a number of places where the conductive adhesive is not transferred to the protruding electrodes on the semiconductor chip occur, resulting in an open defect.

【0025】[発明の目的]本発明の目的は、上記課題
を解決して、ガラス基板の透明電極パッドおよび半導体
チップ上の突起電極の高密度、および狭ピッチ化の際、
狭面積化しても、ショートやオープン等の導通不良や導
通不安定のない接続を、安定かつ安価に供給できる半導
体装置とその製造方法ならびに半導体装置の実装構造を
提供することである。
[Object of the Invention] An object of the present invention is to solve the above-mentioned problems and to reduce the pitch and pitch of the transparent electrode pads on the glass substrate and the bump electrodes on the semiconductor chip.
An object of the present invention is to provide a semiconductor device, a method of manufacturing the semiconductor device, and a mounting structure of the semiconductor device, which can supply a connection without a conduction failure such as a short circuit or an open circuit or a conduction instability even when the area is reduced, stably and inexpensively.

【0026】[0026]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置とその製造方法ならびに半導体
装置の実装構造は、下記記載の手段を採用する。
Means for Solving the Problems In order to achieve the above object, the following means are adopted for a semiconductor device, a method of manufacturing the same and a mounting structure of the semiconductor device according to the present invention.

【0027】本発明の半導体装置は、半導体基板に設け
る入出力端子である電極パッドと、その半導体基板上に
設け、電極パッドが露出するように設ける絶縁膜と、電
極パッド上に設け、すくなくともアルミニウムを有する
下部電極と、その下部電極上に設ける突起電極とを備
え、下部電極表面には針状突起を有し、その下部電極表
面の針状突起に対応して突起電極の頂部には凹凸を有す
ることを特徴とする。
A semiconductor device according to the present invention comprises an electrode pad as an input / output terminal provided on a semiconductor substrate, an insulating film provided on the semiconductor substrate so that the electrode pad is exposed, and an aluminum film provided on the electrode pad. And a protruding electrode provided on the lower electrode, having a needle-like projection on the surface of the lower electrode, and having irregularities on the top of the projection electrode corresponding to the needle-like projections on the surface of the lower electrode. It is characterized by having.

【0028】本発明の半導体装置の製造方法において
は、パッド電極を形成した半導体基板上に絶縁膜を形成
し、その絶縁膜を選択的に開口してパッド電極を露出さ
せる工程と、全面にすくなくともアルミニウムを有する
共通電極膜を形成する工程と、高温と低温との温度サイ
クルを行ない、その共通電極膜表面に針状突起を形成す
る工程と、全面にメッキレジストを形成し、フォトリソ
グラフィー処理によりパッド電極領域上に開口を形成す
る工程と、メッキレジストの開口内に突起電極をメッキ
処理によって形成する工程と、突起電極に整合する領域
の突起電極膜を残すようにその共通電極膜をエッチング
処理して下部電極を形成する工程と、半導体基板をダイ
シングして半導体チップを形成する工程とを有すること
を特徴とする。
In the method of manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a semiconductor substrate having a pad electrode formed thereon and selectively opening the insulating film to expose the pad electrode; A step of forming a common electrode film having aluminum, a step of performing a temperature cycle of high and low temperatures to form needle-like projections on the surface of the common electrode film, forming a plating resist on the entire surface, and forming a pad by photolithography. Forming an opening on the electrode region, forming a protruding electrode in the opening of the plating resist by plating, and etching the common electrode film so as to leave a protruding electrode film in a region matching the protruding electrode. And forming a semiconductor chip by dicing the semiconductor substrate.

【0029】本発明の半導体装置の実装構造は、半導体
基板に設ける入出力端子である電極パッドと、その半導
体基板上に設け、電極パッドが露出するように設ける絶
縁膜と、電極パッド上に設け、すくなくともアルミニウ
ムを有する下部電極と、その下部電極上に設ける突起電
極とを備え、下部電極表面には針状突起を有し、その下
部電極表面の針状突起に対応して突起電極の頂部には凹
凸を有する半導体チップと、配線パターンを有する回路
基板と、頂部に凹凸を有する突起電極と配線パターンと
を接続し、半導体チップと回路基板のあいだに設ける封
止樹脂を有することを特徴とする。
The mounting structure of the semiconductor device according to the present invention comprises an electrode pad which is an input / output terminal provided on a semiconductor substrate, an insulating film provided on the semiconductor substrate so as to expose the electrode pad, and an electrode film provided on the electrode pad. A lower electrode having at least aluminum, and a protruding electrode provided on the lower electrode, having a needle-like projection on the surface of the lower electrode, and corresponding to the needle-like projection on the surface of the lower electrode, on the top of the protruding electrode. Is characterized by having a sealing resin provided between the semiconductor chip and the circuit board, connecting the semiconductor chip having the unevenness, the circuit board having the wiring pattern, and the projection electrode having the unevenness on the top and the wiring pattern. .

【0030】[作用]半導体基板上に突起電極を形成す
る際、共通電極膜を形成するとき、共通電極膜の第1の
突起電極膜であるアルミニウム(Al)の膜上に針状突
起を形成することによって、共通電極膜上に微小突起を
多数形成する。
[Operation] When forming a projection electrode on a semiconductor substrate, when forming a common electrode film, needle-like projections are formed on an aluminum (Al) film which is a first projection electrode film of the common electrode film. By doing so, a large number of minute projections are formed on the common electrode film.

【0031】そして、その後、メッキ工程にて突起電極
を形成するが、このときバンプ表面には、共通電極膜の
表面に形成された針状突起にメッキが等方的成長し、突
起電極上に微小突起が形成される。
Thereafter, a protruding electrode is formed in a plating step. At this time, plating isotropically grows on needle-like protrusions formed on the surface of the common electrode film on the bump surfaces, and the bumps are formed on the protruding electrodes. Small protrusions are formed.

【0032】半導体基板上に形成した突起電極表面をフ
ラットではなく、本発明の半導体装置においては凹凸状
にし、回路基板上の電極パッドと半導体チップ上に形成
された突起電極との接続を面接触実装から点接触実装に
する。
The surface of the protruding electrode formed on the semiconductor substrate is not flat, but is made uneven in the semiconductor device of the present invention, and the connection between the electrode pad on the circuit board and the protruding electrode formed on the semiconductor chip is made in surface contact. Change from mounting to point contact mounting.

【0033】回路基板と半導体チップの機械的な接着
は、エポキシ樹脂等の熱硬化樹脂を介し、熱圧着を行な
う。
The mechanical bonding between the circuit board and the semiconductor chip is performed by thermocompression bonding via a thermosetting resin such as an epoxy resin.

【0034】本発明による半導体装置の構造と製造方法
は、半導体基板上に形成した突起電極上に選択的に微小
突起を多数形成し、突起電極表面を微細な凹凸が多数形
成された状態にする。
According to the structure and the manufacturing method of a semiconductor device of the present invention, a large number of fine projections are selectively formed on a projection electrode formed on a semiconductor substrate, and the surface of the projection electrode is in a state where a large number of fine irregularities are formed. .

【0035】このことにより、回路基板に形成された電
極パッドと突起電極の点接続を促すための接続点を多く
意図的に作製することにより、本発明の半導体装置にお
いては、狭ピッチで小面積化された半導体装置の接続安
定化が図れる。
In this way, a large number of connection points for promoting the point connection between the electrode pads formed on the circuit board and the protruding electrodes are intentionally produced, so that the semiconductor device of the present invention has a small pitch and a small area. Connection of the integrated semiconductor device can be stabilized.

【0036】さらに、突起電極上に微小突起を多数形成
することで、熱圧着する際の表面積を増やすことがで
き、エポキシ等の熱硬化性樹脂で接続した箇所の機械的
接着力が増加する。
Further, by forming a large number of fine projections on the projection electrodes, the surface area at the time of thermocompression bonding can be increased, and the mechanical adhesive strength at the place connected by a thermosetting resin such as epoxy increases.

【0037】また、熱硬化樹脂中に導電粒子を混入した
異方性導電膜を使用しないため、簡便でしかも安価に工
業的に優れた半導体構造とその製造方法を提供できる。
Since an anisotropic conductive film in which conductive particles are mixed in a thermosetting resin is not used, a simple and inexpensive industrially excellent semiconductor structure and a method for manufacturing the same can be provided.

【0038】[0038]

【発明の実施の形態】以下、図面を用いて本発明の最適
な実施の形態における半導体装置とその製造方法、およ
び半導体装置の実装構造を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described with reference to the accompanying drawings.

【0039】〔半導体装置の構造説明:図1〕図1に示
すように、本発明における半導体基板上に形成された突
起電極の構造を説明する。
[Structural Description of Semiconductor Device: FIG. 1] As shown in FIG. 1, the structure of a bump electrode formed on a semiconductor substrate according to the present invention will be described.

【0040】半導体基板2のアルミ電極12上に、アル
ミニウム(Al)とクロム(Cr)と銅(Cu)との積
層膜からなる共通電極膜14を有し、共通電極膜14上
に銅(Cu)と金(Au)とからなる突起電極を有して
いる。
A common electrode film 14 made of a laminated film of aluminum (Al), chromium (Cr), and copper (Cu) is provided on the aluminum electrode 12 of the semiconductor substrate 2, and copper (Cu) is provided on the common electrode film 14. ) And gold (Au).

【0041】この銅(Cu)と金(Au)とからなる突
起電極の頂部には多数のこぶ状の微小突起18が形成さ
れており、突起電極4表面は多数の凹凸を有することが
本発明の特徴となっている。
The bump electrode made of copper (Cu) and gold (Au) has a large number of bumps 18 formed on the top of the bump electrode, and the surface of the bump electrode 4 has a large number of irregularities. It is a feature of.

【0042】本発明における半導体装置の実装構造は、
15μm高さの金(Au)からなる突起電極4を有する
半導体チップと回路基板10上に形成された電極パッド
16を機械的および電気的にエポキシ樹脂などの熱硬化
性樹脂30で接続する。
The mounting structure of the semiconductor device according to the present invention is as follows.
A semiconductor chip having a projecting electrode 4 made of gold (Au) having a height of 15 μm and an electrode pad 16 formed on a circuit board 10 are mechanically and electrically connected with a thermosetting resin 30 such as an epoxy resin.

【0043】このエポキシ樹脂などの熱硬化性樹脂30
は、半導体チップ8と回路基板10の隙間の封止も兼ね
る構造となっている。
The thermosetting resin 30 such as the epoxy resin
Has a structure that also serves to seal the gap between the semiconductor chip 8 and the circuit board 10.

【0044】〔半導体装置の製造方法の説明:図1から
図6〕つぎに、本発明の実施の形態における半導体装置
の製造方法を説明する。なおこの実施形態の説明では、
COG実装を例に取り、半導体装置の製造方法を説明す
る。
[Description of Method for Manufacturing Semiconductor Device: FIGS. 1 to 6] Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. In the description of this embodiment,
A method for manufacturing a semiconductor device will be described using COG mounting as an example.

【0045】図2で示したように、半導体基板2上は半
導体基板2のアルミ配線12の開口部を有する絶縁膜6
で覆われている。
As shown in FIG. 2, on the semiconductor substrate 2, an insulating film 6 having an opening of the aluminum wiring 12 of the semiconductor substrate 2 is formed.
Covered with.

【0046】半導体基板2のアルミ配線12上に、電解
メッキ時の共通電極をとるための共通電極膜14を形成
する。この共通電極膜14は、半導体基板2全面に真空
蒸着法、またはスパッタリング法により形成する。
On the aluminum wiring 12 of the semiconductor substrate 2, a common electrode film 14 for forming a common electrode at the time of electrolytic plating is formed. The common electrode film 14 is formed on the entire surface of the semiconductor substrate 2 by a vacuum evaporation method or a sputtering method.

【0047】共通電極膜14は、半導体基板2側からア
ルミニウム(Al)を0.8μm、クロム(Cr)を
0.01μm、銅(Cu)を0.8μmの厚さにて順次
形成する。
The common electrode film 14 is formed by sequentially forming aluminum (Al) with a thickness of 0.8 μm, chromium (Cr) with a thickness of 0.01 μm, and copper (Cu) with a thickness of 0.8 μm from the semiconductor substrate 2 side.

【0048】図2に示すように、共通電極の第1の膜で
あるアルミニウム(Al)の共通電極膜の形成したの
ち、すなわちクロム(Cr)と銅(Cu)を形成するま
えに、4μm程度の針状突起をアルミニウム(Al)膜
の表面に形成する。
As shown in FIG. 2, after forming the common electrode film of aluminum (Al) which is the first film of the common electrode, that is, before forming chromium (Cr) and copper (Cu), about 4 μm. Are formed on the surface of the aluminum (Al) film.

【0049】針状突起は、アルミニウム(Al)薄膜表
面から突き出した刺に似た突起である。針状突起は、一
般にアルミニウム(Al)薄膜形成時、あるいは、アル
ミニウム(Al)シンタのようなアルミニウム(Al)
薄膜形成後に半導体基板2に加えられる温度サイクル時
に発生する。
The needle-like projection is a projection similar to a stab protruding from the surface of the aluminum (Al) thin film. The needle-like projections are generally formed at the time of forming an aluminum (Al) thin film or aluminum (Al) such as aluminum (Al) sinter.
It occurs during a temperature cycle applied to the semiconductor substrate 2 after the formation of the thin film.

【0050】アルミニウム(Al)は、半導体基板2と
このアルミニウム(Al)の熱膨張係数差により、常温
から400℃程度、さらには冷却までの温度サイクルを
2回程度加えることで、針状突起が半導体基板2全面に
発生し、針状の突起が形成される。
Due to the difference in the thermal expansion coefficient between the semiconductor substrate 2 and the aluminum (Al), the aluminum (Al) is subjected to a temperature cycle from room temperature to about 400 ° C. and further to about two cycles of cooling to form needle-like projections. Needle-like projections are formed on the entire surface of the semiconductor substrate 2.

【0051】アルミニウム(Al)薄膜上の針状突起
は、圧縮圧力の大きさに応じて成長するが、圧縮圧力の
主な発生原因は、半導体基板2とアルミニウム(Al)
薄膜の熱膨張係数の差である。
The needle-like projections on the aluminum (Al) thin film grow according to the magnitude of the compression pressure. The main cause of the compression pressure is that the semiconductor substrate 2 and the aluminum (Al)
This is the difference between the thermal expansion coefficients of the thin films.

【0052】アルミニウム(Al)の熱膨張係数は2
3.5×10-6-1であるが、半導体基板2は、2.5
×10-6-1である。
The coefficient of thermal expansion of aluminum (Al) is 2
3.5 × 10 −6 ° C. −1 , but the semiconductor substrate 2
× 10 -6 ° C -1 .

【0053】したがって、アルミニウム(Al)の薄膜
を形成した半導体基板2に加熱、冷却等の温度サイクル
を加えると、その上のアルミニウム(Al)薄膜は、1
0倍も伸縮しようとする。
Therefore, when a temperature cycle such as heating and cooling is applied to the semiconductor substrate 2 on which the aluminum (Al) thin film is formed, the aluminum (Al) thin film thereon becomes 1
Try to expand and contract 0 times.

【0054】この結果、圧縮圧力が発生し、針状突起の
成長を引き起こす。すなわち、図2に示したように、半
導体基板2上には、針状の微小突起を多数形成すること
ができる。
As a result, a compressive pressure is generated, causing the growth of needle-like projections. That is, as shown in FIG. 2, a large number of needle-like minute projections can be formed on the semiconductor substrate 2.

【0055】つぎに、針状突起を形成したアルミニウム
(Al)上に、クロム(Cr)膜、銅(Cu)膜を順次
形成する。
Next, a chromium (Cr) film and a copper (Cu) film are sequentially formed on the aluminum (Al) on which the acicular projections are formed.

【0056】その後、図3に示すように、レジスト膜2
6である感光性樹脂(フォトレジスト)を回転塗布法に
より共通電極膜14上の全面に厚さ17μmで形成す
る。
Thereafter, as shown in FIG.
A photosensitive resin (photoresist) 6 having a thickness of 17 μm is formed on the entire surface of the common electrode film 14 by a spin coating method.

【0057】さらに、露光装置により所定のフォトマス
クを使用して感光性樹脂を露光し、その後、現像処理を
行なうフォトリソグラフィー処理により、感光性樹脂の
パターンニングを行なう。
Further, the photosensitive resin is exposed using a predetermined photomask by an exposure device, and thereafter, the photosensitive resin is patterned by a photolithography process of performing a developing process.

【0058】このパターンニングによって感光性樹脂
は、後で突起電極4を形成する予定領域に開口を形成し
て、共通電極膜14を露出させる。
By this patterning, the photosensitive resin forms an opening in a region where the bump electrode 4 is to be formed later, exposing the common electrode film 14.

【0059】このとき、突起電極4をもうけるための開
口部以外の針状突起42は、厚膜レジスト膜に覆われる
ことになるため、突起電極を形成する開口部以外にメッ
キはされることが無い。
At this time, the needle-like protrusions 42 other than the openings for forming the protrusion electrodes 4 are covered with the thick resist film, so that plating may be performed on the portions other than the openings for forming the protrusion electrodes. There is no.

【0060】つぎに、図4に示すように、共通電極膜1
4をメッキ電極として用い、金メッキ処理により、スト
レートウオール形状で10μm〜15μmの厚さの突起
電極4を感光性樹脂の開口内の共通電極膜14上に形成
する。
Next, as shown in FIG.
4 is used as a plating electrode, and a protruding electrode 4 having a thickness of 10 μm to 15 μm in a straight wall shape is formed on the common electrode film 14 in the opening of the photosensitive resin by gold plating.

【0061】このとき、共通電極膜14上に形成された
針状突起42を核としながらメッキが等方的に成長する
ため、突起電極の最上面はフラットではなく、針状突起
を核としたこぶ状の微小突起18が多数形成される。
At this time, the plating grows isotropically with the needle-like projections 42 formed on the common electrode film 14 as nuclei, so that the uppermost surface of the projection electrodes is not flat but the needle-like projections are nuclei. Many bump-like minute projections 18 are formed.

【0062】その後、図5に示すように、レジスト膜で
ある感光性樹脂を除去し、突起電極4をエッチングマス
クに用いて、共通電極膜を湿式エッチング法によりエッ
チングし、図6に示すように、突起電極に整合した領域
に下部電極を形成する。
Thereafter, as shown in FIG. 5, the photosensitive resin, which is a resist film, is removed, and the common electrode film is etched by wet etching using the bump electrodes 4 as an etching mask, as shown in FIG. Then, a lower electrode is formed in a region corresponding to the protruding electrode.

【0063】最後に、半導体基板2内の隣接する半導体
チップ8の境界部を切断(以下ダイシングと称す)する
ことにより、半導体基板2を単個の半導体チップ8に切
り分ける。
Lastly, the semiconductor substrate 2 is cut into single semiconductor chips 8 by cutting the boundary between adjacent semiconductor chips 8 in the semiconductor substrate 2 (hereinafter referred to as dicing).

【0064】なお、図6で説明した共通電極膜をエッチ
ング処理して下部電極を形成する際に湿式エッチングを
行なうのは、つぎの理由による。
The reason why wet etching is performed when forming the lower electrode by etching the common electrode film described with reference to FIG. 6 is as follows.

【0065】共通電極膜14は、半導体基板2側からア
ルミニウムを0.8μm、クロムを0.01μm、銅を
0.8μmの厚さで3層構造で、前述のように形成して
いるため、乾式エッチング法では、被エッチング層と他
層とのエッチング選択比を得るために使用するエッチン
グガスを使用しなければいけないので、その複合エッチ
ングガスの選択が複雑になってしまうためである。
The common electrode film 14 has a three-layer structure of 0.8 μm of aluminum, 0.01 μm of chromium, and 0.8 μm of copper from the semiconductor substrate 2 side, and is formed as described above. This is because in the dry etching method, an etching gas used to obtain an etching selectivity between a layer to be etched and another layer must be used, so that the selection of the composite etching gas becomes complicated.

【0066】また、乾式エッチング法では、エッチング
加工するために要する時間が非常に長くかかるため、工
業的に生産する上で不利であり、さらにそのエッチング
処理に使用する装置も高価なものになってしまうという
問題点もあるためである。
In addition, the dry etching method takes a very long time to perform the etching process, which is disadvantageous in industrial production, and the equipment used for the etching process is expensive. This is because there is also a problem that it is lost.

【0067】しかしながら、湿式エッチング法によれ
ば、エッチング選択比のとれるエッチング液を選択する
ことで、大がかりな設備を必要とせずに、簡便にエッチ
ング処理を行なうことができる。
However, according to the wet etching method, by selecting an etching solution having an etching selectivity, an etching process can be easily performed without requiring a large-scale facility.

【0068】〔半導体装置の実装構造の説明:図7から
図9〕つぎに本発明における半導体装置の実装構造の最
適な実施の形態について図面を用いて説明を行なう。
[Description of Mounting Structure of Semiconductor Device: FIGS. 7 to 9] Next, an embodiment of a mounting structure of a semiconductor device according to the present invention will be described with reference to the drawings.

【0069】上述した製造方法により形成した半導体チ
ップ8を、液晶表示パネルの回路基板であるガラス基板
24に接続する。実装構造として液晶表示パネルを例に
して図7から図9を参照して説明する。
The semiconductor chip 8 formed by the above-described manufacturing method is connected to a glass substrate 24 which is a circuit substrate of a liquid crystal display panel. A liquid crystal display panel will be described as an example of the mounting structure with reference to FIGS.

【0070】図7に示したように、ガラス基板24上に
半導体チップ8を実装するには、半導体素子の形成面側
を下向きにするフェースダウンし、半導体チップ8上に
形成された突起電極4とガラス基板24上に形成された
透明電極46を位置合わせする。
As shown in FIG. 7, in order to mount the semiconductor chip 8 on the glass substrate 24, the semiconductor chip 8 is face-down with the surface on which the semiconductor element is formed facing downward, and the projecting electrode 4 formed on the semiconductor chip 8 is turned down. And the transparent electrode 46 formed on the glass substrate 24 are aligned.

【0071】そして、図8に示したように、半導体チッ
プ8および半導体チップ8上に形成された突起電極4と
ガラス基板24およびガラス基板24上に形成された透
明電極46との間にエポキシ等の熱硬化性樹脂30を介
在させる。
As shown in FIG. 8, an epoxy or the like is provided between the semiconductor chip 8 and the protruding electrode 4 formed on the semiconductor chip 8 and the glass substrate 24 and the transparent electrode 46 formed on the glass substrate 24. The thermosetting resin 30 is interposed.

【0072】さらに、図9に示したように、半導体チッ
プ8をガラス基板24上にセットした状態で、半導体チ
ップ8をガラス基板24に加圧しながら加熱処理するこ
とにより、半導体チップ上の突起電極4とガラス基板2
4上の透明電極46とを機械的および電気的に接続させ
る。
Further, as shown in FIG. 9, in a state where the semiconductor chip 8 is set on the glass substrate 24, the semiconductor chip 8 is subjected to a heat treatment while being pressed against the glass substrate 24, so that the protruding electrodes on the semiconductor chip are formed. 4 and glass substrate 2
4 and the transparent electrode 46 are mechanically and electrically connected.

【0073】本発明の半導体装置の実装構造によれば接
続ピッチ40μm以下、突起電極上部の接続面積に関し
ても2000μm2以下の超微細接続も可能になる。
According to the mounting structure of the semiconductor device of the present invention, ultra-fine connection with a connection pitch of 40 μm or less and a connection area of 2000 μm 2 or less with respect to the connection area above the protruding electrodes is also possible.

【0074】[0074]

【発明の効果】以上説明したように、本発明による半導
体装置の実装構造およびその製造方法によれば、ガラス
基板上の透明電極パッド、および半導体チップ上の突起
電極とをフェースダウン接続する際、半導体チップに形
成する突起電極上に形成する微小突起で、多数の点接続
をさせるため、接続ピッチの微細化を達成し、しかも接
続抵抗の低抵抗化を図ることが可能となる。
As described above, according to the semiconductor device mounting structure and the method of manufacturing the same of the present invention, when the transparent electrode pad on the glass substrate and the protruding electrode on the semiconductor chip are face-down connected, A minute projection formed on a projection electrode formed on a semiconductor chip makes a large number of point connections, so that a finer connection pitch can be achieved and a lower connection resistance can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態における半導体チップと回路
基板を接続した状態を示す断面図である。
FIG. 1 is a cross-sectional view showing a state where a semiconductor chip and a circuit board according to an embodiment of the present invention are connected.

【図2】本発明の実施形態における半導体基板上に共通
電極膜と針状突起を形成した状態を示す断面図である。
FIG. 2 is a cross-sectional view showing a state in which a common electrode film and needle-like protrusions are formed on a semiconductor substrate according to the embodiment of the present invention.

【図3】本発明の実施形態における半導体基板上に厚膜
レジスト膜を形成した状態を示す断面図である。
FIG. 3 is a cross-sectional view showing a state in which a thick resist film is formed on a semiconductor substrate according to the embodiment of the present invention.

【図4】本発明の実施形態における半導体基板上に金
(Au)メッキを行ない突起電極を形成した状態を示す
断面図である。
FIG. 4 is a cross-sectional view showing a state in which gold (Au) plating is performed on a semiconductor substrate to form a protruding electrode in the embodiment of the present invention.

【図5】本発明の実施形態における半導体基板上のレジ
ストを除去した後の金(Au)の微小突起が形成された
ストレート形状の突起電極完成した状態を示す断面図で
ある。
FIG. 5 is a cross-sectional view showing a completed state of a straight protruding electrode on which fine protrusions of gold (Au) have been formed after removing a resist on a semiconductor substrate according to an embodiment of the present invention.

【図6】本発明の実施形態における半導体基板上の共通
電極膜を除去したのちにおける金(Au)の微小突起が
形成されたストレート形状の突起電極完成した状態を示
す断面図である。
FIG. 6 is a cross-sectional view showing a completed state of a straight protruding electrode on which fine protrusions of gold (Au) are formed after removing a common electrode film on a semiconductor substrate according to an embodiment of the present invention.

【図7】本発明の実施形態における半導体チップとガラ
ス基板位置合わせした状態を示す断面図である。
FIG. 7 is a cross-sectional view showing a state in which the semiconductor chip and the glass substrate are aligned in the embodiment of the present invention.

【図8】本発明の実施形態における半導体チップとガラ
ス基板位置合わせ後、ガラス基板上にエポキシ樹脂など
の熱硬化性樹脂を塗布した状態を示す断面図である。
FIG. 8 is a cross-sectional view showing a state in which a thermosetting resin such as an epoxy resin is applied on the glass substrate after the alignment of the semiconductor chip and the glass substrate in the embodiment of the present invention.

【図9】本発明の実施形態における半導体チップとガラ
ス基板熱圧着した状態を示す断面図である。
FIG. 9 is a cross-sectional view showing a state in which the semiconductor chip and the glass substrate are thermocompression-bonded in the embodiment of the present invention.

【図10】従来技術における液晶表示装置のCOGペー
スト実装で半導体チップを実装した状態を示す断面図で
ある。
FIG. 10 is a cross-sectional view showing a state where a semiconductor chip is mounted by COG paste mounting of a liquid crystal display device according to a conventional technique.

【図11】従来技術における半導体基板上に共通電極膜
を形成した状態を示す断面図である。
FIG. 11 is a cross-sectional view showing a state in which a common electrode film is formed on a semiconductor substrate in a conventional technique.

【図12】従来技術における半導体基板上にレジスト膜
を形成した状態を示す断面図である。
FIG. 12 is a cross-sectional view showing a state in which a resist film is formed on a semiconductor substrate in a conventional technique.

【図13】従来技術における半導体基板に電解メッキを
行ない、バンプを形成した状態を示す断面図である。
FIG. 13 is a cross-sectional view showing a state where bumps are formed by performing electroplating on a semiconductor substrate according to a conventional technique.

【図14】従来技術における半導体基板上のレジスト膜
を除去した状態を示す断面図である。
FIG. 14 is a cross-sectional view showing a state in which a resist film on a semiconductor substrate is removed in a conventional technique.

【図15】従来技術における半導体基板上の共通電極膜
を除去した状態を示す断面図である。
FIG. 15 is a cross-sectional view showing a state in which a common electrode film on a semiconductor substrate is removed in a conventional technique.

【図16】従来技術における半導体チップ上の突起電極
上に導電性接着剤を転写した状態を示す断面図である。
FIG. 16 is a cross-sectional view showing a state in which a conductive adhesive is transferred onto a protruding electrode on a semiconductor chip in a conventional technique.

【図17】従来技術における半導体チップとガラス基板
位置合わせした状態を示す断面図である。
FIG. 17 is a cross-sectional view showing a state in which a semiconductor chip and a glass substrate are aligned in a conventional technique.

【図18】従来技術における半導体チップとガラス基板
をボンディングした状態を示す断面図である。
FIG. 18 is a cross-sectional view showing a state in which a semiconductor chip and a glass substrate are bonded in a conventional technique.

【図19】従来技術における半導体チップとガラス基板
を封止した状態を示す断面図である。
FIG. 19 is a cross-sectional view showing a state in which a semiconductor chip and a glass substrate are sealed in a conventional technique.

【符号の説明】[Explanation of symbols]

2:半導体基板 4:突起電極
6:絶縁膜 8 :半導体チップ 10:回路基板 12:アルミ配線 14:共通電極膜 16:電極パッド 18:こぶ状の微小突
起 22:封止樹脂 24:ガラス基板 26:レジスト膜 28:液晶表示装置 30:エポキシ等の熱硬化性樹脂 32:
FPC基板 36:FPC用異方性導電膜 38:液晶
表示装置 42:針状突起 44:導電性接着剤 46:透明電極 48:液晶 54:シール材
2: Semiconductor substrate 4: Protruding electrode
6: Insulating film 8: Semiconductor chip 10: Circuit board 12: Aluminum wiring 14: Common electrode film 16: Electrode pad 18: Hump-shaped minute protrusion 22: Sealing resin 24: Glass substrate 26: Resist film 28: Liquid crystal display device 30: thermosetting resin such as epoxy 32:
FPC board 36: Anisotropic conductive film for FPC 38: Liquid crystal display device 42: Needle-like projection 44: Conductive adhesive 46: Transparent electrode 48: Liquid crystal 54: Seal material

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板に設ける入出力端子である電
極パッドと、 その半導体基板上に設け、電極パッドが露出するように
設ける絶縁膜と、 電極パッド上に設け、すくなくともアルミニウムを有す
る下部電極と、 その下部電極上に設ける突起電極とを備え、 下部電極表面には針状突起を有し、 その下部電極表面の針状突起に対応して突起電極の頂部
には凹凸を有することを特徴とする半導体装置。
1. An electrode pad which is an input / output terminal provided on a semiconductor substrate, an insulating film provided on the semiconductor substrate so as to expose the electrode pad, and a lower electrode provided on the electrode pad and containing at least aluminum. A projection electrode provided on the lower electrode, having a needle-like projection on the surface of the lower electrode, and having irregularities on the top of the projection electrode corresponding to the needle-like projection on the surface of the lower electrode. Semiconductor device.
【請求項2】 下部電極は、 半導体基板側からアルミニウムとクロムと銅との積層膜
である請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the lower electrode is a laminated film of aluminum, chromium, and copper from the semiconductor substrate side.
【請求項3】 突起電極の断面形状は、 マッシュルーム、またはストレートウオールである請求
項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the cross-sectional shape of the protruding electrode is mushroom or straight wall.
【請求項4】 パッド電極を形成した半導体基板上に絶
縁膜を形成し、その絶縁膜を選択的に開口してパッド電
極を露出させる工程と、 全面にすくなくともアルミニウムを有する共通電極膜を
形成する工程と、 高温と低温との温度サイクルを行ない、その共通電極膜
表面に針状突起を形成する工程と、 全面にメッキレジストを形成し、フォトリソグラフィー
処理によりパッド電極領域上に開口を形成する工程と、 メッキレジストの開口内に突起電極をメッキ処理によっ
て形成する工程と、 突起電極に整合する領域の突起電極膜を残すようにその
共通電極膜をエッチング処理して下部電極を形成する工
程と、 半導体基板をダイシングして半導体チップを形成する工
程とを有することを特徴とする半導体装置の製造方法。
4. A step of forming an insulating film on a semiconductor substrate on which a pad electrode is formed, selectively opening the insulating film to expose the pad electrode, and forming a common electrode film having at least aluminum on the entire surface. Forming a needle-like protrusion on the surface of the common electrode film by performing a temperature cycle of high and low temperatures; forming a plating resist on the entire surface; and forming an opening on the pad electrode region by photolithography. Forming a protruding electrode in the opening of the plating resist by plating; and etching the common electrode film so as to leave a protruding electrode film in a region matching the protruding electrode, thereby forming a lower electrode. Dicing the semiconductor substrate to form a semiconductor chip.
【請求項5】 半導体基板に設ける入出力端子である電
極パッドと、 その半導体基板上に設け、電極パッドが露出するように
設ける絶縁膜と、 電極パッド上に設け、すくなくともアルミニウムを有す
る下部電極と、 その下部電極上に設ける突起電極とを備え、 下部電極表面には針状突起を有し、その下部電極表面の
針状突起に対応して突起電極の頂部には凹凸を有する半
導体チップと、 配線パターンを有する回路基板と、 頂部に凹凸を有する突起電極と配線パターンとを接続
し、 半導体チップと回路基板のあいだに設ける封止樹脂を有
することを特徴とする半導体装置の実装構造。
5. An electrode pad which is an input / output terminal provided on a semiconductor substrate, an insulating film provided on the semiconductor substrate so as to expose the electrode pad, and a lower electrode provided on the electrode pad and containing at least aluminum. A protruding electrode provided on the lower electrode, a semiconductor chip having an acicular projection on the lower electrode surface, and having an irregularity on the top of the protruding electrode corresponding to the acicular projection on the lower electrode surface; A mounting structure for a semiconductor device, comprising: a circuit board having a wiring pattern; and a sealing resin provided between the semiconductor chip and the circuit board, for connecting a protruding electrode having irregularities on the top and the wiring pattern.
JP2000101816A 2000-04-04 2000-04-04 Semiconductor device and method of manufacture, and mounting structure of the semiconductor device Pending JP2001284387A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000101816A JP2001284387A (en) 2000-04-04 2000-04-04 Semiconductor device and method of manufacture, and mounting structure of the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000101816A JP2001284387A (en) 2000-04-04 2000-04-04 Semiconductor device and method of manufacture, and mounting structure of the semiconductor device

Publications (1)

Publication Number Publication Date
JP2001284387A true JP2001284387A (en) 2001-10-12

Family

ID=18615795

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001284387A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005045268A (en) * 2003-07-23 2005-02-17 Samsung Electronics Co Ltd Method for forming re-wiring bump, semiconductor chip and mounting structure using its method
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
JP2012023528A (en) * 2010-07-14 2012-02-02 Daishinku Corp Piezoelectric vibrating piece and piezoelectric transducer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US7271084B2 (en) 2003-01-10 2007-09-18 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
JP2005045268A (en) * 2003-07-23 2005-02-17 Samsung Electronics Co Ltd Method for forming re-wiring bump, semiconductor chip and mounting structure using its method
JP2012023528A (en) * 2010-07-14 2012-02-02 Daishinku Corp Piezoelectric vibrating piece and piezoelectric transducer

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