JP2005229044A - Electronic component, manufacturing method thereof, and electronic equipment - Google Patents

Electronic component, manufacturing method thereof, and electronic equipment Download PDF

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Publication number
JP2005229044A
JP2005229044A JP2004038324A JP2004038324A JP2005229044A JP 2005229044 A JP2005229044 A JP 2005229044A JP 2004038324 A JP2004038324 A JP 2004038324A JP 2004038324 A JP2004038324 A JP 2004038324A JP 2005229044 A JP2005229044 A JP 2005229044A
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Prior art keywords
bump
conductive particles
mask
electronic component
manufacturing
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JP2004038324A
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Japanese (ja)
Inventor
Atsushi Saito
淳 斎藤
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2004038324A priority Critical patent/JP2005229044A/en
Publication of JP2005229044A publication Critical patent/JP2005229044A/en
Withdrawn legal-status Critical Current

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    • H01L2224/13438—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13455—Nickel [Ni] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of electronic components capable of ensuring the electrical connection between the electronic components and a mating board. <P>SOLUTION: The manufacturing method includes a process for forming a resist 20 on the active surface of the electronic components, a process for forming a fluororesin film 21 on the surface of the resist 20, a process for forming the opening of the resist 20 at the upper portion of an electrode pad 42; a process for forming a bump 44 inside the opening, a process for scattering conductive particles 50 onto the surface of a bump 44 (a), and a process for fixing the conductive particles 50 onto the surface of the bump 44 by a thermoplastic resin 52 (b). In the manufacturing method, the separation of the thermoplastic resin 52 accompanied with that of the resist 20 is prevented (c). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、電子部品の製造方法、電子部品および電子機器に関するものである。   The present invention relates to an electronic component manufacturing method, an electronic component, and an electronic apparatus.

半導体素子等の電子部品は、回路基板等に実装されて使用されている。この電子部品を回路基板に実装する方法について、さまざまな方法が提案されている。図１５に、従来技術に係る電子部品の実装方法の説明図を示す。図１５（ａ）では、異方導電性フィルム（ＡＣＦ）１９０を挟んで、ＩＣ等の電子部品１７０が相手側基板１２０に実装されている。異方導電性フィルム１９０は、熱硬化性樹脂１９２に導電性粒子１９５を分散させたものである。この導電性粒子１９５が、電子部品１７０の能動面に形成された電極パッド１７２と、相手側基板１２０の表面に形成された電極パッド１２２との間に入り込んで、両者が電気的に接続されている。また、加熱により硬化した熱硬化性樹脂１９２により、電子部品１７０と相手側基板１２０とが機械的に接続されている。   Electronic parts such as semiconductor elements are used by being mounted on a circuit board or the like. Various methods have been proposed for mounting electronic components on circuit boards. FIG. 15 is an explanatory diagram of a method for mounting an electronic component according to a conventional technique. In FIG. 15A, an electronic component 170 such as an IC is mounted on the counterpart substrate 120 with an anisotropic conductive film (ACF) 190 interposed therebetween. The anisotropic conductive film 190 is obtained by dispersing conductive particles 195 in a thermosetting resin 192. The conductive particles 195 enter between the electrode pad 172 formed on the active surface of the electronic component 170 and the electrode pad 122 formed on the surface of the counterpart substrate 120, and both are electrically connected. Yes. Further, the electronic component 170 and the counterpart substrate 120 are mechanically connected by a thermosetting resin 192 cured by heating.

近年では、電子部品の小型化にともなって、電極パッド相互の狭ピッチ化が進んでいる。ところが、異方導電性フィルムを使用した上記の実装方法では、水平方向に隣接する電極パッドの間にも導電性粒子が配置されるため、電極パッド相互の短絡が発生するおそれがある。また、電極パッドの狭ピッチ化にともなって電極パッド自体も小さくなるため、各電極パッドが捕捉する導電性粒子の個数が減少し、電気的接続の信頼性が低下する。さらに、高価な導電性粒子のすべてを電気的接続に利用することができないといった問題がある。   In recent years, with the miniaturization of electronic components, the pitch between electrode pads has been reduced. However, in the above mounting method using an anisotropic conductive film, the conductive particles are also disposed between the electrode pads adjacent in the horizontal direction, which may cause a short circuit between the electrode pads. Further, since the electrode pads themselves become smaller as the pitch of the electrode pads becomes narrower, the number of conductive particles captured by each electrode pad decreases, and the reliability of electrical connection decreases. Furthermore, there is a problem that not all of the expensive conductive particles can be used for electrical connection.

そこで、特許文献１ないし３には、あらかじめ電極パッドの表面に導電性粒子を固着させて相手側基板に実装することにより、隣接する電極パッドの間に導電性粒子を配置しない構造が開示されている。図１５（ｂ）に、特許文献３に開示された実装方法の説明図を示す。この実装方法では、導電粒子２９５を接着剤２９６で被覆して接着性導電粒子２９８を形成し、この接着性導電粒子２９８を電子部品２７０における電極パッド２７２の表面に接着する。その接着方法は、まず電子部品２７０の能動面における電極パッド２７２の形成部分以外の部分に、レジスト膜２８０を形成する。次に、接着性導電粒子２９８を平面上に分散し、分散された接着性導電粒子２９８に対して電子部品２７０を加熱加圧する。これにより、電子部品２７０の能動面全体に接着性導電粒子２９８が接着される。次に、電極パッド２７２以外のレジスト膜２８０の表面に接着された接着性導電粒子２９８を、レジスト膜２８０とともに除去する。以上により、電極パッド２７２の表面のみに接着性導電粒子２９８が接着された状態となる。そして、残された接着性導電粒子２９８を相手側基板２２０の電極パッド２２２に位置決めして、電子部品２７０を相手側基板２２０に加熱圧着する。これにより、接着性導電粒子２９８の接着剤２９６が溶解して電子部品２７０と相手側基板２２０とが機械的に接続され、また露出した導電粒子２９５により両者が電気的に接続される。
特開平７−６７９９号公報 特開平１０−８４１７８号公報 特開２００２−１７０８３７号公報 Thus, Patent Documents 1 to 3 disclose a structure in which conductive particles are not fixed between adjacent electrode pads by fixing conductive particles on the surface of the electrode pads in advance and mounting them on the counterpart substrate. Yes. FIG. 15B is an explanatory diagram of the mounting method disclosed in Patent Document 3. In this mounting method, the conductive particles 295 are covered with an adhesive 296 to form adhesive conductive particles 298, and the adhesive conductive particles 298 are bonded to the surface of the electrode pad 272 in the electronic component 270. In the bonding method, first, a resist film 280 is formed on a portion of the active surface of the electronic component 270 other than the portion where the electrode pad 272 is formed. Next, the adhesive conductive particles 298 are dispersed on a plane, and the electronic component 270 is heated and pressed against the dispersed adhesive conductive particles 298. As a result, the adhesive conductive particles 298 are bonded to the entire active surface of the electronic component 270. Next, the adhesive conductive particles 298 adhered to the surface of the resist film 280 other than the electrode pads 272 are removed together with the resist film 280. As described above, the adhesive conductive particles 298 are adhered to only the surface of the electrode pad 272. Then, the remaining adhesive conductive particles 298 are positioned on the electrode pads 222 of the counterpart substrate 220, and the electronic component 270 is thermocompression bonded to the counterpart substrate 220. As a result, the adhesive 296 of the adhesive conductive particles 298 is dissolved and the electronic component 270 and the counterpart substrate 220 are mechanically connected, and both are electrically connected by the exposed conductive particles 295.
JP 7-6799 A JP-A-10-84178 JP 2002-170837 A

しかしながら、特許文献３に記載された実装方法では、レジスト膜２８０を除去する際に、電極パッド２７２に接着された導電性微粒子２９８も同時に除去される場合がある。この場合、電子部品と相手側基板とを確実に電気的接続することができないという問題がある。また、レジスト膜２８０を除去する際に、レジスト膜２８０に接着された接着性導電粒子２９８を同時に除去するので、余った接着性導電粒子２９８を再利用することができないという問題がある。なお、導電粒子２９５は高価であり、これを接着剤２９６で被覆した接着性導電粒子２９８はさらに高価であることから、余った接着性導電粒子２９８を廃棄することにより多くの製造コストを浪費することになる。   However, in the mounting method described in Patent Document 3, when the resist film 280 is removed, the conductive fine particles 298 adhered to the electrode pads 272 may be removed at the same time. In this case, there is a problem that the electronic component and the counterpart substrate cannot be reliably electrically connected. Further, when the resist film 280 is removed, the adhesive conductive particles 298 adhered to the resist film 280 are removed at the same time, so that there is a problem that the remaining adhesive conductive particles 298 cannot be reused. The conductive particles 295 are expensive, and the adhesive conductive particles 298 covered with the adhesive 296 are more expensive. Therefore, a lot of manufacturing cost is wasted by discarding the remaining adhesive conductive particles 298. It will be.

さらに、特許文献３に記載された実装方法では、接着性導電粒子２９８を平面上に分散し、その表面に電子部品２７０を加熱加圧して接着性導電粒子２９８を接着させるが、接着性導電粒子２９８を平面上に均等に分散させるのは困難である。接着性導電粒子２９８が不均等に分散された場合には、電子部品２７０の電極パッド２７２の表面に接着性導電粒子２９８を配置することが困難になり、電子部品２７０と相手側基板２２０とを電気的に接続することができなくなるという問題がある。   Furthermore, in the mounting method described in Patent Document 3, the adhesive conductive particles 298 are dispersed on a flat surface, and the electronic component 270 is heated and pressed on the surface to adhere the adhesive conductive particles 298. It is difficult to distribute 298 evenly on a plane. If the adhesive conductive particles 298 are unevenly dispersed, it becomes difficult to dispose the adhesive conductive particles 298 on the surface of the electrode pad 272 of the electronic component 270, and the electronic component 270 and the counterpart substrate 220 are separated from each other. There is a problem that electrical connection becomes impossible.

本発明は、上記課題を解決するためになされたものであり、電子部品と相手側基板とを確実に電気的接続することが可能であり、また余った導電性粒子を再利用することが可能な、電子部品の製造方法の提供を目的とする。
また、電気的接続の信頼性に優れた電子部品および電子機器の提供を目的とする。 The present invention has been made to solve the above-mentioned problems, and can reliably connect an electronic component and a counterpart substrate, and can reuse surplus conductive particles. Another object is to provide a method for manufacturing an electronic component.
It is another object of the present invention to provide an electronic component and an electronic device with excellent electrical connection reliability.

上記目的を達成するため、本発明の電子部品の製造方法は、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記能動面上に配置され、表面が撥液性を示し、前記電極パッドの上方に開口部を有するマスクと、前記開口部の内側に配置され、前記マスクより高さの低いバンプと、を形成する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記マスクを除去する工程と、を有することを特徴とする。   In order to achieve the above object, an electronic component manufacturing method of the present invention is a method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, and is disposed on the active surface. Forming a mask having a liquid repellent surface and having an opening above the electrode pad, and a bump disposed inside the opening and having a height lower than that of the mask, and the bump The method includes a step of spraying conductive particles on the surface, a step of fixing the conductive particles to the surface of the bump with an adhesive, and a step of removing the mask.

なお、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記能動面にマスクを形成する工程と、前記マスクの表面を撥液処理する工程と、前記電極パッドの上方に前記マスクの開口部を形成する工程と、前記開口部の内側に、前記マスクより高さの低いバンプを形成する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記マスクを除去する工程と、を有する構成としてもよい。   A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, the step of forming a mask on the active surface, and the step of lyophobizing the surface of the mask A step of forming an opening of the mask above the electrode pad, a step of forming a bump having a height lower than the mask inside the opening, and spraying conductive particles on the surface of the bump A step of fixing the conductive particles to the surface of the bump with an adhesive, and a step of removing the mask.

また、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記能動面にマスクを形成する工程と、前記電極パッドの上方に前記マスクの開口部を形成する工程と、前記開口部の内側に、前記マスクより高さの低いバンプを形成する工程と、前記マスクの表面を撥液処理する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記マスクを除去する工程と、を有する構成としてもよい。   Also, a method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, the step of forming a mask on the active surface, and an opening of the mask above the electrode pad Forming a bump, forming a bump having a height lower than that of the mask inside the opening, applying a liquid repellent treatment to the surface of the mask, and spreading conductive particles on the surface of the bump. A step of fixing the conductive particles to the surface of the bump with an adhesive, and a step of removing the mask.

上記の各構成によれば、撥液処理されたマスクの表面には接着剤が付着せず、バンプの表面のみに接着剤が塗布される。これにより、マスクの除去にともなってバンプ表面から接着剤が剥離されることがなくなり、バンプ表面から導電性粒子が離脱するのを防止することが可能になる。したがって、電子部品と相手側基板とを確実に電気的接続することができる。   According to each of the above configurations, the adhesive does not adhere to the surface of the mask subjected to the liquid repellent treatment, and the adhesive is applied only to the surface of the bump. As a result, the adhesive is not peeled off from the bump surface as the mask is removed, and it is possible to prevent the conductive particles from detaching from the bump surface. Therefore, the electronic component and the counterpart substrate can be reliably electrically connected.

また、前記導電性粒子を接着剤により固着させる工程の前に、前記バンプの表面を親液処理する工程を有することが望ましい。
この構成によれば、バンプ表面に対して接着剤を強固に固着させることができる。これにより、マスクの除去にともなってバンプ表面から接着剤が剥離されることがなくなり、バンプ表面から導電性粒子が離脱するのを防止することが可能になる。したがって、電子部品と相手側基板とを確実に電気的接続することができる。 Further, it is desirable to have a step of lyophilic treatment of the surface of the bump before the step of fixing the conductive particles with an adhesive.
According to this configuration, the adhesive can be firmly fixed to the bump surface. As a result, the adhesive is not peeled off from the bump surface as the mask is removed, and it is possible to prevent the conductive particles from detaching from the bump surface. Therefore, the electronic component and the counterpart substrate can be reliably electrically connected.

また、本発明の他の電子部品の製造方法は、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記電極パッドの上方に開口部を有するマスクを、前記能動面に形成する工程と、前記開口部の内側に、前記マスクより高さが低いバンプを形成する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記マスクの表面に紫外線を照射して、前記接着剤を除去する工程と、前記マスクを除去する工程と、を有することを特徴とする。
この構成によれば、マスク表面の接着剤を除去することができるので、マスクの除去にともなってバンプ表面から接着剤が剥離されるのを防止することが可能になる。したがって、電子部品と相手側基板とを確実に電気的接続することができる。 Further, another electronic component manufacturing method of the present invention is a method for manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, wherein an opening is provided above the electrode pad. Forming a mask having the active surface on the active surface; forming a bump having a height lower than the mask inside the opening; spraying conductive particles on the surface of the bump; A step of fixing the adhesive particles to the surface of the bump with an adhesive, a step of irradiating the surface of the mask with ultraviolet rays to remove the adhesive, and a step of removing the mask. To do.
According to this configuration, since the adhesive on the mask surface can be removed, it is possible to prevent the adhesive from being peeled off from the bump surface as the mask is removed. Therefore, the electronic component and the counterpart substrate can be reliably electrically connected.

また、本発明の他の電子部品の製造方法は、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記電極パッドの上方に開口部を有するマスクを、前記能動面に形成する工程と、前記開口部の内側に、前記マスクより高さが５μｍ以上低いバンプを形成する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記マスクを除去する工程と、を有することを特徴とする。
この構成によれば、マスクとバンプとの高さが大きく異なるので、ステップカバレッジが困難になり、バンプ表面の接着剤およびマスク表面の接着剤が相互に分断された状態で配置される。これにより、マスクの除去にともなってバンプ表面から接着剤が剥離されるのを防止することが可能になる。したがって、電子部品と相手側基板とを確実に電気的接続することができる。 Further, another electronic component manufacturing method of the present invention is a method for manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, wherein an opening is provided above the electrode pad. Forming a mask on the active surface, forming a bump having a height of 5 μm or more lower than the mask inside the opening, and spraying conductive particles on the surface of the bump; The method includes a step of fixing the conductive particles to the surface of the bump with an adhesive and a step of removing the mask.
According to this configuration, since the heights of the mask and the bump are greatly different, step coverage becomes difficult and the bump surface adhesive and the mask surface adhesive are arranged in a mutually separated state. As a result, it is possible to prevent the adhesive from being peeled off from the bump surface as the mask is removed. Therefore, the electronic component and the counterpart substrate can be reliably electrically connected.

また、本発明の他の電子部品の製造方法は、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記能動面上に、前記電極パッドの表面から上方にかけて開口面積が小さくなる開口部を有するマスクを形成する工程と、前記開口部の内側に、前記マスクより高さが低いバンプを形成する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記マスクを除去する工程と、を有することを特徴とする。
この構成によれば、マスク開口部の側壁にアンダーカットが形成されるので、ステップカバレッジが不可能になり、バンプ表面の接着剤およびマスク表面の接着剤が相互に分断された状態で配置される。これにより、マスクの除去にともなってバンプ表面から接着剤が剥離されるのを防止することが可能になる。したがって、電子部品と相手側基板とを確実に電気的接続することができる。 In addition, another electronic component manufacturing method of the present invention is a method for manufacturing an electronic component mounted on a mating substrate via an electrode pad formed on an active surface, and the electrode pad is formed on the active surface. Forming a mask having an opening with a smaller opening area from the surface of the substrate, forming a bump having a height lower than the mask inside the opening, and conductive particles on the surface of the bump A step of spraying the conductive particles, a step of fixing the conductive particles to the surface of the bumps with an adhesive, and a step of removing the mask.
According to this configuration, since an undercut is formed on the side wall of the mask opening, step coverage becomes impossible, and the adhesive on the bump surface and the adhesive on the mask surface are arranged in a mutually separated state. . As a result, it is possible to prevent the adhesive from being peeled off from the bump surface as the mask is removed. Therefore, the electronic component and the counterpart substrate can be reliably electrically connected.

また、本発明の他の電子部品の製造方法は、能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、前記電極パッドの上方に開口部を有するマスクを、前記能動面に形成する工程と、前記開口部の内側に、前記マスクより高さが低いバンプを形成する工程と、前記バンプの表面に導電性粒子を散布する工程と、前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、前記接着剤を冷却して、前記マスクの表面に配置された接着剤を、前記バンプの表面に配置された前記接着剤から分離する工程と、前記マスクを除去する工程と、を有することを特徴とする。
この構成によれば、マスクおよびバンプの高さが異なっているので、バンプ表面の接着剤とマスク表面の接着剤との連結部分では、接着剤の厚さが薄くなっている。そのため、接着剤が冷却によって収縮すると、前記連結部分に応力集中が発生して、バンプ表面の接着剤とレジスト表面の接着剤とが分断される。これにより、マスクの除去にともなってバンプ表面から接着剤が剥離されるのを防止することが可能になる。したがって、電子部品と相手側基板とを確実に電気的接続することができる。 Further, another electronic component manufacturing method of the present invention is a method for manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, wherein an opening is provided above the electrode pad. Forming a mask on the active surface, forming a bump having a height lower than the mask inside the opening, spraying conductive particles on the surface of the bump, and conducting the conductive material Fixing the adhesive particles to the surface of the bump with an adhesive, and cooling the adhesive to separate the adhesive disposed on the surface of the mask from the adhesive disposed on the surface of the bump. And a step of removing the mask.
According to this configuration, since the heights of the mask and the bump are different, the thickness of the adhesive is thin at the connecting portion between the adhesive on the bump surface and the adhesive on the mask surface. Therefore, when the adhesive shrinks due to cooling, stress concentration occurs in the connecting portion, and the adhesive on the bump surface and the adhesive on the resist surface are divided. As a result, it is possible to prevent the adhesive from being peeled off from the bump surface as the mask is removed. Therefore, the electronic component and the counterpart substrate can be reliably electrically connected.

また、前記導電性粒子を固着させる工程の前に、前記マスクの表面に残存する前記導電性粒子を除去することが望ましい。
この構成によれば、余った導電性粒子を再利用することができる。 Further, it is desirable to remove the conductive particles remaining on the surface of the mask before the step of fixing the conductive particles.
According to this configuration, surplus conductive particles can be reused.

また、前記導電性粒子を散布する工程の前および／または後に、前記バンプの表面に熱可塑性樹脂からなる前記接着剤を塗布する工程を有し、前記導電性粒子を固着させる工程では、前記接着剤を可塑化させた後に、前記接着剤を硬化させることにより、前記バンプの表面に前記導電性粒子を固着させることが望ましい。
この構成によれば、導電性粒子がバンプの表面に確実に固着されるので、電子部品と相手側基板とを確実に電気的接続することができる。なお、前記熱可塑性樹脂は、ポリアミドであることが望ましい。 Further, before and / or after the step of spraying the conductive particles, the step of applying the adhesive made of a thermoplastic resin to the surface of the bump, and in the step of fixing the conductive particles, It is desirable to fix the conductive particles to the surface of the bump by curing the adhesive after plasticizing the agent.
According to this configuration, since the conductive particles are reliably fixed to the surface of the bump, the electronic component and the counterpart substrate can be reliably electrically connected. The thermoplastic resin is preferably a polyamide.

また、本発明の電子部品は、上述した電子部品の製造方法を使用して製造したことを特徴とする。
この構成によれば、相手側基板との電気的接続を確実に行うことが可能な電子部品を提供することができる。 The electronic component of the present invention is manufactured using the above-described electronic component manufacturing method.
According to this configuration, it is possible to provide an electronic component capable of reliably performing electrical connection with the counterpart substrate.

また、本発明の電子機器は、上述した電子部品を備えたことを特徴とする。
この構成によれば、電気的接続の信頼性に優れた電子機器を提供することができる。 In addition, an electronic apparatus according to the present invention includes the above-described electronic component.
According to this configuration, it is possible to provide an electronic device having excellent electrical connection reliability.

［第１実施形態］
以下、本発明の実施形態につき、図面を参照して説明する。なお、以下の説明に用いる各図面では、各部材を認識可能な大きさとするため、各部材の縮尺を適宜変更している。
最初に、本発明の第１実施形態につき、図１ないし図５を用いて説明する。 [First Embodiment]
Embodiments of the present invention will be described below with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.
First, a first embodiment of the present invention will be described with reference to FIGS.

［電子部品の実装構造］
図１は、ＩＣ等の半導体素子（電子部品）４０の実装状態の説明図であって、図１１のＢ−Ｂ線における正面断面図である。図１に示すように、半導体素子４０の能動面には、Ａｌ等の導電材料からなる複数の電極パッド４２が、所定ピッチで形成されている。なお、電極パッド４２の周縁部は絶縁膜４８で覆われている。また、各電極パッド４２の表面には、ＡｕメッキやＡｕ／Ｎｉメッキ等によるバンプ４４が形成されている。一例をあげれば、各バンプ４４は３０μｍ程度の幅に形成され、隣接するバンプ４４は１０μｍ程度の間隔で配置されて、各バンプのピッチは４０μｍ程度となっている。 [Electronic component mounting structure]
FIG. 1 is an explanatory diagram of a mounted state of a semiconductor element (electronic component) 40 such as an IC, and is a front sectional view taken along line BB of FIG. As shown in FIG. 1, a plurality of electrode pads 42 made of a conductive material such as Al are formed on the active surface of the semiconductor element 40 at a predetermined pitch. The peripheral portion of the electrode pad 42 is covered with an insulating film 48. Further, bumps 44 made of Au plating, Au / Ni plating, or the like are formed on the surface of each electrode pad 42. As an example, each bump 44 is formed with a width of about 30 μm, adjacent bumps 44 are arranged at intervals of about 10 μm, and the pitch of each bump is about 40 μm.

さらに、各バンプ４４の表面には、複数の導電性粒子５０が配置されている。導電性粒子５０は、樹脂ボール等の表面に、ハンダコートや金属メッキ等を施したものである。この金属メッキには、電解Ａｕメッキや無電解Ｎｉメッキ等を採用することができる。また、下地に無電解Ｎｉメッキを施し、上地に無電解Ａｕメッキを施してもよい。この導電性粒子５０は、たとえば直径４．５μｍ程度に形成されている。そして、この導電性粒子５０は、ポリアミド等の熱可塑性樹脂５２を固着手段として、バンプ４４の表面に固着されている。このポリアミドは、１５０〜２００℃程度の低温で可塑化するので、加工性に優れるとともに、電子部品に対する熱影響を抑制することができる。   Furthermore, a plurality of conductive particles 50 are arranged on the surface of each bump 44. The conductive particles 50 are obtained by performing solder coating, metal plating, or the like on the surface of a resin ball or the like. For this metal plating, electrolytic Au plating, electroless Ni plating, or the like can be employed. Further, electroless Ni plating may be applied to the base, and electroless Au plating may be applied to the top. The conductive particles 50 are formed with a diameter of about 4.5 μm, for example. The conductive particles 50 are fixed to the surface of the bump 44 using a thermoplastic resin 52 such as polyamide as a fixing means. Since this polyamide is plasticized at a low temperature of about 150 to 200 ° C., it is excellent in workability and can suppress the thermal influence on the electronic component.

なお、導電性粒子５０の固着手段として、エポキシ等の熱硬化性樹脂を採用することも可能である。特にエポキシは、１５０〜２００℃程度の低温で硬化するので、加工性に優れるとともに、電子部品に対する熱影響を抑制することができる。また、導電性粒子５０の固着手段として、アクリル等の光硬化性樹脂を採用することも可能である。この場合、紫外線等の光を照射することによって簡単に硬化性樹脂を硬化させることができる。また、導電性粒子５０の固着手段として、インジウム（Ｉｎ）や錫（Ｓｎ）、亜鉛（Ｚｎ）等の低融点金属、またはハンダを含むこれらの合金を採用することも可能である。この場合、低温で金属を溶融させることができるので、電子部品に対する熱影響を抑制することができる。特に、錫（Ｓｎ）は、濡れ性がよく、また２３０℃程度の低温で溶融することから、前記金属として好適である。   It is possible to employ a thermosetting resin such as epoxy as a fixing means for the conductive particles 50. In particular, since epoxy cures at a low temperature of about 150 to 200 ° C., it is excellent in workability and can suppress the thermal influence on the electronic component. Moreover, it is also possible to employ a photocurable resin such as acrylic as a fixing means for the conductive particles 50. In this case, the curable resin can be easily cured by irradiating light such as ultraviolet rays. Further, as a means for fixing the conductive particles 50, it is also possible to employ a low melting point metal such as indium (In), tin (Sn), or zinc (Zn), or an alloy containing solder. In this case, since the metal can be melted at a low temperature, the thermal influence on the electronic component can be suppressed. In particular, tin (Sn) is suitable as the metal because it has good wettability and melts at a low temperature of about 230 ° C.

一方、相手側基板１０の表面には、半導体素子４０の電極パッド４２と対向するように、電極パッド１２が形成されている。この電極パッド１２は、図１１に示すガラス基板８０（相手側基板１０）のデータ線８１等の端部に形成されている。そして、図１に示すように、半導体素子４０に固着された導電性粒子５０の先端が、相手側基板１０の電極パッド１２の表面に接触して、相手側基板１０の信号電極と半導体素子４０とが電気的に接続されている。また、半導体素子４０と相手側基板１０との間には、エポキシ樹脂等からなる熱硬化性樹脂層６０が配置され、半導体素子４０と相手側基板１０とが機械的に接続されている。なお、熱硬化性樹脂層６０により、半導体素子４０の能動面ならびに半導体素子４０および相手側基板１０の電気的接続部が保護されている。   On the other hand, the electrode pad 12 is formed on the surface of the counterpart substrate 10 so as to face the electrode pad 42 of the semiconductor element 40. The electrode pad 12 is formed at the end of the data line 81 and the like of the glass substrate 80 (mating substrate 10) shown in FIG. Then, as shown in FIG. 1, the tips of the conductive particles 50 fixed to the semiconductor element 40 come into contact with the surface of the electrode pad 12 of the counterpart substrate 10, and the signal electrode of the counterpart substrate 10 and the semiconductor element 40. And are electrically connected. Further, a thermosetting resin layer 60 made of an epoxy resin or the like is disposed between the semiconductor element 40 and the counterpart substrate 10, and the semiconductor element 40 and the counterpart substrate 10 are mechanically connected. Note that the thermosetting resin layer 60 protects the active surface of the semiconductor element 40 and the electrical connection portions of the semiconductor element 40 and the counterpart substrate 10.

［電子部品の製造方法］
次に、第１実施形態に係る電子部品の製造方法につき、図２および図３を用いて説明する。図２および図３は、半導体素子の製造方法の説明図であり、半導体素子の能動面を上にして記載したものである。第１実施形態に係る電子部品の製造方法は、図２に示すように、（ａ）能動面にレジスト２０を形成する工程と、（ｂ）レジスト２０の表面を撥液処理する工程と、（ｃ）電極パッド４２の上方にレジスト２０の開口部２２を形成する工程と、（ｄ）開口部２２の内側にレジスト２０より高さの低いバンプ４４を形成する工程とを有するものである。また図３に示すように、（ａ）バンプ４４の表面に導電性粒子５０を散布する工程と、（ｂ）導電性粒子５０を熱可塑性樹脂５２によりバンプ４４の表面に固着させる工程と、（ｃ）レジスト２０を除去する工程とを有するものである。なお本実施形態では、ウエハに形成された複数の半導体素子に対して同時に以下の処理を行い、最後にウエハから半導体素子を分離する。これにより、製造コストを低減することができる。 [Method of manufacturing electronic parts]
Next, a method for manufacturing an electronic component according to the first embodiment will be described with reference to FIGS. 2 and 3 are explanatory views of a method for manufacturing a semiconductor element, which are described with the active surface of the semiconductor element facing up. As shown in FIG. 2, the manufacturing method of the electronic component according to the first embodiment includes (a) a step of forming a resist 20 on an active surface, (b) a step of performing a liquid repellent treatment on the surface of the resist 20; c) a step of forming the opening portion 22 of the resist 20 above the electrode pad 42; and (d) a step of forming a bump 44 having a height lower than that of the resist 20 inside the opening portion 22. As shown in FIG. 3, (a) a step of dispersing the conductive particles 50 on the surface of the bumps 44, (b) a step of fixing the conductive particles 50 to the surfaces of the bumps 44 with a thermoplastic resin 52, c) a step of removing the resist 20. In the present embodiment, the following processing is simultaneously performed on a plurality of semiconductor elements formed on the wafer, and finally the semiconductor elements are separated from the wafer. Thereby, manufacturing cost can be reduced.

まず、図２（ａ）に示すように、バンプを形成するためのマスク２０を形成する。このマスク２０は、レジスト等を塗布して形成する。レジスト２０は、フォトレジストや電子線レジスト、Ｘ線レジスト等のいずれであってもよく、ポジ型またはネガ型のいずれであってもよいが、後述するメッキ液に対する耐性を有するものを使用する。このようなレジスト２０として、たとえばノボラック樹脂を使用することができる。なお、バンプはウエハ４１の能動面の電極パッド４２上に形成するので、レジスト２０は半導体素子の能動面全体に塗布する。レジスト２０の塗布は、スピンコート法やディッピング法、スプレーコート法などによって行う。ここで、レジスト２０の厚さは、形成すべきバンプの高さ以上に設定する。なお、レジスト２０を塗布した後にプリベークを行う。   First, as shown in FIG. 2A, a mask 20 for forming bumps is formed. The mask 20 is formed by applying a resist or the like. The resist 20 may be any of a photoresist, an electron beam resist, an X-ray resist, etc., and may be either a positive type or a negative type, but a resist having resistance to a plating solution described later is used. As such a resist 20, for example, a novolac resin can be used. Since the bump is formed on the electrode pad 42 on the active surface of the wafer 41, the resist 20 is applied to the entire active surface of the semiconductor element. The resist 20 is applied by spin coating, dipping, spray coating, or the like. Here, the thickness of the resist 20 is set to be equal to or higher than the height of the bump to be formed. Note that pre-baking is performed after the resist 20 is applied.

次に、図２（ｂ）に示すように、レジスト２０の表面を撥液処理する。撥液処理は、あらゆる有機溶剤に対して撥液性を示すフッ素樹脂膜２１を、レジスト２０の表面に形成することによって行う。フッ素樹脂膜２１の形成は、レジスト２０の表面にフッ素樹脂溶液を塗布することによって行う。フッ素樹脂溶液として、テトラフルオロエチレン等のフッ素樹脂を、デカフルオロペンタン等のフッ素系溶媒に溶解させたものを使用することが可能である。またフッ素樹脂溶液の塗布には、スピンコート法やスプレーコート法などを採用することが可能である。次に、塗布したフッ素樹脂溶液を１０分程度自然乾燥させた後に加熱処理する。加熱処理の条件は、例えば２００℃×３０分または２５０℃×１５分程度とする。これにより、レジスト２０の表面に厚さ１μｍ程度のフッ素樹脂膜２１が形成される。   Next, as shown in FIG. 2B, the surface of the resist 20 is subjected to a liquid repellent treatment. The liquid repellent treatment is performed by forming on the surface of the resist 20 a fluororesin film 21 that exhibits liquid repellency to any organic solvent. The fluororesin film 21 is formed by applying a fluororesin solution to the surface of the resist 20. As the fluororesin solution, it is possible to use a fluororesin such as tetrafluoroethylene dissolved in a fluorine-based solvent such as decafluoropentane. In addition, a spin coating method, a spray coating method, or the like can be employed for applying the fluororesin solution. Next, the applied fluororesin solution is naturally dried for about 10 minutes and then heat-treated. The conditions for the heat treatment are, for example, about 200 ° C. × 30 minutes or 250 ° C. × 15 minutes. As a result, a fluororesin film 21 having a thickness of about 1 μm is formed on the surface of the resist 20.

次に、図２（ｃ）に示すように、形成すべきバンプの平面形状を、レジスト２０にパターニングする。具体的には、レジスト２０における電極パッド４２の上方に、バンプの平面形状に対応した開口部２２を形成する。なお、バンプの平面形状は矩形に限られず、円形等であってもよい。レジスト２０のパターニングは、まず所定のパターンが形成されたフォトマスクを用いてレジスト２０を露光し、さらに露光されたレジスト２０を現像することによって行う。なお、レジスト２０の表面に形成されたフッ素樹脂膜２１も、レジスト２０と同時にパターニングされる。また、レジスト２０のパターニング後にポストベークを行う。   Next, as shown in FIG. 2C, the planar shape of the bump to be formed is patterned on the resist 20. Specifically, the opening 22 corresponding to the planar shape of the bump is formed above the electrode pad 42 in the resist 20. The planar shape of the bump is not limited to a rectangle, and may be a circle or the like. The patterning of the resist 20 is performed by first exposing the resist 20 using a photomask on which a predetermined pattern is formed, and further developing the exposed resist 20. Note that the fluororesin film 21 formed on the surface of the resist 20 is also patterned simultaneously with the resist 20. Further, post-baking is performed after the patterning of the resist 20.

次に、図２（ｄ）に示すように、レジスト２０をマスクとして、その開口部２２に導電材料を充填することにより、バンプ４４を形成する。バンプ４４は、ＡｕメッキやＮｉメッキ等によって形成する。また、バンプ４４の下地をＮｉメッキで形成し、上地をＡｕメッキで形成してもよい。なお、メッキ法として、例えば電気化学プレーティング（ＥＣＰ）法等を用いることができる。また、メッキ法における電極として、電極パッド４２を用いることができる。なお、メッキ法以外のＣＶＤ法やスパッタ法等を採用して導電材料を充填し、バンプ４４を形成してもよい。ここで、バンプ４４の高さは、レジスト２０の厚さから導電性粒子の直径を減算した高さ以下に形成するのが好ましい。   Next, as shown in FIG. 2D, the bumps 44 are formed by filling the openings 22 with a conductive material using the resist 20 as a mask. The bumps 44 are formed by Au plating, Ni plating, or the like. Further, the base of the bump 44 may be formed by Ni plating, and the top may be formed by Au plating. As a plating method, for example, an electrochemical plating (ECP) method or the like can be used. Moreover, the electrode pad 42 can be used as an electrode in a plating method. Note that the bump 44 may be formed by filling the conductive material using a CVD method or a sputtering method other than the plating method. Here, the height of the bump 44 is preferably formed to be equal to or lower than the height obtained by subtracting the diameter of the conductive particles from the thickness of the resist 20.

次に、図３（ａ）に示すように、ウエハ４１の能動面上に導電性粒子５０を散布する。散布された導電性粒子５０は、バンプ４４の上方およびレジスト２０の上方に均等に分散して配置される。ここで、レジスト２０の高さはバンプ４４より高いので、バンプ４４の上方にはレジスト２０の開口部２６が形成されている。そのため、散布された導電性粒子５０の多くは開口部２６に捕捉される。これにより、バンプ４４の表面に確実に導電性粒子５０を配置することができる。   Next, as shown in FIG. 3A, conductive particles 50 are dispersed on the active surface of the wafer 41. The dispersed conductive particles 50 are uniformly distributed above the bumps 44 and the resist 20. Here, since the height of the resist 20 is higher than that of the bump 44, an opening 26 of the resist 20 is formed above the bump 44. Therefore, most of the dispersed conductive particles 50 are captured by the openings 26. Thereby, the conductive particles 50 can be reliably arranged on the surface of the bump 44.

ここで、ウエハ４１を振動させることにより、レジスト２０の上方に配置された導電性粒子５０を開口部２６に落下させて、より多くの導電性粒子をバンプ４４の上方に配置することが望ましい。具体的には、ウエハ４１を５０〜１０００Ｈｚの高周波数で振動させる。特に、２５０〜５００Ｈｚの高周波数で振動させた場合には導電性粒子５０が活発に動くので、より多くの導電性粒子をバンプ４４の上方に配置することができる。また、ウエハ４１の振動方向は、ウエハ４１の能動面と平行な方向（水平方向）であっても、能動面と垂直な方向（垂直方向）であってもよい。その振幅は、水平方向振動の場合には、隣接するバンプ４４のピッチ以下とするのが好ましく、たとえば４０μｍ程度とする。また、垂直方向振動の場合には、開口部２６の深さ以下とするのが好ましく、たとえば１０μｍ程度とする。これにより、開口部２６内に捕捉されていた導電性粒子５０が、開口部２６から飛び出すのを防止することができる。   Here, it is desirable that the conductive particles 50 disposed above the resist 20 are dropped into the openings 26 by vibrating the wafer 41 so that more conductive particles are disposed above the bumps 44. Specifically, the wafer 41 is vibrated at a high frequency of 50 to 1000 Hz. In particular, when vibrated at a high frequency of 250 to 500 Hz, the conductive particles 50 move actively, so that more conductive particles can be disposed above the bumps 44. Further, the vibration direction of the wafer 41 may be a direction parallel to the active surface of the wafer 41 (horizontal direction) or a direction perpendicular to the active surface (vertical direction). In the case of horizontal vibration, the amplitude is preferably equal to or less than the pitch of the adjacent bumps 44, for example, about 40 μm. In the case of vertical vibration, the depth is preferably equal to or less than the depth of the opening 26, for example, about 10 μm. Thereby, it is possible to prevent the conductive particles 50 captured in the opening 26 from jumping out of the opening 26.

さらに、レジスト２０の上方に残存している導電性粒子５０を除去する。導電性粒子５０の除去は、１．ウエハ４１の能動面に気体を吹き付けて、導電性粒子５０を飛ばす方法、２．ウエハ４１を振動させて、ウエハ４１の周縁部から導電性粒子５０を落下させる方法、３．ウエハ４１を傾斜させつつ振動させることによりことにより、ウエハ４１の周縁部から導電性粒子５０を落下させる方法、４．可撓性を有する平板状のスキージを用いて導電性粒子５０を掻き取ることにより、導電性粒子５０を強制的に排除する方法などがあり、いずれの方法を採用してもよい。これにより、レジスト２０の表面に残存する導電性粒子５０の多くを除去することができる。また、レジスト２０の表面に残存する導電性粒子５０を除去しつつ、一部の導電性粒子を開口部に落下させることができる。したがって、より多くの導電性粒子５０をバンプ４４の表面に配置することができる。
なお、前工程では導電性粒子５０を開口部２６に落下させるためにウエハ４１を振動させたが、その振幅を徐々に大きくして２．または３．の方法を実施してもよい。これにより、製造工程を簡略化することができる。 Further, the conductive particles 50 remaining above the resist 20 are removed. The removal of the conductive particles 50 is as follows. 1. a method for blowing conductive particles 50 by blowing gas on the active surface of the wafer 41; 2. a method of dropping the conductive particles 50 from the peripheral edge of the wafer 41 by vibrating the wafer 41; 3. a method of dropping the conductive particles 50 from the peripheral portion of the wafer 41 by vibrating the wafer 41 while tilting; There is a method of forcibly removing the conductive particles 50 by scraping the conductive particles 50 using a flat plate squeegee having flexibility, and any method may be adopted. Thereby, most of the conductive particles 50 remaining on the surface of the resist 20 can be removed. In addition, some of the conductive particles can be dropped into the opening while removing the conductive particles 50 remaining on the surface of the resist 20. Therefore, more conductive particles 50 can be disposed on the surface of the bump 44.
In the previous step, the wafer 41 was vibrated to drop the conductive particles 50 into the opening 26, but the amplitude was gradually increased. Or 3. You may implement the method of. Thereby, a manufacturing process can be simplified.

ここで、レジスト２０の厚さは、バンプ４４の高さに導電性粒子５０の直径を加算した厚さ以上に設定している。そのため、バンプ４４の上方の導電性粒子５０は、開口部２６内に安定して捕捉されている。したがって、上述したいずれの除去方法を採用した場合でも、レジスト２０の上方に配置された導電性粒子５０のみを除去することが可能であり、バンプ４４の上方に配置された導電性粒子５０が同時に除去されるおそれは少ない。以上により、レジスト２０の上方に残存する導電性粒子５０の多くを除去すれば、図３（ａ）に示す状態となる。   Here, the thickness of the resist 20 is set to be equal to or greater than the thickness obtained by adding the diameter of the conductive particles 50 to the height of the bumps 44. Therefore, the conductive particles 50 above the bumps 44 are stably captured in the openings 26. Therefore, even when any of the above-described removal methods is employed, it is possible to remove only the conductive particles 50 disposed above the resist 20, and the conductive particles 50 disposed above the bumps 44 are simultaneously removed. There is little risk of being removed. As described above, when most of the conductive particles 50 remaining above the resist 20 are removed, the state shown in FIG.

次に、図３（ｂ）に示すように、バンプ４４の表面に熱可塑性樹脂溶液を塗布して、熱可塑性樹脂膜５２を形成する。具体的には、ポリアミド等の熱可塑性樹脂をトルエンＩＰＡ等の溶剤に溶解して１０ｗｔ％程度の熱可塑性樹脂溶液を製造し、これをウエハ４１の能動面上に塗布する。熱可塑性樹脂溶液の塗布は、ディスペンス法やスプレーコート法、スピンコート法、ディッピング法などによって行うことが可能である。なお、塗布する厚さは導電性粒子５０の直径程度とするのが好ましい。
上述したように、レジスト２０の表面にはフッ素樹脂膜２１が形成されている。このフッ素樹脂膜２１は、熱可塑性樹脂溶液の溶媒であるトルエンＩＰＡをはじめ、あらゆる有機溶媒に対して撥液性を示すものである。そのため、熱可塑性樹脂溶液は、フッ素樹脂膜２１にはじかれて、レジスト２０の表面に付着しない。したがって、バンプ４４の表面のみに選択的に熱可塑性樹脂溶液を塗布することができる。 Next, as shown in FIG. 3B, a thermoplastic resin solution is applied to the surface of the bump 44 to form a thermoplastic resin film 52. Specifically, a thermoplastic resin such as polyamide is dissolved in a solvent such as toluene IPA to produce a thermoplastic resin solution of about 10 wt%, and this is applied onto the active surface of the wafer 41. The thermoplastic resin solution can be applied by a dispensing method, a spray coating method, a spin coating method, a dipping method, or the like. The thickness to be applied is preferably about the diameter of the conductive particles 50.
As described above, the fluororesin film 21 is formed on the surface of the resist 20. The fluororesin film 21 exhibits liquid repellency with respect to all organic solvents including toluene IPA which is a solvent for the thermoplastic resin solution. Therefore, the thermoplastic resin solution is repelled by the fluororesin film 21 and does not adhere to the surface of the resist 20. Therefore, the thermoplastic resin solution can be selectively applied only to the surface of the bump 44.

次に、塗布した熱可塑性樹脂溶液を乾燥させ、溶剤を蒸発させる。すると、溶剤に溶解されていた熱可塑性樹脂が凝結し、バンプ４４の表面のみに熱可塑性樹脂膜５２が形成される。これにより、バンプ４４の表面に導電性粒子５０が固着される。   Next, the applied thermoplastic resin solution is dried to evaporate the solvent. As a result, the thermoplastic resin dissolved in the solvent is condensed, and the thermoplastic resin film 52 is formed only on the surface of the bump 44. Thereby, the conductive particles 50 are fixed to the surface of the bump 44.

なお、上述した熱可塑性樹脂溶液の塗布方法では、バンプ４４の表面に加えてレジスト２０の表面にも熱可塑性樹脂溶液が塗布されるので、レジスト２０の表面にも熱可塑性樹脂膜５２が形成されることになる。この点、インクジェット装置等の液滴吐出装置によれば、バンプ４４の表面のみに一定量の熱可塑性樹脂溶液を吐出することができる。これにより、バンプ４４の表面に対する導電性粒子５０の固着状態を均一化することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。また、熱可塑性樹脂溶液の消費量を低減することが可能になり、製造コストを低減することができる。   In the above-described method for applying the thermoplastic resin solution, since the thermoplastic resin solution is applied to the surface of the resist 20 in addition to the surface of the bump 44, the thermoplastic resin film 52 is also formed on the surface of the resist 20. It will be. In this regard, according to a droplet discharge device such as an inkjet device, a certain amount of thermoplastic resin solution can be discharged only to the surface of the bump 44. As a result, it is possible to make the conductive particles 50 fixed to the surface of the bump 44 uniform, and the semiconductor element and the counterpart substrate can be reliably electrically connected. In addition, the consumption of the thermoplastic resin solution can be reduced, and the manufacturing cost can be reduced.

なお、導電性粒子５０の散布工程の前に熱可塑性樹脂溶液を塗布して、あらかじめバンプ４４の表面に熱可塑性樹脂膜５２を形成しておいてもよい。この場合、導電性粒子５０を散布した後に、熱可塑性樹脂膜５２を加熱処理して可塑化させることにより、バンプ４４の表面に導電性粒子５０を固着させることができる。   In addition, a thermoplastic resin solution may be applied before the step of spreading the conductive particles 50 to form the thermoplastic resin film 52 on the surface of the bump 44 in advance. In this case, the conductive particles 50 can be fixed to the surface of the bump 44 by spraying the conductive particles 50 and plasticizing the thermoplastic resin film 52 by heat treatment.

また、導電性粒子の散布工程の前に熱可塑性樹脂膜を形成するとともに、導電性粒子の散布工程の後に熱可塑性樹脂溶液を塗布して、バンプ４４の上方に熱可塑性樹脂膜５２を形成してもよい。この場合、後に塗布された熱可塑性樹脂溶液に含まれている溶剤が、先に形成された熱可塑性樹脂膜に浸透し、先に形成された熱可塑性樹脂膜が再溶解して、後に塗布された熱可塑性樹脂溶液と一体になる。すると、熱可塑性樹脂溶液が導電性粒子５０の表面に沿って濡れ上がり、導電性粒子５０が熱可塑性樹脂膜の内部に沈没してバンプ４４の表面に配置される。その後、まず５０℃程度で加熱して溶剤を蒸発させ、熱可塑性樹脂を凝結させる。これにより、熱可塑性樹脂膜５２が形成されて、導電性粒子５０がバンプ４４の表面に固着される。さらに、２００℃で１０分程度アニール（加熱）処理することにより、先に形成した熱可塑性樹脂膜の熱可塑性樹脂と、後に塗布した熱可塑性樹脂溶液の熱可塑性樹脂とを溶着させる。これにより、導電性粒子５０に対する固着力を向上させることができる。このように、２回に分けて熱可塑性樹脂を塗布することにより、導電性粒子５０をバンプ４４の表面に確実に固着させることができる。
なお、先に形成する熱可塑性樹脂膜の厚さは、導電性粒子５０の直径の半分程度とし、最終的に形成する熱可塑性樹脂膜５２の厚さは、導電性粒子５０の直径程度とすることが望ましい。また、上述した導電性粒子５０を固着させる工程は、バンプ４４の表面に向かって導電性粒子５０を加圧しつつ行うことが望ましい。これにより、導電性粒子５０がバンプ４４の表面に接触した状態で固着され、両者が確実に電気的接続される。 Further, a thermoplastic resin film is formed before the conductive particle spraying process, and a thermoplastic resin solution is applied after the conductive particle spraying process to form a thermoplastic resin film 52 above the bumps 44. May be. In this case, the solvent contained in the thermoplastic resin solution applied later penetrates into the previously formed thermoplastic resin film, and the previously formed thermoplastic resin film is redissolved and applied later. Integrated with the thermoplastic resin solution. Then, the thermoplastic resin solution wets along the surface of the conductive particles 50, and the conductive particles 50 sink to the inside of the thermoplastic resin film and are disposed on the surfaces of the bumps 44. Thereafter, the solvent is first evaporated by heating at about 50 ° C. to condense the thermoplastic resin. Thereby, the thermoplastic resin film 52 is formed, and the conductive particles 50 are fixed to the surface of the bump 44. Furthermore, an annealing (heating) treatment is performed at 200 ° C. for about 10 minutes, thereby welding the thermoplastic resin of the previously formed thermoplastic resin film and the thermoplastic resin of the thermoplastic resin solution applied later. Thereby, the adhering force with respect to the electroconductive particle 50 can be improved. Thus, the conductive particles 50 can be reliably fixed to the surface of the bump 44 by applying the thermoplastic resin in two steps.
The thickness of the thermoplastic resin film formed first is about half the diameter of the conductive particles 50, and the thickness of the thermoplastic resin film 52 finally formed is about the diameter of the conductive particles 50. It is desirable. Further, it is desirable that the step of fixing the conductive particles 50 described above is performed while pressurizing the conductive particles 50 toward the surface of the bump 44. As a result, the conductive particles 50 are fixed in contact with the surface of the bump 44, and the two are reliably electrically connected.

次に、図３（ｃ）に示すように、レジストを除去する。レジストの除去は、レジスト剥離液にウエハ４１を浸漬することによって行う。レジスト剥離液には、モノエタノールアミンとジメチルスルホキシドとを７：３の割合で混合した液体等を使用する。なお、レジストの上方に散布された導電性粒子を除去した後にレジストを剥離するので、除去した導電性粒子を再利用することができる。
次に、ダイシング等により、ウエハ４１から半導体素子を分離する。以上により、本実施形態の半導体素子が形成される。 Next, as shown in FIG. 3C, the resist is removed. The resist is removed by immersing the wafer 41 in a resist stripping solution. As the resist stripping solution, a liquid in which monoethanolamine and dimethyl sulfoxide are mixed at a ratio of 7: 3 is used. Note that since the resist is peeled after the conductive particles dispersed above the resist are removed, the removed conductive particles can be reused.
Next, the semiconductor element is separated from the wafer 41 by dicing or the like. Thus, the semiconductor element of this embodiment is formed.

以上に詳述したように、本実施形態の半導体素子の形成方法では、レジストの表面にフッ素樹脂膜を形成して撥液処理する構成とした。これにより、撥液処理されたレジストの表面には熱可塑性樹脂溶液が付着せず、バンプの表面のみに熱可塑性樹脂溶液が塗布される。したがって、バンプの表面のみに熱可塑性樹脂膜が形成され、レジストの上方には熱可塑性樹脂膜が形成されない。この場合、レジストの剥離にともなって、バンプ表面から熱可塑性樹脂膜が剥離されることがなくなる。したがって、導電性粒子がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   As described in detail above, in the method for forming a semiconductor element of this embodiment, a fluororesin film is formed on the resist surface and a liquid repellent treatment is performed. Thereby, the thermoplastic resin solution does not adhere to the surface of the resist subjected to the liquid repellent treatment, and the thermoplastic resin solution is applied only to the surface of the bump. Therefore, the thermoplastic resin film is formed only on the surface of the bump, and the thermoplastic resin film is not formed above the resist. In this case, the thermoplastic resin film is not peeled off from the bump surface as the resist is peeled off. Therefore, it is possible to prevent the conductive particles from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

これに加えて、本実施形態では、導電性粒子がレジストの表面に散布された場合でも、その導電性粒子を除去してから半導体素子を実装するので、除去された導電性粒子を再利用することができる。これにより、高価な導電性粒子を無駄に廃棄することなく、そのすべてを電気的接続に利用することができる。また、本実施形態では、レジストの厚さをバンプの高さより厚く形成するので、バンプの上方にレジストの開口部が形成される。この場合、散布された導電性粒子の多くが開口部に捕捉されるので、バンプの表面に確実に導電性粒子を配置することができる。したがって、半導体素子と相手側基板とを確実に電気的接続することができる。   In addition, in this embodiment, even when conductive particles are dispersed on the surface of the resist, the semiconductor particles are mounted after removing the conductive particles, so the removed conductive particles are reused. be able to. Thereby, all of the expensive conductive particles can be used for electrical connection without wastefully discarding them. In this embodiment, since the resist is formed thicker than the bump, a resist opening is formed above the bump. In this case, most of the dispersed conductive particles are captured by the openings, so that the conductive particles can be reliably arranged on the surface of the bump. Therefore, the semiconductor element and the counterpart substrate can be reliably electrically connected.

ここで、第１実施形態に係る半導体素子の製造方法の変形例につき、図４を用いて説明する。図４は、第１実施形態に係る半導体素子の製造方法の変形例の説明図である。なお、第１実施形態と同様の構成となる部分については、その詳細な説明を省略する。   Here, a modification of the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 4 is an explanatory diagram of a modified example of the method for manufacturing a semiconductor device according to the first embodiment. Note that detailed description of portions having the same configuration as in the first embodiment is omitted.

変形例では、図４（ａ）に示すように、まずウエハ４１の能動面全体にレジスト２０を塗布する。次に、図４（ｂ）に示すように、電極パッド４２の上方にレジスト２０の開口部２２を形成する。なお、これ以外にも、例えばドライフィルムを用いることにより、またスクリーン印刷等の印刷法を用いることにより、パターニングされた状態でレジスト２０を形成することができる。また、インクジェット装置等の液滴吐出装置を用いて、レジストの液滴をレジスト２０の形成位置のみに吐出することにより、パターニングされた状態でレジスト２０を形成してもよい。これらにより、フォトリソグラフィに使用するフォトマスクが不要となり、製造コストを削減することができる。次に、図４（ｃ）に示すように、開口部２２の内側に、レジスト２０より高さの低いバンプ４４を形成する。   In the modification, as shown in FIG. 4A, first, a resist 20 is applied to the entire active surface of the wafer 41. Next, as shown in FIG. 4B, an opening 22 of the resist 20 is formed above the electrode pad 42. In addition, the resist 20 can be formed in a patterned state by using, for example, a dry film or by using a printing method such as screen printing. Alternatively, the resist 20 may be formed in a patterned state by discharging a droplet of a resist only to a position where the resist 20 is formed using a droplet discharge device such as an inkjet device. As a result, a photomask used for photolithography becomes unnecessary, and manufacturing costs can be reduced. Next, as shown in FIG. 4C, a bump 44 having a height lower than that of the resist 20 is formed inside the opening 22.

次に、図４（ｄ）に示すように、レジスト２０の表面を撥液処理する。撥液処理の方法として、例えばテトラフルオロメタンを処理ガスとして大気雰囲気中でプラズマ処理するＣＦ4 プラズマ処理法を採用することが可能である。具体的なＣＦ4 プラズマ処理法の条件として、例えばプラズマパワーを１００〜８００ｋＷ、４フッ化メタンガス流量を５０〜１００ｍｌ／ｍｉｎ、プラズマ放電電極に対するウエハ搬送速度を０．５〜１０２０ｍｍ／ｓｅｃ、ウエハ温度を７０〜９０℃とすればよい。なお、処理ガスとしては、テトラフルオロメタン（四フッ化炭素）に限らず、他のフルオロカーボン系のガスを用いることもできる。このような撥液処理を行うことにより、レジスト２０を構成する樹脂中にフッ素基が導入される一方で、バンプ４４の表面にはフッ素基が導入されない。したがって、レジスト２０の表面のみに撥液性を付与することが可能になる。
なお、撥液性を有する材料（例えばフッ素基を有する樹脂材料）によってレジスト２０を構成することにより、上述した撥液処理を省略することも可能である。 Next, as shown in FIG. 4D, the surface of the resist 20 is subjected to a liquid repellent treatment. As a liquid repellent treatment method, for example, a CF 4 plasma treatment method in which plasma treatment is performed in an air atmosphere using tetrafluoromethane as a treatment gas can be employed. As specific CF 4 plasma processing conditions, for example, the plasma power is 100 to 800 kW, the tetrafluoromethane gas flow rate is 50 to 100 ml / min, the wafer transfer speed to the plasma discharge electrode is 0.5 to 1020 mm / sec, and the wafer temperature. May be set to 70 to 90 ° C. The processing gas is not limited to tetrafluoromethane (carbon tetrafluoride), and other fluorocarbon gases can also be used. By performing such a liquid repellent treatment, fluorine groups are introduced into the resin constituting the resist 20, while no fluorine groups are introduced onto the surface of the bump 44. Accordingly, it is possible to impart liquid repellency only to the surface of the resist 20.
Note that the liquid repellent treatment described above can be omitted by forming the resist 20 with a liquid repellent material (for example, a resin material having a fluorine group).

その後、図３に示す第１実施形態と同様に、バンプ４４の表面に導電性粒子５０を散布して、熱可塑性樹脂溶液を塗布する。ここで、レジスト２０の表面は撥液処理されているので、レジスト２０の上方には熱可塑性樹脂膜が形成されず、バンプ４４の表面のみに熱可塑性樹脂膜５２が形成されて導電性粒子５０が固着される。この場合、図３（ｃ）に示すようにレジストを剥離しても、バンプ４４の表面から熱可塑性樹脂膜５２が剥離されることはない。したがって、第１実施形態と同様に、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   Thereafter, similarly to the first embodiment shown in FIG. 3, the conductive particles 50 are dispersed on the surface of the bump 44 and a thermoplastic resin solution is applied. Here, since the surface of the resist 20 has been subjected to a liquid repellent treatment, the thermoplastic resin film is not formed above the resist 20, and the thermoplastic resin film 52 is formed only on the surface of the bump 44, thereby forming the conductive particles 50. Is fixed. In this case, even if the resist is peeled off as shown in FIG. 3C, the thermoplastic resin film 52 is not peeled off from the surface of the bump 44. Therefore, similarly to the first embodiment, it becomes possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

［電子部品の実装方法］
次に、本実施形態に係る半導体素子の実装方法につき、図５を用いて説明する。図５は、本実施形態に係る半導体素子の実装方法の説明図である。
図５（ａ）に示すように、まず相手側基板１０の表面に熱硬化性樹脂層６０を形成する。熱硬化性樹脂層６０の形成は、未硬化のエポキシ樹脂フィルムを貼り付けることによって行う。なお、未硬化のエポキシ樹脂ペーストを相手側基板１０の表面に塗布することによって熱硬化性樹脂層６０を形成してもよい。また、熱硬化性樹脂層６０は半導体素子４０の能動面上に形成してもよい。この場合には、ウエハの能動面に熱硬化性樹脂層６０を形成した後に、ウエハから半導体素子４０を分離する。また、半導体素子４０を相手側基板１０に実装した後に、半導体素子４０と相手側基板１０との隙間にアンダーフィルを充填して熱硬化性樹脂層６０を形成してもよい。なお、いずれの場合でも、異方導電性フィルム（ＡＣＦ）とは異なり、熱硬化性樹脂層６０には導電性粒子が含まれていないことに注意されたい。 [Electronic component mounting method]
Next, a semiconductor device mounting method according to the present embodiment will be described with reference to FIG. FIG. 5 is an explanatory diagram of the semiconductor element mounting method according to the present embodiment.
As shown in FIG. 5A, first, a thermosetting resin layer 60 is formed on the surface of the counterpart substrate 10. The thermosetting resin layer 60 is formed by attaching an uncured epoxy resin film. The thermosetting resin layer 60 may be formed by applying an uncured epoxy resin paste to the surface of the counterpart substrate 10. Further, the thermosetting resin layer 60 may be formed on the active surface of the semiconductor element 40. In this case, after forming the thermosetting resin layer 60 on the active surface of the wafer, the semiconductor element 40 is separated from the wafer. Alternatively, the thermosetting resin layer 60 may be formed by filling the gap between the semiconductor element 40 and the counterpart substrate 10 with an underfill after mounting the semiconductor element 40 on the counterpart substrate 10. Note that in any case, unlike the anisotropic conductive film (ACF), the thermosetting resin layer 60 does not contain conductive particles.

そして、上記のように形成した半導体素子４０を、上下反転して相手側基板１０の上方に配置する。その際、半導体素子４０に形成されたバンプ４４と、相手側基板１０に形成された電極パッド１２とが対向するように、半導体素子４０と相手側基板１０とを配置する。   Then, the semiconductor element 40 formed as described above is turned upside down and disposed above the counterpart substrate 10. At this time, the semiconductor element 40 and the counterpart substrate 10 are arranged so that the bumps 44 formed on the semiconductor element 40 and the electrode pads 12 formed on the counterpart substrate 10 face each other.

次に、図５（ｂ）に示すように、相手側基板１０の表面に半導体素子４０を押し付けて加圧する。これにより、半導体素子４０のバンプ４４上に固着された導電性粒子５０が、相手側基板１０の電極パッド１２に接触して、両者が電気的に接続される。そして、この状態で熱硬化性樹脂層６０を加熱する。加熱温度は、たとえば２００℃とする。なお、相手側基板１０への半導体素子４０の加圧と同時に熱硬化性樹脂層６０への加熱を行ってもよい。これにより、熱硬化性樹脂層６０が硬化して、半導体素子４０と相手側基板１０とが機械的に接続される。また、半導体素子４０および相手側基板１０の電気的接続部が保護される。   Next, as shown in FIG. 5B, the semiconductor element 40 is pressed against the surface of the counterpart substrate 10 and is pressurized. As a result, the conductive particles 50 fixed on the bumps 44 of the semiconductor element 40 come into contact with the electrode pads 12 of the counterpart substrate 10 and are electrically connected. In this state, the thermosetting resin layer 60 is heated. The heating temperature is, for example, 200 ° C. In addition, you may heat the thermosetting resin layer 60 simultaneously with the pressurization of the semiconductor element 40 to the other party board | substrate 10. FIG. Thereby, the thermosetting resin layer 60 is cured and the semiconductor element 40 and the counterpart substrate 10 are mechanically connected. In addition, the electrical connection between the semiconductor element 40 and the counterpart substrate 10 is protected.

なお、導電性粒子５０をバンプに固着している熱可塑性樹脂膜５２は、１５０℃程度で軟化する。加えて、半導体素子４０を相手側基板１０に加圧しているので、バンプ４４の表面に導電性粒子５０が積層されていた場合でも、導電性粒子５０を平坦化してバンプ４４の表面のみに配置することができる。また、バンプ４４の表面と導電性粒子５０との間に熱可塑性樹脂膜５２が介在していた場合でも、その熱可塑性樹脂膜５２が軟化するので、バンプ４４の表面と導電性粒子５０とを接触させることができる。さらに、導電性粒子５０と相手側基板１０の電極パッド１２との間に熱可塑性樹脂膜５２が介在していた場合でも、その熱可塑性樹脂膜５２が軟化するので、導電性粒子５０と電極パッド１２とを接触させることができる。したがって、半導体素子４０と相手側基板１０とを確実に電気的接続することができる。以上により、半導体素子４０が相手側基板１０に実装される。   Note that the thermoplastic resin film 52 in which the conductive particles 50 are fixed to the bumps is softened at about 150 ° C. In addition, since the semiconductor element 40 is pressed against the counterpart substrate 10, even when the conductive particles 50 are stacked on the surface of the bump 44, the conductive particles 50 are flattened and disposed only on the surface of the bump 44. can do. Further, even when the thermoplastic resin film 52 is interposed between the surface of the bump 44 and the conductive particles 50, the thermoplastic resin film 52 is softened, so that the surface of the bump 44 and the conductive particles 50 are bonded to each other. Can be contacted. Further, even when the thermoplastic resin film 52 is interposed between the conductive particles 50 and the electrode pad 12 of the counterpart substrate 10, the thermoplastic resin film 52 is softened. 12 can be brought into contact with each other. Therefore, the semiconductor element 40 and the counterpart substrate 10 can be reliably electrically connected. As described above, the semiconductor element 40 is mounted on the counterpart substrate 10.

近年では、電子部品の小型化にともなって、電極パッド相互の狭ピッチ化が進んでいる。その場合でも、上述した熱硬化性樹脂層６０には導電性粒子が含まれていないので、隣接する電極パッドが相互に短絡するおそれはない。また、バンプ４４の表面にあらかじめ導電性粒子を固着してから実装するので、電極パッド自体が小さくなっても、確実に電気的接続を行うことができる。   In recent years, with the miniaturization of electronic components, the pitch between electrode pads has been reduced. Even in that case, since the thermosetting resin layer 60 does not contain conductive particles, there is no possibility that adjacent electrode pads are short-circuited to each other. In addition, since the conductive particles are fixed on the surface of the bump 44 before mounting, the electrical connection can be reliably performed even if the electrode pad itself is reduced.

なお、半導体素子と相手側基板との間に異方導電性フィルム（ＡＣＦ）を配置した場合には、半導体素子のバンプと相手側基板の電極パッドとの間に配置される導電性粒子の個数は１０〜２０個程度である。そして、これ以上の導電性粒子を配置するには、ＡＣＦに含まれる導電性粒子の密度を増加させる必要があるが、隣接する電極パッドが相互に短絡する可能性が大きくなる。これに対して、本実施形態に係る電子部品の製造方法を使用して半導体素子を製造すれば、バンプの表面に多数の導電性粒子を配置することができる。一例をあげれば、バンプの表面積の８０％以上に導電性粒子を配置することも可能である。これにより、半導体素子のバンプと相手側基板の電極パッドとの間の電気抵抗が小さくなり、液晶モジュールの電力消費量を低減することができる。この場合でも、隣接する電極パッドが相互に短絡するおそれがないのは、上述した通りである。   When an anisotropic conductive film (ACF) is arranged between the semiconductor element and the counterpart substrate, the number of conductive particles arranged between the bump of the semiconductor element and the electrode pad of the counterpart substrate Is about 10-20. In order to dispose more conductive particles than this, it is necessary to increase the density of the conductive particles contained in the ACF, but there is a high possibility that adjacent electrode pads are short-circuited to each other. On the other hand, if a semiconductor element is manufactured using the method for manufacturing an electronic component according to this embodiment, a large number of conductive particles can be arranged on the surface of the bump. For example, it is possible to dispose conductive particles on 80% or more of the surface area of the bump. Thereby, the electrical resistance between the bump of the semiconductor element and the electrode pad of the counterpart substrate is reduced, and the power consumption of the liquid crystal module can be reduced. Even in this case, as described above, there is no possibility that adjacent electrode pads short-circuit each other.

［第２実施形態］
次に、本発明の第２実施形態に係る半導体素子の製造方法つき、図６を用いて説明する。図６は、第２実施形態に係る半導体素子の製造方法の説明図である。第２実施形態に係る半導体素子の製造方法は、熱可塑性樹脂溶液を塗布して導電性粒子をバンプ４４の表面に固着させる工程の前に、バンプ４４の表面を親液処理する工程を有するものである。なお、第１実施形態およびその変形例と同様の構成となる部分については、その詳細な説明を省略する。 [Second Embodiment]
Next, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is an explanatory diagram of a method for manufacturing a semiconductor device according to the second embodiment. The method for manufacturing a semiconductor device according to the second embodiment includes a step of lyophilicizing the surface of the bump 44 before the step of applying the thermoplastic resin solution and fixing the conductive particles to the surface of the bump 44. It is. In addition, the detailed description is abbreviate | omitted about the part which becomes the same structure as 1st Embodiment and its modification.

図６（ａ）は、図４（ｃ）と同様に、レジスト２０の開口部２２の内側にバンプ４４を形成した状態を示している。次に第２実施形態では、図６（ｂ）に示すように、ウエハ４１の能動面全体を親液処理する。具体的には、熱可塑性樹脂溶液の溶媒であるトルエンＩＰＡとの親和性が増加するように、バンプ４４の表面を処理する。
その具体的な方法として、酸素を処理ガスとして大気雰囲気中でプラズマ処理するＯ2 プラズマ処理法を採用することが可能である。このＯ2 プラズマ処理法は、ウエハ４１に対してプラズマ放電電極からプラズマ状態の酸素を照射するものである。Ｏ2 プラズマ処理法の具体的な条件として、例えばプラズマパワーを１００〜８００ｋＷ、酸素ガス流量を５０〜１００ｍｌ／ｍｉｎ、プラズマ放電電極に対するウエハ搬送速度を０．５〜１０ｍｍ／ｓｅｃ、ウエハ温度を７０〜９０℃とすればよい。このＯ２プラズマ処理により、バンプ４４の表面に付着している有機物が分解・除去されて、親液性が付与される。 FIG. 6A shows a state in which bumps 44 are formed inside the opening 22 of the resist 20 as in FIG. 4C. Next, in the second embodiment, as shown in FIG. 6B, the entire active surface of the wafer 41 is subjected to lyophilic processing. Specifically, the surface of the bump 44 is treated so as to increase the affinity with toluene IPA which is a solvent of the thermoplastic resin solution.
As a specific method thereof, it is possible to employ an O 2 plasma processing method in which plasma processing is performed in an air atmosphere using oxygen as a processing gas. In this O 2 plasma treatment method, the wafer 41 is irradiated with oxygen in a plasma state from a plasma discharge electrode. As specific conditions for the O 2 plasma processing method, for example, the plasma power is 100 to 800 kW, the oxygen gas flow rate is 50 to 100 ml / min, the wafer transfer speed to the plasma discharge electrode is 0.5 to 10 mm / sec, and the wafer temperature is 70. What is necessary is just to be -90 degreeC. By this O 2 plasma treatment, organic substances adhering to the surface of the bump 44 are decomposed and removed, and lyophilicity is imparted.

次に、図６（ｃ）に示すように、レジスト２０の表面を撥液処理する。撥液処理の方法として、第１実施形態の変形例において説明したＣＦ4 プラズマ処理法を採用する。ＣＦ4 プラズマ処理法では、バンプ４４の表面がフッ化処理されないので、バンプ表面の親液性は維持される。一方で、レジスト２０を構成するアクリル樹脂やポリイミド樹脂等は、Ｏ2 プラズマによる前処理を行うことによりフッ化されやすくなる性質を有する。そのため、前記Ｏ2 プラズマ処理を行った後に、ＣＦ4 プラズマ処理を行うことにより、レジスト２０の表面に強い撥液性を付与することができる。 Next, as shown in FIG. 6C, the surface of the resist 20 is subjected to a liquid repellent treatment. As the liquid repellent treatment method, the CF 4 plasma treatment method described in the modification of the first embodiment is adopted. In the CF 4 plasma processing method, since the surface of the bump 44 is not fluorinated, the lyophilicity of the bump surface is maintained. On the other hand, an acrylic resin, a polyimide resin, or the like constituting the resist 20 has a property of being easily fluorinated by performing a pretreatment with O 2 plasma. Therefore, strong liquid repellency can be imparted to the surface of the resist 20 by performing the CF 4 plasma treatment after the O 2 plasma treatment.

その後、図３に示す第１実施形態と同様に、バンプ４４の表面に導電性粒子５０を散布し、熱可塑性樹脂溶液を塗布する。ここで、レジスト２０の表面は強い撥液性を示すので、レジスト２０の表面には熱可塑性樹脂溶液が付着せず、熱可塑性樹脂膜が形成されない。一方、バンプ４４の表面は親液性を示すので、バンプ４４の表面には熱可塑性樹脂溶液が付着しやすくなって、熱可塑性樹脂膜５２が形成される。この場合、図３（ｃ）に示すようにレジストを剥離しても、これに随伴して熱可塑性樹脂膜５２がバンプ４４の表面から剥離されることはない。したがって、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   Thereafter, similarly to the first embodiment shown in FIG. 3, conductive particles 50 are sprayed on the surface of the bump 44 and a thermoplastic resin solution is applied. Here, since the surface of the resist 20 exhibits strong liquid repellency, the thermoplastic resin solution does not adhere to the surface of the resist 20, and a thermoplastic resin film is not formed. On the other hand, since the surface of the bump 44 is lyophilic, the thermoplastic resin solution is likely to adhere to the surface of the bump 44, and the thermoplastic resin film 52 is formed. In this case, even if the resist is peeled off as shown in FIG. 3C, the thermoplastic resin film 52 is not peeled off from the surface of the bump 44 as a result. Therefore, it is possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

［第３実施形態］
次に、本発明の第３実施形態に係る半導体素子の製造方法つき、図７を用いて説明する。図７は、第３実施形態に係る半導体素子の製造方法の説明図である。第３実施形態に係る半導体素子の製造方法は、熱可塑性樹脂溶液を塗布する工程の後に、レジスト２０の表面に紫外線２８を照射して、レジスト２０の表面に形成された熱可塑性樹脂膜５２ａを除去するものである。なお、上記各実施形態と同様の構成となる部分については、その詳細な説明を省略する。 [Third Embodiment]
Next, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is an explanatory diagram of the method for manufacturing the semiconductor device according to the third embodiment. In the method of manufacturing a semiconductor element according to the third embodiment, after the step of applying the thermoplastic resin solution, the surface of the resist 20 is irradiated with ultraviolet rays 28 to form the thermoplastic resin film 52a formed on the surface of the resist 20. To be removed. Note that detailed description of portions having the same configurations as those of the above embodiments is omitted.

まず、第１実施形態の変形例と同様に、レジストの開口部の内側にバンプを形成する。具体的には、図４（ａ）に示すように、ウエハ４１の能動面全体にレジスト２０を塗布する。次に、図４（ｂ）に示すように、電極パッド４２の上方にレジスト２０の開口部２２を形成する。次に、図４（ｃ）に示すように、開口部２２の内側にバンプ４４を形成する。その後、第１実施形態と同様に、バンプの表面に導電性粒子を固着する。具体的には、図３（ａ）に示すように、バンプ４４の表面に導電性粒子５０を散布する。次に、図３（ｂ）に示すように、熱可塑性樹脂溶液を塗布して、バンプ４４の表面に熱可塑性樹脂膜５２を形成する。なお、ウエハ４１の能動面にシランカップリング剤等を塗布して、バンプ４４の表面に親液性を付与することが望ましい。一方、レジスト２０の表面には撥液処理を施していないので、図７（ａ）に示すように、レジスト２０の表面にも熱可塑性樹脂膜５２ａが形成される。   First, as in the modification of the first embodiment, bumps are formed inside the resist openings. Specifically, as shown in FIG. 4A, the resist 20 is applied to the entire active surface of the wafer 41. Next, as shown in FIG. 4B, an opening 22 of the resist 20 is formed above the electrode pad 42. Next, as shown in FIG. 4C, bumps 44 are formed inside the openings 22. Thereafter, similarly to the first embodiment, conductive particles are fixed to the surface of the bump. Specifically, as shown in FIG. 3A, conductive particles 50 are scattered on the surface of the bump 44. Next, as shown in FIG. 3B, a thermoplastic resin solution is applied to form a thermoplastic resin film 52 on the surface of the bump 44. It is desirable to apply a silane coupling agent or the like to the active surface of the wafer 41 to impart lyophilicity to the surface of the bump 44. On the other hand, since the surface of the resist 20 is not subjected to a liquid repellent treatment, a thermoplastic resin film 52a is also formed on the surface of the resist 20 as shown in FIG.

次に、図７（ｂ）に示すように、レジスト２０の表面に形成された熱可塑性樹脂膜５２ａを除去する。熱可塑性樹脂膜５２ａの除去は、熱可塑性樹脂膜５２ａに紫外線レーザ２８を照射して、熱可塑性樹脂膜５２ａを分解・除去することによって行う。紫外線レーザ２８として、ＡｒＦ（波長１９３ｎｍ）やＫｒＦ（波長２４９ｎｍ）、ＸｅＣｌ（波長３０８ｎｍ）、ＸｅＦ（波長３５０ｎｍ）等のエキシマレーザを採用することが可能である。なお、レジスト２０の表面に前記シランカップリング剤が塗布された場合でも、紫外線レーザ２８の照射により、レジスト２０の表面に形成された熱可塑性樹脂膜５２ａを分解・除去することが可能である。   Next, as shown in FIG. 7B, the thermoplastic resin film 52a formed on the surface of the resist 20 is removed. The removal of the thermoplastic resin film 52a is performed by irradiating the ultraviolet resin 28 to the thermoplastic resin film 52a to decompose and remove the thermoplastic resin film 52a. As the ultraviolet laser 28, an excimer laser such as ArF (wavelength 193 nm), KrF (wavelength 249 nm), XeCl (wavelength 308 nm), XeF (wavelength 350 nm), or the like can be used. Even when the silane coupling agent is applied to the surface of the resist 20, the thermoplastic resin film 52 a formed on the surface of the resist 20 can be decomposed and removed by irradiation with the ultraviolet laser 28.

上述した紫外線レーザ２８の照射は、レジスト２０の形成領域に対応した開口部を有するメタルマスク３０を介して行うことが望ましい。特に、狭ピッチのバンプ間にレーザを照射する場合には、レーザの分解能に限界があるため、メタルマスク３０を使用するのが有効である。これにより、バンプ４４の表面にレーザが照射されなくなり、バンプ表面に形成された熱可塑性樹脂膜の分解・除去が防止される。したがって、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   The above-described irradiation with the ultraviolet laser 28 is preferably performed through a metal mask 30 having an opening corresponding to the region where the resist 20 is formed. In particular, when irradiating a laser between bumps having a narrow pitch, it is effective to use the metal mask 30 because the resolution of the laser is limited. As a result, the surface of the bump 44 is not irradiated with laser, and the thermoplastic resin film formed on the bump surface is prevented from being decomposed and removed. Therefore, it is possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

次に、図７（ｃ）に示すように、レジストを剥離する。この場合、レジストに随伴して熱可塑性樹脂膜５２がバンプ４４の表面から剥離されることはない。したがって、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   Next, as shown in FIG. 7C, the resist is removed. In this case, the thermoplastic resin film 52 is not peeled off from the surface of the bump 44 along with the resist. Therefore, it is possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

［第４実施形態］
次に、本発明の第４実施形態に係る半導体素子の製造方法つき、図８を用いて説明する。図８は、第４実施形態に係る半導体素子の製造方法の説明図である。第４実施形態に係る半導体素子の製造方法は、レジスト２０の開口部の内側に、レジスト２０より高さが５μｍ以上低いバンプ４４を形成するものである。なお、上記各実施形態と同様の構成となる部分については、その詳細な説明を省略する。 [Fourth Embodiment]
Next, a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is an explanatory diagram of a method for manufacturing a semiconductor device according to the fourth embodiment. In the semiconductor element manufacturing method according to the fourth embodiment, bumps 44 that are 5 μm or more lower than the resist 20 are formed inside the opening of the resist 20. Note that detailed description of portions having the same configurations as those of the above embodiments is omitted.

まず、第１実施形態の変形例と同様に、レジストの開口部を形成する。具体的には、図４（ａ）に示すように、ウエハ４１の能動面全体にレジスト２０を塗布する。次に、図４（ｂ）に示すように、電極パッド４２の上方にレジスト２０の開口部２２を形成する。
第４実施形態では、図８（ａ）に示すように、レジスト２０より高さが５μｍ以上低いバンプ４４を形成する。具体的には、形成すべきバンプ４４より高さが５μｍ以上高いレジスト２０をあらかじめウエハ４１の能動面に形成しておき、その上でレジスト２０より高さが５μｍ以上低いバンプ４４を形成する。より好ましくは、レジスト２０より高さが１０μｍ以上低いバンプ４４を形成する。なお、バンプ４４をメッキ法によって形成する場合には、メッキ浴の時間を調整することにより、バンプの高さを調整することが可能である。 First, similarly to the modification of the first embodiment, a resist opening is formed. Specifically, as shown in FIG. 4A, the resist 20 is applied to the entire active surface of the wafer 41. Next, as shown in FIG. 4B, an opening 22 of the resist 20 is formed above the electrode pad 42.
In the fourth embodiment, as shown in FIG. 8A, bumps 44 that are 5 μm or more lower than the resist 20 are formed. Specifically, a resist 20 having a height 5 μm or more higher than the bump 44 to be formed is previously formed on the active surface of the wafer 41, and a bump 44 having a height 5 μm or more lower than the resist 20 is formed thereon. More preferably, the bump 44 having a height lower than the resist 20 by 10 μm or more is formed. When the bumps 44 are formed by a plating method, the bump height can be adjusted by adjusting the plating bath time.

次に、図８（ｂ）に示すように、バンプ４４の表面に導電性粒子５０を散布する。さらに、ウエハ４１の能動面に熱可塑性樹脂溶液を塗布して熱処理する。これにより、バンプ４４の表面に熱可塑性樹脂膜５２が形成されて導電性粒子５０が固着されるとともに、レジスト２０の表面にも熱可塑性樹脂膜５２ａが形成される。ところが、レジスト２０とバンプ４４とは高さが５μｍ以上異なるので、ステップカバレッジが困難になり、バンプ表面の熱可塑性樹脂膜５２およびレジスト表面の熱可塑性樹脂膜５２ａが分断した状態で形成される。この場合、図８（ｃ）に示すようにレジストを剥離しても、バンプ４４の表面から熱可塑性樹脂膜５２が剥離されることはない。したがって、第１実施形態と同様に、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   Next, as shown in FIG. 8B, conductive particles 50 are dispersed on the surface of the bump 44. Further, a thermoplastic resin solution is applied to the active surface of the wafer 41 and heat treated. As a result, the thermoplastic resin film 52 is formed on the surface of the bump 44 to fix the conductive particles 50, and the thermoplastic resin film 52 a is also formed on the surface of the resist 20. However, since the resist 20 and the bump 44 are different in height by 5 μm or more, the step coverage becomes difficult, and the thermoplastic resin film 52 on the bump surface and the thermoplastic resin film 52a on the resist surface are formed in a divided state. In this case, even if the resist is peeled off as shown in FIG. 8C, the thermoplastic resin film 52 is not peeled off from the surface of the bump 44. Therefore, similarly to the first embodiment, it becomes possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

ここで、第４実施形態に係る半導体素子の製造方法の変形例につき、図９を用いて説明する。図９は、第４実施形態に係る半導体素子の製造方法の変形例の説明図である。第４実施形態の変形例は、電極パッド４２の表面から上方にかけて開口面積が小さくなる開口部２２をレジスト２０に形成するものである。なお、上記各実施形態と同様の構成となる部分については、その詳細な説明を省略する。   Here, a modified example of the method of manufacturing a semiconductor device according to the fourth embodiment will be described with reference to FIG. FIG. 9 is an explanatory view of a modification of the method for manufacturing a semiconductor device according to the fourth embodiment. In the modification of the fourth embodiment, an opening 22 whose opening area decreases from the surface of the electrode pad 42 to the upper side is formed in the resist 20. Note that detailed description of portions having the same configurations as those of the above embodiments is omitted.

変形例では、まずウエハ４１の能動面全体にレジスト２０を塗布する。次に、図９（ａ）に示すように、電極パッド４２の表面から上方にかけて開口面積が小さくなる開口部２２をレジスト２０に形成する。具体的には、ネガ型レジストを使用して、非開口部の表面のみを硬化させるようにハーフ露光する。その後、現像処理を行って開口部２２のレジストを除去すれば、開口部の側壁にアンダーカットが形成される。次に、開口部２２の内側にバンプ４４を形成する。このバンプ４４は、前記開口部２２の形状にしたがって台形状に形成される。   In the modification, first, the resist 20 is applied to the entire active surface of the wafer 41. Next, as shown in FIG. 9A, an opening 22 with a smaller opening area is formed in the resist 20 from the surface of the electrode pad 42 upward. Specifically, using a negative resist, half exposure is performed so that only the surface of the non-opening portion is cured. Thereafter, when the resist is removed from the opening 22 by developing, an undercut is formed on the side wall of the opening. Next, a bump 44 is formed inside the opening 22. The bumps 44 are formed in a trapezoidal shape according to the shape of the opening 22.

次に、図９（ｂ）に示すように、バンプ４４の表面に導電性粒子５０を散布する。さらに、ウエハ４１の能動面に熱可塑性樹脂溶液を塗布して熱処理する。これにより、バンプ４４の表面に熱可塑性樹脂膜５２が形成されて導電性粒子５０が固着されるとともに、レジスト２０の表面にも熱可塑性樹脂膜５２ａが形成される。ところが、レジスト２０の開口部２２の側壁にはアンダーカットが形成されているので、ステップカバレッジが不可能になり、バンプ表面の熱可塑性樹脂膜５２およびレジスト表面の熱可塑性樹脂膜５２ａが分断した状態で形成される。この場合、図９（ｃ）に示すようにレジストを剥離しても、バンプ４４の表面から熱可塑性樹脂膜５２が剥離されることはない。したがって、第１実施形態と同様に、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   Next, as shown in FIG. 9B, conductive particles 50 are dispersed on the surface of the bump 44. Further, a thermoplastic resin solution is applied to the active surface of the wafer 41 and heat treated. As a result, the thermoplastic resin film 52 is formed on the surface of the bump 44 to fix the conductive particles 50, and the thermoplastic resin film 52 a is also formed on the surface of the resist 20. However, since the undercut is formed on the side wall of the opening 22 of the resist 20, step coverage is impossible, and the thermoplastic resin film 52 on the bump surface and the thermoplastic resin film 52a on the resist surface are divided. Formed with. In this case, even if the resist is peeled off as shown in FIG. 9C, the thermoplastic resin film 52 is not peeled off from the surface of the bump 44. Therefore, similarly to the first embodiment, it becomes possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

［第５実施形態］
次に、本発明の第５実施形態に係る半導体素子の製造方法つき、図１０を用いて説明する。図１０は、第５実施形態に係る半導体素子の製造方法の説明図である。第５実施形態に係る半導体素子の製造方法は、熱可塑性樹脂膜５２を冷却することにより、レジスト表面に配置された熱可塑性樹脂膜５２ａをバンプ表面に配置された熱可塑性樹脂膜５２から分断するものである。なお、上記各実施形態と同様の構成となる部分については、その詳細な説明を省略する。 [Fifth Embodiment]
Next, a semiconductor device manufacturing method according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 10 is an explanatory diagram of a method of manufacturing a semiconductor device according to the fifth embodiment. In the semiconductor element manufacturing method according to the fifth embodiment, the thermoplastic resin film 52 is cooled, so that the thermoplastic resin film 52a disposed on the resist surface is separated from the thermoplastic resin film 52 disposed on the bump surface. Is. Note that detailed description of portions having the same configurations as those of the above embodiments is omitted.

まず、第３実施形態と同様に、レジスト２０の開口部２２の内側にバンプ４４を形成する。次に、熱可塑性樹脂溶液を塗布して熱可塑性樹脂膜５２を形成することにより、バンプ４４の表面に導電性粒子５０を固着する。熱可塑性樹脂膜５２を形成するには、まず熱可塑性樹脂溶液を５０℃程度で加熱して溶剤を蒸発させ、溶質である熱可塑性樹脂を凝結させる。さらに、２５０℃で１０分程度アニール（加熱）処理することにより、熱可塑性樹脂を溶着させる。なお、レジスト２０の表面を撥液処理していないので、レジスト２０の表面にも熱可塑性樹脂膜５２ａが形成されることになる。以上により、図１０（ａ）に示す状態となる。   First, as in the third embodiment, bumps 44 are formed inside the openings 22 of the resist 20. Next, the conductive particles 50 are fixed to the surfaces of the bumps 44 by applying a thermoplastic resin solution to form the thermoplastic resin film 52. In order to form the thermoplastic resin film 52, first, the thermoplastic resin solution is heated at about 50 ° C. to evaporate the solvent, thereby condensing the thermoplastic resin as a solute. Furthermore, the thermoplastic resin is welded by annealing (heating) treatment at 250 ° C. for about 10 minutes. Since the surface of the resist 20 is not subjected to the liquid repellent treatment, the thermoplastic resin film 52a is also formed on the surface of the resist 20. As a result, the state shown in FIG.

次に、図１０（ｂ）に示すように、熱可塑性樹脂膜５２を冷却する。具体的には、ウエハ４１を液体窒素に浸漬する方法等により、熱可塑性樹脂膜５２を例えば−４０℃程度まで冷却する。ところで、レジスト２０およびバンプ４４は高さが異なっているので、バンプ表面の熱可塑性樹脂膜５２とレジスト表面の熱可塑性樹脂膜５２ａとの連結部分では、熱可塑性樹脂膜の厚さが薄くなっている。そのため、熱可塑性樹脂膜５２が冷却によって収縮すると、前記連結部分に応力集中が発生して、バンプ表面の熱可塑性樹脂膜５２とレジスト表面の熱可塑性樹脂膜５２ａとが分断される。なお、熱可塑性樹脂膜５２の加熱および冷却を繰り返し行えば、より確実にバンプ表面の熱可塑性樹脂膜５２とレジスト表面の熱可塑性樹脂膜５２ａとを分断することができる。   Next, as shown in FIG. 10B, the thermoplastic resin film 52 is cooled. Specifically, the thermoplastic resin film 52 is cooled to about −40 ° C., for example, by a method of immersing the wafer 41 in liquid nitrogen. By the way, since the resist 20 and the bump 44 are different in height, the thickness of the thermoplastic resin film is reduced at the connecting portion between the thermoplastic resin film 52 on the bump surface and the thermoplastic resin film 52a on the resist surface. Yes. Therefore, when the thermoplastic resin film 52 contracts due to cooling, stress concentration occurs in the connecting portion, and the thermoplastic resin film 52 on the bump surface and the thermoplastic resin film 52a on the resist surface are divided. If heating and cooling of the thermoplastic resin film 52 are repeated, the thermoplastic resin film 52 on the bump surface and the thermoplastic resin film 52a on the resist surface can be more reliably separated.

この場合、図１０（ｃ）に示すようにレジストを剥離しても、バンプ４４の表面から熱可塑性樹脂膜５２が剥離されることはない。したがって、第１実施形態と同様に、導電性粒子５０がバンプ表面から離脱するのを防止することが可能になり、半導体素子と相手側基板とを確実に電気的接続することができる。   In this case, even if the resist is peeled off as shown in FIG. 10C, the thermoplastic resin film 52 is not peeled off from the surface of the bump 44. Therefore, similarly to the first embodiment, it becomes possible to prevent the conductive particles 50 from separating from the bump surface, and the semiconductor element and the counterpart substrate can be reliably electrically connected.

［電気光学装置］
次に、前記半導体素子が実装された電気光学装置の一例である液晶モジュールにつき、図１１ないし図１３を用いて説明する。
図１１は、液晶モジュールの分解斜視図である。図１１に示す液晶モジュール１は、カラー画像を表示する液晶パネル９０と、液晶パネル９０の上基板８０（相手側基板１０）に実装される液晶パネル９０の駆動用半導体素子４０とを主として構成されている。 [Electro-optical device]
Next, a liquid crystal module which is an example of an electro-optical device on which the semiconductor element is mounted will be described with reference to FIGS.
FIG. 11 is an exploded perspective view of the liquid crystal module. The liquid crystal module 1 shown in FIG. 11 mainly includes a liquid crystal panel 90 that displays a color image, and a driving semiconductor element 40 of the liquid crystal panel 90 that is mounted on the upper substrate 80 (the counterpart substrate 10) of the liquid crystal panel 90. ing.

図１２は液晶パネルの分解斜視図であり、図１３は図１２のＡ−Ａ線における側面断面図である。図１３に示すように、液晶パネル９０は、下基板７０および上基板８０により液晶層９２を挟持して構成されている。この液晶層９２にはネマチック液晶等が採用され、液晶パネル９０の動作モードとしてツイステッドネマチック（ＴＮ）モードが採用されている。なお上記以外の液晶材料を採用することも可能であり、また上記以外の動作モードを採用することも可能である。なお以下には、スイッチング素子としてＴＦＤ素子を用いたアクティブマトリクス型の液晶パネルを例にして説明するが、これ以外のアクティブマトリクス型の液晶パネルやパッシブマトリクス型の液晶パネルに本発明を適用することも可能である。   12 is an exploded perspective view of the liquid crystal panel, and FIG. 13 is a side sectional view taken along line AA of FIG. As shown in FIG. 13, the liquid crystal panel 90 is configured by sandwiching a liquid crystal layer 92 between a lower substrate 70 and an upper substrate 80. A nematic liquid crystal or the like is employed for the liquid crystal layer 92, and a twisted nematic (TN) mode is employed as an operation mode of the liquid crystal panel 90. Note that liquid crystal materials other than those described above can be employed, and operation modes other than those described above can be employed. Hereinafter, an active matrix type liquid crystal panel using a TFD element as a switching element will be described as an example. However, the present invention is applied to other active matrix type liquid crystal panels and passive matrix type liquid crystal panels. Is also possible.

図１２に示すように、液晶パネル９０では、ガラス等の透明材料からなる下基板７０および上基板８０が対向配置されている。
上基板８０の内側には、複数のデータ線８１が形成されている。そのデータ線８１の側方には、ＩＴＯ等の透明導電性材料からなる複数の画素電極８２が、マトリクス状に配置されている。なお、各画素電極８２の形成領域により画素領域が構成されている。この画素電極８２は、ＴＦＤ素子８３を介して各データ線８１に接続されている。このＴＦＤ素子８３は、基板表面に形成されたＴａを主成分とする第１導電膜と、その第１導電膜の表面に形成されたＴａ２Ｏ３を主成分とする絶縁膜と、その絶縁膜の表面に形成されたＣｒを主成分とする第２導電膜とによって構成されている（いわゆるＭＩＭ構造）。そして、第１導電膜がデータ線８１に接続され、第２導電膜が画素電極８２に接続されている。これによりＴＦＤ素子８３は、画素電極８２への通電を制御するスイッチング素子として機能する。 As shown in FIG. 12, in the liquid crystal panel 90, a lower substrate 70 and an upper substrate 80 made of a transparent material such as glass are disposed to face each other.
A plurality of data lines 81 are formed inside the upper substrate 80. A plurality of pixel electrodes 82 made of a transparent conductive material such as ITO are arranged in a matrix on the side of the data line 81. Note that a pixel region is constituted by the formation region of each pixel electrode 82. The pixel electrode 82 is connected to each data line 81 via the TFD element 83. The TFD element 83 includes a first conductive film mainly composed of Ta formed on the surface of the substrate, an insulating film mainly composed of Ta 2 O 3 formed on the surface of the first conductive film, and an insulation thereof. A second conductive film mainly composed of Cr formed on the surface of the film (so-called MIM structure). The first conductive film is connected to the data line 81 and the second conductive film is connected to the pixel electrode 82. Accordingly, the TFD element 83 functions as a switching element that controls energization to the pixel electrode 82.

一方、下基板７０の内側には、カラーフィルタ膜７６が形成されている。カラーフィルタ膜７６は、平面視略矩形状のカラーフィルタ７６Ｒ，７６Ｇ，７６Ｂによって構成されている。各カラーフィルタ７６Ｒ，７６Ｇ，７６Ｂは、それぞれ異なる色光のみを透過する顔料等によって構成され、各画素領域に対応してマトリクス状に配置されている。また、隣接する画素領域からの光洩れを防止するため、各カラーフィルタの周縁部には遮光膜７７が形成されている。この遮光膜７７は、光吸収性を有する黒色の金属クロム等により、額縁状に形成されている。さらに、カラーフィルタ膜７６および遮光膜７７を覆うように、透明な絶縁膜７９が形成されている。   On the other hand, a color filter film 76 is formed inside the lower substrate 70. The color filter film 76 is composed of color filters 76R, 76G, and 76B having a substantially rectangular shape in plan view. Each of the color filters 76R, 76G, and 76B is made of a pigment that transmits only different color light, and is arranged in a matrix corresponding to each pixel region. Further, in order to prevent light leakage from adjacent pixel regions, a light shielding film 77 is formed on the peripheral edge of each color filter. The light shielding film 77 is formed in a frame shape from black metal chrome having light absorptivity. Further, a transparent insulating film 79 is formed so as to cover the color filter film 76 and the light shielding film 77.

その絶縁膜７９の内側には、複数の走査線７２が形成されている。この走査線７２は、ＩＴＯ等の透明導電材料によって略帯状に形成され、上基板８０のデータ線８１と交差する方向に延在している。そして走査線７２は、その延在方向に配列された前記カラーフィルタ７６Ｒ，７６Ｇ，７６Ｂを覆うように形成され、対向電極として機能するようになっている。そして、走査線７２に走査信号が供給され、データ線８１にデータ信号が供給されると、対向する画素電極８２および対向電極７２により、液晶層に電界が印加されるようになっている。   A plurality of scanning lines 72 are formed inside the insulating film 79. The scanning line 72 is formed in a substantially strip shape by a transparent conductive material such as ITO and extends in a direction intersecting the data line 81 of the upper substrate 80. The scanning line 72 is formed so as to cover the color filters 76R, 76G, and 76B arranged in the extending direction, and functions as a counter electrode. When a scanning signal is supplied to the scanning line 72 and a data signal is supplied to the data line 81, an electric field is applied to the liquid crystal layer by the opposing pixel electrode 82 and the opposing electrode 72.

また図１３に示すように、画素電極８２および対向電極７２を覆うように、配向膜７４，８４が形成されている。この配向膜７４，８４は、電界無印加時における液晶分子の配向状態を制御するものであり、ポリイミド等の有機高分子材料によって構成され、その表面にラビング処理が施されている。これにより電界無印加時には、配向膜７４，８４の表面付近における液晶分子が、その長軸方向をラビング処理方向に一致させて、配向膜７４，８４と略平行に配向されるようになっている。なお、配向膜７４の表面付近における液晶分子の配向方向と、配向膜８４の表面付近における液晶分子の配向方向とが、所定角度だけずれるように、各配向膜７４，８４に対してラビング処理が施されている。これにより、液晶層９２を構成する液晶分子は、液晶層９２の厚さ方向に沿ってらせん状に積層されるようになっている。   As shown in FIG. 13, alignment films 74 and 84 are formed so as to cover the pixel electrode 82 and the counter electrode 72. The alignment films 74 and 84 control the alignment state of the liquid crystal molecules when no electric field is applied, and are made of an organic polymer material such as polyimide, and the surface thereof is rubbed. As a result, when no electric field is applied, the liquid crystal molecules in the vicinity of the surfaces of the alignment films 74 and 84 are aligned substantially parallel to the alignment films 74 and 84 with the major axis direction coinciding with the rubbing treatment direction. . The alignment films 74 and 84 are rubbed so that the alignment direction of the liquid crystal molecules near the surface of the alignment film 74 and the alignment direction of the liquid crystal molecules near the surface of the alignment film 84 are shifted by a predetermined angle. It has been subjected. Thereby, the liquid crystal molecules constituting the liquid crystal layer 92 are spirally stacked along the thickness direction of the liquid crystal layer 92.

また、両基板７０，８０は、熱硬化型や紫外線硬化型などの接着剤からなるシール材９３によって周縁部が接合されている。そして、両基板７０，８０とシール材９３とによって囲まれた空間に、液晶層９２が封止されている。なお、液晶層９２の厚さ（セルギャップ）は、両基板の間に配置されたスペーサ粒子９５によって規制されている。
一方、下基板７０および上基板８０の外側には、偏光板（不図示）が配置されている。各偏光板は、相互の偏光軸（透過軸）が所定角度だけずれた状態で配置されている。また入射側偏光板の外側には、バックライト（不図示）が配置されている。 Further, the peripheral portions of the substrates 70 and 80 are joined by a sealing material 93 made of an adhesive such as a thermosetting type or an ultraviolet curable type. A liquid crystal layer 92 is sealed in a space surrounded by the substrates 70 and 80 and the sealing material 93. Note that the thickness (cell gap) of the liquid crystal layer 92 is regulated by the spacer particles 95 arranged between the two substrates.
On the other hand, a polarizing plate (not shown) is disposed outside the lower substrate 70 and the upper substrate 80. Each polarizing plate is arranged in a state in which the mutual polarization axes (transmission axes) are shifted by a predetermined angle. Further, a backlight (not shown) is disposed outside the incident side polarizing plate.

そして、バックライトから照射された光は、入射側偏光板の偏光軸に沿った直線偏光に変換されて、下基板７０から液晶層９２に入射する。この直線偏光は、電界無印加状態の液晶層９２を透過する過程で、液晶分子のねじれ方向に沿って所定角度だけ旋回し、出射側偏光板を透過する。これにより、電界無印加時には白表示が行われる（ノーマリーホワイトモード）。一方、液晶層９２に電界を印加すると、電界方向に沿って配向膜７４，８４と垂直に液晶分子が再配向する。この場合、液晶層９２に入射した直線偏光は旋回しないので、出射側偏光板を透過しない。これにより、電界無印加時には黒表示が行われる。なお、印加する電界の強さによって階調表示を行うことも可能である。
液晶パネル９０は、以上のように構成されている。 The light emitted from the backlight is converted into linearly polarized light along the polarization axis of the incident-side polarizing plate and enters the liquid crystal layer 92 from the lower substrate 70. This linearly polarized light is rotated by a predetermined angle along the twist direction of the liquid crystal molecules in the process of passing through the liquid crystal layer 92 in a state where no electric field is applied, and is transmitted through the output side polarizing plate. Thereby, white display is performed when no electric field is applied (normally white mode). On the other hand, when an electric field is applied to the liquid crystal layer 92, the liquid crystal molecules are reoriented perpendicularly to the alignment films 74 and 84 along the electric field direction. In this case, the linearly polarized light incident on the liquid crystal layer 92 does not rotate, and therefore does not pass through the output side polarizing plate. Thereby, black display is performed when no electric field is applied. Note that gradation display can also be performed depending on the strength of an applied electric field.
The liquid crystal panel 90 is configured as described above.

図１１に戻り、液晶パネル９０を構成する上基板８０の一辺に、下基板７０からの張り出し部８０ａが形成されている。その張り出し部８０ａには、上基板８０からデータ線８１が、下基板７０から走査線７２がそれぞれ引き回され、これらの端部には上述した電極パッド（不図示）が形成されている。そして、その電極パッドに対し、上述した熱硬化性樹脂層６０を介して、本実施形態の半導体素子４０が実装されている。この半導体素子４０により、液晶パネル９０のデータ線８１および走査線７２に対する通電が制御され、液晶パネル９０の各画素が駆動されて、画像表示が行われるようになっている。   Returning to FIG. 11, a protruding portion 80 a from the lower substrate 70 is formed on one side of the upper substrate 80 constituting the liquid crystal panel 90. A data line 81 is routed from the upper substrate 80 and a scanning line 72 is routed from the lower substrate 70 to the projecting portion 80a, and the above-described electrode pads (not shown) are formed at these end portions. And the semiconductor element 40 of this embodiment is mounted through the thermosetting resin layer 60 mentioned above with respect to the electrode pad. The semiconductor element 40 controls the energization of the data lines 81 and the scanning lines 72 of the liquid crystal panel 90 and drives each pixel of the liquid crystal panel 90 to display an image.

以上には、半導体素子４０をガラス基板８０に実装するＣＯＧ（Chip On Grass）に対して本発明を適用する場合について述べたが、ポリイミド等からなるフレキシブルプリント基板（ＦＰＣ）に半導体素子４０を実装するＣＯＦ（Chip On Film）に対して本発明を適用することも可能である。この場合、ＦＰＣは、異方導電性フィルム（ＡＣＦ）等を介して、液晶パネル９０の上基板８０における張り出し部８０ａに実装される。   Although the case where the present invention is applied to COG (Chip On Grass) in which the semiconductor element 40 is mounted on the glass substrate 80 has been described above, the semiconductor element 40 is mounted on a flexible printed circuit board (FPC) made of polyimide or the like. It is also possible to apply the present invention to a COF (Chip On Film). In this case, the FPC is mounted on the protruding portion 80a of the upper substrate 80 of the liquid crystal panel 90 via an anisotropic conductive film (ACF) or the like.

［電子機器］
図１４は、本発明に係る電子機器の一例を示す斜視図である。この図に示す携帯電話１３００は、上述した電気光学装置を小サイズの表示部１３０１として備え、複数の操作ボタン１３０２、受話口１３０３、及び送話口１３０４を備えて構成されている。
上述した電気光学装置は、上記携帯電話に限らず、電子ブック、パーソナルコンピュータ、ディジタルスチルカメラ、液晶テレビ、ビューファインダ型あるいはモニタ直視型のビデオテープレコーダ、カーナビゲーション装置、ページャ、電子手帳、電卓、ワードプロセッサ、ワークステーション、テレビ電話、ＰＯＳ端末、タッチパネルを備えた機器等々の画像表示手段として好適に用いることができ、いずれの場合にも電気的接続の信頼性に優れた電子機器を提供することができる。 [Electronics]
FIG. 14 is a perspective view showing an example of an electronic apparatus according to the invention. A cellular phone 1300 shown in the figure includes the above-described electro-optical device as a small-sized display unit 1301 and includes a plurality of operation buttons 1302, a mouthpiece 1303, and a mouthpiece 1304.
The above-described electro-optical device is not limited to the above mobile phone, but an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, It can be suitably used as an image display means for a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, etc., and in any case, an electronic device having excellent electrical connection reliability can be provided. it can.

なお、本発明の技術範囲は、上述した各実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において、上述した実施形態に種々の変更を加えたものを含む。すなわち、各実施形態で挙げた具体的な材料や構成などはほんの一例に過ぎず、適宜変更が可能である。   The technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. That is, the specific materials and configurations described in the embodiments are merely examples, and can be changed as appropriate.

第１実施形態に係る半導体素子の実装状態の側面断面図である。It is side surface sectional drawing of the mounting state of the semiconductor element which concerns on 1st Embodiment. 第１実施形態に係る半導体素子の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on 1st Embodiment. 第１実施形態に係る半導体素子の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on 1st Embodiment. 第１実施形態に係る半導体素子の製造方法の変形例の説明図である。It is explanatory drawing of the modification of the manufacturing method of the semiconductor element which concerns on 1st Embodiment. 第１実施形態に係る半導体素子の実装方法の説明図である。It is explanatory drawing of the mounting method of the semiconductor element which concerns on 1st Embodiment. 第２実施形態に係る半導体素子の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on 2nd Embodiment. 第３実施形態に係る半導体素子の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on 3rd Embodiment. 第４実施形態に係る半導体素子の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on 4th Embodiment. 第４実施形態に係る半導体素子の製造方法の変形例の説明図である。It is explanatory drawing of the modification of the manufacturing method of the semiconductor element which concerns on 4th Embodiment. 第５実施形態に係る半導体素子の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on 5th Embodiment. 液晶モジュールの分解斜視図である。It is a disassembled perspective view of a liquid crystal module. 液晶パネルの分解斜視図である。It is a disassembled perspective view of a liquid crystal panel. 液晶パネルの側面断面図である。It is side surface sectional drawing of a liquid crystal panel. 携帯電話の斜視図である。It is a perspective view of a mobile phone. 従来技術に係る半導体素子の実装状態の側面断面図である。It is side surface sectional drawing of the mounting state of the semiconductor element which concerns on a prior art.

符号の説明Explanation of symbols

２０レジスト ２１フッ素樹脂膜 ４２電極パッド ４４バンプ ５０導電性粒子 ５２熱可塑性樹脂   20 resist 21 fluorine resin film 42 electrode pad 44 bump 50 conductive particle 52 thermoplastic resin

Claims (12)

能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記能動面上に配置され、表面が撥液性を示し、前記電極パッドの上方に開口部を有するマスクと、前記開口部の内側に配置され、前記マスクより高さの低いバンプと、を形成する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
A mask disposed on the active surface and having a liquid-repellent surface and having an opening above the electrode pad, and a bump disposed inside the opening and having a height lower than the mask are formed. And a process of
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Removing the mask;
A method for manufacturing an electronic component, comprising: 能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記能動面にマスクを形成する工程と、
前記マスクの表面を撥液処理する工程と、
前記電極パッドの上方に前記マスクの開口部を形成する工程と、
前記開口部の内側に、前記マスクより高さの低いバンプを形成する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a mask on the active surface;
A liquid repellent treatment of the surface of the mask;
Forming an opening of the mask above the electrode pad;
Forming a bump having a height lower than that of the mask inside the opening;
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Removing the mask;
A method for manufacturing an electronic component, comprising: 能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記能動面にマスクを形成する工程と、
前記電極パッドの上方に前記マスクの開口部を形成する工程と、
前記開口部の内側に、前記マスクより高さの低いバンプを形成する工程と、
前記マスクの表面を撥液処理する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a mask on the active surface;
Forming an opening of the mask above the electrode pad;
Forming a bump having a height lower than that of the mask inside the opening;
A liquid repellent treatment of the surface of the mask;
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Removing the mask;
A method for manufacturing an electronic component, comprising: 前記導電性粒子を接着剤により固着させる工程の前に、前記バンプの表面を親液処理する工程を有することを特徴とする請求項１ないし請求項３のいずれかに記載の電子部品の製造方法。   4. The method of manufacturing an electronic component according to claim 1, further comprising a step of performing a lyophilic treatment on a surface of the bump before the step of fixing the conductive particles with an adhesive. 5. . 能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記電極パッドの上方に開口部を有するマスクを、前記能動面に形成する工程と、
前記開口部の内側に、前記マスクより高さが低いバンプを形成する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記マスクの表面に紫外線を照射して、前記接着剤を除去する工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a mask on the active surface with an opening above the electrode pad;
Forming a bump having a height lower than that of the mask inside the opening;
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Irradiating the surface of the mask with ultraviolet rays to remove the adhesive;
Removing the mask;
A method for manufacturing an electronic component, comprising: 能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記電極パッドの上方に開口部を有するマスクを、前記能動面に形成する工程と、
前記開口部の内側に、前記マスクより高さが５μｍ以上低いバンプを形成する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a mask on the active surface with an opening above the electrode pad;
Forming a bump 5 μm or more lower than the mask inside the opening; and
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Removing the mask;
A method for manufacturing an electronic component, comprising: 能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記能動面上に、前記電極パッドの表面から上方にかけて開口面積が小さくなる開口部を有するマスクを形成する工程と、
前記開口部の内側に、前記マスクより高さが低いバンプを形成する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a mask on the active surface having an opening with a smaller opening area from the surface of the electrode pad to the upper side;
Forming a bump having a height lower than that of the mask inside the opening;
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Removing the mask;
A method for manufacturing an electronic component, comprising: 能動面に形成された電極パッドを介して相手側基板に実装される電子部品の製造方法であって、
前記電極パッドの上方に開口部を有するマスクを、前記能動面に形成する工程と、
前記開口部の内側に、前記マスクより高さが低いバンプを形成する工程と、
前記バンプの表面に導電性粒子を散布する工程と、
前記導電性粒子を接着剤により前記バンプの表面に固着させる工程と、
前記接着剤を冷却して、前記マスクの表面に配置された接着剤を、前記バンプの表面に配置された前記接着剤から分離する工程と、
前記マスクを除去する工程と、
を有することを特徴とする電子部品の製造方法。 A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a mask on the active surface with an opening above the electrode pad;
Forming a bump having a height lower than that of the mask inside the opening;
Spraying conductive particles on the surface of the bump;
Fixing the conductive particles to the surface of the bump with an adhesive; and
Cooling the adhesive to separate the adhesive disposed on the surface of the mask from the adhesive disposed on the surface of the bump;
Removing the mask;
A method for manufacturing an electronic component, comprising: 前記導電性粒子を固着させる工程の前に、前記マスクの表面に残存する前記導電性粒子を除去することを特徴とする請求項１ないし請求項８のいずれかに記載の電子部品の製造方法。   9. The method of manufacturing an electronic component according to claim 1, wherein the conductive particles remaining on the surface of the mask are removed before the step of fixing the conductive particles. 前記導電性粒子を散布する工程の前および／または後に、前記バンプの表面に熱可塑性樹脂からなる前記接着剤を塗布する工程を有し、
前記導電性粒子を固着させる工程では、前記接着剤を可塑化させた後に、前記接着剤を硬化させることにより、前記バンプの表面に前記導電性粒子を固着させることを特徴とする請求項１ないし請求項９のいずれかに記載の電子部品の製造方法。 Before and / or after the step of spraying the conductive particles, the step of applying the adhesive made of a thermoplastic resin on the surface of the bump,
2. The step of fixing the conductive particles includes fixing the conductive particles to the surface of the bump by hardening the adhesive after plasticizing the adhesive. The manufacturing method of the electronic component in any one of Claim 9. 請求項１ないし請求項１０のいずれかに記載の電子部品の製造方法を使用して製造したことを特徴とする電子部品。   An electronic component manufactured using the method for manufacturing an electronic component according to claim 1. 請求項１１に記載の電子部品を備えたことを特徴とする電子機器。   An electronic device comprising the electronic component according to claim 11.
JP2004038324A 2004-02-16 2004-02-16 Electronic component, manufacturing method thereof, and electronic equipment Withdrawn JP2005229044A (en)

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Cited By (4)

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JP2008129595A (en) * 2006-11-22 2008-06-05 Samsung Electronics Co Ltd Drive circuit for liquid crystal display, method of manufacturing the same, and liquid crystal display mounting drive circuit for liquid crystal display
JP2008244256A (en) * 2007-03-28 2008-10-09 Casio Comput Co Ltd Electronic chip component and manufacturing method therefor
WO2015091673A1 (en) * 2013-12-17 2015-06-25 Conpart As Bonded assemblies with pre-deposited polymer balls on demarcated areas and methods of forming such bonded assemblies
JPWO2017078039A1 (en) * 2015-11-04 2018-02-15 リンテック株式会社 Thermosetting resin film, first protective film forming sheet, and first protective film forming method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008129595A (en) * 2006-11-22 2008-06-05 Samsung Electronics Co Ltd Drive circuit for liquid crystal display, method of manufacturing the same, and liquid crystal display mounting drive circuit for liquid crystal display
KR101309319B1 (en) * 2006-11-22 2013-09-13 삼성디스플레이 주식회사 Driving circuit, method of manufacturing thereof and liquid crystal display apparatus having the same
US8576368B2 (en) 2006-11-22 2013-11-05 Samsung Display Co., Ltd. Driving circuit for a liquid crystal display device, method of manufacturing the same and display device having the same
JP2008244256A (en) * 2007-03-28 2008-10-09 Casio Comput Co Ltd Electronic chip component and manufacturing method therefor
WO2015091673A1 (en) * 2013-12-17 2015-06-25 Conpart As Bonded assemblies with pre-deposited polymer balls on demarcated areas and methods of forming such bonded assemblies
JPWO2017078039A1 (en) * 2015-11-04 2018-02-15 リンテック株式会社 Thermosetting resin film, first protective film forming sheet, and first protective film forming method

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