JP4103835B2 - Manufacturing method of electronic parts - Google Patents

Description

  The present invention relates to an electronic component manufacturing method, an electronic component, an electro-optical device, and an electronic apparatus.

Electronic parts such as semiconductor elements are used by being mounted on a circuit board or the like. Various methods have been proposed for mounting electronic components on circuit boards.
FIG. 10 is an explanatory diagram of a method for mounting an electronic component according to the prior art. In FIG. 10A, an electronic component 170 such as an IC is mounted on the counterpart substrate 120 with an anisotropic conductive film (ACF) 190 interposed therebetween. The anisotropic conductive film 190 is obtained by dispersing conductive particles 195 in a thermosetting resin 192. The conductive particles 195 enter between the electrode pad 172 formed on the active surface of the electronic component 170 and the electrode pad 122 formed on the surface of the counterpart substrate 120, and both are electrically connected. Yes. Further, the electronic component 170 and the counterpart substrate 120 are mechanically connected by a thermosetting resin 192 cured by heating.

  In recent years, with the miniaturization of electronic components, the pitch between electrode pads has been reduced. However, in the above mounting method using an anisotropic conductive film, the conductive particles are also disposed between the electrode pads adjacent in the horizontal direction, which may cause a short circuit between the electrode pads. In addition, since the electrode pads themselves become smaller as the pitch of the electrode pads becomes smaller, the number of conductive particles captured by each electrode pad may decrease, and the reliability of electrical connection may be reduced. Furthermore, there is a problem that not all of the expensive conductive particles can be used for electrical connection.

Thus, Patent Documents 1 to 3 disclose a structure in which conductive particles are not fixed between adjacent electrode pads by fixing conductive particles on the surface of the electrode pads in advance and mounting them on the counterpart substrate. Yes.
FIG. 10B is an explanatory diagram of the mounting method disclosed in Patent Document 3. In this mounting method, the conductive particles 295 are covered with an adhesive 296 to form adhesive conductive particles 298, and the adhesive conductive particles 298 are bonded to the surface of the electrode pad 272 in the electronic component 270. In the bonding method, first, a resist film 280 is formed on a portion of the active surface of the electronic component 270 other than the portion where the electrode pad 272 is formed. Next, the adhesive conductive particles 298 are dispersed on a plane, and the electronic component 270 is heated and pressed against the dispersed adhesive conductive particles 298. As a result, the adhesive conductive particles 298 are bonded to the entire active surface of the electronic component 270. Next, the adhesive conductive particles 298 adhered to the surface of the resist film 280 other than the electrode pads 272 are removed together with the resist film 280. As described above, the adhesive conductive particles 298 are adhered to only the surface of the electrode pad 272. Then, the remaining adhesive conductive particles 298 are positioned on the electrode pads 222 of the counterpart substrate 220, and the electronic component 270 is thermocompression bonded to the counterpart substrate 220. As a result, the adhesive 296 of the adhesive conductive particles 298 is dissolved and the electronic component 270 and the counterpart substrate 220 are mechanically connected, and both are electrically connected by the exposed conductive particles 295.
JP 7-6799 A JP-A-10-84178 JP 2002-170837 A

  However, in the mounting method described in Patent Document 3, when the height of the resist film 280 is larger than the diameter of the adhesive conductive particles 298, the adhesive conductive particles 298 are formed on the surface of the electrode pad 272 in the electronic component 270. There are cases where they are stacked. In this case, when the electronic component 270 is thermocompression bonded to the mating substrate 220, the adhesive conductive particles 298 laminated on the surface of the electrode pad 272 are sandwiched between the electrode pads 222 of the mating substrate 220, Rearranged to one layer. Here, the remaining adhesive conductive particles 298 overflow around the electrode pads 222 and 272. The overflowing conductive conductive particles 298 may cause a short circuit between adjacent electrode pads 222. This problem becomes conspicuous as the electrode pad pitch becomes narrower.

The present invention has been made to solve the above problems, and an object thereof is to provide an electronic component manufacturing method and an electronic component capable of preventing a short circuit between adjacent electrodes.
It is another object of the present invention to provide an electronic device with excellent electrical connection reliability.

In order to achieve the above object, an electronic component manufacturing method of the present invention is a method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, and is provided on the surface of the electrode pad. A step of forming a bump, a step of forming a mask having an opening on a surface of the bump on the active surface, a step of spraying conductive particles on the active surface and capturing the opening in the opening, and the opening Fixing the conductive particles stacked on the surface of the bump, and the mask and the opening are arranged so that the height h and the opening area A of the opening satisfy the following formula: It is characterized by forming.
(N-1) · d <h <n · d
A <S / n
Here, d is the diameter of the conductive particles, S is the surface area of the bump, and n is a natural number of 2 or more.
According to this configuration, the conductive particles stacked and arranged on the bump surface can be prevented from overflowing around the bump when the electronic component is mounted on the counterpart substrate. Therefore, even when a plurality of bumps are arranged at a narrow pitch, a short circuit between adjacent electrodes can be prevented.

Further, another electronic component manufacturing method of the present invention is a method for manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface, wherein bumps are formed on the surface of the electrode pad. A step of forming a mask having an opening on the surface of the bump on the active surface, a step of spraying conductive particles on the active surface to capture the opening, and a stacked arrangement in the opening Fixing the conductive particles formed on the surface of the bump, and the height h of the opening and the width B of the opening in the arrangement direction of the narrow pitch of the plurality of bumps are expressed by the following equation: The mask and the opening are formed so as to satisfy.
(N-1) · d <h <n · d
B <W / n
Here, d is the diameter of the conductive particles, W is the width of the bump in the arrangement direction of the narrow pitch of the plurality of bumps, and n is a natural number of 2 or more.
According to this configuration, it is possible to prevent the conductive particles stacked on the bump surface from overflowing in the bump arrangement direction when the electronic component is mounted on the counterpart substrate. Therefore, even when a plurality of bumps are arranged at a narrow pitch, a short circuit between the electrodes can be prevented. Even when the conductive particles overflow in the non-arrangement direction of the bumps, the short circuit between the electrodes does not cause a problem because the bumps are not arranged at a narrow pitch in that direction.

The n is preferably 2 or 3.
According to this structure, it becomes possible to make the width | variety of the some electroconductive particle laminated | stacked and arrange | positioned on the surface of a bump larger than the height, and can arrange | position electroconductive particle stably.

On the other hand, the electronic component of the present invention is manufactured using the above-described electronic component manufacturing method.
According to this configuration, when the electronic component is mounted on the counterpart substrate, a short circuit between the electrodes can be prevented.

Further, another electronic component of the present invention is an electronic component mounted on a mating substrate via an electrode pad formed on an active surface, wherein a bump is formed on the surface of the electrode pad, and the surface of the bump A plurality of conductive particles are laminated in a part of the structure.
According to this configuration, it is possible to prevent the conductive particles stacked and arranged on the surface of the bump from overflowing around the bump when the electronic component is mounted on the counterpart substrate. Therefore, even when a plurality of bumps are arranged at a narrow pitch, a short circuit between the electrodes can be prevented.

The part of the surface of the bump is preferably a central portion of the bump in the arrangement direction of the plurality of bumps.
According to this configuration, it is possible to reliably prevent the conductive particles stacked on the surface of the bump from overflowing around the bump when the electronic component is mounted on the counterpart substrate. Therefore, a short circuit between the electrodes can be reliably prevented.

On the other hand, the electro-optical device of the present invention is characterized in that the above-described electronic component is mounted on a substrate and / or a circuit board constituting the electro-optical panel.
According to this configuration, the electronic component described above can prevent a short circuit between the electrodes, so that an electro-optical device having excellent electrical connection reliability can be provided.

On the other hand, an electronic apparatus according to the present invention includes the above-described electro-optical device.
According to this configuration, it is possible to provide an electronic device having excellent electrical connection reliability.

  Embodiments of the present invention will be described below with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.

[Electronic components and their mounting structure]
FIG. 1A is an explanatory diagram of a semiconductor element and its mounting process, and FIG. 1B is an explanatory diagram of a semiconductor element mounting structure, both of which are front sectional views taken along line BB in FIG. is there. 6 and 1 are shown upside down. As shown in FIG. 1A, a plurality of electrode pads 42 made of a conductive material such as Al are formed at a predetermined pitch on the active surface of a semiconductor element (electronic component) 40 such as an IC. The peripheral portion of the electrode pad 42 is covered with an insulating film 48. Further, bumps 44 made of Au plating, Au / Ni plating, or the like are formed on the surface of each electrode pad 42. As an example, each bump 44 is formed with a width of about 30 μm, adjacent bumps 44 are arranged at intervals of about 10 μm, and the pitch of each bump is about 40 μm.

  Furthermore, a plurality of conductive particles 50 are arranged on the surface of each bump 44. The conductive particles 50 are obtained by performing solder coating, metal plating, or the like on the surface of a resin ball or the like. For this metal plating, electrolytic Au plating, electroless Ni plating, or the like can be employed. Further, electroless Ni plating may be applied to the base, and electroless Au plating may be applied to the top. The conductive particles 50 are formed with a diameter of about 4.5 μm, for example. A plurality of conductive particles 50 are stacked on a part of the surface of each bump 44. Specifically, the conductive particles 50 are stacked and arranged at the center of the bump 44 in the arrangement direction of the plurality of bumps 44 formed on the semiconductor element 40. When a plurality of bumps 44 are arranged in two directions (in a matrix), it is desirable to stack conductive particles 50 at the central part of the bumps 44 in both directions. In addition, when the plurality of bumps 44 are arranged at different pitches in two directions, the conductive particles 50 may be laminated and disposed only in the central portion of the bumps 44 in the narrow pitch arrangement direction.

  The conductive particles 50 described above are fixed to the surface of the bump 44 using a thermoplastic resin 52 such as polyamide as a fixing means. Since this polyamide is plasticized at a low temperature of about 150 to 200 ° C., it is excellent in workability and can suppress the thermal influence on the semiconductor element 40. It is possible to employ a thermosetting resin such as epoxy as a fixing means for the conductive particles 50. In particular, epoxy can be cured at a low temperature of about 150 to 200 ° C. Moreover, it is also possible to employ a photocurable resin such as acrylic as a fixing means for the conductive particles 50. In this case, the curable resin can be easily cured by irradiating light such as ultraviolet rays. Further, as a means for fixing the conductive particles 50, it is also possible to employ a low melting point metal such as indium (In), tin (Sn), or zinc (Zn), or an alloy containing solder. In this case, since the metal can be melted at a low temperature, the thermal influence on the semiconductor element 40 can be suppressed. In particular, tin (Sn) is suitable as the metal because it has good wettability and melts at a low temperature of about 230 ° C.

  On the other hand, a plurality of electrode pads 12 are formed on the surface of the counterpart substrate 10 on which the semiconductor element 40 described above is mounted so as to face the electrode pads 42 of the semiconductor element 40. For example, the electrode pad 12 is formed at the end of the data line 81 or the like of the glass substrate 80 (mating substrate 10) shown in FIG.

  Then, as shown in FIG. 1B, the tips of the conductive particles 50 fixed to the semiconductor element 40 come into contact with the surface of the electrode pad 12 of the counterpart substrate 10 and the signal electrodes of the counterpart substrate 10 The semiconductor element 40 is electrically connected. The conductive particles 50 stacked on a part of the surface of the bump 44 as described above are sandwiched between the electrode pad 42 of the semiconductor element 40 and the electrode pad 12 of the counterpart substrate 10, and 1 It has been relocated to the layer only. Further, a thermosetting resin layer 60 made of an epoxy resin or the like is disposed between the semiconductor element 40 and the counterpart substrate 10, and the semiconductor element 40 and the counterpart substrate 10 are mechanically connected. Note that the thermosetting resin layer 60 protects the active surface of the semiconductor element 40 and the electrical connection portions of the semiconductor element 40 and the counterpart substrate 10.

[Method of manufacturing electronic parts]
Next, a method for manufacturing the above-described semiconductor element will be described with reference to FIGS. 2 to 4 are explanatory views of a method for manufacturing a semiconductor device, and the active surface of the semiconductor device is shown upward. In the present embodiment, the following processing is simultaneously performed on a plurality of semiconductor elements formed on the wafer, and finally the semiconductor elements are separated from the wafer. Thereby, manufacturing cost can be reduced.

  First, as shown in FIG. 2A, a mask 20 for forming the bumps 44 is formed. The mask 20 is composed of a resist or the like. The resist 20 may be any of a photoresist, an electron beam resist, an X-ray resist, etc., and may be either a positive type or a negative type, but a resist having resistance to a plating solution described later is used. As such a resist 20, for example, a novolac resin can be used. Since the bumps 44 are formed on the electrode pads 42 on the active surface of the wafer 41, the mask 20 is formed in a region other than the region where the electrode pads 42 are formed. Therefore, first, the resist 20 is applied to the entire active surface of the semiconductor element. The resist 20 is applied by spin coating, dipping, spray coating, or the like. Here, the thickness of the resist 20 is set to be equal to or higher than the height of the bump 44 to be formed. Note that pre-baking is performed after the resist 20 is applied.

  Next, the planar shape of the bump 44 to be formed is patterned on the resist 20. Specifically, the opening 22 corresponding to the planar shape of the bump 44 is formed above the electrode pad 42 in the resist 20. The planar shape of the bump 44 is not limited to a rectangle, and may be a circle or the like. Patterning of the resist 20 is performed by first exposing the resist 20 using a photomask on which a predetermined pattern is formed, and developing the exposed resist 20. Note that post-baking is performed after the patterning of the resist 20.

  The method for forming the resist 20 using photolithography has been described above, but in addition to this, in a patterned state, for example, by using a dry film, or by using a printing method such as screen printing. A resist 20 can be formed. Alternatively, the resist 20 may be formed in a patterned state by discharging a droplet of a resist only to a position where the resist 20 is formed using a droplet discharge device such as an inkjet device. As a result, a photomask used for photolithography becomes unnecessary, and manufacturing costs can be reduced.

  Next, the bumps 44 are formed by filling the openings 22 with a conductive material using the resist 20 as a mask. The bumps 44 are formed by Au plating, Ni plating, or the like. Further, the base of the bump 44 may be formed by Ni plating, and the top may be formed by Au plating. As a plating method, for example, an electrochemical plating (ECP) method or the like can be used. Moreover, the electrode pad 42 can be used as an electrode in a plating method. Note that the bump 44 may be formed by filling the conductive material using a CVD method or a sputtering method other than the plating method.

  Next, as shown in FIG. 2B, the resist 20 is removed. The resist 20 is removed by immersing the wafer 41 in a resist stripping solution. As the resist stripping solution, it is possible to use a liquid in which monoethanolamine and dimethyl sulfoxide are mixed at a ratio of 7: 3.

Next, as shown in FIG. 2C, a mask 25 is formed in order to dispose the conductive particles on the surface of the bump 44. This mask 25 is formed of a resist or the like. Therefore, first, a resist is applied to the entire active surface of the wafer 41. The resist type and coating method are the same as described above.
Next, as shown in FIG. 2D, the opening 26 of the mask 25 is formed on the surface of the bump 44. The opening 26 is opened assuming the number of stacked conductive particles, which will be described in detail later. The method for forming the opening 26 is the same as described above.

  Next, as shown in FIG. 3A, conductive particles 50 are dispersed on the active surface of the wafer 41. The dispersed conductive particles 50 are dispersed and arranged above the mask 25, fall into the openings 26 formed in the mask 25, and are arranged above the bumps 44.

  Furthermore, it is desirable that the conductive particles 50 disposed above the mask 25 are dropped into the opening 26 by vibrating the wafer 41 so that more conductive particles are disposed above the bumps 44. Specifically, the wafer 41 is vibrated at a high frequency of 50 to 1000 Hz. In particular, when vibrated at a high frequency of 250 to 500 Hz, the conductive particles 50 move actively, so that more conductive particles can be disposed above the bumps 44. Further, the vibration direction of the wafer 41 may be a direction parallel to the active surface of the wafer 41 (horizontal direction) or a direction perpendicular to the active surface (vertical direction). In the case of horizontal vibration, the amplitude is preferably equal to or less than the pitch of the adjacent bumps 44, for example, about 40 μm. In the case of vertical vibration, the depth is preferably equal to or less than the depth of the opening 26, for example, about 10 μm. Thereby, it is possible to prevent the conductive particles 50 captured in the opening 26 from jumping out of the opening 26.

Further, the conductive particles 50 remaining above the mask 25 are removed. The removal of the conductive particles 50 is as follows. 1. a method for blowing conductive particles 50 by blowing gas on the active surface of the wafer 41; 2. a method of dropping the conductive particles 50 from the peripheral edge of the wafer 41 by vibrating the wafer 41; 3. a method of dropping the conductive particles 50 from the peripheral portion of the wafer 41 by vibrating the wafer 41 while tilting; There is a method of forcibly removing the conductive particles 50 by scraping the conductive particles 50 using a flat plate squeegee having flexibility, and any method may be adopted. Thereby, most of the conductive particles 50 remaining on the surface of the mask 25 can be removed. Further, it is possible to capture some of the conductive particles in the opening while removing the conductive particles 50 remaining on the surface of the mask 25. Therefore, more conductive particles 50 can be disposed on the surface of the bump 44.
In the previous step, the wafer 41 was vibrated to drop the conductive particles 50 into the opening 26, but the amplitude was gradually increased. Or 3. You may implement the method of. Thereby, a manufacturing process can be simplified.

  As will be described later, the height of the opening 26 is formed to be equal to or larger than the diameter of the conductive particles 50. Therefore, the conductive particles 50 above the bumps 44 are stably captured in the openings 26. Therefore, when any of the above-described removal methods is adopted, it is possible to remove only the conductive particles 50 disposed above the mask 25, and the conductive particles 50 disposed above the bumps 44 are simultaneously removed. There is little risk of being removed. As described above, when most of the conductive particles 50 remaining above the mask 25 are removed, the state shown in FIG.

  Next, as shown in FIG. 3B, a thermoplastic resin solution is applied to the surface of the bump 44 to form a thermoplastic resin film 52. Specifically, a thermoplastic resin solution in which a thermoplastic resin such as polyamide is dissolved in a solvent such as toluene / ethanol is prepared, and this is applied onto the active surface of the wafer 41. The thermoplastic resin solution can be applied by a dispensing method, a spray coating method, a spin coating method, a dipping method, or the like. Next, the applied thermoplastic resin solution is dried to evaporate the solvent. Then, the thermoplastic resin dissolved in the solvent is condensed, and the thermoplastic resin film 52 is formed. Thereby, the conductive particles 50 are fixed to the surface of the bump 44.

Here, it is desirable to apply the thermoplastic resin solution so that the thickness t of the formed thermoplastic resin film satisfies the following formula.
h−d <t <h
Here, h is the height of the opening 26, and d is the diameter of the conductive particles 50. As a result, all of the conductive particles 50 arranged inside the opening 26 can be fixed to the surface of the bump 44 by the thermoplastic resin film 52.

  In the above-described method for applying the thermoplastic resin solution, since the thermoplastic resin solution is applied to the surface of the mask 25 in addition to the surface of the bump 44, the thermoplastic resin film 52 is also formed on the surface of the mask 25. Will be. In this regard, according to a droplet discharge device such as an inkjet device, a certain amount of thermoplastic resin solution can be discharged only to the surface of the bump 44. As a result, it is possible to make the conductive particles 50 fixed to the surface of the bump 44 uniform, and the semiconductor element and the counterpart substrate can be reliably electrically connected. In addition, the consumption of the thermoplastic resin solution can be reduced, and the manufacturing cost can be reduced.

In addition, if a liquid repellency is given to the surface of the mask 25 in advance before the step of applying the thermoplastic resin solution, the thermoplastic resin solution can be applied only to the surface of the bump 44. As a method for imparting liquid repellency to the surface of the mask 25, for example, a CF ₄ plasma treatment method in which plasma treatment is performed in an air atmosphere using tetrafluoromethane as a treatment gas can be employed. In addition, a fluororesin film may be formed on the surface of the mask 25 in advance before forming the opening 26 in the mask 25.

Next, as shown in FIG. 3C, the mask 25 is removed. The mask 25 is removed by immersing the wafer 41 in a resist stripping solution. As the resist stripping solution, it is possible to use a liquid in which monoethanolamine and dimethyl sulfoxide are mixed at a ratio of 7: 3. When removing the mask 25, the thermoplastic resin film formed above the mask 25 is also removed. In addition, since the mask 25 is peeled after removing the conductive particles dispersed above the mask 25, the removed conductive particles can be reused. Thereby, all of the expensive conductive particles can be used for electrical connection without wastefully discarding them.
Next, the semiconductor element is separated from the wafer 41 by dicing or the like. As described above, as shown in FIG. 1A, the semiconductor element 40 of the present embodiment is formed.

[Electronic component mounting method]
Next, returning to FIG. 1, a method for mounting a semiconductor device according to the present embodiment will be described.
First, as shown in FIG. 1A, a thermosetting resin layer 60 is formed on the surface of the counterpart substrate 10. The thermosetting resin layer 60 is formed by attaching an uncured epoxy resin film. The thermosetting resin layer 60 may be formed by applying an uncured epoxy resin paste to the surface of the counterpart substrate 10. Further, the thermosetting resin layer 60 may be formed on the active surface of the semiconductor element 40. In this case, after forming the thermosetting resin layer 60 on the active surface of the wafer, the semiconductor element 40 is separated from the wafer. Furthermore, after the semiconductor element 40 is mounted on the counterpart substrate 10, the thermosetting resin layer 60 may be formed by filling the gap between the semiconductor element 40 and the counterpart substrate 10 with an underfill. Note that in any case, unlike the anisotropic conductive film (ACF), the thermosetting resin layer 60 does not contain conductive particles.

  Then, the semiconductor element 40 formed as described above is turned upside down and disposed above the counterpart substrate 10. At this time, the semiconductor element 40 and the counterpart substrate 10 are arranged so that the bumps 44 formed on the semiconductor element 40 and the electrode pads 12 formed on the counterpart substrate 10 face each other.

  Next, as shown in FIG. 1B, the semiconductor element 40 is pressed against the surface of the counterpart substrate 10 and is pressurized. As a result, the conductive particles 50 fixed on the bumps 44 of the semiconductor element 40 come into contact with the electrode pads 12 of the counterpart substrate 10 and are electrically connected. In this state, the thermosetting resin layer 60 is heated. The heating temperature is 200 ° C., for example. In addition, you may heat the thermosetting resin layer 60 simultaneously with the pressurization of the semiconductor element 40 to the other party board | substrate 10. FIG. Thereby, the thermosetting resin layer 60 is cured and the semiconductor element 40 and the counterpart substrate 10 are mechanically connected. In addition, the electrical connection between the semiconductor element 40 and the counterpart substrate 10 is protected.

  Note that the thermoplastic resin film 52 in which the conductive particles 50 are fixed to the bumps is softened at about 150 ° C. Since the semiconductor element 40 is pressed against the mating substrate 10, the conductive particles 50 stacked on the surface of the bump 44 are sandwiched between the electrode pads 12 of the mating substrate 10 and 1. Rearranged in layers. Further, even when the thermoplastic resin film 52 is interposed between the surface of the bump 44 and the conductive particles 50, the thermoplastic resin film 52 is softened, so that the surface of the bump 44 and the conductive particles 50 are bonded to each other. Can be contacted. Further, even when the thermoplastic resin film 52 is interposed between the conductive particles 50 and the electrode pad 12 of the counterpart substrate 10, the thermoplastic resin film 52 is softened. 12 can be brought into contact with each other. Therefore, the semiconductor element 40 and the counterpart substrate 10 can be reliably electrically connected. As described above, the semiconductor element 40 is mounted on the counterpart substrate 10.

  In recent years, with the miniaturization of electronic components, the pitch between electrode pads has been reduced. Even in that case, since the thermosetting resin layer 60 does not contain conductive particles, there is no possibility that adjacent electrode pads are short-circuited to each other. In addition, since the conductive particles are fixed on the surface of the bump 44 before mounting, the electrical connection can be reliably performed even if the electrode pad itself is reduced.

(Shape of mask opening)
Here, the shape of the opening 26 formed in the mask 25 in FIG. 2D will be described with reference to FIG.
FIG. 4 is an explanatory diagram of the shape of the opening of the mask. FIG. 4A shows a case where conductive particles are arranged in two layers, and FIG. 4B shows a case where conductive particles are arranged in three layers. Is the case. Hereinafter, the layer of the conductive particles 50 disposed on the surface of the bump 44 is referred to as a first layer, and the layers of the conductive particles 50 disposed above the first layer are sequentially arranged as a second layer and a third layer. , ... called the nth layer. Note that n is a natural number.

The shape of the opening 26 is determined assuming the number of stacked conductive particles 50 on the surface of the bump 44. As shown in FIG. 4, when the conductive particles 50 are stacked in the n layer, the mask 25 is formed so that the height h from the surface of the bump 44 to the surface of the mask 25 satisfies the following formula. That's fine.
(N-1) · d <h <n · d (1)
Where d is the diameter of the conductive particles 50.
In this case, the opening 26 is formed in the mask 25 so that the opening area A of the opening 26 satisfies the following expression.
A <S / n (2)
Here, S is the area of the surface of the bump 44.

The meanings of the mathematical formulas (1) and (2) will be described with reference to FIG. 4A, taking as an example the case where the conductive particles 50 are stacked in two layers (that is, n = 2).
As described above, the present embodiment includes a step of removing the conductive particles 50 arranged on the surface of the mask 25 after the conductive particles 50 are dispersed on the active surface of the wafer. The conductive particles 50 are removed by a method of scraping the surface of the mask 25 using a squeegee. Here, the height h from the surface of the bump 44 to the surface of the mask 25 is
d <h <2d (3)
If the mask 25 is formed so as to satisfy the condition, the conductive particles 50 arranged in the first layer and the second layer are not removed while being captured by the opening 26. This mathematical formula (3) matches when n = 2 is substituted into the mathematical formula (1). Therefore, the conductive particles 50 can be stacked in two layers above the bumps 44.

However, when the semiconductor element is mounted on the counterpart substrate, the conductive particles 50 stacked on the surface of the bump 44 are sandwiched between the electrode pads of the counterpart substrate and rearranged in one layer. The surplus conductive particles 50 may overflow around the bumps 44 and short-circuit between adjacent bumps 44. Therefore, in order to prevent the conductive particles 50 from overflowing around the bumps 44, the conductive particles 50 are laminated and disposed only on a part of the surface of the bumps 44.
FIG. 5A is a plan view of the semiconductor element. In the present embodiment, conductive particles are laminated and disposed only on the central portion 50 a of the surface of the bump 44. Thereby, it is possible to reliably prevent the conductive particles from overflowing around the bumps 44.

And the opening part 26 of the mask 25 shown to Fig.4 (a) is formed so that arrangement | positioning of the above electroconductive particle may be implement | achieved. When the conductive particles 50 stacked in two layers are rearranged in one layer, the area occupied by the conductive particles 50 on the surface of the bump 44 is doubled. The area occupied by the conductive particles 50 on the surface of the bump 44 depends on the opening area of the opening 26 of the mask 25. Therefore, the opening area A of the opening 26 is related to the area S of the upper surface of the bump 44.
A <S / 2 (4)
The opening 26 is formed so as to satisfy the above. This equation (4) matches when n = 2 is substituted into equation (2). As a result, even if the conductive particles 50 stacked in two layers are rearranged in one layer, the area occupied by the conductive particles 50 does not exceed the area of the surface of the bump 44. Therefore, it is possible to prevent the conductive particles from overflowing around the bumps 44 when the semiconductor element is mounted on the counterpart substrate.

On the other hand, as shown in FIG. 4B, when the conductive particles 50 are stacked in three layers, the height h from the surface of the bump 44 to the surface of the mask 25 and the opening area A of the opening 26 are shown. The mask 25 and the opening 26 are formed so that the following equation is satisfied.
2d <h <3d (5)
A <S / 3 (6)
Equations (5) and (6) match when n = 3 is substituted into Equations (1) and (2).

  A case where the conductive particles 50 are stacked in four or more layers is also conceivable. However, as described above, since the width of the bumps 44 is as narrow as 30 μm, for example, when the conductive particles 50 are stacked in four or more layers while satisfying the formulas (1) and (2), the layers are stacked. The width of the plurality of conductive particles 50 becomes smaller than the height and becomes unstable. Therefore, it is desirable that the conductive particles 50 are laminated in two or three layers (that is, n = 2 or n = 3).

  As described in detail above, in the method of manufacturing an electronic component according to the present embodiment, the mask and the opening are formed so as to satisfy Equation (1) and Equation (2), and the conductive particles are stacked on the bump surface. The configuration. According to this configuration, the conductive particles stacked on the bump surface can be prevented from overflowing around the bump even if the conductive particles are rearranged in one layer when the semiconductor element is mounted on the counterpart substrate. it can. Therefore, even when a plurality of bumps are arranged at a narrow pitch, a short circuit between the bumps can be prevented.

  In addition, since the conductive particles can be prevented from overflowing around the bumps, all the conductive particles can be used for electrical connection between the semiconductor element and the counterpart substrate. Thereby, expensive conductive particles are not wasted, and the manufacturing cost can be reduced. Furthermore, since all the conductive particles can be used for electrical connection, the electrical resistance between the bumps of the semiconductor element and the electrode pads of the counterpart substrate is reduced, reducing the power consumption of the liquid crystal module. Can do.

  When an anisotropic conductive film (ACF) is arranged between the semiconductor element and the counterpart substrate, the number of conductive particles arranged between the bump of the semiconductor element and the electrode pad of the counterpart substrate Is about 10-20. In order to dispose more conductive particles than this, it is necessary to increase the density of the conductive particles contained in the ACF, but there is a high possibility that adjacent electrode pads are short-circuited to each other. On the other hand, if a semiconductor element is manufactured using the method for manufacturing an electronic component according to this embodiment, a large number of conductive particles can be arranged on the surface of the bump. For example, it is possible to dispose conductive particles on 80% or more of the surface area of the bump. Thereby, the electrical resistance between the bump of the semiconductor element and the electrode pad of the counterpart substrate is reduced, and the power consumption of the liquid crystal module can be reduced. Even in this case, as described above, there is no possibility that adjacent electrode pads short-circuit each other.

[Modification]
FIG. 5B is an explanatory diagram of a modification of the present embodiment. In the present embodiment described above, as shown in FIG. 5A, conductive particles are stacked and arranged at the central portion 50 a on the surface of the bump 44. However, as shown in FIG. 5B, when a plurality of bumps 44 are arranged at a narrow pitch in the X direction and are arranged at a wide interval in the Y direction, a short circuit between the bumps in the X direction. Only matters. Therefore, conductive particles may be laminated and disposed in the central portion 50 b of the bump 44 in the narrow pitch arrangement direction (X direction) of the bump 44. In this case, with respect to the non-arrangement direction (Y direction) of the bumps 44, conductive particles are laminated and arranged in the same width as the bumps 44.

Therefore, the width B in the X direction at the opening 26 of the mask 25 shown in FIG. 4 is related to the width W in the X direction of the bump 44.
B <W / n (7)
The opening 26 is formed so as to satisfy the above. That is, by forming the mask 25 and the opening 26 so as to satisfy the expressions (1) and (7) at the same time, the arrangement of the conductive particles as in the present modification can be realized.

  And according to this modification, even if the conductive particles laminated on the bump surface are rearranged in one layer when the semiconductor element is mounted on the counterpart substrate, the arrangement direction of the narrow pitch of the plurality of bumps It is possible to prevent overflowing in the (X direction). Therefore, even when the bumps are arranged at a narrow pitch, a short circuit between the bumps can be prevented. Even if the conductive particles overflow in the non-arrangement direction (Y direction) of the bumps, the bumps are not arranged in a narrow pitch in that direction, so that a short circuit between the bumps is not a problem.

  When a plurality of bumps 44 are arranged in two directions (in a matrix) at a narrow pitch, conductive particles 50 are stacked and arranged at the center of the bumps 44 in both directions. In this case, as shown in FIG. 5A, conductive particles are stacked and disposed in the central portion 50a of the bump 44. When a plurality of bumps 44 are arranged at different pitches in two directions, conductive particles may be laminated and arranged only at the center of the bumps 44 in the narrow pitch arrangement direction. For example, in the case where a plurality of bumps 44 are arranged at a narrow pitch in the X direction in FIG. 5B, conductive particles may be stacked and disposed at the central portion 50b of the bump 44 in the X direction.

[Electro-optical device]
Next, a liquid crystal module which is an example of an electro-optical device on which the semiconductor element is mounted will be described with reference to FIGS.
FIG. 6 is an exploded perspective view of the liquid crystal module. The liquid crystal module 1 shown in FIG. 6 mainly includes a liquid crystal panel 90 that displays a color image, and a driving semiconductor element 40 of the liquid crystal panel 90 that is mounted on the upper substrate 80 (the counterpart substrate 10) of the liquid crystal panel 90. ing.

  FIG. 7 is an exploded perspective view of the liquid crystal panel, and FIG. 8 is a side sectional view taken along line AA of FIG. As shown in FIG. 8, the liquid crystal panel 90 is configured by sandwiching a liquid crystal layer 92 between a lower substrate 70 and an upper substrate 80. A nematic liquid crystal or the like is employed for the liquid crystal layer 92, and a twisted nematic (TN) mode is employed as an operation mode of the liquid crystal panel 90. Note that liquid crystal materials other than those described above can be employed, and operation modes other than those described above can be employed. Hereinafter, an active matrix type liquid crystal panel using a TFD element as a switching element will be described as an example. However, the present invention is applied to other active matrix type liquid crystal panels and passive matrix type liquid crystal panels. Is also possible.

As shown in FIG. 7, in the liquid crystal panel 90, a lower substrate 70 and an upper substrate 80 made of a transparent material such as glass are disposed to face each other.
A plurality of data lines 81 are formed inside the upper substrate 80. A plurality of pixel electrodes 82 made of a transparent conductive material such as ITO are arranged in a matrix on the side of the data line 81. Note that a pixel region is constituted by the formation region of each pixel electrode 82. The pixel electrode 82 is connected to each data line 81 via the TFD element 83. The TFD element 83 includes a first conductive film mainly composed of Ta formed on the surface of the substrate, an insulating film mainly composed of Ta ₂ O ₃ formed on the surface of the first conductive film, and an insulation thereof. A second conductive film mainly composed of Cr formed on the surface of the film (so-called MIM structure). The first conductive film is connected to the data line 81 and the second conductive film is connected to the pixel electrode 82. Accordingly, the TFD element 83 functions as a switching element that controls energization to the pixel electrode 82.

  On the other hand, a color filter film 76 is formed inside the lower substrate 70. The color filter film 76 is composed of color filters 76R, 76G, and 76B having a substantially rectangular shape in plan view. Each of the color filters 76R, 76G, and 76B is made of a pigment that transmits only different color light, and is arranged in a matrix corresponding to each pixel region. Further, in order to prevent light leakage from adjacent pixel regions, a light shielding film 77 is formed on the peripheral edge of each color filter. The light shielding film 77 is formed in a frame shape from black metal chrome having light absorptivity. Further, a transparent insulating film 79 is formed so as to cover the color filter film 76 and the light shielding film 77.

  A plurality of scanning lines 72 are formed inside the insulating film 79. The scanning line 72 is formed in a substantially strip shape by a transparent conductive material such as ITO and extends in a direction intersecting the data line 81 of the upper substrate 80. The scanning line 72 is formed so as to cover the color filters 76R, 76G, and 76B arranged in the extending direction, and functions as a counter electrode. When a scanning signal is supplied to the scanning line 72 and a data signal is supplied to the data line 81, an electric field is applied to the liquid crystal layer by the opposing pixel electrode 82 and the opposing electrode 72.

  Further, as shown in FIG. 8, alignment films 74 and 84 are formed so as to cover the pixel electrode 82 and the counter electrode 72. The alignment films 74 and 84 control the alignment state of the liquid crystal molecules when no electric field is applied, and are made of an organic polymer material such as polyimide, and the surface thereof is rubbed. As a result, when no electric field is applied, the liquid crystal molecules in the vicinity of the surfaces of the alignment films 74 and 84 are aligned substantially parallel to the alignment films 74 and 84 with the major axis direction coinciding with the rubbing treatment direction. . The alignment films 74 and 84 are rubbed so that the alignment direction of the liquid crystal molecules near the surface of the alignment film 74 and the alignment direction of the liquid crystal molecules near the surface of the alignment film 84 are shifted by a predetermined angle. Has been. Thereby, the liquid crystal molecules constituting the liquid crystal layer 92 are spirally stacked along the thickness direction of the liquid crystal layer 92.

Further, the peripheral portions of the substrates 70 and 80 are joined by a sealing material 93 made of an adhesive such as a thermosetting type or an ultraviolet curable type. A liquid crystal layer 92 is sealed in a space surrounded by the substrates 70 and 80 and the sealing material 93. Note that the thickness (cell gap) of the liquid crystal layer 92 is regulated by the spacer particles 95 arranged between the two substrates.
On the other hand, a polarizing plate (not shown) is disposed outside the lower substrate 70 and the upper substrate 80. Each polarizing plate is arranged in a state in which the mutual polarization axes (transmission axes) are shifted by a predetermined angle. Further, a backlight (not shown) is disposed outside the incident side polarizing plate.

The light emitted from the backlight is converted into linearly polarized light along the polarization axis of the incident-side polarizing plate and enters the liquid crystal layer 92 from the lower substrate 70. This linearly polarized light is rotated by a predetermined angle along the twist direction of the liquid crystal molecules in the process of passing through the liquid crystal layer 92 in a state where no electric field is applied, and is transmitted through the output side polarizing plate. Thereby, white display is performed when no electric field is applied (normally white mode). On the other hand, when an electric field is applied to the liquid crystal layer 92, the liquid crystal molecules are reoriented perpendicularly to the alignment films 74 and 84 along the electric field direction. In this case, the linearly polarized light incident on the liquid crystal layer 92 does not rotate, and therefore does not pass through the output side polarizing plate. Thereby, black display is performed when no electric field is applied. Note that gradation display can also be performed depending on the strength of an applied electric field.
The liquid crystal panel 90 is configured as described above.

  Returning to FIG. 6, a protruding portion 80 a from the lower substrate 70 is formed on one side of the upper substrate 80 constituting the liquid crystal panel 90. A data line 81 is routed from the upper substrate 80 and a scanning line 72 is routed from the lower substrate 70 to the projecting portion 80a, and the above-described electrode pads (not shown) are formed at these end portions. And the semiconductor element 40 of this embodiment is mounted through the thermosetting resin layer 60 mentioned above with respect to the electrode pad. The semiconductor element 40 controls the energization of the data lines 81 and the scanning lines 72 of the liquid crystal panel 90 and drives each pixel of the liquid crystal panel 90 to display an image.

  Although the case where the present invention is applied to COG (Chip On Grass) in which the semiconductor element 40 is mounted on the glass substrate 10 has been described above, the COF (mounting semiconductor element 40 on a flexible printed circuit board made of polyimide or the like) It is also possible to apply the present invention to (Chip On Film). In this case, the FPC is mounted on the protruding portion 80a of the upper substrate 80 of the liquid crystal panel 90 via an anisotropic conductive film (ACF) or the like.

[Electronics]
FIG. 9 is a perspective view showing an example of an electronic apparatus according to the present invention. A cellular phone 1300 shown in the figure includes the above-described electro-optical device as a small-sized display unit 1301 and includes a plurality of operation buttons 1302, a mouthpiece 1303, and a mouthpiece 1304.
The above-described electro-optical device is not limited to the above mobile phone, but an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, It can be suitably used as an image display means for a word processor, a workstation, a videophone, a POS terminal, a device equipped with a touch panel, etc., and in any case, an electronic device having excellent electrical connection reliability can be provided. it can.

  The technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. That is, the specific materials and configurations described in the embodiments are merely examples, and can be changed as appropriate.

It is explanatory drawing of the semiconductor element which concerns on embodiment, and its mounting structure. It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on embodiment. It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on embodiment. It is explanatory drawing of the manufacturing method of the semiconductor element which concerns on embodiment. It is explanatory drawing of the opening part shape of a mask. It is a disassembled perspective view of a liquid crystal module. It is a disassembled perspective view of a liquid crystal panel. It is side surface sectional drawing of a liquid crystal panel. It is a perspective view of a mobile phone. It is explanatory drawing of the mounting method of the semiconductor element which concerns on a prior art.

Explanation of symbols

  25 masks 26 openings 44 bumps 50 conductive particles

Claims (2)

A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a bump on the surface of the electrode pad; forming a mask having an opening on the surface of the bump on the active surface; and spraying conductive particles on the active surface to capture the opening. And a step of fixing the conductive particles stacked and arranged in the opening to the surface of the bump,
The method of manufacturing an electronic component, wherein the mask and the opening are formed so that a height h and an opening area A of the opening satisfy the following expression.
(N-1) · d <h <n · d
A <S / n
Here, d is the diameter of the conductive particles, S is the surface area of the bump, and n is 2 or 3 . A method of manufacturing an electronic component mounted on a counterpart substrate via an electrode pad formed on an active surface,
Forming a bump on the surface of the electrode pad; forming a mask having an opening on the surface of the bump on the active surface; and spraying conductive particles on the active surface to capture the opening. And a step of fixing the conductive particles stacked and arranged in the opening to the surface of the bump,
The mask and the opening are formed so that the height h of the opening and the width B of the opening in a narrow pitch arrangement direction of the plurality of bumps satisfy the following expression: Production method.
(N-1) · d <h <n · d
B <W / n
Here, d is the diameter of the conductive particles, W is the width of the bump in the narrow pitch arrangement direction of the bumps, and n is 2 or 3 .

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