WO2007135906A1 - Procédé de gravure à sec d'un film intermédiaire isolant - Google Patents

Procédé de gravure à sec d'un film intermédiaire isolant Download PDF

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Publication number
WO2007135906A1
WO2007135906A1 PCT/JP2007/060010 JP2007060010W WO2007135906A1 WO 2007135906 A1 WO2007135906 A1 WO 2007135906A1 JP 2007060010 W JP2007060010 W JP 2007060010W WO 2007135906 A1 WO2007135906 A1 WO 2007135906A1
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WO
WIPO (PCT)
Prior art keywords
gas
etching
interlayer insulating
insulating film
dry etching
Prior art date
Application number
PCT/JP2007/060010
Other languages
English (en)
Japanese (ja)
Inventor
Yasuhiro Morikawa
Koukou Suu
Original Assignee
Ulvac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac, Inc. filed Critical Ulvac, Inc.
Priority to KR1020087028192A priority Critical patent/KR101190137B1/ko
Priority to CN2007800189986A priority patent/CN101454878B/zh
Priority to DE112007001243.9T priority patent/DE112007001243B4/de
Priority to US12/301,786 priority patent/US20100219158A1/en
Priority to JP2008516618A priority patent/JP4950188B2/ja
Publication of WO2007135906A1 publication Critical patent/WO2007135906A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Definitions

  • the present invention relates to a method for dry etching an interlayer insulating film.
  • the material of the interlayer insulation film that solves the problem of wiring delay is SiO to low dielectric constant material (low
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-72518 (Description of paragraph (0005), etc.)
  • ArF resist materials generally have poor plasma resistance, and therefore are easily damaged and deformed during plasma etching as the exposure pattern becomes finer. This deformation is directly transferred to the low dielectric constant film under the resist by etching, so that it is easy for roughness such as striations to occur at the edges of the grooves microfabricated in the low dielectric constant film. Problems arise.
  • an object of the present invention is to solve the above-mentioned problems of the prior art and provide a dry etching method for an interlayer insulating film without causing resist damage.
  • the dry etching method for an interlayer insulating film of the present invention is an interlayer insulating film that finely processes an interlayer insulating film while forming a polymer film on an ArF resist or KrF resist provided on the interlayer insulating film by an etching gas.
  • a dry etching method for film wherein the etching gas is introduced at a pressure of less 0. 5 Pa, the peak of C-F bond in the vicinity of 1200 cm _1, 160 OCM near to the C-N bond _1 peaks and 3300cm around _1 C—H bond peak (Furi Etching while forming a polymer film having a spectrum measured by a conversion infrared spectrophotometer.
  • the etching gas is preferably an etching gas obtained by mixing a CF-based gas, an N-containing gas, and a lower hydrocarbon gas.
  • etching gases it is possible to form a polymer film having a C—F bond peak, a CN bond peak, and a CH bond peak, reducing resist damage, and having a low dielectric constant. It is possible to etch the film without etching stop.
  • the etching gas is preferably an etching gas in which CFHF gas and N-containing gas are mixed. Even if these etching gases are used, it is possible to form a polymer film having a C—F bond peak, a CN bond peak, and a CH bond peak, reducing resist damage, and reducing the dielectric constant film. It is possible to etch without etching stop.
  • the CF gas is a small amount selected from CF, C F, C F, C F, C F and C F I gas.
  • the lower hydrocarbon is preferably CH, C H, C H, C H, or C H.
  • the C F H gas is preferably CHF gas! /.
  • the N-containing gas is selected from nitrogen gas, NO, NH, methylamine, and dimethylamine.
  • At least one gas Preferably at least one gas.
  • the CFI gas is preferably CFI gas or CFI gas.
  • the interlayer is preferably CFI gas or CFI gas.
  • the insulating film also has a SiOCH material strength.
  • resist damage is reduced by etching under low pressure, As a result, when the etching becomes possible with a small amount of striation, an excellent effect is obtained.
  • resist damage can be reduced by the polymer film, so that etching with a high selectivity can be achieved.
  • FIG. 1 shows an etching apparatus 1 used in the dry etching method for an interlayer insulating film of the present invention.
  • 1 includes a vacuum chamber 11 that enables etching with low-temperature, high-density plasma.
  • the vacuum chamber 11 is equipped with a vacuum exhaust means 12 such as a turbo molecular pump.
  • the vacuum chamber 11 is composed of a lower substrate processing chamber 13 and an upper plasma generation chamber 14.
  • a substrate placement unit 2 is provided in the center of the bottom of the substrate processing chamber 13.
  • the substrate platform 2 includes a substrate electrode 21 on which the processing substrate S is placed, an insulator 22, and a support base 23.
  • the substrate electrode 21 and the support base 23 are provided via the insulator 22. ing.
  • the substrate electrode 21 is connected to the first high-frequency power source 25 via the blocking capacitor 24, and becomes a floating electrode in terms of potential and has a negative noise potential.
  • the top plate 31 provided on the upper part of the plasma generation chamber 14 facing the substrate platform 2 is fixed to the side wall of the plasma generation chamber 14 and connected to the second high-frequency power source 33 via the variable capacitor 32.
  • the counter electrode is formed in a floating state in terms of potential.
  • a gas introduction path 41 of a gas introduction means 4 for introducing an etching gas into the vacuum chamber 11 is connected to the top plate 31.
  • This gas introduction path 41 is connected to a gas source 43 via a gas flow rate control means 42.
  • the number of gas sources 43 shown in only one gas introduction path is appropriately determined according to the number of gas types used for etching. In this case, the number of gas sources 43 is adjusted according to the number of gas sources 43.
  • the gas introduction path 41 may be branched into two or more.
  • the plasma generation chamber 14 includes a cylindrical dielectric side wall, and a magnetic field coil 51 as a magnetic field generation means may be provided outside the side wall.
  • An annular magnetic neutral line (not shown) is formed in the plasma generation chamber 14.
  • a high frequency antenna coil 52 for generating plasma is arranged between the magnetic field coil 51 and the outside of the side wall of the plasma generation chamber 14.
  • This high frequency antenna coil 52 is parallel It has an antenna structure, and is connected to a branch point 34 provided in the feeding path between the variable capacitor 32 and the second high-frequency power source 33 described above, so that a voltage can be applied from the second high-frequency power source 33. Yes.
  • a magnetic neutral line is formed by the magnetic field coil 51, an alternating electric field is applied along the formed magnetic neutral line to generate discharge plasma on the magnetic neutral line.
  • a voltage is applied to the antenna coil 52 from the second high-frequency power source 33.
  • a third high-frequency power source is prepared without providing a branch path, and this is connected to the antenna coil 52. Connection may be made to generate plasma. Also, a mechanism is provided so that the voltage applied to the antenna coil becomes a predetermined value.
  • the interlayer insulating film formed on the substrate S in the present invention is a film made of a low dielectric constant material (low-k material).
  • a SiOCH material such as H SQ or MSQ that can be formed by application such as spin coating is used.
  • This material may be a porous material.
  • SiOCH material examples include, for example, trade name LKD5109r5 (manufactured by JSR), trade name HSG-7000 (manufactured by Hitachi Chemical Co., Ltd.), trade name HOSP (manufactured by Honeywell Electric Materials), trade name Nan oglass (Honeywell Electric Materials), product name OCD T-12 (manufactured by Tokyo Ohka Co., Ltd.), product name OCD ⁇ -32 (manufactured by Tokyo Ohka Kogyo Co., Ltd.), product name IPS 2.4 (manufactured by Catalyst Kasei Kogyo Co., Ltd.), product name IPS 2.2 (catalyst) Kasei Kogyo Co., Ltd.), trade name ALCAP-S 5100 (Asahi Kasei Co., Ltd.), trade name ISM (ULVAC, Inc.) and the like can be used.
  • a predetermined pattern is formed by photolithography.
  • a known KrF resist material for example, KrFM78 Y: manufactured by JSR Corporation
  • a known ArF resist material for example, UV-II
  • SiOCH-based material is used as the interlayer insulating film
  • a BARC antireflection film
  • a resist material may be applied thereon!
  • the substrate S on which the film is formed in this way is placed on the substrate electrode 21 in the vacuum chamber 11, and an etching gas is introduced from the etching gas introducing means 4, and the second high frequency power source 33 is used.
  • the etching gas is introduced into the vacuum chamber 11 under an operating pressure of 0.5 Pa or less, more preferably 0.1 to 0.5 Pa, capable of suppressing radical reaction.
  • the etching gas used in the etching method of the present invention is a gas that can etch the interlayer insulating film without etching stop and can form a predetermined polymer film on the resist during the etching.
  • an etching gas there is an etching gas in which a CF-based gas, an N-containing gas, and a lower hydrocarbon gas are mixed.
  • CF-based gas contributes to SiO etching among the constituents of the interlayer insulating film
  • N-containing gas contributes to CH etching
  • lower hydrocarbon gas also contributes to CH etching.
  • These mixed gases contribute to suppression of resist damage.
  • CFI gas containing iodine may be used as CF-based gas.
  • CFI gas examples include CFI and CFI.
  • I is the gas phase
  • the lower hydrocarbon is preferably a straight chain, such as CH, CH, CH, CH, or CH.
  • N-containing gases include nitrogen gas, NO, NH, methylamine, dimethylamine, etc.
  • etching gas there is an etching gas in which a CFHF gas and an N-containing gas are mixed.
  • the action of each gas is the same as that of the above three mixed gases.
  • An example of C F H gas is CHF.
  • N-containing gas includes nitrogen gas, NO
  • etching gas is not supplemented with a rare gas selected from helium, neon, argon, krypton, and xenon force as a diluent gas for reducing resist damage.
  • the predetermined polymer film is a nitrogen-containing CF-based polymer in which the constituent components F, N, and H in the etching gas are bonded to C in the etching gas.
  • CF-based gas containing iodine When CF-based gas containing iodine is used, a CF-based polymer film further containing iodine is formed.
  • the CF-based gas is preferably introduced at about 20 to 40%, more preferably about 20 to 30%, based on the total flow rate of the etching gas.
  • C F H gas is preferably introduced at about 20 to 40%, more preferably about 30 to 40%, based on the total etching gas flow rate.
  • CF gas flow rate of 60sccm (flow rate) was set at a pressure of 3mTorr, antenna power of 2200W, bias power of OW, Tc (substrate set temperature) of 10 ° C.
  • a polymer film was deposited on top, and the FT-IR ⁇ vector of this polymer film was measured with a Fourier transform infrared spectrophotometer.
  • N gas flow rate 90 sccm
  • CH gas flow rate 70 sccm
  • the etching gas used in the present invention is compared.
  • the polymer film has a C—N bond peak (1600 cm
  • the polymer film formed by the etching gas used in the etching of the present invention has a C—N bond, a C—F bond, and a C—H bond.
  • an SiOCH film was formed by plasma CVD as an interlayer insulating film on a substrate S made of silicon, and then an organic film was formed by spin coating as BARC.
  • UV-II was applied as an ArF resist to a film thickness of 430 nm, and a predetermined pattern was formed by photolithography.
  • the substrate on which these films are formed is placed on the substrate electrode 21 of the etching apparatus 1 shown in FIG. 1. First, from the CF gas (flow rate 25 sccm) and the CHF gas (flow rate 25 sccm) to which the BARC should be etched.
  • Etching apparatus 1 is set to the conditions of high frequency power supply on antenna side: 2200W, high frequency power supply on substrate side: 100W, substrate set temperature: 10 ° C, pressure lOmTorr, plasma is generated, and BARC is etched. did. Next, CF gas (flow rate 60sccm), N gas (
  • the ring device 1 the antenna-side RF power: 2200W, the substrate-side high-frequency power supply: 100W, substrate set temperature: 10 ° C, and set the conditions of pressure 3MTo rr, to generate a plasma, was etched in the interlayer insulating film.
  • Figures 3 (a) and 3 (b) show the top surface SEM photograph of the etched substrate and the cross-sectional SEM photograph of the hole surrounded by dotted line A in this SEM photograph, respectively.
  • the flow ratio of the etching gas is changed to select the selectivity (interlayer insulating film etch).
  • the etching rate of the Ngrate Z resist was investigated.
  • Etching was performed under the same conditions as in Example 2 except that the antenna-side high-frequency power source was set to 2000 W and the flow rate ratio of the etching gas was changed.
  • the etching gas is constant only at 70sccm for CH, and the flow rates of CF and N are respectively
  • the mixing ratio of the etching gas was changed.
  • the etching gas conditions in (4) are the same as in Example 2. Under each etching gas condition, the etching rate of the interlayer insulating film and the resist was measured to obtain the selection ratio. The results are shown in Fig. 4.
  • the cross-sectional SEM photographs of the substrates in cases (1), (2), (3), and (5) are shown in FIGS. 5 (a), (b), (c), and (d), respectively.
  • the etching rate of the interlayer insulating film was 160 nm / min and the etching rate of the resist was 12 nmZmin, so the selection ratio was about 13.
  • CF 32sccm
  • N 48sccm (21% and 32%, respectively, based on the total etching gas flow rate)
  • the etching rate of the interlayer insulating film was 195 nm / min and the etching rate of the resist was 3 nm Zmin, so the selectivity increased to 65.
  • the etching rate of the interlayer insulating film was 200 nmZmin and the etching rate of the resist was 18 nmZmin, so the selectivity was about 11.
  • the CF-based gas is between 21 to 28% based on the total flow rate of the etching gas. In this case, it has been proved that the selectivity is good because the etching rate of the resist is low.
  • etching was performed by adding Ar gas to the etching gas.
  • an etching gas was supplied under the following conditions, and etching apparatus 1 was supplied with antenna-side high-frequency power supply: 2750 W, substrate-side high-frequency power supply: 450 W, and substrate setting temperature: 10 Etching was performed at a temperature of ° C and a pressure of 0.26 Pa.
  • Figure 6 shows cross-sectional SEM photographs of the substrate under each condition.
  • the etching rates of the interlayer insulating film and the resist under each condition were measured, and the selectivity under each condition was obtained from the results. The results are shown in FIG.
  • the present invention even a resist material having low plasma resistance can be etched with reduced resist damage, so that a low-k material having an ArF resist material as a resist in particular.
  • the present invention can be effectively applied to dry etching of an interlayer insulating film that has high power. Therefore, the present invention can be used in the field of semiconductor manufacturing equipment.
  • FIG. 1 is a configuration diagram schematically showing an example of a configuration of an etching apparatus for performing a dry etching method of the present invention.
  • FIG. 2 is a graph showing a spectrum by FT-IR measurement of a film obtained by the dry etching method of the present invention.
  • FIG. 3 is an SEM photograph showing the state of the substrate obtained by the etching method of the present invention, where (a) is a top view of the substrate and (b) is a cross-sectional view thereof.
  • FIG. 4 is a graph showing an etching rate (nmZmin) and a selection ratio when the mixing ratio of the etching gas is changed.
  • FIG. 5 (a) to (d) are cross-sectional SEM photographs of the substrate when the mixing ratio of the etching gas is changed.
  • FIG. 6 (a) to (e) are cross-sectional SEM photographs of a substrate etched by a conventional etching method, respectively.
  • FIG. 7 is a graph showing an etching rate (nmZmin) and a selection ratio of each substrate etched by a conventional etching method.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de gravure à sec d'un film intermédiaire isolant, le film intermédiaire isolant étant microfabriqué tout en formant un film polymère sur une résine ARF ou une résine KrF disposée sur le film intermédiaire isolant par un gaz de gravure. Le gaz de gravure est introduit à une pression de 0,5 Pa ou moins et la gravure est réalisée tout en formant le film polymère ayant un pic de liaison C-F voisin de 1 200 cm-1, et un pic de liaison C-N voisin de 1 600 cm-1 et un pic de liaison C-H (spectre mesuré par un spectrophotomètre à infrarouge de transformation de Fourier) voisin de 3 300 cm-1.
PCT/JP2007/060010 2006-05-24 2007-05-16 Procédé de gravure à sec d'un film intermédiaire isolant WO2007135906A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020087028192A KR101190137B1 (ko) 2006-05-24 2007-05-16 층간 절연막의 드라이 에칭 방법
CN2007800189986A CN101454878B (zh) 2006-05-24 2007-05-16 层间绝缘膜的干式蚀刻方法
DE112007001243.9T DE112007001243B4 (de) 2006-05-24 2007-05-16 Verfahren zum Trockenätzen einer Zwischenisolierschicht
US12/301,786 US20100219158A1 (en) 2006-05-24 2007-05-16 Method for dry etching interlayer insulating film
JP2008516618A JP4950188B2 (ja) 2006-05-24 2007-05-16 層間絶縁膜のドライエッチング方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-143868 2006-05-24
JP2006143868 2006-05-24

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WO2007135906A1 true WO2007135906A1 (fr) 2007-11-29

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US (1) US20100219158A1 (fr)
JP (1) JP4950188B2 (fr)
KR (1) KR101190137B1 (fr)
CN (1) CN101454878B (fr)
DE (1) DE112007001243B4 (fr)
TW (1) TWI437633B (fr)
WO (1) WO2007135906A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009193988A (ja) * 2008-02-12 2009-08-27 Tokyo Electron Ltd プラズマエッチング方法及びコンピュータ記憶媒体
JP2012096823A (ja) * 2010-11-01 2012-05-24 Takagi Seiko Corp 液体貯蔵容器
JPWO2021161368A1 (fr) * 2020-02-10 2021-08-19
JP7445150B2 (ja) 2019-03-22 2024-03-07 セントラル硝子株式会社 ドライエッチング方法及び半導体デバイスの製造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7637269B1 (en) * 2009-07-29 2009-12-29 Tokyo Electron Limited Low damage method for ashing a substrate using CO2/CO-based process
KR101102495B1 (ko) * 2011-08-11 2012-01-05 주식회사 미로 가로등
US11798811B2 (en) * 2020-06-26 2023-10-24 American Air Liquide, Inc. Iodine-containing fluorocarbon and hydrofluorocarbon compounds for etching semiconductor structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004071731A (ja) * 2002-08-05 2004-03-04 Ulvac Japan Ltd エッチング方法
JP2005251814A (ja) * 2004-03-02 2005-09-15 Ulvac Japan Ltd 層間絶縁膜のドライエッチング方法及びその装置
JP2006100628A (ja) * 2004-09-30 2006-04-13 Hitachi High-Technologies Corp プラズマ処理方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6635185B2 (en) * 1997-12-31 2003-10-21 Alliedsignal Inc. Method of etching and cleaning using fluorinated carbonyl compounds
JP4538209B2 (ja) * 2003-08-28 2010-09-08 株式会社日立ハイテクノロジーズ 半導体装置の製造方法
US20050266691A1 (en) * 2004-05-11 2005-12-01 Applied Materials Inc. Carbon-doped-Si oxide etch using H2 additive in fluorocarbon etch chemistry
US20060051965A1 (en) * 2004-09-07 2006-03-09 Lam Research Corporation Methods of etching photoresist on substrates
US7794880B2 (en) * 2005-11-16 2010-09-14 California Institute Of Technology Fluorination of multi-layered carbon nanomaterials

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004071731A (ja) * 2002-08-05 2004-03-04 Ulvac Japan Ltd エッチング方法
JP2005251814A (ja) * 2004-03-02 2005-09-15 Ulvac Japan Ltd 層間絶縁膜のドライエッチング方法及びその装置
JP2006100628A (ja) * 2004-09-30 2006-04-13 Hitachi High-Technologies Corp プラズマ処理方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009193988A (ja) * 2008-02-12 2009-08-27 Tokyo Electron Ltd プラズマエッチング方法及びコンピュータ記憶媒体
CN102254813A (zh) * 2008-02-12 2011-11-23 东京毅力科创株式会社 等离子体蚀刻方法
JP2012096823A (ja) * 2010-11-01 2012-05-24 Takagi Seiko Corp 液体貯蔵容器
JP7445150B2 (ja) 2019-03-22 2024-03-07 セントラル硝子株式会社 ドライエッチング方法及び半導体デバイスの製造方法
JPWO2021161368A1 (fr) * 2020-02-10 2021-08-19
WO2021161368A1 (fr) * 2020-02-10 2021-08-19 株式会社日立ハイテク Procédé de traitement par plasma
JP7075537B2 (ja) 2020-02-10 2022-05-25 株式会社日立ハイテク プラズマ処理方法
TWI783362B (zh) * 2020-02-10 2022-11-11 日商日立全球先端科技股份有限公司 電漿處理方法
US11887814B2 (en) 2020-02-10 2024-01-30 Hitachi High-Tech Corporation Plasma processing method

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KR20090012329A (ko) 2009-02-03
CN101454878B (zh) 2011-03-23
JPWO2007135906A1 (ja) 2009-10-01
TWI437633B (zh) 2014-05-11
KR101190137B1 (ko) 2012-10-12
DE112007001243B4 (de) 2015-01-22
TW200809961A (en) 2008-02-16
CN101454878A (zh) 2009-06-10
JP4950188B2 (ja) 2012-06-13
DE112007001243T5 (de) 2009-05-28

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