Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds

Definitions

• This invention relates to optical annealing during semiconductor device fabrication and refers particularly, though not exclusively, to annealing during semiconductor device fabrication by use of lasers or lamps after the substrate is removed.
• Many semiconductor devices are fabricated in large numbers on a substrate. During fabrication they incorporate at least one layer of a metal. Most metal layers applied to semiconductors devices during the fabrication of the semiconductor devices are annealed following their application. Annealing is normally in an oven or the like for a period of time and a predetermined temperature. Often the temperature is relatively high, for example, the annealing temperature for the Ohmic contact metal to n-type GaN is done at 900 C [Z. Fan et al, Applied Physics Letters, Volume 68, page 1672, 1996]. The use of relatively high temperatures has many problems that degrade device performance. For example, unwanted atomic diffusions can take place at high annealing temperatures, degrading the device performance.
• annealing done at low temperatures, preferably at room temperature. Due to the difference between the thermal expansion coefficients of different materials on a wafer (such as, for example, the substrate, epitaxial layers, metals, dielectrics, and so forth), conventional annealing often causes thermal stress in the wafer as the heating is applied to the whole wafer. If the stress is not buffered properly, it often causes cracking in the wafer or the peeling of thin films from the wafer, or creating defects in the wafer. This is especially true in certain wafer fabrication technologies where the substrate is removed and the epitaxial layers are bonded to another mechanical support that acts like a new substrate.
• a process for the fabrication of semiconductor devices being fabricated on a substrate and including at least one metal layer after removal of the substrate and applying a second substrate, there is provided the step of annealing the at least one metal layer by application of a beam of electromagnetic radiation on the least one metal layer.
• a process for the fabrication of semiconductor devices being fabricated on a substrate and including at least one metal layer, the process comprising removing the substrate from the semiconductor devices, forming a second substrate on the at least one metal layer, and annealing the at least one metal layer by application of a beam of electromagnetic radiation at a number of locations on the at least one metal layer.
• the second substrate may be applied to the semiconductor devices before or after the substrate is removed.
• the beam of electromagnetic radiation may be a laser beam, light from at least one lamp, or light from a bank of lamps.
• the second substrate may be applied to the semiconductor devices on a second surface of the semiconductor devices, the substrate having been removed from a first surface of the semiconductor devices, the first and second surfaces being different.
• the first surface may be opposite the second surface.
• the duration of the application of the laser beam may also be determined by the metal of the at least one metal layer, and the thickness of the at least one metal layer.
• the laser beam may be of a frequency and intensity determined by the metal of the at least one metal layer, the thickness of the at least one metal layer, and the material of the semiconductor devices.
• the plurality of metal layers may be annealed sequentially or simultaneously.
• the laser beam may be sequentially applied to the number of locations.
• the laser beam may be applied directly to the at least one layer, or may be applied through the semiconductor device to the at least one metal layer. It may be to an interface of the at least one metal layer and the semiconductor device.
• the beam of electromagnetic radiation may be applied at a number of locations on the at least one metal layer.
• the number and spacing of the locations may be determined by the metal of the at least one metal layer, and a thickness of the at least one metal layer.
• a mask may be placed between a source of the beam of electromagnetic radiation and the semiconductor devices; the screen having at least one aperture therethrough for the passage through the at least one aperture of the beam of electromagnetic radiation.
• the at least one aperture may be sized and shaped to be substantially the same as the at least one metal layer.
• Figure 1 is a schematic vertical cross-sectional view of a preferred form of semiconductor device on which will be performed a preferred method
• Figure 2 is a view corresponding to Figure 1 after removal of the first substrate
• Figure 3 is a view corresponding to Figures 1 and 2 after formation of the second substrate
• Figure 4 is a side view corresponding to Figures 1 to 3 after formation of an ohmic contact layer
• Figure 5 is a top view corresponding to Figure 4.
• Figure 6 is a schematic top view of the semiconductor devices of Figures 4 and 5 during annealing
• Figure 7 is a side view corresponding to the Figure 6;
• Figure 8 is a localized side view corresponding to Figure 7;
• Figure 9 is a schematic side view corresponding to Figure 6 of a second embodiment
• a substrate 3 on which are epitaxial layers 1 and quantum well layer that together from the beginning of a semiconductor device.
• the substrate is removed from the quantum well layer 2 and expitaxial layers 1 by any known technique.
• a second substrate 4 (such as for example, copper) is added above the epitaxial layer 1 ( Figure 3).
• Figures 4 and 5 show that ohmic contact layers 5 are then formed on the epitaxial layers 1.
• the second substrate 4 is preferably formed on a second surface 32 of the semiconductor device 20, the substrate 3 having been removed from a first surface 30 of the semiconductor devices 20, the first and second surfaces 30, 32 being different.
• the first and second surfaces 30, 32 are opposite surfaces.
• the second substrate 4 may be formed on or applied to the second surface either before or after the substrate 3 is removed.
• FIG. 6 there is shown an apparatus 14 for producing a beam 16 of electromagnetic radiation.
• the apparatus 14 may be a laser, at least one lamp, or a bank of lamps.
• the substrate 4 has a number of semiconductor devices 20 being fabricated on the substrate 4. Although twelve semiconductor devices 20 and shown, there may be any suitable number.
• the ohmic contacts 5 are annealed to enable them to be more strongly adhered to the epitaxial layers 1. This is by a form of fusion of the ohmic contacts 5 and the epitaxial layers 1 at their interface.
• the apparatus 14 produces the beam 16.
• the beam 16 will be a laser beam if apparatus 14 is a laser, or will be light of desired frequency if apparatus 14 is at least one lamp, or a bank of lamps.
• the beam 16 is focused on the exposed surface of the ohmic contact 5. As such the ohmic contact 5 is heated by the beam 16. Due to the inherent heat conductivity of the ohmic contact 5, the beam 16 does not need to be applied to the entirety of the surface of the ohmic contact 5
• the beam 16 is shown being applied to one semiconductor device 20. It may be applied to two or more simultaneously, up to being simultaneously applied to all semiconductor devices 20.
• the heat conductivity of the ohmic contact 5 means that heating is limited to the immediate area 30 of the ohmic contact 5 and thus not all of the epitaxial layers 1 are heated. In this way the heat in the expitaxial layers 1 is dispersed through the epitaxial layers 1 and does not affect the interface of epitaxial layers 1 and the second substrate 4. Therefore the temperature at the interface of the epitaxial layer 1 and the second substrate 4 will be less that the temperature at the interface of the ohmic contact 5 and the epitaxail layer 1.
• the duration, wavelength, radiation power, and radiation power density of the application of the electromagnetic beam 16 may be determined by the metal of the at least one metal layer 5, and the thickness of the at least one metal layer 5, and the materials of the semiconductor devices 20.
• Figure 9 shows a second embodiment. This may be used when the beam 16 is laser beam, but should be used when the beam 16 is of light.
• a mask 24 is placed between source 14 and the semiconductor devices 20.
• the mask 24 has at least one aperture 26 that is preferably sized and shaped to be substantially the same as that of the area to be annealed - in this case the ohmic contact 5. In that way the light 28 passing through the aperture 26 only contacts the ohmic contact 5 and not the epitaxial layers 1.
• localized optical annealing is used in semiconductor device fabrication, where the original wafer substrate is removed and the semiconductor layers are transferred to a new substrate either before or after the optical_annealing.
• Both laser annealing and lamp annealing may be used.
• Laser annealing can be applied to where annealing is required by directing the laser beam to that area.
• a broad light beam that is generated by a lamp, a bank of lamps, or a broadened laser beam can also be applied to the whole surface of the wafer, or to an interface in the wafer if the light is so chosen that it can pass certain layers (or substrate) of the wafer without being significantly absorbed before reaching the interface.
• the above-described process may also be used to anneal a more substantial metal layer such as, for example, the second substrate 4.
• the beam 16 does not need to be applied to the entirety of the metal layer 4, but is applied sequentially to locations on the surface of the metal layer 4 for annealing of the metal layer 4 to take place.
• the number and spacing of the locations, the duration of the application of the beam 16 at each location, the intensity of the laser beam 16 and the frequency of the laser beam 16 will be determined by the metal of the metal layer 4, and the thickness of the metal layer 4.
• the beam 16 may be applied simultaneously to the number of locations.
• the order of application of the beam 16 matches heat flow in the metal layer 4 to maximize the annealing.
• the aperture(s) 26 will be sized, shaped, spaced and located to substantially match the size, shape, spacing and location of the metal layers 4.
• the beam 16 may be applied directly to the at least one metal layer 22, or may be applied to the at least one metal layer 22 through the semiconductor device 20. in the latter case, the beam 16 is preferably applied to the interface between the at least one metal layer 22 and the semiconductor devices 20.
• each layer may be annealed sequentially, or simultaneously.
• the nature of the beam 16 will depend significantly on the materials of the ohmic or metal layer 5, and the epitaxial layers 1. This will include the thickness of the ohmic or metal layer 5.
• Laser conditions include pulse width of the laser, number of pulses, the frequency of the pulses, and the power and density of the laser beam.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• High Energy & Nuclear Physics (AREA)
• Power Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
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• Optics & Photonics (AREA)
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• Electrodes Of Semiconductors (AREA)
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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2005
  • 2005-12-20 SG SG200508210-2A patent/SG133432A1/en unknown
• 2006
  • 2006-12-19 WO PCT/SG2006/000395 patent/WO2007073354A1/en not_active Ceased
  • 2006-12-19 CN CN2006800481382A patent/CN101410991B/zh not_active Expired - Fee Related
  • 2006-12-19 KR KR1020087017343A patent/KR20080096510A/ko not_active Withdrawn
  • 2006-12-19 JP JP2008547189A patent/JP2009520376A/ja not_active Withdrawn
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