Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• This invention relates to the fabrication of transistors and refers particularly, though not exclusively, to the fabrication of gallium nitride high electron mobility transistors ("HEMT”) and to transistors so fabricated.
• HEMT gallium nitride high electron mobility transistors
• HEMT devices have been proposed for a few years. They are capable of high power with over 100W/chip being possible; high frequency — 1 to 40GHz being possible; and can operate at temperatures of over 6QO 0 C. This generates a lot of heat so heat dissipation becomes important as not all devices can withstand such temperatures, and the HEMT device may be used with many other devices.
• a method for fabricating transistors comprising: forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; forming at least one drain contact on the first surface; forming at least one gate contact on the first surface; forming at least one insulating layer over and between the gate contact, source contacts and drain contact to insulate the gate contact, source contacts and the drain contact; forming a conductive layer over and through at least a part of the at least one insulating layer for connecting the source contacts; and forming at least one heat sink layer over the conductive layer.
• an apparatus comprising transistors, each transistor comprising: a plurality of epitaxial layers having a first surface; a plurality source contacts, at least one drain contact, and at least one gate contact, all on the first surface; at (east one insulating layer over arid ' between the gate contact, source contacts and drain contact for insulating the gate contact, source contacts and the drain contact; a conductive layer over and through at least a part of the at least one insulating layer for connecting the source contacts; and at least one heat sink layer over the conductive layer.
• the transistors may be high electron mobility transistors.
• the plurality of epitaxial layers may comprise a layer of gallium nitride, a layer of aluminium gallium nitride, a layer of n+ aluminium gallium nitride and a final layer of gallium nitride.
• the first surface may be on the final layer of gallium nitride.
• the conductive layer may connect the plurality of source contacts through vias in the at least one insulating layer.
• the at least one insulating layer may be heat conductive and electrically insulating.
• a relatively thick layer of a heat conductive metal may be formed over the conductive layer. At least one seed layer-may be formed on the conductive layer before the relatively thick layer is formed.
• the drain, gate and source connections may be' formed by creating then filling vias through the substrate and the epitaxial layers to the drain contact, gate contact and the conductive layer respectively.
• the substrate may be removed and the drain, gate and source connections formed by creating then filling vias through the expitaxial layers to the drain contact, gate contact and conductive layer respectively.
• a further layer of heat conductive but electrically insulating material may be applied in place of the substrate.
• Figure 1 is a schematic illustration of a device at a first stage of the fabrication process
• Figure 2 is a schematic illustration of the device at a second stage of the fabrication process
• Figure 3 is a schematic illustration of the device at a third stage of the fabrication process
• Figure 4 is a schematic illustration of the device -at a fourth stage of the fabrication process
• Figure 5 is a schematic illustration of the device at a fifth stage of the fabrication process
• Figure 6 is a schematic illustration of the device at a sixth stage of the fabrication process
• Figure 7 is a schematic illustration of the device at a seventh stage of the fabrication process
• Figure 8 is a schematic illustration of the device at an eighth stage of the fabrication process
• Figure 9 is a schematic illustration of the device at a ninth stage of the fabrication process.
• Figure 10 is a schematic illustration of the device at a tenth stage of the fabrication process
• Figure 11 is a schematic illustration of the device at an eleventh stage of the fabrication process
• Figure 12 is a schematic illustration of the device at a twelfth stage of the fabrication process
• Figure 13 is a schematic illustration of the device at a thirteenth stage of the fabrication process
• Figure 14 in a full cross-sectional view along the lines and in the direction of arrows 14 - 14 on Figure 13;
• Figure 15 is a schematic illustration of the device at a fourteenth stage of the fabrication process;
• Figure 16 a full cross-sectional view along the lines and in the direction of arrows 16 - 16 on Figure 15;
• Figure 17 is a schematic illustration of the device at a fifteenth stage of the .fabrication process.
• Figure 18 is a schematic illustration of the device at a sixteenth stage of the fabrication process
• Figure 19 is a full cross sectional view along the lines and in the direction of arrows 19 - 19 on Figure 18;
• Figure 20 is a schematic illustration of the device at a seventeenth stage of the fabrication process
• Figure 21 is a schematic illustration of the device at a final stage of the fabrication process.
• Figure 22 is a schematic illustration of the device at an alternative final stage of the fabrication process.
• Figure 1 shows the structure at the commencement of fabrication.
• a sapphire substrate 1 has a buffer layer 2 above it, and the epitaxial layers 3 are on the buffer layer 2.
• the epitaxial layers 3 comprise a layer 4 of GaN, a layer 5 of AIGaN, and n+ layer 6 of AIGaN 1 and a final GaN layer 7.
• Source 8 and drain 9 contacts are then formed on the surface of the final GaN layer ( Figure 2) there being a source 8 and a drain contact 9 for each transistor.
• Gate contacts 10 are then formed between each source contact 8 and each drain contact 9 ( Figure 3). In this way when each gate 10 is activated current will flow from one source 8 to the two drains 9, one on each side of source contact 8.
• an electrically insulating layer such as a passivation layer 11 of, for example AIN 1 is then applied to electrically insulate the contacts 8, 9, 10 while being able to conduct heat.
• the layer 11 is preferably heat conductive.
• a resist is applied over passivation layer 11 ( Figure 5) and vias 12 formed through passivation layer 11 down to the source contacts 8 and the resist removed.
• a further layer 13 of an electrically and heat conductive metal is applied over the passivation layer 13, the layer 16 also filling the vias 12. This connects the source contacts 8 ( Figure 6). In this way, all contacts 8, 9 and 10 are in the one plane.
• At least one further layer 14 is applied over the conductive metal layer 13 and the passivation layer 11 not covered by the conductive metal layer 13.
• the further layer 14 is a seed layer.
• the seed layer 14 may be a number of layers - for example, three different metal layers.
• the first seed layer should adhere well to the conductive layer 13 and may be of chromium or titanium. It may be followed by second layer and third layer that may be of tantalum and copper respectively. Other materials may be used for all seed layers.
• the second seed layer may act as a diffusion barrier, preventing copper or other materials placed on top of it (such as, for example, the third seed layer) from diffusing into the expitaxial layers 3.
• the third seed layer acts as a seeding layer for subsequent electroplating.
• the seed layers can be used to buffer the stress. This may be by one or more of: by having sufficient flexibility to absorb the stress, by having sufficient internal slip characteristics to absorb the stress, by having sufficient rigidity to withstand the stress, and by having graded thermal expansion coefficients.
• the first layer 15 may be tantalum with a coefficient of thermal expansion of 6.3
• the second layer 6 may be copper with a coefficient of thermal expansion of 16.5.
• coefficients of thermal expansion are graded from the passivation layer 13 and to the outer, copper layer 18.
• An alternative is to have coefficients of expansion that differ such that at the temperatures concerned, one metal layer expands while another contracts.
• the outer, copper layer 18 was applied directly to the contact layer 13 and passivation layer 11, the differences in their thermal expansion rates may cause cracking, separation, and/or failure.
• the intermediate. layer(s) should have coefficient(s) of expansion " between those of layers 15 and 16, and should be graded from that of the first layer 15 to that of the final layer 16. There may be no intermediate layer, or there may be any required or desired number of intermediate layers (one, two, three and so forth).
• a pattern of thick resists 17 is applied to the seed layer 15 by standard photolithography ( Figure 8), and the remaining metal 18 is plated between and over the thick resists 17 ( Figure 9) to form a single metal support layer 18.
• the removal or lift-off of the sapphire substrate 1 then takes place ( Figures 10 and 11 ) in accordance with known techniques such as, for example, that described in Kelly [M. K. Kelly, O. Ambacher, R. Dimitrov, R. Handschuh, and M. Stutzmann, phys. stat. sol. (a) 159, R3 (1997)].
• the substrate 1 may also be removed by polishing or wet etching. This exposes the lowermost surface 19 of the GaN layer 4. It is preferred for lift-off of the substrate to take place while the epitaxial layers 3 are intact to improve the quality of removal, and for structural strength. By having the epitaxial layers 3 intact at the time of removal the electrical and mechanical properties of the epitaxial layers 3 are preserved.
• the thickly plated metal 18 is able to act as one or more of: the new mechanical support; and during operation of the semiconductor device is able to act as one or more of: a heat sink, a heat dissipater, and a connecting layer.
• the final GaN layer 7 is relatively thin, the heat generated in active layers 3 is more easily able to be conducted to the thick layer 18.
• each of the layers 11, 13 and 14 are heat conductive.
• the seed layer(s) 14 may be an electrical insulating layer but must be a good thermal conductor e.g. AIN.
• the thick layer 18 creates a parasitic capacitance that slows the speed of operation. By increasing the distance between layer 18 and the epitaxial layers 3, the parasitic capacitance is decreased.
• a resist layer is applied to the now-exposed surface 19 of the GaN layer 4 and etching takes place to form at least one via 20 through epitaxial layers 13 to the drain contact 9 ( Figure 12). Via 20 is then filled ( Figure 13) to form a drain connection 21.
• Figure 14 show a view of the drain connection 20, source contacts 8 and gate contacts 10.
• a separate via 22 is formed ( Figure 15) through the expitaxial layers 3 to the gate contact 10 and via 22 is filled to form a gate connection 23.
• Figure 16 shows a view of the gate connection 23 as well as the drain connection 20, and source contact 8.
• Figures 17 and 18 show a similar process for the source connection 8.
• a via 24 is formed through the expitaxia! layers 3 to the source connector layer 13 and the via 24 filled to form the source connection 25.
• Figure 19 shows a view of the source connection 25.
• the substrate 1 may be left in place and holes drilled by, for examples, lasers to enable the connections 20, 23 and 25 to be formed.
• a further layer 27 of a material that is a heat conductive but electronically insulating (e.g. AIN) may be added in place of substrate 1.
• the device HEMT device can be used with the relatively thick metal layer 18 acting as one or more of: a contact, heat sink, heat diffuser, and a physical support for the device.
• the combined effect of the passivation layer 11 , the conductive layer 13, the seed layer 14 and the relatively thick layer 18 is that they are all conductive so they all combine to conduct heat away from the epitaxial layers 3, and for them to combine to be a heat sink.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Junction Field-Effect Transistors (AREA)
• Thin Film Transistor (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=37962779

Family Applications (1)

Country Status (7)

Cited By (8)

Families Citing this family (5)

Citations (6)

Family Cites Families (146)

• 2005
  • 2005-10-19 SG SG200506897-8A patent/SG131803A1/en unknown
• 2006
  • 2006-09-01 CN CN2006800390468A patent/CN101351887B/zh not_active Expired - Fee Related
  • 2006-09-01 KR KR1020087011945A patent/KR20080074892A/ko not_active Withdrawn
  • 2006-09-01 JP JP2008536553A patent/JP2009513014A/ja not_active Withdrawn
  • 2006-09-01 US US12/091,036 patent/US8067269B2/en not_active Expired - Fee Related
  • 2006-09-01 EP EP06784267A patent/EP1949442A4/en not_active Withdrawn
  • 2006-09-01 WO PCT/SG2006/000255 patent/WO2007046773A1/en not_active Ceased

Patent Citations (6)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events