WO2006103949A1 - フリップチップ実装方法および基板間接続方法 - Google Patents

フリップチップ実装方法および基板間接続方法 Download PDF

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Publication number
WO2006103949A1
WO2006103949A1 PCT/JP2006/305274 JP2006305274W WO2006103949A1 WO 2006103949 A1 WO2006103949 A1 WO 2006103949A1 JP 2006305274 W JP2006305274 W JP 2006305274W WO 2006103949 A1 WO2006103949 A1 WO 2006103949A1
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WIPO (PCT)
Prior art keywords
resin
circuit board
semiconductor chip
terminals
generating agent
Prior art date
Application number
PCT/JP2006/305274
Other languages
English (en)
French (fr)
Inventor
Seiji Karashima
Takashi Kitae
Seiichi Nakatani
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to JP2007510387A priority Critical patent/JP4084835B2/ja
Priority to US11/887,331 priority patent/US7531385B1/en
Priority to EP06729267A priority patent/EP1865550A4/en
Priority to KR1020077020987A priority patent/KR101181140B1/ko
Publication of WO2006103949A1 publication Critical patent/WO2006103949A1/ja
Priority to US12/078,891 priority patent/US7820021B2/en

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    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Definitions

  • the present invention relates to a flip chip mounting method for mounting a semiconductor chip on a circuit board, and an inter-substrate connection method for connecting substrates on which a plurality of electrodes are formed.
  • solder bumps are generally formed on the electrode terminals of the LSI chip, and are generally bonded together to connection terminals formed on the circuit board via the solder bumps.
  • the semiconductor integrated circuit is changed to an electrode terminal of a peripheral electrode terminal force area arrangement due to an increase in electrode terminals.
  • semiconductor process power will progress from S90nm to 65nm and 45nm due to demands for higher density and higher integration.
  • the miniaturization of wiring has further progressed and the capacitance between wirings has increased, and the problems of speeding up and power consumption loss have become serious.
  • Low dielectric constant (Low-K) ) Is more demanding.
  • the realization of such a low-K layer of an insulating film is obtained by making the insulating layer material porous, which is an obstacle to the thinning of a semiconductor with weak mechanical strength.
  • a plating method As a bump forming technique, a plating method, a screen printing method, or the like has been developed. Although the plating method is suitable for narrow pitches, the process is complicated and there are problems in productivity. The screen printing method is excellent in productivity but is narrow in terms of using a mask. Not suitable for moths.
  • solder paste made of a mixture of conductive particles and flux is solid-coated on a substrate on which an electrode is formed, and the substrate is heated. By doing so, the conductive particles are melted, and solder bumps are selectively formed on the highly wettable electrodes.
  • Patent Document 3 is a method in which a base composition (chemical reaction deposition solder) mainly composed of an organic acid lead salt and metallic tin is applied onto a substrate on which electrodes are formed. By coating and heating the substrate, a substitution reaction of Pb and Sn occurs, and the Pb / Sn alloy is selectively deposited on the substrate electrode.
  • a base composition chemical reaction deposition solder
  • flip-chip mounting using a conventional bump forming technique is a resin called underfill for mounting a semiconductor chip on a circuit board on which bumps are formed and then fixing the semiconductor chip to the circuit board. Process of injecting between the semiconductor chip and the circuit board Need more.
  • Patent Document 1 JP 2000-94179 A
  • Patent Document 2 JP-A-6-125169
  • Patent Document 3 Japanese Patent Laid-Open No. 1-157796
  • Patent Document 4 Japanese Unexamined Patent Publication No. 2000-332055
  • Patent Document 5 Japanese Patent Application Laid-Open No. 2002-26070
  • Patent Document 6 Japanese Patent Laid-Open No. 11-186334
  • Patent Document 7 Japanese Unexamined Patent Application Publication No. 2004-260131
  • Non-Patent Document 1 Masahiro Yasuda et al., “Self-organized bonding process using low melting point metal filler-containing resin”, 10th Symposium on icrojoing and Assembly Technology in Electronics), 183-188, 2004
  • the conductive particles are uniformly dispersed in the resin.
  • the dispersed conductive particles are dispersed between the semiconductor chip and the circuit board. Physically contacts the electrode terminals, thereby allowing an electrical connection between the opposing electrode terminals, while the anisotropic conductive material lubricates between adjacent electrode terminals. Ensures insulation.
  • the conductive particles are uniformly dispersed in the resin, the conductive particles contributing to conduction between the opposing electrode terminals are only a part of the conductive particles, and stable conduction is achieved. There is a problem that sufficient reliability cannot be obtained for an electrical connection which is difficult to obtain. Also, even if the adjacent electrode terminals are insulated by grease, it contributes to the conduction between the opposing electrode terminals, and the conductive particles are dispersed in the grease! There is a possibility that sufficient insulation cannot be secured.
  • flip-chip mounting using anisotropic conductive material is a problem to be solved in terms of reliability in order to be applied to next-generation LSI chips having more than 5,000 connection terminals. Is leaving.
  • the present invention has been made in view of the strong points, and includes a flip chip mounting method with high productivity and reliability applicable to the flip chip mounting of the next generation LSI, and the method and basic steps. It is an object of the present invention to provide an inter-board connection method.
  • a semiconductor chip having a plurality of electrode terminals is arranged facing a circuit board having a plurality of connection terminals, and the connection terminals of the circuit board and the electrodes of the semiconductor chip are arranged.
  • the second step of generating bubbles from the bubble generating agent contained in the resin the third step of pressing the semiconductor chip against the circuit board, and the fourth step of curing the resin
  • the resin is pushed out of the bubbles by the growth of bubbles generated from the bubble generating agent, thereby causing the gap between the connection terminals of the circuit board and the electrode terminals of the semiconductor chip.
  • Self-assemble and terminal in the third step When the conductive particles contained in the self-assembled resin are brought into contact with each other, the terminals are electrically connected, and in the fourth step, the resin is cured between the terminals by curing the resin.
  • the body chip is fixed to the circuit board.
  • the bubble generating agent also has a material force that boils when the resin is heated.
  • bubble generators can also have two or more material strengths with different boiling points. May be.
  • the bubble generating agent may also have a material force for generating gas by thermally decomposing the bubble generating agent when the resin is heated.
  • the bubble generating agent is composed of a compound containing water of crystallization, and decomposes to generate water vapor when the resin is heated.
  • the second step is performed while varying the gap between the circuit board and the semiconductor chip.
  • the semiconductor chip is disposed on the surface of the resin. It is executed from Toko.
  • the fourth step is performed by heating the resin to thermally cure the resin. Further, after the fourth step, the method may further include a step of supplying an underfill material to the gap between the circuit board and the semiconductor chip and then curing the underfill material.
  • the semiconductor chip having a plurality of electrode terminals has a configuration in which a semiconductor bare chip is mounted on an interposer having a plurality of electrode terminals.
  • a second substrate having a plurality of electrodes is disposed opposite to a first substrate having a plurality of electrodes, and the electrodes of the first substrate and the second substrate are arranged.
  • the second step of generating bubbles, the third step of pressing the second substrate against the first substrate, and curing the resin In the second step, the resin is pushed out of the bubbles by the growth of bubbles generated from the bubble generating agent.
  • the conductive particles contained in the resin self-assembled between the electrodes are mutually assembled.
  • the first substrate is fixed to the second substrate by electrically connecting the electrodes by contact with each other, and curing the resin self-assembled between the electrodes in the fourth step. It is characterized by this.
  • the bubble generating agent also has a material force that boils when the resin is heated.
  • the second step is performed while varying the gap between the first substrate and the second substrate.
  • the second resin is applied to the surface of the resin. This is done by placing the board.
  • an underfill material is supplied to a gap between the first substrate and the second substrate, and then the underfill material is cured.
  • the method further includes a step.
  • a semiconductor chip having a plurality of electrode terminals is arranged facing a circuit board having a plurality of connection terminals, and the connection terminals of the circuit board and the electrode terminals of the semiconductor chip are arranged.
  • the connection terminal and the electrode terminal are connected to the connection terminal by a resin containing conductive particles and a bubble generating agent supplied in a gap between the circuit board and the semiconductor chip.
  • self-assembled between the electrode terminals, and the conductive particles in the self-assembled resin are in contact with each other to be electrically connected.
  • the flip chip mounting body is fixed by an underfill material supplied to a gap between the circuit board and the semiconductor chip.
  • the flip chip mounting apparatus of the present invention is a flip chip mounting apparatus for flip chip mounting a semiconductor chip on a circuit board, and holds the semiconductor chip and the circuit board facing each other with a certain gap.
  • a supply means for supplying a resin containing conductive particles and a bubble generating agent into a gap between the semiconductor chip and the circuit board, a heating means for heating the resin, and a pressure for pressing the semiconductor chip against the circuit board.
  • a heating means comprising: a first heating means for controlling the temperature to generate bubbles from the bubble generating agent contained in the resin; and a second heating means for controlling the temperature to thermally cure the resin. It is characterized by having.
  • the fat heated by the first heating means is generated by bubbles. Bubbles generated from the raw material grow and are pushed out of the bubbles to self-assemble between the connection terminals of the circuit board and the electrode terminals of the semiconductor chip, and the semiconductor chip is pressed against the circuit board by the pressing means. By doing so, the conductive particles contained in the resin self-assembled between the terminals are brought into contact with each other, an electrical connection is made between the terminals, and the resin is heated by the second heating means, The semiconductor chip is fixed to the circuit board in a state where the conductive particles contained in the resin are in contact with each other.
  • the flip chip mounting method generates bubbles from the bubble generating agent by heating the resin containing the conductive particles and the bubble generating agent supplied to the gap between the circuit board and the semiconductor chip.
  • the bubbles can be self-assembled between the connection terminals of the circuit board and the electrode terminals of the semiconductor chip by pushing the resin out of the bubbles as the bubbles grow.
  • the conductive particles contained in the resin self-assembled between the opposing terminals can be brought into contact with each other to electrically connect the terminals.
  • the conductive particles dispersed in the resin can efficiently self-assemble between the terminals and contribute to the conduction between the terminals, so that a stable conduction state is obtained and the reliability is high! Electrical connection can be achieved.
  • the resin containing the conductive particles and the bubble generating agent supplied between the opposing substrates By heating the resin containing the conductive particles and the bubble generating agent supplied between the opposing substrates, By generating bubbles and pushing the resin out of the bubbles as the bubbles grow, the resin can be self-assembled between the electrodes of the opposing substrate. Then, by pressing the same substrate, the conductive particles contained in the resin self-assembled between the electrodes can be brought into contact with each other to electrically connect the electrodes. As a result, the conductive particles dispersed in the resin can efficiently self-assemble between the electrodes and contribute to the conduction between the electrodes, so that a stable conduction state is obtained and the connection between the substrates is highly reliable. Can be achieved.
  • FIGS. 1A to 1D are cross-sectional views showing a flip-chip mounting method in an embodiment of the present invention.
  • FIGS. 2A to 2C are cross-sectional views showing a flip chip mounting method according to an embodiment of the present invention.
  • FIG. 3 (a) is a diagram showing a heating temperature profile of the resin in the present invention
  • FIG. 3 (b) is a diagram showing a pressure profile when a semiconductor chip is pressed against a circuit board.
  • FIGS. 4 (a) and 4 (b) are diagrams for explaining the mechanism of the self-assembly of coffin in the present invention.
  • FIGS. 5 (a) to 5 (c) are process cross-sectional views illustrating a process of heating while varying a gap between a circuit board and a semiconductor chip in the present invention.
  • FIG. 6 is a diagram for explaining self-assembly of a resin containing two or more types of bubble generating agents in the present invention.
  • Fig. 7 is a view showing a material of a bubble generating agent in the present invention.
  • FIG. 8 is a view showing the material of the bubble generating powder that is thermally decomposed in the present invention.
  • FIG. 9 is a block diagram showing a configuration of a flip chip mounting apparatus according to the present invention.
  • FIGS. 1 (a) to (d) and FIGS. 2 (a) to (c) are process cross-sectional views illustrating basic processes of a flip chip mounting method according to an embodiment of the present invention.
  • conductive particles (eg, Cu) 12 and a bubble generating agent (eg, isopropyl alcohol) are placed on a circuit board 10 having a plurality of connection terminals 11.
  • Supply the containing resin (for example, epoxy resin) 13 13.
  • a semiconductor chip 20 having a plurality of electrode terminals 21 is disposed on the surface of the resin 13 so as to face the circuit board 10. At this time, the electrode terminal 21 of the semiconductor chip 20 is aligned with the connection terminal 11 of the circuit board 10.
  • the circuit board 10 and the semiconductor chip 20 are arranged facing each other with a certain gap (for example, 10 to 80 / ⁇ ⁇ ), and thereafter Alternatively, the resin particles 12 containing the conductive particles 12 and the bubble generating agent may be supplied to the gap.
  • the extruded resin 13 is self-aligned in a columnar shape (for example, substantially cylindrical shape) between the connection terminal 11 of the circuit board 10 and the electrode terminal 21 of the semiconductor chip 20. Gather. At this time, most of the resin 13 that does not self-assemble between the terminals is pushed out of the gap between the circuit board 10 and the semiconductor chip 20 by the pressure of the grown bubbles 30.
  • a columnar shape for example, substantially cylindrical shape
  • the semiconductor chip 20 is pressed against the circuit board 10 in the direction of the arrow.
  • the magnitude of the pressure is set to about 20 k to 200 kPa, for example.
  • the conductive particles contained in the resin 13 self-assembled between the opposing terminals by this pressing.
  • the terminals are electrically connected.
  • the terminals are electrically connected with at least one conductive particle 12 interposed between the terminals. It should be noted that the conductive particles 12 contained in the resin 13 do not flow out of the resin 13 due to the stress caused by the viscosity of the resin 13 during pressing.
  • the semiconductor chip 20 is fixed to the circuit board 10 by curing the resin 13 self-assembled between the opposing terminals. Since the resin 13 spreads over the entire terminal surface, it is sufficient to fix the semiconductor chip 20 to the circuit board 10, but if necessary, an underfill material 14 is provided in the gap between the semiconductor chip 20 and the circuit board 10. Then, the underfill material 14 may be hardened to further strengthen the fixing of the semiconductor chip 20 to the circuit board 10. The underfill material 14 may be supplied before the semiconductor chip 20 is pressed against the circuit board 10.
  • bubbles are generated from the bubble generating agent by heating the conductive particles 12 supplied to the gap between the circuit board 10 and the semiconductor chip 20 and the resin 13 containing the bubble generating agent.
  • the resin 13 is pushed out of the bubbles so that the resin 13 can be self-assembled between the connection terminal 11 of the circuit board 10 and the electrode terminal 21 of the semiconductor chip 20.
  • the conductive particles 12 contained in the resin 13 self-assembled between the opposing terminals are brought into contact with each other to electrically connect the terminals. Can do.
  • the conductive particles 12 dispersed in the resin 13 can be efficiently self-assembled between the terminals and contribute to the conduction between the terminals, so that a stable conduction state can be obtained and highly reliable electric power can be obtained. Connection can be achieved.
  • FIGS. 1 (a) to (d) and FIGS. 2 (a) to (c) for example, the size of the conductive particles 12,
  • the gap between the circuit board 10 and the semiconductor chip 20 is shown for convenience of explanation, and does not indicate the actual size or the like.
  • FIGS. 3 (a) and 3 (b) are graphs showing examples of the temperature profile in the heating step of the resin 13 and the pressure profile in the pressing step in the above-described flip-chip mounting method.
  • the resin 13 is heated to a temperature T at which bubbles 30 are generated from the bubble generating agent contained in the resin 13. This temperature T is maintained for a certain period of time t.
  • the resin 13 is pushed out of the bubble 30 and self-assembles in a columnar shape between the terminals facing each other.
  • the temperature T is, for example, 100 to 180 ° C
  • the constant time t is
  • it is set to about 5 to 10 seconds.
  • the semiconductor chip 20 is t-pressed against the circuit board 10 in the direction of the arrow at a pressure P for a predetermined time. This pressure causes self-collection between the opposing terminals.
  • the terminals are electrically connected. At this time, the resin 13 is maintained at a constant heating temperature T.
  • the pressure P is, for example, 70 to 200 kPa
  • the constant time t is, for example, about 0 to 5 seconds.
  • the resin 13 is heated to a temperature T at which the resin 13 is cured.
  • This temperature T is maintained for a certain period of time t, and the resin 13 remaining between the opposing terminals is cured.
  • the predetermined time t is set to about 10 to 20 seconds, for example.
  • Fig. 3 (a) the temperature profile shown in Fig. 3 (a) is such that the heating temperature at which the bubble generating agent force also generates bubbles 30 is maintained at a constant temperature T for time t (or t + t).
  • the temperature may be gradually increased.
  • FIG. 4 (a) shows a state in which the resin 13 is pushed out between the connection terminal 11 of the circuit board 10 and the electrode terminal 21 of the semiconductor chip 20 by the grown bubbles (not shown). It is a figure.
  • the resin 13 in contact with the connection terminal 11 and the electrode terminal 21 has a stress F ⁇ generated by the interfacial tension (force due to the soaking and spreading of the resin) Fs due to the viscosity of the resin 7 Therefore, it spreads over the entire surface of the connection terminal 11 and the electrode terminal 21, and finally, a columnar resin with the end portions of the terminals 11 and 12 as a boundary is formed. Therefore, even if the opposing positions of the connection terminal 11 and the electrode terminal 21 are slightly shifted, the resin 13 is surely self-adhered between the terminals by the interfacial tension. Can be assembled.
  • the shape can be maintained by the action of the direction stress F ⁇ , and the self-assembled resin 13 never disappears.
  • surface tension or gas-liquid interface tension acts on the boundary between the resin 13 and gas (for example, bubbles 30), and this surface tension also acts to maintain the shape of the columnar resin 13. obtain.
  • the growth of bubbles generated from the bubble generating agent is responsible for the self-assembly of the resin between the terminals.
  • it is effective to vary the gap (gap) between the circuit board 10 and the semiconductor chip 20 during the resin heating process.
  • FIGS. 5 (a) to 5 (c) show that during the heating process of the resin 13, bubbles are generated from the bubble generating agent contained in the resin 13 and the bubbles grow, thereby generating the resin.
  • FIG. 6 is a diagram showing an example in which the gap between the circuit board 10 and the semiconductor chip 20 is changed so that 13 is self-assembled between terminals.
  • FIG. 5 (a) shows a state where the resin 13 containing the conductive particles 12 and the bubble generating agent (not shown) is supplied to the gap between the circuit board 10 and the semiconductor chip 20.
  • the gap L between the circuit board 10 and the semiconductor chip 20 at this time is narrow! /.
  • a certain amount of the resin 13 can be self-assembled between the connection terminal 11 and the electrode terminal 21 efficiently.
  • FIG. 5 (c) shows terminals facing each other when the gap between the circuit board 10 and the semiconductor chip 20 is L.
  • One of the features of the flip chip mounting method of the present invention is that bubbles are generated from a bubble generating agent contained in the resin 13, and the bubbles grow, whereby the resin 13 is placed between the opposing terminals. The point is to self-assemble.
  • Fig. 1 (a) to (c) and Fig. 2 (a) to (c) only one type of bubble generating agent is shown. It can consist of a fee! /.
  • FIG. 6 is a diagram showing an example in which two types of bubble generating agents having different boiling points are contained in the resin 13, and shows a state in which bubbles are generated from the bubble generating agent by heating the resin 13. ing.
  • the bubble 30a which has a low boiling point V and also has the ability to generate a bubble generator, has a higher boiling point !, compared to the bubble 30b generated from the other bubble generator. ing.
  • the grown bubble 30b pushes the resin 13 out of the bubble by the growing pressure, and a part of the bubble 30b is carried between the connection terminal 11 of the circuit board 10 and the electrode terminal 21 of the semiconductor chip 20. There are also some fats 13 left behind. Therefore, the resin 13 can be efficiently transported between the terminals by repeating the operation of extruding the remaining resin 13 out of the bubbles again by the bubbles 30b that grow late. As a result, the resin 13 can be self-assembled between the terminals with good uniformity.
  • the resin 13, the conductive particles 12, and the bubble generating agent used in the flip chip mounting method of the present invention are not particularly limited, but the following materials can be used respectively. .
  • thermosetting resin such as an epoxy resin, a phenol resin, a silicone resin, or a thermoplastic resin can be used. It is preferable to have a viscosity that allows fluidization during the thermal process.
  • the conductive particles 12, Cu, Ag, AgCu, or the like can be used.
  • the electrical connection between the terminals is achieved by contact between the conductive particles, it is preferable to prevent the oxide film from growing on the surface of the conductive particles as much as possible. That's right. Further, it may be in a state in which only the surfaces of the conductive particles in contact with each other are melted to form a metal bond at the mutual interface.
  • the content of the conductive particles 12 in the resin 13 is preferably about 0.5 to 30% by volume, for example. Further, the content of the bubble generating agent in the resin 13 is preferably, for example, about 0.1 to 20% by weight.
  • the material shown in FIG. 7 can be used.
  • conductive particles 1 In the heating process for generating bubbles (gas such as H 0, CO, N) from the bubble generating agent, conductive particles 1
  • the bubble generating agent a material that generates bubbles by thermally decomposing the bubble generating agent when the resin is heated can also be used.
  • the materials shown in FIG. 8 can be used.
  • a compound containing water of crystallization aluminum hydroxide
  • the semiconductor chip 20 has a configuration (for example, CSP, BGA, etc.) in which a semiconductor chip is mounted on an interposer having a plurality of electrode terminals (lands). Also good. Further, the present invention can also be applied to inter-substrate connection in which electrodes between substrates each having a plurality of electrodes are electrically connected only by flip chip mounting. Inter-substrate connection can be performed by the following method.
  • a resin containing conductive particles and a bubble generating agent is supplied to a gap between a first substrate having a plurality of electrodes and a second substrate, and then the resin is heated. Then, bubbles are generated from the bubble generating agent contained in the resin. In this heating process, the resin is self-assembled between the electrode of the first substrate and the electrode of the second substrate by the bubbles generated from the bubble generating agent growing and being pushed out of the bubbles. .
  • the second substrate is pressed against the first substrate so that the conductive particles contained in the resin self-assembled between the opposing electrodes are brought into contact with each other.
  • the opposing electrodes can be electrically connected to each other.
  • the first and second substrates are fixed by curing the self-assembled resin between the electrodes, thereby completing the connection between the substrates.
  • a circuit board, a semiconductor wafer, a semiconductor chip (including a bare chip and a mounting chip), or the like can be used as the first substrate or the second substrate.
  • the various conditions or methods described in the above flip chip mounting method can be applied to the inter-substrate connection method.
  • the temperature profile in the heating step of the resin 13 can be applied to the profile shown in FIG. 3 (a), and the variation shown in FIG.
  • the materials described in the flip chip mounting method can be appropriately selected and used.
  • flip chip mounting method and the inter-substrate connection method according to the present invention have been described above, for example, an apparatus for manufacturing a flip chip mounting body by executing the flip chip mounting method is described. This can be realized by a flip chip mounting apparatus 40 as shown in FIG.
  • the flip chip mounting apparatus 40 includes a holding means 41 that holds the semiconductor chip 20 and the circuit board 10 facing each other with a certain gap, the semiconductor chip 20 and the circuit board.
  • the heating means 43 includes a first heating means 44 that controls heating to a temperature at which bubbles are generated from the bubble generating agent contained in the resin 13, and a second heating control that controls the temperature of the resin 13 to thermoset.
  • the heating means 45 is provided.
  • the holding means 41 is provided with an alignment mechanism for aligning the positions of the electrode terminals of the semiconductor chip 20 and the connection terminals of the circuit board 10.
  • the supply means 42 can be a dispenser or the like if the resin is pasty, and the heating means 43 is a heating stage (hot plate) or a heating box (oven) heated by hot air or infrared rays. ) Etc. can be used.
  • the resin 13 heated by the first heating means 44 is pushed out of the bubbles by the bubbles generated by the bubble generating agent force growing, and thereby the circuit board. It self-assembles between the 10 connection terminals 11 and the electrode terminal 21 of the semiconductor chip 20. Then, the semiconductor chip 20 is pressed against the circuit board 10 by the pressing means 46. Thus, the conductive particles 12 contained in the resin 13 self-assembled between the opposing electrodes are brought into contact with each other to complete the flip chip mounting body.
  • the method described here solders the terminals by a so-called reflow process, and therefore, even after sealing the grease, the dust is dispersed in the grease.
  • the conductive particles contained in the resin are brought into contact with each other to establish electrical connection between the terminals. This is a technology that is essentially different from the present invention.
  • Patent Document 7 and Non-Patent Document 1 only suggest the possibility of a process for selectively (self-assembling) bonding between opposing terminals, and are exclusively used for molten conductive particles. Since the agglomeration (self-assembly) is made between the terminals only by wettability, it is difficult to uniformly form the connection body formed between the terminals.
  • the resin containing the conductive particles can move the molten conductive particles freely. It does not serve as a “sea” to the extent that the conductive particles are bonded uniformly, and as a result, a uniform bonded body cannot be formed between the terminals.
  • a semiconductor chip having a large number of electrode terminals can be flip-chip mounted with a high yield, and a useful method applicable to a mass production process is provided. .

Description

明 細 書
フリップチップ実装方法および基板間接続方法
技術分野
[0001] 本発明は、半導体チップを回路基板に実装するフリップチップ実装方法、及び複 数の電極が形成された基板間を接続する基板間接続方法に関する。
背景技術
[0002] 近年、電子機器に使用される半導体集積回路 (LSI)の高密度、高集積化に伴い、 LSIチップの電極端子の多ピン、狭ピッチ化が急速に進んでいる。これら LSIチップ の回路基板への実装には、配線遅延を少なくするために、フリップチップ実装が広く 用いられている。そして、このフリップチップ実装においては、 LSIチップの電極端子 上にはんだバンプを形成し、当該はんだバンプを介して、回路基板上に形成された 接続端子に一括接合されるのが一般である。
[0003] し力しながら、電極端子数が 5, 000を超えるような次世代 LSIを回路基板に実装す るためには、 100 m以下の狭ピッチに対応したバンプを形成する必要がある力 現 在のはんだバンプ形成技術では、それに適応することが難しい。また、電極端子数に 応じた多数のバンプを形成する必要があるので、低コスト化を図るためには、チップ 当たりの搭載タクトの短縮による高い生産性も要求される。
[0004] 同様に、半導体集積回路は、電極端子の増大でペリフエラル電極端子力 エリア配 置の電極端子に変化している。また、高密度化、高集積化の要求で半導体プロセス 力 S90nmから 65nm、 45nmへと進展していくことが予想される。その結果、配線の微 細化が更に進み、配線間の容量が増大することにより、高速化、消費電力ロスの問 題が深刻になり、配線層間の絶縁膜の低誘電率化 (Low— K)の要求が更に高まつ ている。このような絶縁膜の Low— Kィ匕の実現は、絶縁層材料の多孔質化 (ポーラス ィ匕）によって得られるため、機械的強度が弱ぐ半導体の薄型化の障害になっている 。また、上述のように、エリア配置の電極端子を構成する場合、 Low— Kィ匕による多 孔質膜上の強度に問題があるため、エリア配置電極上にバンプを形成すること、およ びフリップチップ実装そのものが困難となっている。従って、今後の半導体プロセスの 進展に対応した薄型 ·高密度半導体に適した低荷重フリップチップ実装法が要求さ れている。
[0005] 従来、バンプの形成技術としては、メツキ法やスクリーン印刷法などが開発されてい る。メツキ法は狭ピッチには適するものの、工程が複雑になる点、生産性に問題があ り、また、スクリーン印刷法は、生産性には優れているが、マスクを用いる点で、狭ピッ チイ匕には適していない。
[0006] こうした中、最近では、 LSIチップや回路基板の電極上に、はんだバンプを選択的 に形成する技術力^、くつか開発されている。これらの技術は、微細バンプの形成に 適しているだけでなぐバンプの一括形成ができるので、生産性にも優れており、次 世代 LSIの回路基板への実装に適応可能な技術として注目されている。
[0007] 例えば、特許文献 1又は特許文献 2等に開示された技術は、導電性粒子とフラック スの混合物によるソルダーペーストを、表面に電極が形成された基板上にベタ塗りし 、基板を加熱することによって、導電性粒子を溶融させ、濡れ性の高い電極上に選 択的にはんだバンプを形成させるものである。
[0008] また、特許文献 3に開示された技術は、有機酸鉛塩と金属錫を主要成分とするベー スト状組成物 (化学反応析出型はんだ)を、電極が形成された基板上にベタ塗りし、 基板を加熱することによって、 Pbと Snの置換反応を起こさせ、 Pb/Snの合金を基板 の電極上に選択的に析出させるものである。
[0009] し力しながら、上記特許文献 1乃至 3に開示された技術は、いずれも、ペースト状組 成物を基板上に塗布により供給するので、局所的な厚みや濃度のバラツキが生じ、 そのため、電極ごとのはんだ析出量が異なり、均一な高さのバンプが得られない。ま た、これらの方法は、表面に電極の形成された凹凸のある回路基板上に、ペースト状 組成物を塗布により供給するので、凸部となる電極上には、十分なはんだ量が供給 できず、フリップチップ実装において必要とされる所望のバンプ高さを得ることが難し い。
[0010] ところで、従来のバンプ形成技術を用いたフリップチップ実装は、バンプが形成され た回路基板に半導体チップを搭載した後、半導体チップを回路基板に固定するため に、アンダーフィルと呼ばれる榭脂を、半導体チップと回路基板の間に注入する工程 をさらに必要とする。
[0011] そこで、半導体チップと回路基板の対向する電極端子間の電気的接続と、半導体 チップの回路基板への固定を同時に行なう方法として、異方性導電材料を用いたフ リップチップ実装技術 (例えば、特許文献 4参照）が開発されている。これは、回路基 板と半導体チップの間に、導電粒子を含有させた熱硬化性榭脂を供給し、半導体チ ップを押圧すると同時に、熱硬化性榭脂を加熱することによって、半導体チップと回 路基板の電極端子間の電気的接続と、半導体チップの回路基板への固定を同時に 実現するものである。
特許文献 1 :特開 2000— 94179号公報
特許文献 2：特開平 6 - 125169号公報
特許文献 3：特開平 1― 157796号公報
特許文献 4：特開 2000— 332055号公報
特許文献 5：特開 2002 - 26070号公報
特許文献 6：特開平 11― 186334号公報
特許文献 7：特開 2004— 260131号公報
非特許文献 1：安田真大他，「低融点金属フィラー含有榭脂による自己組織化接合プ ロセス」，第 10回「エレクトロニクスにおけるマイクロ接合'実装技術」シンポジウム（10t h Symposium on icrojoing and Assembly Technology in Electronics ) , 183— 188 頁， 2004年
発明の開示
発明が解決しょうとする課題
[0012] 異方性導電材料を用いたフリップチップ実装は、半導体チップと回路基板の電極 端子間の電気的接続と、半導体チップの回路基板への固定を同時に実現するものと して生産性に優れて 、ると言える力 以下のような課題がある。
[0013] 上記異方性導電材料は、榭脂中に導電粒子が均一に分散されているが、半導体 チップを回路基板に押圧することによって、分散された導電粒子が、半導体チップと 回路基板の電極端子に物理的に接触し、これにより、対向する電極端子間の電気的 な接続を可能にする一方、異方性導電材料の榭脂によって、隣接する電極端子間 の絶縁性を確保している。
[0014] し力しながら、導電粒子は榭脂中に均一に分散されているため、対向する電極端 子間の導通に寄与している導電粒子は、その一部に過ぎず、安定した導通状態を得 ることが難しぐ電気的接続に十分な信頼性が得られないという問題がある。また、た とえ隣接する電極端子間は榭脂で絶縁されているとしても、対向する電極端子間の 導通に寄与して 、な 、導電粒子が榭脂中に分散されて!、るので、十分な絶縁性が 確保できな 、可能性もある。
[0015] すなわち、異方性導電材料を用いたフリップチップ実装は、接続端子数が 5, 000 を超えるような次世代 LSIチップに適用するためには、信頼性の面で解決すべき課 題を残している。
[0016] 本発明は、力かる点に鑑みてなされたもので、次世代 LSIのフリップチップ実装に 適用可能な、生産性及び信頼性の高いフリップチップ実装方法、及び当該方法と基 本工程を一にする基板間接続方法を提供することを目的とする。
課題を解決するための手段
[0017] 本発明のフリップチップ実装方法は、複数の接続端子を有する回路基板に対向さ せて、複数の電極端子を有する半導体チップを配置し、回路基板の接続端子と半導 体チップの電極端子とを電気的に接続するフリップチップ実装方法において、回路 基板と半導体チップとの隙間に、導電性粒子と気泡発生剤を含有した榭脂を供給す る第 1の工程と、榭脂を加熱して、榭脂中に含有する気泡発生剤から気泡を発生さ せる第 2の工程と、半導体チップを、回路基板に押圧する第 3の工程と、榭脂を硬化 する第 4の工程とを含み、第 2の工程において、榭脂は、気泡発生剤から発生した気 泡が成長することで該気泡外に押し出されることによって、回路基板の接続端子と半 導体チップの電極端子との間に自己集合し、第 3の工程において、端子間に自己集 合した榭脂中に含有する導電性粒子同士が互いに接触することによって、端子間を 電気的に接続し、第 4の工程において、端子間の榭脂を硬化することによって、半導 体チップを回路基板に固定することを特徴とする。
[0018] ここで、上記気泡発生剤は、榭脂が加熱されたときに沸騰する材料力もなることが 好ましい。また、気泡発生剤は、沸点の異なる 2種類以上の材料力もなるものであつ てもよい。さらに、気泡発生剤は、榭脂が加熱されたときに、気泡発生剤が熱分解す ることにより気体を発生する材料力もなるものであってもよい。例えば、気泡発生剤は 、結晶水を含む化合物からなり、榭脂が加熱されたとき分解されて水蒸気を発生する
[0019] ある好適な実施形態において、上記第 2の工程は、回路基板と半導体チップとの隙 間の間隔を変動させながら実行される。
[0020] ある好適な実施形態において、上記第 1の工程は、回路基板上に、導電性粒子と 気泡発生剤を含有した榭脂を供給した後、該榭脂表面に前記半導体チップを配設 すること〖こより実行される。
[0021] ある好適な実施形態において、上記第 4の工程は、榭脂を加熱して、該榭脂を熱 硬化させることにより行なわれる。また、第 4の工程の後、回路基板と半導体チップと の隙間にアンダーフィル材を供給し、然る後、該アンダーフィル材を硬化させる工程 をさらに含むものであってもよい。
[0022] ある好適な実施形態において、上記複数の電極端子を有する半導体チップは、半 導体ベアチップが複数の電極端子を有するインターポーザに搭載された構成になつ ている。
[0023] 本発明の基板間接続方法は、複数の電極を有する第 1の基板に対向させて、複数 の電極を有する第 2の基板を配置し、第 1の基板の電極と第 2の基板の電極とを電気 的に接続する基板間接続方法において、第 1の基板と第 2の基板との隙間に、導電 性粒子と気泡発生剤を含有した榭脂を供給する第 1の工程と、榭脂を加熱して、榭 脂中に含有する気泡発生剤力 気泡を発生させる第 2の工程と、第 2の基板を、第 1 の基板に押圧する第 3の工程と、榭脂を硬化する第 4の工程とを含み、第 2の工程に おいて、榭脂は、気泡発生剤から発生した気泡が成長することで該気泡外に押し出 されること〖こよって、第 1の基板の電極と第 2の基板の電極間に自己集合し、第 3のェ 程において、電極間に自己集合した榭脂中に含有する導電性粒子同士が互いに接 触すること〖こよって、電極間を電気的に接続し、第 4の工程において、電極間に自己 集合した榭脂を硬化することによって、第 1の基板を第 2の基板に固定することを特 徴とする。 [0024] ここで、上記気泡発生剤は、榭脂が加熱されたときに沸騰する材料力もなることが 好ましい。
[0025] ある好適な実施形態において、上記第 2の工程は、第 1の基板と第 2の基板との隙 間の間隔を変動させながら実行される。
[0026] ある好適な実施形態において、上記第 1の工程は、第 1の基板上に、導電性粒子と 気泡発生剤を含有した榭脂を供給した後、該榭脂表面に前記第 2の基板を配設する こと〖こより実行される。
[0027] ある好適な実施形態において、上記第 4の工程の後、第 1の基板と第 2の基板との 隙間にアンダーフィル材を供給し、然る後、該アンダーフィル材を硬化させること工程 をさらに含む。
[0028] 本発明のフリップチップ実装体は、複数の接続端子を有する回路基板に対向させ て、複数の電極端子を有する半導体チップを配置され、回路基板の接続端子と半導 体チップの電極端子とが電気的に接続されたフリップチップ実装体において、接続 端子と電極端子は、回路基板と半導体チップとの隙間に供給された導電性粒子と気 泡発生剤を含有する榭脂が、接続端子と電極端子間に自己集合し、該自己集合し た榭脂中の導電性粒子同士が接触することによって、電気的に接続されていることを 特徴とする。
[0029] ある好適な実施形態にぉ 、て、上記フリップチップ実装体は、回路基板と半導体チ ップとの隙間に供給されたアンダーフィル材で固定されて 、る。
[0030] 本発明のフリップチップ実装装置は、半導体チップを回路基板にフリップチップ実 装するフリップチップ実装装置であって、半導体チップ及び回路基板を、一定の隙間 をもって互いに対向させて保持する保持手段と、半導体チップと回路基板との隙間 に、導電性粒子と気泡発生剤を含有した榭脂を供給する供給手段と、榭脂を加熱す る加熱手段と、半導体チップを回路基板に押圧する押圧手段とを備え、加熱手段は 、榭脂中に含有する気泡発生剤から気泡を発生させる温度に制御する第 1の加熱手 段と、榭脂を熱硬化させる温度に制御する第 2の加熱手段を有していることを特徴と する。
[0031] ある好適な実施形態において、上記第 1の加熱手段で加熱された榭脂は、気泡発 生剤から発生した気泡が成長することで該気泡外に押し出されることによって、回路 基板の接続端子と半導体チップの電極端子との間に自己集合し、押圧手段により半 導体チップを回路基板に押圧することによって、端子間に自己集合した榭脂中に含 有する導電性粒子同士が互いに接触し、端子間に電気的な接続がなされ、第 2の加 熱手段により榭脂を加熱することによって、榭脂中に含有する導電性粒子同士が互 いに接触した状態で、半導体チップを前記回路基板に固定される。
発明の効果
[0032] 本発明に係るフリップチップ実装方法は、回路基板と半導体チップの隙間に供給さ れた導電性粒子と気泡発生剤を含有した榭脂を加熱することによって、気泡発生剤 から気泡を発生させ、当該気泡が成長することで榭脂を気泡外に押し出すことにより 、当該榭脂を回路基板の接続端子と半導体チップの電極端子との間に自己集合さ せることができる。そして、半導体チップを回路基板に押圧することによって、対向す る端子間に自己集合した榭脂中に含有する導電性粒子同士を互いに接触させて、 端子間を電気的に接続することができる。これにより、榭脂中に分散した導電性粒子 を効率よく端子間に自己集合させ、端子間の導電に寄与させることができるので、安 定した導通状態が得られ、信頼性の高！、電気的接続が達成できる。
[0033] また、同様に、本発明に係る基板間接続法においても、対向する基板間に供給さ れた導電性粒子と気泡発生剤を含有した榭脂を加熱することによって、気泡発生剤 から気泡を発生させ、当該気泡が成長することで榭脂を気泡外に押し出すことにより 、当該榭脂を対向する基板の電極間に自己集合させることができる。そして、基板同 士を押圧することによって、電極間に自己集合した榭脂中に含有する導電性粒子同 士を互いに接触させて、電極間を電気的に接続することができる。これにより、榭脂 中に分散した導電性粒子を効率よく電極間に自己集合させ、電極間の導電に寄与さ せることができるので、安定した導通状態が得られ、信頼性の高い基板間接続が達 成できる。
図面の簡単な説明
[0034] [図 1]図 1 (a)〜 (d)は、本発明の実施形態におけるフリップチップ実装方法を示すェ 程断面図である。 圆 2]図 2 (a)〜 (c)は、本発明の実施形態におけるフリップチップ実装方法を示すェ 程断面図である。
圆 3]図 3 (a)は、本発明における榭脂の加熱温度プロファイルを示す図、図 3 (b)は 半導体チップを回路基板に押力したときの圧力プロファイルを示す図である。
圆 4]図 4 (a)、 (b)は、本発明における榭脂の自己集合のメカニズムを説明するため の図である。
[図 5]図 5 (a)〜 (c)は、本発明における回路基板と半導体チップのギャップを変動さ せながら加熱する工程を説明する工程断面図である。
[図 6]図 6は、本発明における 2種類以上の気泡発生剤を含む樹脂の自己集合を説 明するための図である。
[図 7]図 7は、本発明における気泡発生剤の材料を示す図である。
[図 8]図 8は、本発明における加熱分解する気泡発生剤粉の材料を示す図である。
[図 9]図 9は、本発明におけるフリップチップ実装装置の構成を示すブロック図である 符号の説明
10 回路基板
11 接続端子
12 導電性粒子
13 樹脂
14 アンダーフィル材
20 半導体チップ
21 電極端子
30, 30a, 30b 気泡
40 フリップチップ実装装置
41 保持手段
42 供給手段
43 加熱手段
44 第 1の加熱手段 45 第 2の加熱手段
46 押圧手段
発明を実施するための最良の形態
[0036] 以下に、本発明の実施の形態について、図面を参照しながら説明する。以下の図 面においては、説明の簡略化のため、実質的に同一の機能を有する構成要素を同 一の参照符号で示す。本発明は以下の実施形態に限定されない。
[0037] 図 1 (a)〜（d)、及び図 2 (a)〜（c)は、本発明の実施形態におけるフリップチップ実 装方法の基本的な工程を示した工程断面図である。
[0038] まず、図 1 (a)に示すように、複数の接続端子 11を有する回路基板 10上に、導電 性粒子 (例えば、 Cu等） 12と気泡発生剤（例えば、イソプロピルアルコール等）を含 有した榭脂 (例えば、エポキシ榭脂等） 13を供給する。次に、図 1 (b)に示すように、 榭脂 13表面に、複数の電極端子 21を有する半導体チップ 20を、回路基板 10に対 向させて配設する。このとき、半導体チップ 20の電極端子 21は、回路基板 10の接続 端子 11に位置合わせされて!/、る。
[0039] なお、ここに示した工程は、先に、回路基板 10と半導体チップ 20を一定の隙間（例 えば、 10〜80 /ζ πι)を設けて互いに対向させて配置し、然る後、導電性粒子 12と気 泡発生剤を含有した榭脂 13を、この隙間に供給してもよい。
[0040] この状態で、榭脂 13を所定の温度 (例えば、 100〜150°C)に加熱すると、図 1 (c) に示すように、榭脂 13中に含有する気泡発生剤から気泡 30が発生する。発生した 気泡 30は、図 1 (d)に示すように、徐々に成長し、成長した気泡 30によって、榭脂 13 は、この気泡 30外に押し出される。
[0041] 押し出された榭脂 13は、図 2 (a)に示すように、回路基板 10の接続端子 11と半導 体チップ 20の電極端子 21間に柱状 (例えば、略円柱状）に自己集合する。このとき、 端子間に自己集合しな力つた榭脂 13のほとんどは、成長した気泡 30の圧力によって 、回路基板 10と半導体チップ 20の隙間から外部に押し出される。
[0042] 次に、この状態で、図 2 (b)に示すように、半導体チップ 20を回路基板 10に矢印の 方向に押圧する。ここで、押圧の大きさは、例えば、 20k〜200kPa程度に設定され る。この押圧により、対向する端子間に自己集合した榭脂 13中に含有する導電性粒 子 12同士が互いに接触することによって、端子間を電気的に接続する。このとき、端 子間には、少なくとも一つ以上の導電性粒子 12が介在した状態で、端子間の電気 的接続を図っている。なお、押圧の際、榭脂 13中に含有する導電性粒子 12は、榭 脂 13の粘性による応力が働くので、榭脂 13外に流出することはな 、。
[0043] この状態で、図 2 (c)に示すように、対向する端子間に自己集合した榭脂 13を硬化 させることによって、半導体チップ 20を回路基板 10に固定させる。榭脂 13は、端子 面全体に拡がっているので、半導体チップ 20を回路基板 10に固定するには十分で あるが、必要に応じて、半導体チップ 20と回路基板 10の隙間にアンダーフィル材 14 を注入し、然る後、アンダーフィル材 14を硬化させて、半導体チップ 20の回路基板 1 0への固定をさらに強化してもよい。なお、アンダーフィル材 14の供給は、半導体チ ップ 20を回路基板 10に押圧する前に行なってもよい。
[0044] 本発明によれば、回路基板 10と半導体チップ 20の隙間に供給された導電性粒子 12と気泡発生剤を含有した榭脂 13を加熱することによって、気泡発生剤から気泡を 発生させ、当該気泡が成長することで榭脂 13を気泡外に押し出すことにより、榭脂 1 3を回路基板 10の接続端子 11と半導体チップ 20の電極端子 21との間に自己集合 させることができる。そして、半導体チップ 20を回路基板 10に押圧することによって、 対向する端子間に自己集合した榭脂 13中に含有する導電性粒子 12同士を互いに 接触させて、端子間を電気的に接続することができる。これにより、榭脂 13中に分散 した導電性粒子 12を効率よく端子間に自己集合させ、端子間の導電に寄与させるこ とができるので、安定した導通状態が得られ、信頼性の高い電気的接続が達成でき る。
[0045] ここで、図 1 (a)〜（d)、及び図 2 (a)〜（c)に示した各構成の大きさや相対的な位置 関係 (例えば、導電性粒子 12の大きさや、回路基板 10と半導体チップ 20との隙間の 間隔等）は、説明を容易にするために便宜的に現されたもので、実際の大きさ等を示 したものではない。
[0046] 図 3 (a)及び (b)は、上記のフリップチップ実装方法において、榭脂 13の加熱工程 における温度プロファイル、及び押圧工程における圧力プロファイルの一例をそれぞ れ示したグラフである。 [0047] 図 3 (a)に示すように、まず、榭脂 13を、榭脂 13中に含有する気泡発生剤から気泡 30が発生する温度 Tに加熱する。この温度 Tを一定時間 t保持し、この間、発生し
1 1 1
た気泡 30が成長することによって、榭脂 13が気泡 30外に押し出され、対向する端子 間に柱状に自己集合する。ここで、温度 Tは、例えば、 100〜180°C、一定時間 tは
1 1
、例えば、 5〜10秒程度に設定される。
[0048] 次に、この状態で、図 3 (b)に示すように、半導体チップ 20を回路基板 10に矢印の 方向に圧力 Pで、一定時間 t押圧する。この押圧により、対向する端子間に自己集
1 2
合した榭脂 13中に含有する導電性粒子 12同士が互いに接触することによって、端 子間を電気的に接続する。なお、このときの榭脂 13は、一定の加熱温度 Tに維持さ
1 れる。ここで、圧力 Pは、例えば、 70〜200kPa、一定時間 tは、例えば、 0〜5秒程
1 2
度に設定される。
[0049] そして、最後に、図 3 (a)に示すように、榭脂 13を、榭脂 13が硬化する温度 Tにカロ
3 熱する。この温度 Tを一定時間 t保持し、対向する端子間に残存する榭脂 13を硬化
3 3
させることによって、半導体チップ 20を回路基板 10に固定させる。ここで、温度 Tは
3
、例えば、 150〜250°C、一定時間 tは、例えば、 10〜20秒程度に設定される。
3
[0050] なお、図 3 (a)に示した温度プロファイルは、気泡発生剤力も気泡 30を発生させる 加熱温度を、時間 t (または t +tの時間）の間、一定温度 Tに保つようにしているが
1 1 2 1
、この間、徐々に温度を上昇させていってもよい。
[0051] ここで、本発明のフリップチップ実装方法において、そのポイントとなる榭脂 13の端 子間への自己集合について、図 4 (a)、（b)を参照しながら、そのメカニズムを簡単に 説明する。
[0052] 図 4 (a)は、榭脂 13が、成長した気泡 (不図示）によって、回路基板 10の接続端子 1 1と半導体チップ 20の電極端子 21との間に押し出された状態を示した図である。接 続端子 11及び電極端子 21に接した榭脂 13は、その界面における界面張力（いわゆ る榭脂の濡れ広がりに起因する力） Fsが、榭脂の粘度 7?から発生する応力 F ηよりも 大きいので、接続端子 11及び電極端子 21の全面に亙って広がり、最終的に、端子 1 1、 12の端部を境とした柱状樹脂が形成される。そのため、接続端子 11と電極端子 2 1の対向する位置が多少ずれていても、確実に榭脂 13を端子間に界面張力で自己 集合させることができる。
[0053] なお、端子間に自己成長して形成された柱状の榭脂 13には、図 4 (b)に示すように 、気泡 30の成長（または移動）による応力 Fが加わる力 榭脂 13の粘度 7?による逆 b
向きの応力 F ηの作用により、その形状を維持することができ、一旦自己集合した榭 脂 13が消滅することはない。また、榭脂 13と気体 (例えば気泡 30)との境界には、表 面張力（又は、気 液の界面張力）が働いており、この表面張力も柱状の榭脂 13の 形状維持に作用し得る。
[0054] 上述のように、本発明のフリップチップ実装方法においては、気泡発生剤から発生 する気泡の成長が、榭脂を端子間に自己集合させる作用を担うものであるが、さらに 、その作用効果を高めるために、榭脂の加熱工程中において、回路基板 10と半導 体チップ 20との隙間の間隔 (ギャップ)を変動させることが有効である。
[0055] 図 5 (a)〜(c)は、榭脂 13の加熱工程の中で、榭脂 13中に含有する気泡発生剤か ら気泡を発生させ、当該気泡が成長することで榭脂 13を端子間に自己集合させるェ 程にぉ 、て、回路基板 10と半導体チップ 20とのギャップを変動させる例を示した図 である。
[0056] 図 5 (a)は、回路基板 10と半導体チップ 20との隙間に、導電性粒子 12と気泡発生 剤 (不図示)を含有する榭脂 13を供給した状態を示したものであるが、このときの回 路基板 10と半導体チップ 20のギャップ Lは狭くなつて!/、る。
1
[0057] この状態から、図 5 (b)に示すように、回路基板 10と半導体チップ 20のギャップ Lを
2 広げながら、榭脂 13を加熱する。この加熱工程において、気泡発生剤から発生した 気泡 30は、徐々に成長していくが、その過程で、回路基板 10と半導体チップ 20のギ ヤップ Lも広がっていくので、当初、回路基板 10と半導体チップ 20との隙間に供給さ
2
れた一定の量の榭脂 13を、効率よく接続端子 11と電極端子 21間に自己集合させる ことができる。
[0058] 図 5 (c)は、回路基板 10と半導体チップ 20のギャップが Lの時点で、対向する端子
3
間に自己集合した榭脂 13の状態を示したもので、隣接する端子間には、榭脂 13は ほとんど残存しない。これは、端子間に自己集合しな力つた榭脂 13のほとんど力 成 長した気泡 30の圧力によって、回路基板 10と半導体チップ 20の隙間力も外部に押 し出されたこと〖こよる。
[0059] なお、図 5 (a)〜（c)では、加熱工程において、回路基板 10と半導体チップ 20のギ ヤップを広げる例を説明した力 ギャップを周期的に変動させながら行なっても、同様 の作用効果を得ることができる。
[0060] 本発明のフリップチップ実装方法の特徴の一つは、榭脂 13中に含有する気泡発生 剤から気泡を発生させ、当該気泡が成長することによって、榭脂 13を対向する端子 間に自己集合させる点にある。図 1 (a)〜（c)、及び図 2 (a)〜（c)に示した例では、 気泡発生剤として、 1種類のものを示したが、例えば、沸点の異なる 2種類以上の材 料からなるものであってもよ！/、。
[0061] 図 6は、沸点の異なる 2種類の気泡発生剤が榭脂 13中に含有された例を示した図 で、榭脂 13を加熱し、気泡発生剤から気泡が発生した状態を示している。沸点の低 V、方の気泡発生剤力も発生した気泡 30aは、沸点の高!、方の気泡発生剤から発生 した気泡 30bに比べて、気泡の成長が時間的に進んでいる分、大きくなつている。
[0062] 成長した気泡 30bは、その成長する圧力によって、榭脂 13を気泡外に押し出し、そ の一部を、回路基板 10の接続端子 11と半導体チップ 20の電極端子 21との間に運 ぶことができるが、後に取り残された榭脂 13もある。そこで、この取り残された榭脂 13 を、遅れて成長する気泡 30bによって、再び、気泡外に押し出す動作を繰り返すこと によって、効率よく榭脂 13を端子間に運ぶようにすることができる。これにより、榭脂 1 3を端子間に均一性よく自己集合させることができる。
[0063] ここで、本発明のフリップチップ実装方法に使用する榭脂 13、導電性粒子 12、及 び気泡発生剤は、特に限定されないが、それぞれ、以下のような材料を使用すること ができる。
[0064] 榭脂 13としては、エポキシ榭脂、フエノール榭脂、シリコーン榭脂等の熱硬化性榭 脂、あるいは、熱可塑性榭脂等を使用することができるが、少なくとも、榭脂 13の加 熱工程にぉ 、て、流動可能な程度の粘度を有して 、ることが好ま 、。
[0065] また、導電性粒子 12としては、 Cu、 Ag、 AgCu等を使用することができる。なお、本 発明においては、導電性粒子同士の接触によって端子間の電気的接続を図ることか ら、導電性粒子の表面には、できるだけ酸ィ匕膜が成長しないようにしておくことが好ま しい。また、互いに接触する導電性粒子同士の表面だけ溶融して、互いの界面で金 属結合をなすような状態であってもよい。なお、導電性粒子 12の榭脂 13中の含有率 は、例えば、 0. 5〜30体積％程度が好ましい。また、気泡発生剤の榭脂 13中の含 有率は、例えば、 0. 1〜20重量％程度が好ましい。
[0066] 気泡発生剤としては、図 7に示した材料を使用することができる。なお、気泡発生剤 から気泡 (H 0、 CO、 N等の気体)を発生させる加熱工程において、導電性粒子 1
2 2 2
2が溶融しないように、気泡発生時の沸点が、導電性粒子 12の融点よりも低い材料を 選択する必要がある。
[0067] なお、気泡発生剤として、榭脂が加熱されたときに、気泡発生剤が熱分解すること により気泡を発生する材料も使用することができる。そのような気泡発生剤としては、 図 8に挙げた材料を使用することができる。例えば、結晶水を含む化合物（水酸化ァ ルミ-ゥム)を使用した場合、榭脂が加熱されたときに熱分解し、水蒸気が気泡となつ て発生する。
[0068] 以上説明したフリップチップ実装方法において、半導体チップ 20は、半導体べァチ ップが複数の電極端子 (ランド)を有するインターポーザに搭載された構成 (例えば、 CSP、 BGA等)であってもよい。また、本発明は、フリップチップ実装だけでなぐそ れぞれ複数の電極を有する基板同士の電極間を電気的に接続する基板間接続にも 適用することができる。基板間接続は、以下の方法で行うことができる。
[0069] まず、複数の電極を有する第 1の基板と第 2の基板との隙間に、導電性粒子と気泡 発生剤を含有した榭脂を供給し、然る後、当該榭脂を加熱して、榭脂中に含有する 気泡発生剤から気泡を発生させる。この加熱工程で、榭脂は、気泡発生剤から発生 した気泡が成長することで、当該気泡外に押し出されることによって、第 1の基板の電 極と第 2の基板の電極間に自己集合する。
[0070] 次に、第 2の基板を、第 1の基板に押圧して、対向する電極間に自己集合した榭脂 中に含有する導電性粒子同士を互いに接触させる。これにより、対向する電極間を 電気的〖こ接続させることができる。
[0071] 最後に、電極間に自己集合した榭脂を硬化することによって、第 1の基板と第 2の 基板を固定し、基板間接続を完成させる。 [0072] ここで、第 1の基板又は第 2の基板としては、回路基板、半導体ウェハ、半導体チッ プ (ベアチップ、実装チップを含む)等を使用することができる。
[0073] なお、この基板間接続方法にぉ 、ても、上記のフリップチップ実装方法で説明した 種々の条件又は方法を適用することができる。例えば、榭脂 13の加熱工程における 温度プロファイルは、図 3 (a)に示したプロファイルを、また、基板間のギャップの変動 については、図 5に示した方法を、それぞれ適用することができる。
[0074] また、使用する榭脂 13、導電性粒子 12、気泡発生剤についても、フリップチップ実 装方法で説明した材料を適宜選んで使用することができる。
[0075] 以上、本発明に係るフリップチップ実装方法、及び基板間接続方法につ!ヽて説明 してきたが、例えば、フリップチップ実装方法を実行して、フリップチップ実装体を製 造する装置は、図 9に示すようなフリップチップ実装装置 40で実現することができる。
[0076] 図 9のブロック図に示すように、フリップチップ実装装置 40は、半導体チップ 20と回 路基板 10を、一定の隙間をもって互いに対向させて保持する保持手段 41、半導体 チップ 20と回路基板 10との隙間に、導電性粒子 12と気泡発生剤を含有した榭脂 13 を供給する供給手段 42、榭脂 13を加熱する加熱手段 43、及び半導体チップ 20を 回路基板 10に押圧する押圧手段 46とで構成されている。また、加熱手段 43は、榭 脂 13中に含有する気泡発生剤から気泡を発生させる温度に加熱制御する第 1の加 熱手段 44と、榭脂 13を熱硬化する温度に加熱制御する第 2の加熱手段 45を有して いる。
[0077] ここで、保持手段 41には、半導体チップ 20の電極端子と、回路基板 10の接続端 子との位置を合わせるァライメント機構が付いている。また、供給手段 42は、榭脂が ペースト状であれば、デイスペンサ等を用いることができ、加熱手段 43は、加熱ステ ージ（ホットプレート）や、熱風や赤外線によって加熱される加熱ボックス（オーブン） 等が使用できる。
[0078] このフリップチップ実装装置 40において、第 1の加熱手段 44で加熱された榭脂 13 は、気泡発生剤力 発生した気泡が成長することで、当該気泡外に押し出されること によって、回路基板 10の接続端子 11と半導体チップ 20の電極端子 21との間に自 己集合する。そして、押圧手段 46により、半導体チップ 20を回路基板 10に押圧する こと〖こよって、対向する電極間に自己集合した榭脂 13中に含有する導電性粒子 12 同士を互いに接触させ、フリップチップ実装体を完成させる。
[0079] ところで、はんだ粉 (導電性粒子)を含有させた榭脂を用いて、半導体チップと回路 基板との対向する端子間の電気的接続と、半導体チップの回路基板への固定を同 時に行なう方法が、特許文献 5 (特開 2002— 26070号公報）、及び特許文献 6 (特 開平 11 186334号公報）に記載されている。ここに記載された方法は、榭脂中に 含有させたはんだ粉を溶融することによって、半導体チップ及び回路基板の対向す る端子が当接する部位を半田付けするとともに、その後、榭脂を硬化することによつ て、半導体チップを回路基板に封止、固定するもので、一見、本発明と類似した技術 のようにも見える。し力しながら、ここに記載された方法は、いわゆるリフロー処理によ つて端子間をはんだ付けするもので、従って、榭脂封止後においても、榭脂中には んだ粉は分散されており、本発明のように、導電性粒子を含有する榭脂を対向する 端子間に自己集合させた後、榭脂中に含有する導電性粒子同士を互いに接触させ て端子間の電気的接続を図るものではなぐ本発明とは本質的に異なる技術である。
[0080] また、導電性粒子 (低融点金属フィラー)を含有させた榭脂を用いて、半導体チップ と回路基板の対向する端子間の電気的接続と、半導体チップの回路基板への固定 を同時に行なう方法が、特許文献 7 (特開 2004— 260131号公報）、及び非特許文 献 1 (安田真大他， 「低融点金属フィラー含有榭脂による自己組織ィ匕接合プロセス」 , 第 10回「エレクトロニクスにおけるマイクロ接合'実装技術」シンポジウム（10th Sympos mm on icrojoing and Assembly Technology in Electronics ) , 183— 188頁, 2004 年）に記載されている。ここには、酸ィ匕還元能力を有する榭脂を用いて、榭脂中に含 有する溶融した金属フィラーの凝集や濡れに基づいて、選択的に端子間に導電性 粒子が自己組織化した接続体を形成する技術が開示されている。
[0081] しかしながら、特許文献 7及び非特許文献 1は、対向する端子間を選択的（自己集 合的）に接合を行うプロセスの可能性を示唆するに止まり、もっぱら、溶融した導電性 粒子の濡れ性のみによって端子間に凝集（自己集合)させているので、端子間に形 成される接続体を均一に形成することは難しい。
[0082] 本発明は、導電性粒子を含有する榭脂が、溶融した導電性粒子が自由に移動でき るほどの"海"の役目を果たすものではないために、導電性粒子の結合過程が均一 に進行せず、その結果、端子間に均一な接合体を形成することができないという認識 のもとになされたもので、本発明による方法を適用することによって、多数の電極端子 を有する半導体チップを歩留まりよくフリップチップ実装することができ、量産工程に 適用可能な有用な方法を提供するものである。
[0083] 以上、本発明を好適な実施形態により説明してきたが、こうした記述は限定事項で はなぐ勿論、種々の改変が可能である。
産業上の利用可能性
[0084] 本発明によれば、次世代 LSIのフリップチップ実装に適用可能な、生産性及び信 頼性の高 ヽフリップチップ実装方法、及び基板間接続方法を提供することができる。

Claims

請求の範囲
[1] 複数の接続端子を有する回路基板に対向させて、複数の電極端子を有する半導 体チップを配置し、前記回路基板の接続端子と前記半導体チップの電極端子とを電 気的に接続するフリップチップ実装方法において、
前記回路基板と前記半導体チップとの隙間に、導電性粒子と気泡発生剤を含有し た榭脂を供給する第 1の工程と、
前記榭脂を加熱して、前記榭脂中に含有する前記気泡発生剤から気泡を発生させ る第 2の工程と、
前記半導体チップを、前記回路基板に押圧する第 3の工程と、
前記榭脂を硬化する第 4の工程と
を含み、
前記第 2の工程において、前記榭脂は、前記気泡発生剤から発生した気泡が成長 することで該気泡外に押し出されることによって、前記回路基板の接続端子と前記半 導体チップの電極端子間に自己集合し、
前記第 3の工程において、前記端子間に自己集合した前記榭脂中に含有する導 電性粒子同士が互いに接触することによって、前記端子間を電気的に接続し、 前記第 4の工程において、前記端子間の前記榭脂を硬化することによって、前記半 導体チップを前記回路基板に固定することを特徴とするフリップチップ実装方法。
[2] 前記気泡発生剤は、前記樹脂が加熱されたときに沸騰する材料力もなることを特徴 とする、請求項 1に記載のフリップチップ実装方法。
[3] 前記気泡発生剤は、沸点の異なる 2種類以上の材料力もなることを特徴とする、請 求項 1に記載のフリップチップ実装方法。
[4] 前記気泡発生剤は、前記樹脂が加熱されたときに、前記気泡発生剤が熱分解する ことにより気体を発生する材料力もなることを特徴とする、請求項 1に記載のフリップ チップ実装方法。
[5] 前記気泡発生剤は、結晶水を含む化合物からなり、前記樹脂が加熱されたとき分 解されて水蒸気を発生することを特徴とする、請求項 4に記載のフリップチップ実装 方法。
[6] 前記第 2の工程は、前記回路基板と前記半導体チップとの隙間の間隔を変動させ ながら実行されることを特徴とする、請求項 1に記載のフリップチップ実装方法。
[7] 前記第 1の工程は、前記回路基板上に、前記導電性粒子と気泡発生剤を含有した 榭脂を供給した後、該榭脂表面に前記半導体チップを配設することにより実行される ことを特徴とする、請求項 1に記載のフリップチップ実装方法。
[8] 前記第 4の工程は、前記榭脂を加熱して、該榭脂を熱硬化させることにより行なわ れることを特徴とする、請求項 1に記載のフリップチップ実装方法。
[9] 前記第 4の工程の後、前記回路基板と前記半導体チップとの隙間にアンダーフィル 材を供給し、然る後、該アンダーフィル材を硬化させること工程をさらに含むことを特 徴とする、請求項 1に記載のフリップチップ実装方法。
[10] 前記複数の電極端子を有する半導体チップは、半導体ベアチップが前記複数の 電極端子を有するインターポーザに搭載された構成になっていることを特徴とする、 請求項 1に記載のフリップチップ実装方法。
[11] 複数の電極を有する第 1の基板に対向させて、複数の電極を有する第 2の基板を 配置し、前記第 1の基板の電極と前記第 2の基板の電極とを電気的に接続する基板 間接続方法において、
前記第 1の基板と前記第 2の基板との隙間に、導電性粒子と気泡発生剤を含有し た榭脂を供給する第 1の工程と、
前記榭脂を加熱して、前記榭脂中に含有する前記気泡発生剤から気泡を発生させ る第 2の工程と、
前記第 2の基板を、前記第 1の基板に押圧する第 3の工程と、
前記榭脂を硬化する第 4の工程と
を含み、
前記第 2の工程において、前記榭脂は、前記気泡発生剤から発生した気泡が成長 することで該気泡外に押し出されることによって、前記第 1の基板の電極と前記第 2の 基板の電極間に自己集合し、
前記第 3の工程において、前記電極間に自己集合した前記榭脂中に含有する導 電性粒子同士が互いに接触することによって、前記電極間を電気的に接続し、 前記第 4の工程において、前記電極間に自己集合した前記榭脂を硬化すること〖こ よって、前記第 1の基板を前記第 2の基板に固定することを特徴とする基板間接続方 法。
[12] 前記気泡発生剤は、前記樹脂が加熱されたときに沸騰する材料力 なることを特徴 とする、請求項 11に記載の基板間接続方法。
[13] 前記第 2の工程は、前記第 1の基板と前記第 2の基板との隙間の間隔を変動させな 力 実行されることを特徴とする、請求項 11に記載の基板間接続方法。
[14] 前記第 1の工程は、前記第 1の基板上に、前記導電性粒子と気泡発生剤を含有し た榭脂を供給した後、該榭脂表面に前記第 2の基板を配設することにより実行される ことを特徴とする、請求項 11に記載の基板間接続方法。
[15] 前記第 4の工程の後、前記第 1の基板と前記第 2の基板との隙間にアンダーフィル 材を供給し、然る後、該アンダーフィル材を硬化させる工程をさらに含むことを特徴と する、請求項 11に記載の基板間接続方法。
[16] 複数の接続端子を有する回路基板に対向させて、複数の電極端子を有する半導 体チップが配置され、前記回路基板の接続端子と前記半導体チップの電極端子とが 電気的に接続されたフリップチップ実装体において、
前記接続端子と前記電極端子は、前記回路基板と前記半導体チップとの隙間に供 給された導電性粒子と気泡発生剤を含有する榭脂が、前記接続端子と前記電極端 子間に自己集合し、該自己集合した前記榭脂中の導電性粒子同士が接触すること によって、電気的に接続されていることを特徴とするフリップチップ実装体。
[17] 前記フリップチップ実装体は、前記回路基板と前記半導体チップとの隙間に供給さ れたアンダーフィル材で固定されていることを特徴とする、請求項 16に記載のフリツ プチップ実装体。
[18] 半導体チップを回路基板にフリップチップ実装するフリップチップ実装装置であつ て、
前記半導体チップ及び前記回路基板を、一定の隙間をもって互いに対向させて保 持する保持手段と、
前記半導体チップと前記回路基板との隙間に、導電性粒子と気泡発生剤を含有し た榭脂を供給する供給手段と、
前記榭脂を加熱する加熱手段と
前記半導体チップを前記回路基板に押圧する押圧手段と
を備え、
前記加熱手段は、前記榭脂中に含有する前記気泡発生剤から気泡を発生させる 温度に制御する第 1の加熱手段と、前記榭脂を熱硬化させる温度に制御する第 2の 加熱手段を有していることを特徴とする、フリップチップ実装装置。
前記第 1の加熱手段で加熱された前記榭脂は、前記気泡発生剤から発生した気泡 が成長することで該気泡外に押し出されることによって、前記回路基板の接続端子と 前記半導体チップの電極端子との間に自己集合し、
前記押圧手段により前記半導体チップを前記回路基板に押圧することによって、前 記端子間に自己集合した前記榭脂中に含有する導電性粒子同士が互いに接触し、 前記端子間に電気的な接続がなされ、
前記第 2の加熱手段により前記榭脂を加熱することによって、前記榭脂中に含有す る導電性粒子同士が互いに接触した状態で、前記半導体チップを前記回路基板に 固定されることを特徴とする、請求項 18に記載のフリップチップ実装装置。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288325A (ja) * 2007-05-16 2008-11-27 Panasonic Corp 配線基板の接続方法、配線基板
JP2009283918A (ja) * 2008-04-24 2009-12-03 Panasonic Corp 配線基板と配線基板の接続方法
CN101835342A (zh) * 2009-03-13 2010-09-15 住友电气工业株式会社 连接印刷线路板的结构与方法和具有各向异性电导率的粘合剂
JP2010226140A (ja) * 2010-06-15 2010-10-07 Sony Chemical & Information Device Corp 接続構造体の製造方法
JP2011233921A (ja) * 2011-07-15 2011-11-17 Sumitomo Electric Ind Ltd プリント配線基板の接続構造

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8212004B2 (en) * 1999-03-02 2012-07-03 Human Genome Sciences, Inc. Neutrokine-alpha fusion proteins
JP3955302B2 (ja) * 2004-09-15 2007-08-08 松下電器産業株式会社 フリップチップ実装体の製造方法
KR101109221B1 (ko) * 2005-03-29 2012-01-30 파나소닉 주식회사 플립칩 실장방법 및 범프형성방법
JP4402718B2 (ja) * 2005-05-17 2010-01-20 パナソニック株式会社 フリップチップ実装方法
US7640659B2 (en) * 2005-09-02 2010-01-05 Panasonic Corporation Method for forming conductive pattern and wiring board
JP5002587B2 (ja) * 2006-03-28 2012-08-15 パナソニック株式会社 バンプ形成方法およびバンプ形成装置
KR100886712B1 (ko) * 2007-07-27 2009-03-04 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
US8531848B2 (en) * 2007-12-07 2013-09-10 METAMEMS Corp. Coulomb island and Faraday shield used to create adjustable Coulomb forces
US7812336B2 (en) * 2007-12-07 2010-10-12 METAMEMS Corp. Levitating substrate being charged by a non-volatile device and powered by a charged capacitor or bonding wire
US20090149038A1 (en) * 2007-12-07 2009-06-11 Metamems Llc Forming edge metallic contacts and using coulomb forces to improve ohmic contact
US8159809B2 (en) * 2007-12-07 2012-04-17 METAMEMS Corp. Reconfigurable system that exchanges substrates using coulomb forces to optimize a parameter
US7863651B2 (en) * 2007-12-07 2011-01-04 METAMEMS Corp. Using multiple coulomb islands to reduce voltage stress
US7946174B2 (en) * 2007-12-07 2011-05-24 METAMEMS Corp. Decelerometer formed by levitating a substrate into equilibrium
US8008070B2 (en) * 2007-12-07 2011-08-30 METAMEMS Corp. Using coulomb forces to study charateristics of fluids and biological samples
US8018009B2 (en) * 2007-12-07 2011-09-13 METAMEMS Corp. Forming large planar structures from substrates using edge Coulomb forces
US7728427B2 (en) * 2007-12-07 2010-06-01 Lctank Llc Assembling stacked substrates that can form cylindrical inductors and adjustable transformers
US7965489B2 (en) * 2007-12-07 2011-06-21 METAMEMS Corp. Using coulomb forces to form 3-D reconfigurable antenna structures
JP2009186707A (ja) * 2008-02-06 2009-08-20 Seiko Epson Corp 電気光学装置の製造方法、電気光学装置
JP2010034504A (ja) * 2008-07-02 2010-02-12 Panasonic Corp 基板間の接続方法、フリップチップ実装体及び基板間接続構造
CN101661916B (zh) * 2009-09-18 2012-05-09 可富科技股份有限公司 重新布线层于软膜覆晶封装的结构
US8951445B2 (en) * 2011-04-14 2015-02-10 International Business Machines Corporation Bridging arrangement and method for manufacturing a bridging arrangement
TWI536127B (zh) 2013-05-30 2016-06-01 理光股份有限公司 碳粉容器、處理匣及影像形成裝置
US9726691B2 (en) 2014-01-07 2017-08-08 International Business Machines Corporation 3D chip testing through micro-C4 interface
US9230832B2 (en) * 2014-03-03 2016-01-05 International Business Machines Corporation Method for manufacturing a filled cavity between a first and a second surface
JP7185252B2 (ja) 2018-01-31 2022-12-07 三国電子有限会社 接続構造体の作製方法
JP7160302B2 (ja) * 2018-01-31 2022-10-25 三国電子有限会社 接続構造体および接続構造体の作製方法
JP7046351B2 (ja) 2018-01-31 2022-04-04 三国電子有限会社 接続構造体の作製方法
CN111048499B (zh) * 2019-12-16 2022-05-13 业成科技（成都）有限公司 微发光二极管显示面板及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157796A (ja) 1987-09-14 1989-06-21 Furukawa Electric Co Ltd:The 半田析出用組成物および半田析出方法
JPH06125169A (ja) 1992-10-13 1994-05-06 Fujitsu Ltd 予備はんだ法
JPH11186334A (ja) 1997-12-25 1999-07-09 Toshiba Corp 半導体実装装置及びその製造方法及び異方性導電材料
JP2000094179A (ja) 1998-09-22 2000-04-04 Harima Chem Inc ソルダペースト及びその製造方法並びにはんだプリコート方法
JP2000332055A (ja) 1999-05-17 2000-11-30 Sony Corp フリップチップ実装構造及び実装方法
JP2002026070A (ja) 2000-07-04 2002-01-25 Toshiba Corp 半導体装置およびその製造方法
JP2002329745A (ja) * 2001-05-01 2002-11-15 Fujitsu Ltd 電子部品の実装方法及びペースト材料
JP2004260131A (ja) 2003-02-05 2004-09-16 Japan Science & Technology Agency 端子間の接続方法及び半導体装置の実装方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5597469A (en) * 1995-02-13 1997-01-28 International Business Machines Corporation Process for selective application of solder to circuit packages
DE19640192A1 (de) * 1996-09-30 1998-04-02 Bosch Gmbh Robert Verfahren zur Flip-Chip-Montage
JP3678547B2 (ja) * 1997-07-24 2005-08-03 ソニーケミカル株式会社 多層異方導電性接着剤およびその製造方法
US5904156A (en) * 1997-09-24 1999-05-18 International Business Machines Corporation Dry film resist removal in the presence of electroplated C4's
CN1273993C (zh) * 1998-08-28 2006-09-06 松下电器产业株式会社 导电粘结结构，含该结构的制品及其制造方法
JP4142800B2 (ja) * 1999-04-07 2008-09-03 株式会社ルネサステクノロジ バンプ形成装置及びバンプ形成方法
US6570099B1 (en) * 1999-11-09 2003-05-27 Matsushita Electric Industrial Co., Ltd. Thermal conductive substrate and the method for manufacturing the same
US7524748B2 (en) * 2003-02-05 2009-04-28 Senju Metal Industry Co., Ltd. Method of interconnecting terminals and method of mounting semiconductor devices
JP3964911B2 (ja) * 2004-09-03 2007-08-22 松下電器産業株式会社 バンプ付き基板の製造方法
JP3955302B2 (ja) * 2004-09-15 2007-08-08 松下電器産業株式会社 フリップチップ実装体の製造方法
WO2006064831A1 (ja) * 2004-12-17 2006-06-22 Matsushita Electric Industrial Co., Ltd. フリップチップ実装用樹脂組成物およびバンプ形成用樹脂組成物
US7649267B2 (en) * 2005-03-17 2010-01-19 Panasonic Corporation Package equipped with semiconductor chip and method for producing same
KR101109221B1 (ko) * 2005-03-29 2012-01-30 파나소닉 주식회사 플립칩 실장방법 및 범프형성방법
JP4477062B2 (ja) * 2005-05-17 2010-06-09 パナソニック株式会社 フリップチップ実装方法
US7745013B2 (en) * 2005-12-30 2010-06-29 Intel Corporation Solder foams, nano-porous solders, foamed-solder bumps in chip packages, methods of assembling same, and systems containing same
US8119449B2 (en) * 2006-03-14 2012-02-21 Panasonic Corporation Method of manufacturing an electronic part mounting structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157796A (ja) 1987-09-14 1989-06-21 Furukawa Electric Co Ltd:The 半田析出用組成物および半田析出方法
JPH06125169A (ja) 1992-10-13 1994-05-06 Fujitsu Ltd 予備はんだ法
JPH11186334A (ja) 1997-12-25 1999-07-09 Toshiba Corp 半導体実装装置及びその製造方法及び異方性導電材料
JP2000094179A (ja) 1998-09-22 2000-04-04 Harima Chem Inc ソルダペースト及びその製造方法並びにはんだプリコート方法
JP2000332055A (ja) 1999-05-17 2000-11-30 Sony Corp フリップチップ実装構造及び実装方法
JP2002026070A (ja) 2000-07-04 2002-01-25 Toshiba Corp 半導体装置およびその製造方法
JP2002329745A (ja) * 2001-05-01 2002-11-15 Fujitsu Ltd 電子部品の実装方法及びペースト材料
JP2004260131A (ja) 2003-02-05 2004-09-16 Japan Science & Technology Agency 端子間の接続方法及び半導体装置の実装方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1865550A4

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288325A (ja) * 2007-05-16 2008-11-27 Panasonic Corp 配線基板の接続方法、配線基板
US8353102B2 (en) 2007-05-16 2013-01-15 Panasonic Corporation Wiring board connection method
JP2009283918A (ja) * 2008-04-24 2009-12-03 Panasonic Corp 配線基板と配線基板の接続方法
CN101835342A (zh) * 2009-03-13 2010-09-15 住友电气工业株式会社 连接印刷线路板的结构与方法和具有各向异性电导率的粘合剂
JP2010219135A (ja) * 2009-03-13 2010-09-30 Sumitomo Electric Ind Ltd プリント配線基板の接続構造、プリント配線基板の接続方法、及び異方導電性を有する接着剤
US8507803B2 (en) 2009-03-13 2013-08-13 Sumitomo Electric Industries, Ltd. Structure of connecting printed wiring boards, method of connecting printed wiring boards, and adhesive having anisotropic conductivity
JP2010226140A (ja) * 2010-06-15 2010-10-07 Sony Chemical & Information Device Corp 接続構造体の製造方法
JP2011233921A (ja) * 2011-07-15 2011-11-17 Sumitomo Electric Ind Ltd プリント配線基板の接続構造

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JP4084835B2 (ja) 2008-04-30
KR20070115957A (ko) 2007-12-06
JPWO2006103949A1 (ja) 2008-09-04
CN101142664A (zh) 2008-03-12
US7531385B1 (en) 2009-05-12
CN100495676C (zh) 2009-06-03

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