Classifications

• • H10D64/011—
• • H10P95/04—
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23G—CLEANING OR DE-GREASING OF METALLIC MATERIAL BY CHEMICAL METHODS OTHER THAN ELECTROLYSIS
  • C23G5/00—Cleaning or de-greasing metallic material by other methods; Apparatus for cleaning or de-greasing metallic material with organic solvents
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/32458—Vessel
  • H01J37/32522—Temperature
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
  • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
  • H01L21/67034—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for drying
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
  • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
  • H01L21/67051—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67017—Apparatus for fluid treatment
  • H01L21/67063—Apparatus for fluid treatment for etching
  • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
  • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/7684—Smoothing; Planarisation
• • H10P50/242—
• • H10P50/267—
• • H10P72/0408—
• • H10P72/0414—
• • H10P72/0424—
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
  • H01J2237/02—Details
  • H01J2237/022—Avoiding or removing foreign or contaminating particles, debris or deposits on sample or tube

Definitions

• the present invention relates generally to damascene semiconductor manufacturing processes, and more particularly, to methods and systems for planarizing features and layers in a semiconductor manufacturing process.
• the manufacturing of the integrated circuit devices includes the use of plasma etching chambers.
• the plasma etch chambers are capable of etching selected layers on the substrate as defined by a mask or pattern.
• the plasma etch chambers are configured to receive processing gases (i.e., etch chemistries) while a radio frequency (RF) power is applied to one or more electrodes of the plasma etch chamber.
• RF radio frequency
• the pressure inside the plasma etch chamber is also controlled for the particular process.
• the process gases in the chamber are activated such that a plasma is created.
• the plasma is thus configured to perform the desired etching of the selected layers of the semiconductor wafer.
• Low volatility byproducts are produced in some prior art plasma etch processes.
• the byproduct is CuClx.
• CuClx is non-volatile at room temperature.
• the low- volatility byproducts typically condense on the chamber walls.
• the byproducts build-up on the chamber walls.
• the byproduct build-up then begins to "flake" off of the chamber walls and is therefore becomes a significant particle source. The particles can contaminate the substrates being etched in the chamber.
• the copper etchant chemistries are often corrosive to the surface of the remaining copper. This corrosive action can cause uneven pitting and leave an undesirable residue layer that must be removed before subsequent processing can occur.
• the substrate is removed from the plasma etch chamber and is cleaned and/or rinsed.
• FIG. 1 shows a typical cleaned substrate 100.
• the substrate 100 has a relatively thick layer of oxide 102 (e.g., copper oxide) on top of the exposed copper device 104.
• oxide layer 102 can interfere with subsequent processing (e.g., forming interconnects to the underlying copper device) and therefore must be removed before subsequent processing can be attempted.
• the substrate 100 can also have a barrier layer 106.
• CMP chemistries can cause problems similar to those described above for the etching chemistries.
• a substrate is typically cleaned and rinsed after a CMP operation.
• the CMP process itself and/or cleaning and/or the rinsing operation can also cause an oxide layer to form.
• the present invention fills these needs by providing an improved method of passivating an exposed conductive material. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
• a method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber.
• a hydrogen species plasma is formed in the process chamber.
• a surface layer species is reduced from a top surface of the substrate is reduced.
• the reduced surface layer species are purged from the process chamber.
• the conductive material can include at least one of a group consisting of a copper containing material, elemental copper, alloys such as NiFe, CoFe, elemental Ni, Co, Ru, AIO, Ta, TaN, Pt and Ir.
• the passivation process can be performed in situ.
• the passivation process can be performed ex situ.
• the passivation process can be performed in situ in an etch process.
• the passivation process can be performed in situ in a stress free planarization process.
• the passivation process can be performed ex situ following a CMP operation.
• the process chamber can have a temperature of between about 30 and about 400 degrees C.
• the process chamber can be a small volume plasma chamber.
• the process chamber can be a capacitively coupled system, an inductively coupled system, an ECR or a microwave powered system.
• the process chamber can have a pressure of between about 1 mTorr and about 1000 mTorr.
• the surface layer species can be an oxide, a halide (e.g., chloride, bromide, fluoride or iodide containing species) and a nitride or combinations thereof.
• the hydrogen species can include at least one of a group consisting of H 2 , HC1, HBr, CH 4 and NH 3 .
• Injecting the hydrogen species can also include injecting a carrier gas such as argon, nitrogen, helium, neon and xenon.
• Forming a plasma with the hydrogen species can include volatilizing a residue on at least one of the substrate and an inner wall of the process chamber. Purging the reduced surface layer species from the process chamber can also include purging the volatilized residue.
• Reducing the surface layer species from the top surface of the substrate can also include activating the top surface of the substrate and roughening the top surface of the substrate.
• the exposed conductive material is passivated with a predetermined time.
• the predetermined time being sufficient to reduce the surface layer species from the top surface of the substrate a desired amount.
• the predetermined time can be greater than about 15 seconds.
• Another embodiment provides a method of passivating an exposed copper interconnect.
• the method includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber.
• the method also includes forming a hydrogen species plasma in the process chamber and reducing a copper oxide from a top surface of the exposed copper interconnect.
• the reduced copper oxides are purged from the process chamber.
• Each of several inner surfaces of the process chamber can have a temperature equal to or greater than about 250 degrees C.
• Each of the inner surfaces of the process chamber is exposed to the substrate.
• Another embodiment provides a method of performing a non-contact planarization on a substrate.
• the method includes placing a substrate in an etch process chamber and etching the substrate.
• the method also includes injecting a hydrogen species into the etch process chamber and forming a hydrogen species plasma in the etch process chamber.
• a surface layer species is reduced from a top surface of the substrate and the reduced surface layer species are purged from the process chamber.
• Figure 1 shows a typical cleaned substrate.
• Figure 2A shows a copper matrix, in accordance with one embodiment of the present invention.
• Figure 2B shows a passivated copper matrix, in accordance with one embodiment of the present invention.
• FIG. 3 A is a flowchart of the method operations of a CMP process, in accordance with one embodiment of the present invention.
• FIG. 3B is a flowchart of the method operations of an etch process, in accordance with one embodiment of the present invention.
• FIG. 4 is a flowchart of the method operations of a passivation process, in accordance with one embodiment of the present invention.
• Exposed copper can be vulnerable to corrosion. This is especially true of processed copper when interconnect applications are exposed to various process chemistries (e.g., wet and dry chemistries). Some of these conditions can also employ corrosive chemistries. By way of example, a copper dry etch is typically slow and non-selective due to non- volatility at lower temperatures. Volatile compound formation is feasible in halogen containing chemistries (e.g., chlorine, fluorine, bromine, and iodine chemistries) at high temperatures (i.e., greater than about 200 degrees C).
• halogen containing chemistries e.g., chlorine, fluorine, bromine, and iodine chemistries
• Corrosion is a critical issue due to interaction of residual halogen compounds on the copper surface with moisture or interaction of residual halogen in the process chamber with non-passivated copper surface sites.
• the latter case may include stress free barrier removal following copper CMP or electropolish.
• Another example is copper processing for damascene applications that use CMP that employs corrosive alkaline slurries. Corrosion persists in spite of typical wet treatments. Further, the typical wet treatments can introduce additional process modules, additional chemical requirements and thereby increase production costs and production time.
• Stable, activated surfaces are important in dual damascene processes for electrical as well as next layer deposition requirements.
• the newly exposed copper surface has surface characteristics that are different than that required for further processing. Additional process steps and process modules are required to modify the newly exposed copper surface to meet these needs. Modifications to the newly exposed copper surface include the reduction of the surface copper oxide layer to elemental copper and activation of the copper surface inside vacuum (e.g., less than about 100 mTorr) conditions. Other modifications can include removal of CMP residues that contain many components of the CMP process chemistries (e.g., brighteners, inhibitors, accelerators, etc.), therefore avoiding any wet cleaning processes following the CMP process.
• One embodiment provides a system and method for passivating the newly etched surface so as to prevent corrosion.
• the disclosed system and method can remove the etchant chemistry residue from the etched substrate.
• the disclosed system and method can also remove the etchant chemistry residue from the walls of the etching chamber. Further, the disclosed system and method can also substantially eliminate the oxide layer formed after a copper layer is exposed and further formed in a wet cleaning process.
• the disclosed system and method can be performed in-situ within a plasma etch chamber.
• the in-situ passivation operation can be combined with and in some instances incorporated into other processes that are executed within the plasma etch chamber. In this manner the total processes time within the plasma etch chamber is not significantly changed.
• the passivation operation requires about 30 seconds concurrently with a chuck declamping operation that requires about 60 seconds, thereby resulting no increase in process time within the plasma chamber.
• An alternative embodiment includes an ex-situ process such as following a post CMP cleaning and rinsing operation.
• the substrate undergoes a CMP operation and then a cleaning and rinsing operation.
• the substrate can then be placed in a plasma chamber where the passivation process can be performed so as to reduce the oxide layer formed during the cleaning and rinsing operation(s).
• This embodiment is especially useful if the operation to follow is a plasma etch or deposition operation that can occur within the plasma chamber.
• FIG. 1 shows a copper matrix 200, in accordance with one embodiment of the present invention.
• the matrix of the copper molecules 202 is covered by an oxide layer 204.
• the oxide layer 204 can be several hundreds to several thousands of angstroms in thickness.
• Figure 2B shows a passivated copper matrix 200', in accordance with one embodiment of the present invention. After the passivation operation, oxide layer 204 is substantially reduced such that the matrix of the copper molecules 202 is fully exposed.
• the matrix of the copper molecules 202 has a slightly rougher surface.
• the rougher surface can increase adhesion to a subsequent layer that may be formed on top of the exposed matrix of the copper molecules 202.
• the passivation operation includes exposing the newly exposed copper surface to a hydrogen chemistry to reduce the surface oxide, passivate the surface and prevent corrosion in a single operation.
• a hydrogen gas or other gases generating hydrogen under plasma conditions e.g., HC1, CH4, NH3, etc.
• This plasma process can be used in various types of plasma reactors including inductively or capacitively coupled plasma or microwave reactors.
• Additional additive gases can include, for example by not limited to argon, oxygen and nitrogen.
• FIG. 3 A is a flowchart of the method operations 300 of a CMP process, in accordance with one embodiment of the present invention.
• a bulk removal or planarization or other CMP operation is performed on a substrate.
• the CMP operation can be used to remove an overburden portion of a conductive material such as for a damascene or a dual damascene interconnect structure.
• the CMP operation exposes the conductive interconnects.
• the CMP operation can be any type of CMP operation such as a linear belt or rotary or planar table or a low down force CMP operation.
• the substrate is cleaned in a "wet" operation such as a deionized water rinse or similar clean operation.
• the wet clean operation removes the residual CMP slurry and CMP byproducts from the substrate.
• the wet clean operation can often be incorporated within the CMP process tool or in a separate process tool or module.
• the cleaned substrate is placed in a process chamber.
• the process chamber can be any process chamber suitable for plasma operations.
• the processing chamber includes a processing chamber capable of having all inner surfaces substantially uniformly heated above a temperature necessary volatilize any residues that may be clinging to the inner surfaces of the process chamber (e.g., about 200 to about 400 degrees C).
• the inner surfaces include those internal surfaces of the processing chamber that the substrate is exposed to.
• the process chamber is a small volume process chamber such as described in co-owned and co-pending U.S. Patent application 10/744,355, filed on December 22, 2003, and entitled "Small Volume Process Chamber with Hot Inner Surfaces".
• a small volume process chamber have a top electrode and the bottom electrode that are separated by a distance of between about 0.5 cm to about 5 cm.
• the surface of the exposed conductive interconnect structures are passivated.
• the surface passivation is described in more detail in Figure 4 below.
• the surface passivation operation 340 is an ex-situ operation from the CMP operation 305.
• FIG. 3B is a flowchart of the method operations 320 of an etch process, in accordance with one embodiment of the present invention.
• a substrate is placed in a processing chamber suitable for plasma operations.
• the substrate can be placed within the processing chamber for other operations.
• the other operations can include operations such as a plasma etching process or a deposition process (e.g., chemical vapor deposition).
• a process e.g., a plasma etch process
• the process can be any capable of being performed in the processing chamber, hi one embodiment the process is a stress free plasma etch process such as described in U.S. Patent Application No. 10/390,117 filed on March 14, 2003 and entitled “System, Method and Apparatus For Improved Global Dual-Damascene Planarization” and U.S. Patent Application No. 10/390,520 filed on March 14, 2003 and entitled “System, Method and Apparatus For Improved Local Dual-Damascene Planarization.”
• the plasma etch process exposes a conductive interconnect or device structures.
• the surface of the exposed conductive interconnect structures are passivated.
• the surface passivation is described in more detail in Figure 4 below.
• the surface passivation operation 340 is an in-situ operation capable of being performed within the same process chamber as another previous or subsequent operation.
• FIG. 4 is a flowchart of the method operations 340 of a passivation process, in accordance with one embodiment of the present invention.
• a hydrogen containing species is injected into the plasma chamber.
• the plasma chamber is heated to a range of about 75 degrees C and about 300 degrees C.
• the pressure of the plasma chamber is within a range of about 1 mTorr and about 100 mTorr.
• hydrogen is injected at a flow rate of between about 20 seem (standard cubic centimeters per minute) and about 200 seem.
• the hydrogen can be carried on an inert carrier gas (e.g., argon) at a flow rate of about 20 to about 2000 seem.
• an inert carrier gas e.g., argon
• a plasma is formed with the hydrogen species.
• the high energy of the plasma and the relatively high temperature can cause the majority of the residue materials (e.g., CMP residues or etchant residues) on the substrate to become volatile.
• Desirable temperature range for the substrate is about 200 to about 400 degrees C.
• the etchant residues on the inner surfaces of the processing chamber also become volatile.
• Desirable temperature range for the process chamber is about 200 to about 400 degrees C.
• the volatilized residue materials can be purged in an operation 420 below.
• the plasma can be formed in any type of plasma chamber (e.g., inductive, capacitive, etc.).
• a power applied to top is between about 500 to about 3000 watts of power.
• the bottom electrode can have a power applied of between about 0 to about 100 watts of power.
• system power in the range of about 500 to about 5000W can be applied to the bottom and/or top electrode(s).
• the RF power supply can be affected with either a single or dual frequency.
• the oxide layer is reduced.
• the hydrogen plasma causes the oxygen atoms in the oxide surface layer to disassociate with the conductive material (e.g., copper) and to combine with the hydrogen to form water molecules. Any remaining hydrogen atoms, any oxygen atoms disassociated from the conductive material and the formed water molecules can be purged in an operation 420 below.
• the oxide layer reduction and the volatilized residue materials are completed in about 15 seconds to about 2 minutes. While no maximum time is indicated, the majority of the oxide layer and volatilizing the residue materials can be accomplished in less than about 2 minutes.
• the oxides, hydrogen, water vapor and volatilized residue materials are purged from the processing chamber and the method operations end.
• a substrate is loaded in a capacitively coupled plasma etch chamber.
• the plasma etch chamber is heated to a temperature of about 250 degrees C, at a pressure of about 20 mTorr.
• the top electrode of the plasma etch chamber has about 1000 watts applied and zero power is applied to the bottom electrode.
• About 100 seem of H 2 and about 100 seem of argon is injected into the plasma etch chamber to generate a hydrogen species plasma.
• the substrate is exposed to the hydrogen plasma for about 60 seconds to reduce the oxides in the top surface of the substrate.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Chemical & Material Sciences (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Plasma & Fusion (AREA)
• Chemical Kinetics & Catalysis (AREA)
• General Chemical & Material Sciences (AREA)
• Analytical Chemistry (AREA)
• Materials Engineering (AREA)
• Mechanical Engineering (AREA)
• Metallurgy (AREA)
• Organic Chemistry (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Drying Of Semiconductors (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=34837810

Family Applications (1)

Country Status (7)

Cited By (1)

Families Citing this family (8)

Citations (12)

Family Cites Families (104)

• 2004
  • 2004-01-30 US US10/769,408 patent/US7232766B2/en not_active Expired - Fee Related
  • 2004-12-30 CN CNA2004800411499A patent/CN1906753A/zh active Pending
  • 2004-12-30 EP EP04815900A patent/EP1709679A1/en not_active Withdrawn
  • 2004-12-30 WO PCT/US2004/043910 patent/WO2005076348A1/en not_active Ceased
  • 2004-12-30 JP JP2006551095A patent/JP5153143B2/ja not_active Expired - Fee Related
  • 2004-12-30 KR KR1020067013312A patent/KR101127778B1/ko not_active Expired - Fee Related
• 2006
  • 2006-06-27 IL IL176591A patent/IL176591A/en not_active IP Right Cessation

Patent Citations (13)

Non-Patent Citations (2)

Also Published As

Similar Documents

Legal Events