US20040237997A1 - Method for removal of residue from a substrate - Google Patents

Method for removal of residue from a substrate Download PDF

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US20040237997A1
US20040237997A1 US10446332 US44633203A US2004237997A1 US 20040237997 A1 US20040237997 A1 US 20040237997A1 US 10446332 US10446332 US 10446332 US 44633203 A US44633203 A US 44633203A US 2004237997 A1 US2004237997 A1 US 2004237997A1
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method
hydrogen
substrate
residue
comprises
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US10446332
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Ying Rui
Chun Yan
Guowen Ding
Suzanne Arias
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Applied Materials Inc
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Applied Materials Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/02068Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04Cleaning involving contact with liquid
    • B08B3/08Cleaning involving contact with liquid the liquid having chemical or dissolving effect
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B7/00Cleaning by methods not provided for in a single other subclass or a single group in this subclass
    • B08B7/0035Cleaning by methods not provided for in a single other subclass or a single group in this subclass by radiant energy, e.g. UV, laser, light beam or the like
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

Abstract

A method for removing residues from a substrate. The residue is removed by exposing the substrate to a hydrogen-based plasma. After the substrate is exposed to the hydrogen-based plasma, the substrate may optionally be immersed in an aqueous solution including hydrogen fluoride.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention generally relates to a method of fabricating devices on semiconductor substrates. More specifically, the invention relates to a method for removal of residue from a semiconductor substrate. [0002]
  • 2. Description of the Related Art [0003]
  • Microelectronic devices are generally fabricated on a semiconductor substrate as integrated circuits wherein various metal layers are interconnected to one another to facilitate propagation of electrical signals within the device. One typical process used for fabrication of the microelectronic devices is a plasma etch process. During plasma etch processes, one or more layers that comprise a metal (e.g., tantalum (Ta), titanium (Ti), and the like) or a metal-based compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), and the like) are removed, either partially or in total, to form a feature (e.g., interconnect line or contact via) of the integrated circuit. [0004]
  • Generally, plasma etch processes use gas chemistries that, when reacted with the material comprising the etched layer or etch mask, may produce non-volatile by-products. Such by-products accumulate on the substrate as a residue. In the art, such residue is commonly called a “post-etch residue.” Post-etch residues interfere with processing of the substrate, e.g., the residues may contaminate the remaining layers or cause difficulties in depositing subsequent layers. Metal-containing residue may also cause short-circuits that disrupt or degrade operation of the integrated circuits. [0005]
  • Conventional methods for removing residues typically include multiple wet treatments of the substrate with an intermediate plasma strip process using an oxygen-based chemistry. Multiple wet treatments, along with an intermediate plasma strip process (i.e., etch and strip processes), reduce productivity during fabrication of the microelectronic devices. Further, the oxygen-based plasma strip process may form hard to remove metal oxides on the substrate. [0006]
  • Therefore, there is a need in the art for an improved method for removing residue from a substrate during fabrication of microelectronic devices. [0007]
  • SUMMARY OF THE INVENTION
  • The present invention is a method for removing residue from a substrate. The residue is removed by exposing the substrate to a hydrogen-based plasma. After the substrate is exposed to the hydrogen-based plasma, the substrate may optionally be immersed in an aqueous solution including hydrogen fluoride. In one application, the residue comprises at least one metal (e.g., tantalum (Ta), titanium (Ti), tungsten (W), hafnium (Hf), and the like).[0008]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which: [0009]
  • FIG. 1 depicts a flow diagram of a method for removing residue in accordance with an embodiment of the present invention; [0010]
  • FIGS. 2A-2D depict a sequence of schematic, cross-sectional views of a substrate having a film stack where residue is removed in accordance with the method of FIG. 1; [0011]
  • FIG. 3 depicts a schematic diagram of an exemplary plasma processing apparatus of the kind used in performing portions of the inventive method; and [0012]
  • FIG. 4 is a table summarizing the processing parameters of one exemplary embodiment of the inventive method when practiced using the apparatus of FIG. 3.[0013]
  • To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. [0014]
  • It is to be noted, however, that the appended drawings illustrate only exemplary embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. [0015]
  • DETAILED DESCRIPTION
  • The present invention is a method for removing residue from a substrate (e.g., silicon (Si) wafer, gallium arsenide (GaAs) wafer, and the like) during fabrication of a microelectronic device. In one application, the inventive method is used to remove post-etch residue that comprises at least one metal (e.g., tantalum (Ta), titanium (Ti), tungsten (W), hafnium (Hf), and the like), as well as compounds thereof. [0016]
  • FIG. 1 depicts a flow diagram of one embodiment of the inventive method for removal of residue as sequence [0017] 100. The sequence 100 includes processes performed upon a film stack having at least one metal layer.
  • FIGS. 2A-2D depict a series of schematic, cross-sectional views of a substrate having a film stack from which residue is removed using sequence [0018] 100. The cross-sectional views in FIGS. 2A-2D relate to individual processing steps performed upon the film stack. The images in FIGS. 2A-2D are not depicted to scale and are simplified for illustrative purposes.
  • The sequence [0019] 100 starts at step 101 and proceeds to step 102 when a film stack 202 and etch mask 204 are formed on a wafer 200, e.g., silicon wafer (FIG. 2A). In one embodiment, the film stack 202 comprises a barrier layer 210, a metal-containing layer 208, and an insulating layer 206.
  • The barrier layer [0020] 210 and insulating layer 206 are generally formed of a dielectric material, such as silicon nitride (Si3N4), silicon dioxide (SiO2), hafnium dioxide (HfO2), and the like, to a thickness of about 300 to 600 Angstroms. The metal-containing layer 208 is formed from tantalum nitride (TaN), tantalum (Ta), titanium (Ti), tungsten (W), and the like or compounds thereof, to a thickness of about 600 to 1000 Angstroms.
  • The layers of the film stack [0021] 202 can be formed using any conventional thin film deposition technique, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), and the like. Fabrication of the microelectric devices may be performed using the respective processing reactors of CENTURA®, ENDURA®, and other semiconductor wafer processing systems available from Applied Materials, Inc. of Santa Clara, Calif.
  • The etch mask [0022] 204 is formed on the insulating layer 206 (FIG. 2A). The etch mask 204 protects a region 220 of the film stack 202 while exposing adjacent regions 222 of the stack 202. Generally, the etch mask 204 is a photoresist mask that is fabricated using a conventional lithographic patterning process. For such process, a photoresist layer is exposed through a patterned mask, developed, and the undeveloped portion of the photoresist is removed. The photoresist mask 204 typically has a thickness of about 2000 to 6000 Angstroms.
  • Alternatively, the etch mask [0023] 203 may be a hard mask formed of silicon dioxide (SiO2), Advanced Patterning Film™ (APF) (available from Applied Materials, Inc. of Santa Clara, Calif.) and hafnium dioxide (HfO2).
  • The etch mask [0024] 204 may further comprise an optional anti-reflective layer 205 (shown in broken line) that controls the reflection of the light during exposure of the photoresist. As feature sizes are reduced, inaccuracies in an etch mask pattern transfer process can arise from optical limitations that are inherent to the lithographic process, such as the light reflection. The anti-reflective layer 205 may comprise, for example, silicon oxi-nitride, polyamides, and the like.
  • Processes of applying the etch mask [0025] 204 are described, for example, in commonly assigned U.S. patent application Ser. No. 10/245,130, filed Sep. 16, 2002 (Attorney docket number 7524) and Ser. No. 09/590,322, filed Jun. 8, 2000 (Attorney docket number 4227), which are incorporated herein by reference.
  • At step [0026] 104, the insulating layer 206 and the metal-containing layer 208 are plasma etched and removed in the unprotected regions 222 (FIG. 2B). The insulating layer 206 and the metal-containing layer 208 may be etched using either a chlorine-based gas mixture or, alternatively, a fluorine-based gas mixture. The chlorine-based gas mixture may comprise chlorine (Cl2), BCL3 and an inert diluent gas, such as at least one of argon (Ar), helium (He), neon (Ne), and the like, along with a small amount of a carbon-containing gas, such as carbon tetrafluoride (CF4) and the like. Alternatively, the fluorine-based gas mixture may comprise carbon tetrafluoride (CF4), CHF3 or SF6 and an inert diluent gas, such as at least one of argon (Ar), helium (He), neon (Ne), and the like.
  • In one embodiment, step [0027] 104 uses the mask 204 as an etch mask and the barrier layer 210 as an etch stop layer. Specifically, during etching of the metal-containing film 208, the endpoint detection system of the etch reactor may monitor plasma emissions at a particular wavelength to determine an end of the etch process. Conventionally, the etch process continues until a shallow recess 224 is formed in the barrier layer 210 (FIG. 2B). The shallow recess 224 is formed to a depth 226 of not greater than about 150 Angstroms, e.g., typically about 50 to 75 Angstroms. Such recess 224 facilitates removal of the metal-containing layer 208 (e.g., tantalum nitride (TaN)) from the barrier layer 210 in the regions 222.
  • Step [0028] 104 can be performed in an etch reactor such as a Decoupled Plasma Source (DPS) reactor of the CENTURA® system, commercially available from Applied Materials, Inc. of Santa Clara, Calif. The DPS reactor uses a source of radio-frequency (RF) power at about 50 kHz to 13.56 MHz to produce a high-density inductively coupled plasma.
  • During step [0029] 104, a portion of the material removed from the insulating film 206 and the metal-containing layer 208 combine with components of the etchant gas mixture (e.g., chlorine-containing or fluorine-containing gases and the like), as well as with the components of the etch mask 204 (e.g., polymeric components, and the like) forming non-volatile compounds. Such non-volatile compounds become re-deposited onto the substrate 200, forming a residue 216 (i.e., post-etch residue). After the etch process, the post-etch residue 216 is typically found on the etch mask 204, sidewalls 212 of the film stack 202 and elsewhere on the substrate 200.
  • When a metal-containing layer (i.e., layer [0030] 208) is etched during step 104, the post-etch residue 216 also comprises atoms of such metal (e.g., tantalum (Ta), titanium (Ti), tungsten (W), and the like) and/or compounds of the metal (i.e., metal chlorides, metal fluorides, metal oxides, metal nitrides, and the like) that may be formed during the etch process. In the illustrative embodiment discussed herein, such metallic compounds may comprise TaxCly (where x and y are integers), TaxFy (where x and y are integers), and TaxOy (where x and y are integers), and the like. Metal-containing post-etch residues are generally more difficult to remove from the substrate than other types of residue. Such residues 216 are also considered a contaminant with respect to subsequent processing of the substrate 200.
  • At step [0031] 106, the etch mask 204 (e.g., photoresist mask) and the post-etch residues 216 are removed (or stripped) from the film stack 202 and the substrate 200 (FIG. 2C). In one embodiment, the mask 204 and post-etch residues 216 are removed using a hydrogen-based plasma. The hydrogen-based plasma may comprise one or more hydrogen-containing gases including hydrogen (H2), water vapor (H2O). The hydrogen-based plasma is preferably a remote plasma (i.e., a plasma that is excited outside the reaction volume of the process chamber), such as a microwave plasma excited at about 1.0 to 10 GHz or a radio frequency plasma excited at about 0.05 to 1000 MHz.
  • Step [0032] 106 can be performed in a reactor such as an Advanced Strip and Passivation (ASP) reactor of the CENTURA® system. The ASP reactor (described in detail with reference to FIG. 3 below) is a downstream plasma reactor in which a microwave plasma is confined such that only reactive neutrals are provided to the reaction volume of the process chamber. Such plasma confinement minimizes plasma-related damage of the substrate or circuits formed on the substrate. Alternatively, step 106 can be performed in a DPS reactor or an AXIOM® reactor, both of which are commercially available from Applied Materials, Inc. of Santa Clara, Calif. The AXIOM® reactor is also a remote plasma reactor and is described in U.S. patent application Ser. No. 10/264,664, filed Oct. 4, 2002 (Attorney docket number 6094), which is herein incorporated by reference.
  • Using the CENTURA® system, upon completion of step [0033] 104, the substrate 200 may be transported, under vacuum, from the DPS reactor to the ASP, AXIOM® or another DPS reactor for performing step 106. As such, the substrate is protected from contaminants that may be present in a non-vacuumed portion of the manufacturing environment.
  • In one illustrative embodiment, the etch mask [0034] 204 and post-etch residues 216 are removed in the ASP reactor by providing hydrogen (H2) at a flow rate of about 1000 to 5000 sccm, water vapor (H2O) at a flow rate of up to about 50 sccm (i.e., a H2:H2O flow ratio ranging from about 100% of H2 to 20:1), applying a microwave power of about 1000 to 2000 W at approximately 2.45 GHz and maintaining a wafer temperature at about 100 to 300 degrees Celsius at a pressure in the process chamber of between about 1 and 4 Torr. The duration of step 106 is generally about 40 to 200 sec. One exemplary process provides H2 at a rate of 3000 sccm, H2O at a rate of 30 sccm (i.e., a H2:H2O flow ratio of about 100:1), applies a microwave power of 1400 W and maintains a wafer temperature of 250 degrees Celsius at a chamber pressure of 2 Torr.
  • Step [0035] 106 strips and volatilizes the etch mask 204 and the post-etch residue 216. However, after step 106, traces 228 of post-etch residues 216 and of the etch mask 204 may still remain on the film stack 202 and substrate 200. Additionally, in some applications, the plasma strip process of step 106 may produce a thin film of residue 230 (shown in phantom in FIG. 2C).
  • At step [0036] 108, the residues 216, 230 are removed from the film stack 202 and elsewhere on the substrate 200 (FIG. 2D). In one embodiment, the residues 216, 230 are removed by dipping the substrate 200 in an aqueous solution including hydrogen fluoride (HF). In one illustrative embodiment, the aqueous solution includes between 0.5 and 12% by volume of hydrogen fluoride. The hydrogen fluoride solution may additionally include between 0.5 and 15% by volume of at least one of nitric acid (HNO3) and hydrogen chloride (HCl). After the substrate is dipped in the aqueous solution of hydrogen fluoride, the substrate is conventionally rinsed with deionized water to remove any traces of hydrogen fluoride. During immersion, the aqueous hydrogen fluoride solution may be maintained at a temperature of about 10 to 30 degrees Celsius. The duration of the wet dip process is generally between 1 and 10 minutes. One specific process uses an aqueous solution that comprises about 1% by volume of hydrogen fluoride, at a temperature of about 20 degrees Celsius (i.e., room temperature), for a duration of about 5 minutes.
  • At step [0037] 110, the sequence 100 ends.
  • The inventive method for removing residues from the substrate uses only one wet treatment step (step [0038] 108), and such wet treatment step is performed after the substrate is removed from a vacuumed portion of the manufacturing environment. As a result, in comparable applications, the sequence 100 facilitates about four times higher throughput (measured as a number of wafers processed in a unit of time) than conventional residue removal techniques.
  • FIG. 3 depicts a schematic diagram of the exemplary Advanced Strip and Passivation (ASP) reactor [0039] 300 that may be used to practice portions of the invention. The ASP reactor is available from Applied Materials, Inc. of Santa Clara, Calif. The reactor 300 comprises a process chamber 302, a remote plasma source 306, and a controller 308.
  • The process chamber [0040] 302 generally is a vacuum vessel, which includes a first portion 310 and a second portion 312. In one embodiment, the first portion 310 comprises a substrate pedestal 304, a sidewall 316 and a vacuum pump 314. The second portion 312 comprises a lid 318 and a gas distribution plate (showerhead) 320, which defines a gas mixing volume 322 and a reaction volume 324. The lid 318 and sidewall 316 are generally formed from a metal (e.g., aluminum (Al), stainless steel, and the like) and electrically coupled to a ground reference 360.
  • The substrate pedestal [0041] 304 supports a substrate (wafer) 326 within the reaction volume 324. In one embodiment, the substrate pedestal 304 may comprise a source of radiant heat, such as gas-filled lamps 328, as well as an embedded resistive heater 330 and a conduit 332. The conduit 332 provides a gas (e.g., helium) from a source 334 to the backside of the wafer 326 through grooves (not shown) in the wafer support surface of the pedestal 304. The gas facilitates heat exchange between the support pedestal 304 and the wafer 326. The temperature of the wafer 326 may be controlled between 20 to 400 degrees Celsius.
  • The vacuum pump [0042] 314 is adapted to an exhaust port 336 formed in the bottom 316 of the process chamber 302. The vacuum pump 314 is used to maintain a desired gas pressure in the process chamber 102, as well as evacuate post-processing gases and volatile compounds from the chamber. In one embodiment, the vacuum pump 314 comprises a throttle valve 338 to control a gas pressure in the process chamber 302.
  • The process chamber [0043] 302 also includes conventional systems for retaining and releasing the wafer 326, end of process detection, internal diagnostics, and the like. Such systems are collectively depicted in FIG. 3 as support systems 340.
  • The remote plasma source [0044] 306 includes a microwave power source 346, a gas panel 344, and a remote plasma chamber 342. The microwave power source 346 comprises a microwave generator 348, a tuning assembly 350, and an applicator 352. The microwave generator 348 is generally capable of producing about 200 W to 3000 W at a frequency of about 0.8 to 3.0 GHz. The applicator 352 is coupled to the remote plasma chamber 342 to energize a process gas (or gas mixture) provided to the remote plasma chamber 342 into a microwave plasma 362.
  • The gas panel [0045] 344 uses a conduit 366 to deliver the process gas to the remote plasma chamber 342. The gas panel 344 (or conduit 366) comprises means (not shown), such as mass flow controllers and shut-off valves, to control gas pressure and flow rate for each individual gas supplied to the chamber 342. In the microwave plasma 362, the process gas is ionized and dissociated to form reactive species.
  • The reactive species are directed into the mixing volume [0046] 322 through an inlet port 368 in the lid 318. To minimize plasma damage to devices formed on wafer 326, the ionic species of the process gas 364 are substantially neutralized within the mixing volume 322 before the gas reaches the reaction volume 324 through a plurality of openings 370 in the showerhead 320.
  • To facilitate control of the process chamber [0047] 300 as described above, the controller 308 may be one of any form of general-purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory, or computer-readable medium, 356 of the CPU 354 may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 358 are coupled to the CPU 354 for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. The inventive method is generally stored in the memory 356 as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 354.
  • FIG. 4 is a table [0048] 400 summarizing the process parameters of the plasma strip process described herein using the ASP reactor. The process parameters summarized in column 402 are for one exemplary embodiment of the invention presented above. The process ranges are presented in column 404. Exemplary process parameters for the plasma strip process are presented in column 406. It should be understood, however, that the use of a different plasma reactor may necessitate different process parameter values and ranges.
  • The invention may be practiced in other semiconductor systems wherein the processing parameters may be adjusted to achieve acceptable characteristics by those skilled in the art by utilizing the teachings disclosed herein without departing from the spirit of the invention. [0049]
  • While the foregoing is directed to the illustrative embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. [0050]

Claims (23)

    What is claimed is:
  1. 1. A method for removing residue from a substrate, comprising:
    providing a substrate having a metallic residue thereon; and
    exposing the substrate to a hydrogen-based plasma to volatize the metallic residue.
  2. 2. The method of claim 1 wherein the metallic residue comprises at least one of a metal-containing residue and a polymeric residue.
  3. 3. The method of claim 2 wherein the metal-containing residue comprises at least one metal selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W) and hafnium (Hf).
  4. 4. The method of claim 1 wherein the hydrogen-based plasma comprises at least one of hydrogen (H2), water vapor (H2O).
  5. 5. The method of claim 1 wherein the hydrogen-based plasma comprises hydrogen (H2) and water vapor (H2O) at a H2:H2O flow ratio in a range from 20:1 to 100% of H2.
  6. 6. The method of claim 1 wherein the exposing step comprises:
    providing hydrogen (H2) and water vapor (H2O) at a H2:H2O flow ratio in a range from 20:1 to 100% of H2;
    maintaining the substrate at a temperature of about 100 to 300 degrees Celsius at a process chamber pressure between about 1 to 4 Torr;
    applying about 1000 to 2000 W of microwave power at about 2.45 GHz to form the hydrogen-based plasma; and
    exposing the substrate to the hydrogen-based plasma for about 40 to 200 seconds.
  7. 7. The method of claim 1 further comprising immersing the substrate in an aqueous solution including hydrogen fluoride after exposing the substrate to the hydrogen-based plasma.
  8. 8. The method of claim 7 wherein the aqueous solution comprises between 0.5 and 12% by volume of hydrogen fluoride.
  9. 9. The method of claim 8 wherein the aqueous solution further comprises between 0.5 and 15% by volume of nitric acid (HNO3).
  10. 10. The method of claim 8 wherein the aqueous solution further comprises between 0.5 and 15% by volume of hydrogen chloride (HCl).
  11. 11. The method of claim 7 wherein the substrate is immersed in the aqueous solution for about 1 to 10 minutes.
  12. 12. The method of claim 7 wherein the immersing step comprises:
    immersing the substrate in an aqueous solution comprising between 0.5 and 12% by volume of hydrogen fluoride and deionized water at a temperature of about 10 to 30 degrees Celsius for a duration of about 0.5 to 5 minutes.
  13. 13. A method for removing metallic residue from a substrate, comprising:
    providing a substrate having a metallic residue thereon;
    exposing the substrate to a hydrogen-based plasma to volatize the metallic residue; and
    immersing the substrate in an aqueous solution including hydrogen fluoride.
  14. 14. The method of claim 13 wherein the metallic residue comprises at least one of a metal-containing residue and a polymeric residue.
  15. 15. The method of claim 14 wherein the metal-containing residue comprises at least one metal selected from the group consisting of tantalum (Ta), titanium (Ti), tungsten (W) and hafnium (Hf).
  16. 16. The method of claim 13 wherein the hydrogen-based plasma comprises at least one of hydrogen (H2), water vapor (H2O).
  17. 17. The method of claim 13 wherein the hydrogen-based plasma comprises hydrogen (H2) and water vapor (H2O) at a H2:H2O flow ratio in a range from 20:1 to 100% of H2.
  18. 18. The method of claim 13 wherein the aqueous solution comprises between 0.5 and 12% by volume of hydrogen fluoride.
  19. 19. The method of claim 18 wherein the aqueous solution further comprises between 0.5 and 15% by volume of nitric acid (HNO3).
  20. 20. The method of claim 18 wherein the aqueous solution further comprises between 0.5 and 15% by volume of hydrogen chloride (HCl).
  21. 21. The method of claim 13 wherein the substrate is immersed in the aqueous solution for about 1 to 10 minutes.
  22. 22. The method of claim 13 wherein the exposing step comprises:
    providing hydrogen (H2) and water vapor (H2O) at a H2:H2O flow ratio in a range from 20:1 to 100% of H2;
    maintaining the substrate at a temperature of about 100 to 300 degrees Celsius at a process chamber pressure between about 1 to 4 Torr;
    applying about 1000 to 2000 W of microwave power at about 2.45 GHz to form the hydrogen-based plasma; and
    exposing the substrate to the hydrogen-based plasma for about 40 to 200 seconds.
  23. 23. The method of claim 13 wherein the immersing step comprises:
    immersing the substrate in an aqueous solution comprising between 0.5 and 12% by volume of hydrogen fluoride and deionized water at a temperature of about 10 to 30 degrees Celsius for a duration of about 0.5 to 5 minutes.
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Cited By (15)

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US20050199586A1 (en) * 2004-03-12 2005-09-15 Semiconductor Leading Edge Technologies, Inc. Resist removal method and semiconductor device manufactured by using the same
US20050208756A1 (en) * 2004-03-16 2005-09-22 Semiconductor Leading Edge Technologies, Inc. Method of removing resist, semiconductor device thereby and method of manufacturing a semiconductor device
US20050215445A1 (en) * 2002-07-29 2005-09-29 Mohamed Boumerzoug Methods for residue removal and corrosion prevention in a post-metal etch process
US20060032833A1 (en) * 2004-08-10 2006-02-16 Applied Materials, Inc. Encapsulation of post-etch halogenic residue
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US9564344B2 (en) 2009-12-11 2017-02-07 Novellus Systems, Inc. Ultra low silicon loss high dose implant strip
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
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