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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
  • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
  • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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  • H10D64/00—Electrodes of devices having potential barriers
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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  • H10D64/01—Manufacture or treatment
  • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Definitions

• the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for effectively removing contaminants present on a silicon layer surface and an internal surface before forming an electrode on the silicon layer.
• the present invention relates to a method for manufacturing a semiconductor device capable of forming an electrode having low resistance, high heat resistance and a uniform film thickness by removing the electrode.
• the gate electrode of an N-type field-effect transistor is formed by the following method using salicide technology.
• a polycrystalline silicon film was deposited on the
• the HB silicon film is etched with a reactive ion etching (RIE) method using an etching mask 306 with a relogen-based etching gas.
• RIE reactive ion etching
• low-concentration impurity ions are applied to the obtained silicon substrate 301 through an injection protective film 300 made of a silicon oxide film. Implantation is performed to form LDD (Lightly Doped Drain) region 308. Subsequently, as shown in FIG. 7 (c), a silicon oxide film 310 is deposited on the entire surface of the obtained silicon substrate 301, and as shown in FIG. 7 (d), The silicon oxide film 309 is etched back by the RIE method to form a side wall capacitor 310.
• LDD Lightly Doped Drain
• ion implantation and heat treatment are performed again via the implantation protection film 312 to form the source Z drain region 313.
• a titanium film 314 is deposited, and a RTA (Rapid Thermal Annealing) method is performed in a nitrogen atmosphere. After heat treatment, titanium film 3
• a titanium silicide film 315 is formed.
• the unreacted titanium film and the titanium nitride film formed on the surface are selectively removed using a mixed solution of sulfuric acid and hydrogen peroxide solution, and the titanium film is removed.
• a recycled electrode is formed on the source Z drain region 308 and the gate electrode 305 in a self-aligned manner.
• the thickness of the oxide film 309 and the etching rate vary, the thickness of the oxide film 309 is 10 to 30%. % Over etching I do. For this reason, the surface of the silicon substrate is directly exposed to a halogen-based etching gas, such as CHF 3 or CF 4 , and the surface of the silicon substrate is exposed to halogen atoms in the etching gas. There is a problem of contamination.
• a halogen-based etching gas such as CHF 3 or CF 4
• JP-A-62-94937 and JP-A-8-250463 disclose that an etching damaged layer is formed by a sputtering method or a sacrificial oxidation method. A method of forming an oxide film and removing the oxide film by a method of removing the oxide film has been proposed.
• incineration ashing treatment or a mixed solution of sulfuric acid and hydrogen peroxide, a mixed solution of hydrochloric acid and hydrogen peroxide, a mixed solution of ammonia and hydrogen peroxide, etc.
• a method of cleaning the substrate surface with an acid or an alkaline solution has been used.
• the halogen atoms present on the surface and the inner surface of the silicon layer are removed so as to have a concentration of 10 ppm or less, and an electrode is formed on the obtained silicon layer.
• a method for manufacturing a semiconductor device is provided.
• a gate oxide film and a gate electrode are formed on a silicon substrate, an insulating film is laminated on the silicon substrate including the gate electrode, and the insulating film is etched by halogen.
• a sidewall spacer is formed on the side wall of the gate electrode, and a titanium film is formed on the obtained silicon substrate at a substrate temperature of 500 ° C. or less.
• FIG. 1 is a schematic cross-sectional process diagram of a main part for describing a method for removing halogen atoms present on a silicon layer surface and an internal surface in a method for manufacturing a semiconductor device of the present invention.
• FIG. 2 is a graph for explaining the relationship between the second heat treatment temperature and the sheet resistance value of the refractory metal silicide film formed by the method for manufacturing a semiconductor device of the present invention.
• FIG. 3 shows a semiconductor device formed by the method of manufacturing a semiconductor device of the present invention. This is a graph showing the relationship between the width of the gate electrode made of a refractory metal silicide film, that is, the gate length of a transistor and the sheet resistance.
• FIG. 4 is a schematic cross-sectional process diagram of a main part for describing an embodiment of a method for manufacturing a semiconductor device of the present invention.
• FIG. 5 is a schematic cross-sectional view of an essential part for explaining a state of a silicon layer surface when a titanium film is formed at a substrate temperature of 500 ° C. or more in the method of manufacturing a semiconductor device of the present invention.
• FIG. 6 is a schematic cross-sectional process drawing of a main part for describing another embodiment of the method for manufacturing a semiconductor device of the present invention.
• FIG. 7 is a schematic cross-sectional process drawing of a main part for describing a conventional method of manufacturing a semiconductor device.
• Figure 8 is a graph showing the relationship between the amount of fluorine, which is a contaminant, and the junction leakage current.
• halogen atoms present on the surface of the silicon layer and the internal surface are removed so as to have a concentration of 10 O ppm or less, and the obtained silicon layer is removed.
• An electrode is formed on the substrate.
• the polycrystalline silicon film 305 (gate electrode) was patterned by RIE. Halogen-based atoms in the etching gas enter the interior of the silicon substrate due to the current force, ions and radicals during etching, and contaminate the interior of the substrate.
• the etching damage layer 311 is formed on the surface of the silicon substrate due to over-etching during the formation of the side wall spacer, and contaminants are removed from the silicon substrate.
• the contaminants enter the interior of the substrate 301, but this contamination is caused not only by the over-etching gas but also by the knock-on during ion implantation.
• T i S i 2 and T i - for interfacial free energy between a compound such as F is large
• T i S i 2 and T i - is the reduction compounds such as F are separated Is more stable, and when energy is applied from the outside, it is easily separated and the silicide membrane aggregates.
• a titanium silicide film is formed on a silicon substrate on which a contaminant such as fluorine is present, for example, a junction region between the source Z drain region and the well region is formed.
• Current increases. This is because, in the presence of a contaminant, the salicide-forming reaction becomes non-uniform as described above, and the salicide film becomes non-uniform. In other words, the film thickness becomes very thick in only some areas, In other regions, a phenomenon occurs in which the film thickness becomes extremely thin. In the region where the titanium silicide film is thin, the above-mentioned aggregation is likely to occur, and the electric resistance increases. This is because the distance to the recycled film becomes shorter.
• junction leakage current value shown in Fig. 8 is clear from the relationship between the junction leakage current value shown in Fig. 8 and the contaminants (fluorine) present on the silicon substrate.
• fluorine when fluorine is implanted into the region where the n + / p junction is formed, titanium silicide is formed, and the junction leakage current value is measured. As the amount increases, the junction leakage current increases, and the presence of fluorine deteriorates the junction leakage.
• the silicon layer means a layer mainly composed of silicon, and the silicon substrate itself, electrodes and wirings are formed on the semiconductor substrate. This includes any of the silicon films formed as described above. Further, the silicon layer includes any layer made of a single-crystal silicon, a polycrystalline silicon, and an amorphous silicon. The silicon layer may be unused, unprocessed, or unprocessed before forming a semiconductor device or the like, but may be any silicon substrate or a semiconductor substrate during a semiconductor device manufacturing process. It may be a silicon film.
• an etching gas for example, CHF 3 , CF 3 used for RIE or the like when patterning a gate electrode or the like or forming a side wall spacer is used.
• etching gas for example, CHF 3 , CF 3
• the surface of the silicon layer and the inner surface refer to the surface of the silicon layer in the region where the electrodes are formed in a later step and the inner surface thereof.
• the surface refers to a region near the surface and inside the silicon layer, and is generally formed by etching, ion implantation, heat treatment, or the like performed during a process of a semiconductor device manufacturing method. It means the inner region of the silicon layer into which contaminants are introduced.
• Halogen atom means an atom that is mainly mixed as a contaminant in a cleaning, etching, film forming process, or the like performed during a process of manufacturing a semiconductor device, and is, for example, fluorine, chlorine, or bromine. And the like.
• a silicon layer of 500 ° C. or less is placed on the silicon layer.
• a titanium film is formed at the temperature of the titanium layer, and then the titanium film is removed.
• the titanium film may be a film mainly composed of titanium as atoms constituting the film. In addition to a film composed of 100% titanium atoms, it may be formed by a film forming method. Examples of such a film include a film containing titanium which has become an oxide or a nitride by mixing atoms such as oxygen and nitrogen. Above all, a film composed of about 100% of titanium atoms is preferable.
• the method for forming the titanium film is not particularly limited as long as the temperature of the silicon layer can be maintained at 500 ° C. or lower.
• a sputtering method a chemical
• CVD method chemical vapor deposition method
• plating method a plating method
• vacuum deposition method a vacuum deposition method
• EB method a vacuum deposition method
• MEB method a MEB method.
• the sputtering method is not suitable for titanium film formation.
• the use of energy is preferable because contaminants can be efficiently incorporated into the titanium film.
• the thickness of the titanium film is not particularly limited as long as the contaminants on the silicon surface and the internal surface can be removed, and for example, is about 20 to 10 nm.
• the silicon in the silicon layer and the titanium in the titanium film may be in contact with each other. And a silicon silicide layer is formed on the surface or inside of the silicon layer. As a result, when the titanium film is removed in a later step, the silicon layer is also removed, which causes unevenness on the surface of the silicon layer, which is not preferable.
• the method of removing the titanium film is such that no contaminants such as halogen atoms remain or enter the silicon layer surface and the internal surface after the titanium film is removed. If there is, it is not particularly limited. Examples of such a method include dicing using an acid or alkaline solution such as a mixed solution of sulfuric acid and hydrogen peroxide, a mixed solution of hydrochloric acid and hydrogen peroxide, and a mixed solution of ammonia and hydrogen peroxide. Chemical etching for performing a pre-treatment or the like. After removing the titanium film by chemical etching or the like, it is preferable to perform treatment with a hydrofluoric acid-based solution.
• the treatment with the hydrofluoric acid solution completely removes the compound of titanium and silicon reacted by the externally applied energy such as the substrate temperature and the sputtering energy. You can do it.
• Such a method causes an inhibition of the silicidation reaction, an increase in resistance, and a deterioration in heat resistance (promotion of aggregation), particularly when an electrode is formed using a silicidation reaction in a later step. Contaminants can be removed efficiently.
• ion implantation is performed after forming the titanium film and before removing the titanium film. Is also good.
• the energy of the ion implantation can promote the incorporation of contaminants present on the surface and the inner surface of the silicon layer into the titanium film.
• the ions at this time include, for example, ions such as SiN, As, P, Sb, BGa, and In.
• the acceleration voltage at that time is about 20 to 50 keV, and the dose is 1 ⁇ 10 15 to 1 ⁇ 10 16 cm—about 2 .
• an electrode is formed on the silicon layer whose surface and inner surface have been cleaned.
• the electrodes here are those used as electrodes or wiring, and these include those that become a part of wiring such as contact plugs and metal. These materials are not particularly limited as long as they are conductive materials. For example, metals such as Al, Cu, Au, PtNi, and Ag; refractory metals such as Ti, Ta, W, and Mo; polysilicon; The silicide with the icon; There are various types, such as those of silicon and polysilicon, and among them, when used as a source, drain or gate electrode, the self- From the viewpoint that they can be formed in a consistent manner and have low resistance, a silicide is preferable, and when used as wiring, Al, Cu, W, etc. are preferable. Further, these conductive materials may be a single-layer film or a laminated film. The film thickness of the electrode at this time is not particularly limited, and for example, when it is used for a gate electrode, about 150 to 400 nm.
• the electrodes can be formed by a known method, for example, a sputtering method, a CVD method, a plating method, or the like.
• a refractory metal film is deposited on the silicon layer to a thickness of about 10 to 50 nm, and then the first and second layers are formed. There is a method of performing a second two-stage heat treatment.
• Examples of the heat treatment method include furnace annealing and RTA.
• the RTA method is preferable from the viewpoint of controlling impurity diffusion.
• the first heat treatment is performed at 400 at a temperature range of up to 700 ° C. for about 10 to 30 seconds
• the second heat treatment is performed at 800 to 100 ° C. This may be performed in a temperature range of 0 ° C, preferably around 850 ° C, for about 10 to 30 seconds.
• a C 49 phase titanium silicide layer is formed by the first heat treatment
• a C 49 phase is formed by the second heat treatment.
• Low-resistance stoichiometrically stable titanium silicide layer It can be changed to a 4-phase titanium silicide layer.
• steps such as an ion implantation step and a patterning step may be arbitrarily performed.
• steps such as an ion implantation step and a patterning step may be arbitrarily performed.
• a silicon oxide film is formed on a silicon substrate, and this silicon oxide film is formed by the RIE method using CHF 3 , a mixed gas of CF and Ar as an etching gas.
• the silicon oxide film was removed by performing an etch back so as to overetch by about 20% of the thickness of the silicon oxide film.
• a titanium film 103 was formed on this silicon substrate 101 by a sputtering method so as to have a thickness of about 3 O nm. .
• Substrate temperature during formation of titanium film 103 The degree was set at 200.
• silicon atoms and contaminants 102 on the surface and the inner surface of the silicon substrate 101 react with the titanium film 103 by the sputter ring energy to form titanium. It will be taken into the membrane. In other words, strong contaminants 102 on the surface of the silicon substrate 101 and contaminants 102 on the internal surface, which cannot be removed by ordinary washing with an acid or alkali solution, are removed. By reacting the silicon atom on the surface with the titanium film 103, it is taken into the titanium film 103 including the titanium silicide film 104 formed by this reaction. This is possible.
• the substrate temperature is relatively low at 500 ° C. or less, the reaction between the silicon atoms on the surface of the silicon substrate 101 and the titanium film 103 is minimized. Because it is suppressed, the surface of the silicon substrate 101 is not roughened.
• the fluorine atoms could be further reduced.
• the titanium film is sputtered by setting the substrate temperature to a relatively high value of 440, the fluorine atoms are completely removed after the removal of the titanium film, and it can be reduced to below the detection limit. Was confirmed.
• the contaminant 102 mainly on the surface and the inner surface is reacted with the titanium film 103, and then the titanium film 103 is removed in order to remove the titanium film 103.
• the contaminant 102 can be removed together with the substrate 103, and the surface and the inside of the silicon substrate 101 can be cleaned.
• the heat treatment for reacting the titanium film 103 with the silicon atoms is not particularly performed, no damage is given to the surface of the silicon substrate 101 during the processing.
• a P ⁇ region, a field oxide film, a gate oxide film, and the like are formed on a silicon substrate, and a film thickness of 150 nm or less is formed on the obtained silicon substrate.
• a polycrystalline silicon layer of about 20 O nm is laminated, a gate electrode is formed using a mixed gas of HBr, C12, and O2 as an etching gas, and an injection protection film (
• the LDD region was formed by ion implantation using a film of silicon oxide (thickness of about 10 to 40 nm).
• the impurity ions are implanted to form an N-channel transistor.
• the acceleration voltage is 20 keV
• the dose is about 1 ⁇ 10 13 to 3 ⁇ 10 14 cm 2. I went in.
• ion implantation was performed again using an implantation protection film made of a silicon oxide film to form a source Z drain region. Ion implantation in this case, since the N-channel tiger Njisuta form, a Hisoi on, an acceleration voltage of 3 0 ⁇ 6 0 ke V, de Ichizu weight 1 ⁇ 5 x 1 0 1 5 cm - was carried out in two .
• the obtained silicon substrate surface is immersed and washed in a mixed solution of sulfuric acid and hydrogen peroxide at 150 ° C.
• these methods can be formed by a known method, for example, a method according to FIGS. 7 (a) to 7 (e).
• a titanium film was deposited on the obtained silicon substrate at a substrate temperature of 200 or at a substrate temperature of 44 ° C. with a film thickness of 30 nm in the same manner as in Example 1.
• the titanium silicide film remaining on the silicon substrate surface was removed by chemical etching by dipping in a 0.5% hydrofluoric acid aqueous solution for about 30 to 45 seconds.
• a titanium film having a thickness of about 30 nm is laminated on the obtained silicon substrate, and silicon ions are added, for example, in order to promote a uniform reaction between the silicon and the titanium.
• the injection was performed at an acceleration voltage of 40 keV and a dose of 5 ⁇ 10 15 cm — 2 .
• the test was performed at various temperatures between about 800 and 900 ° C. for about a second.
• Figures 2 (a) to 2 (e) show the obtained sheet resistance of the titanium silicide.
• FIGS. 2 (a) to 2 (e) when the titanium film used for cleaning was formed at a substrate temperature of 200 ° C., the sample film (2) and the titanium film were removed. When the substrate was formed at a substrate temperature of 440 ° C, it is shown as a sample (3). For comparison with these samples, the surface of the silicon substrate was treated with sulfuric acid and peroxide without forming and removing the titanium film. Sample (1) shows the one washed only in step (1), and sample (4) shows the titanium silicide film formed directly on a clean silicon substrate without RIE etching.
• the sheet resistance with respect to the gate length when a gate electrode is formed on the silicon layer by using a titanium silicide film shows about the change of.
• the gate electrode thus formed was formed in the same manner as in Example 2, except that the titanium film was formed at a substrate temperature of 450 and the second heat treatment was performed at 850.
• the gate length of the gate electrode at this time was formed in a range of 0.1 to 0.7 ⁇ m.
• Figure 3 shows the sheet resistance at each gate electrode.
• a gate electrode was formed in the same manner as in this example except that the titanium film was not formed and removed, and the sheet resistance of each gate electrode was measured in the same manner. The results are also shown ( ⁇ ).
• the gate resistance of the gate electrode formed thereafter is reduced to a gate length as small as 0.1 m. Also barely climbed.
• the gate electrode is formed by the same method as the conventional method without forming and removing the titanium film, the sheet resistance is significantly increased, particularly in a thin wire gate of 0.5 m or less.
• the device isolation film 203 is formed by a known method, for example, a method according to FIGS. 7 (a) to 7 (e).
• a gate oxide film 204 is formed on a silicon substrate 201 having a silicon region 201 and a cell region 202, and a polycrystalline silicon is formed on the obtained silicon substrate 201.
• note input protective film is et a (not shown)
• an LDD region 207 was formed.
• a silicon oxide film having a thickness of about 100 to 200 nm is formed on the obtained silicon substrate 201, and the silicon oxide film is etched by RIE.
• RIE reactive ion etching
• ion implantation was again performed using an implantation protection film (not shown) made of a silicon oxide film to form a source / drain region 208. Thereafter, the injection protective film was removed.
• a titanium film 209 was formed to a thickness of 30 nm on the silicon substrate 201 by a sputtering method at a substrate temperature of 440 ° C.
• the contaminants on the surface of the silicon substrate 201 react with the deposited titanium film 209 to form the inside of the titanium film 209 or the sputtering film. It is taken into the titanium silicide film 210 formed by the energy of the time.
• the titanium film 209 containing the impurities was transferred to a mixed solution of sulfuric acid and hydrogen peroxide (5: to 10: 1). (150 ° C), followed by a titanium silicide film 2 containing titanium and contaminant reactants remaining on the silicon substrate 201 surface. 10 was immersed in a 0.5% hydrofluoric acid aqueous solution and removed by chemical etching.
• the etching time was set to 90 seconds or less to protect the previously formed side wall 206. Since titanium deposited on the surface can be completely removed by this chemical etching, titanium contamination on the surfaces of the silicon substrate 201 and the gate electrode 205 is eliminated. Further, there is no fear that the equipment used in the later step will be contaminated with the residual titanium.
• a titanium film 212 having a thickness of about 3 O nm is laminated on the obtained silicon substrate 201, and the silicon and the titanium
• silicon ions were implanted at, for example, an acceleration voltage of 40 keV and a dose of 5 ⁇ 10 15 cm 2 to mix the interface.
• a first heat treatment was performed at about 625 ° C. for about 10 seconds to react titanium and silicon, thereby forming a C49 phase titanium silicide layer 213.
• a silicidation reaction occurs to form a titanium silicide film, while the silicon oxide film and the titanium film are formed.
• the silicidation reaction is suppressed, and no titanium silicide film is formed. Therefore, the mixture of sulfuric acid and hydrogen peroxide
• the unreacted titanium film 211 is removed by hot etching with the combined solution.
• a second heat treatment of about 875 ° C for about 10 seconds is performed to convert the C49 phase titanium resid layer 21 to a lower resistance C54 phase resiliency layer. Layer.
• the titanium silicide film 21 3 can be formed on the source Z drain region 208 and the gate electrode 205 in a self-aligned manner.
• the contamination temperature on the surface of the silicon substrate 201 and the gate electrode 205 is reduced by setting the substrate temperature at the time of forming the titanium film 209 to 500 or less. could be removed.
• the substrate temperature at the time of forming the titanium film 209 is 500 ° C. or higher, for example, 700 ° C.
• the silicon substrate 201 or the gate electrode 20 5 reacts with titanium across the interface to form silicide crystals.
• the silicide crystal is also etched away, as shown in Fig. 5 (a). Then, irregularities 400 are generated on the surface of the silicon substrate 201 or the gate electrode 205.
• the reaction between titanium and silicon occurs in the reaction system containing contaminants, the silicidation reaction does not occur uniformly as described above, and the silicon substrate 201 As a result, significant unevenness 400 is generated on the surface of the electrode 205, and a flat surface cannot be obtained.
• a titanium silicide film 2 13 is formed on the silicon substrate 201 and the gate electrode 205 on which the irregularities 400 are formed.
• a uniform titanium silicide film 213 cannot be obtained, heat resistance is degraded, and the resistance of the titanium silicide film 213 is increased.
• the interface between the titanium silicide film 21 3 finally obtained and the silicon substrate 201 becomes deep, and the junction between the source Z drain region 208 and the well region 202 is formed. As a result, the distance from the titanium silicide film 2 13 becomes shorter, and the junction leakage of the current increases.
• the formation and removal of the titanium film are performed after the formation of the source drain region.
• the titanium film is formed. Formation and removal may be performed.
• This embodiment shows an example in which contaminants are more reliably removed by ion implantation.
• a 30-nm-thick titanium film was mainly formed on a silicon substrate by a gate electrode, a side wall spacer, and a snow ring method. After that, a silicon film is formed on the silicon substrate and the gate electrode through the obtained titanium film. Injection was performed at an accelerating voltage of 20 to 5 O keV and a dose of about 1 ⁇ 10 15 to 1 ⁇ 10 16 cm— 2 .
• This ion implantation can promote the mixing of the titanium film with the contaminants.
• the removal of the titanium film, the formation of the titanium silicide, and the like are performed to complete the semiconductor device.
• the titanium film and the contaminant can be mixed by ion implantation, so that the silicon substrate can be mixed by the ion implantation energy.
• the contaminants existing on the inner surface of the metal can be efficiently taken into the titanium film. Therefore, by removing the titanium film and the titanium silicide film, it is possible to more reliably remove contaminants.
• a gate oxide film 304, a gate electrode 305, and a size are formed on a silicon substrate 301 having an element isolation film 303 and a vinyl region 302.
• a dowel 310 was formed, and a source / drain region 313 having an LDD region 308 was formed on the inside surface of the silicon substrate 301.
• an interlayer insulating film 501 having a thickness of about 400 nm is formed on the obtained silicon substrate 301 so as to have a desired shape.
• a contact hole 502 was opened in the interlayer insulating film 501 on the source Z drain region 313 by RIE using C 4 F 8 or the like as an etching gas.
• the surface 503 of the silicon substrate 301 at the bottom of the contact hole is contaminated by halogen atoms contained in the etching gas.
• the snow was placed on the entire surface of the silicon substrate 301 including the contact hole 502 at a temperature of 44 ° C.
• a titanium film 504 having a thickness of about 30 nm was deposited by the sputtering method.
• the titanium film 504 and the titanium silicide film 505 containing the contaminants are removed by the same method as in the first embodiment.
• a titanium film (not shown) is deposited in a contact hole to a thickness of about 50 to 100 nm in a contact hole by a known method, and a nitrogen atmosphere is formed.
• a nitrogen atmosphere is formed at the bottom of the contact hole 502 to react silicon and titanium, and at the same time, form titanium nitride on the surface of the titanium film to form a barrier metal. (Not shown), and then metal for wiring is buried in the contact hole 502. By turning, a metal wiring 507 was formed.
• the silicide film is not formed on the gate electrode and the source / drain region surface, even if the silicide film is not formed, The bottom of the contact hole can be cleaned.
• the contact resistance can be reduced due to the cleaning of the metal Z silicon interface at the bottom of the contact hole.
• a small amount of contamination can Although this deteriorates the sonic characteristics, the method of the present embodiment becomes more effective as the contact opening area becomes smaller.
• an electrode is formed on the obtained silicon layer in order to reduce the concentration of halogen atoms present on the surface and the internal surface of the silicon layer to 10 ppm or less. In this case, the heat resistance of the electrode itself can be improved, and the resistance of the obtained electrode can be reduced.
• a silicon layer of 500 ° C or less is placed on the silicon layer.
• the conditions for forming the titanium film are relaxed to a silicon layer temperature of 500 ° C. or less, even if the titanium film is removed, the damage on the surface of the silicon layer is damaged. Can be minimized. Therefore, it is possible to prevent not only the deterioration of the omic contact due to the damage of the surface of the silicon layer when an electrode is formed on the silicon layer in a later process, but also it is possible to prevent the deterioration. In addition, it is possible to improve the uniformity of the electrode film, the resistance of the electrode itself, and the heat resistance, and further prevent leakage current.
• such a method can be used as it is in a process normally used in a normal method of manufacturing a MOS semiconductor device, so that it can be realized without requiring the development of a new manufacturing technology or manufacturing equipment. It is possible to do this.

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• 1997
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