TW475239B - Method to form MOS transistor having silicide on source/drain - Google Patents

Abstract

A method to form MOS transistor having silicide on source/drain is disclosed, which comprises: providing a silicon substrate; forming a first dielectric layer on the silicon substrate; forming a conductive layer on the first dielectric layer; forming the second dielectric layer on the conductive layer; performing the pattern transfer procedure to remove part of the second dielectric layer and part of the conductive layer to form a gate structure, forming a spacer on the sidewall of the gate structure; doping plural metal particles into the silicon substrate, wherein these metal particles can penetrate through the first dielectric layer to the silicon substrate but cannot penetrate through the second dielectric layer to the conductive layer; performing the heat treatment procedure to form silicide layer on the silicon substrate; removing the portion of unreacted metal particles.

Description

475239 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a metal oxide semi-electric crystal, particularly a method for forming a metal oxide semi-electric crystal which can reduce side effects and control the position of a metal silicide. 5-2 Background of the Invention: Due to the advantages of low resistance, high temperature resistance, and easy integration with polycrystalline silicon, metal silicides have been widely used in semiconductor device manufacturing processes, such as to connect metals Part of the interconnect and the source-drain of the transistor or part of the polycrystalline silicon silicide metal (po 1 yci de) used as the gate. There are two methods for forming metal silicide in conventional techniques: one is to directly form a metal silicide layer on the substrate; the other is to first form a metal on the substrate and then react the metal and silicon by a heat treatment process And metal silicide is formed. The former method involves reacting a compound containing stone with a compound containing metal to form a metal silicide, so it is difficult to avoid problems such as by-produce and pollution. For example, in the direct formation of tungsten disilicon (WS i 2) by chemical vapor deposition, Si 一般 and WF are generally allowed to spread to form

475239 V. Description of the invention (2) WSi 2, but at this time WSi 2 will contain non-negligible fluorine (F), so that the performance of the gate electrode will be changed by the thermal diffusion of fluorine in the subsequent process (especially the thermal process). Bad. In other words, by-products and pollution are inevitable shortcomings of this method. The latter method forms the metal required to form the metal silicide on the substrate, so the efficiency of the entire method depends on the efficiency of the metal formation process. Metals are generally formed by physical vapor deposition (physica 1 va ρ 〇rdepositi ο η, PCD) (sputtering, evaporation) or chemical vapor deposition (CVD), and it is not easy to control evaporation The composition of the metal plating and the formation of the metal with good step coverage, the energy efficiency of sputtering is not high and the step coverage of the formed metal is not good, and the chemical vapor deposition is as difficult as possible to avoid the problems of by-products and pollution. . Obviously, this method is not efficient and it is not easy to form the required metal accurately. Obviously, the various methods for forming metal silicides in the conventional arts have a lot of room for improvement, so it is necessary to develop more efficient and less side-effect metal silicide forming methods. 5-3 Purpose and Summary of the Invention: The main purpose of the present invention is to propose a method for efficiently forming a metal silicide.

475239 5. Description of the invention (3) Another object of the present invention is to provide a method that can reduce side effects such as by-products and pollution during the formation of metal silicides. A preferred embodiment of the present invention is a method for forming a gold-oxygen semi-electric crystal having a metal silicide on a source drain electrode, which at least includes: providing a silicon substrate; forming a first dielectric layer on the silicon substrate; forming The conductor layer is on the first dielectric layer; a second dielectric layer is formed on the conductor layer; a pattern transfer step is performed to remove at least part of the second dielectric layer and part of the conductor layer to form a gate Electrode structure; forming a spacer on the side wall of the gate structure; doped with a plurality of metal particles to the silicon substrate, where these metal particles can penetrate the first dielectric layer into the silicon substrate but cannot penetrate the second The dielectric layer is inside the conductor layer; a heat treatment process is performed to form a metal silicide layer on the silicon substrate; and an unreacted part of the metal particles is removed. 5-4 Detailed description of the invention: In view of the various defects in the process of forming metal lithotripsy by conventional techniques, the inventor of the present invention proposes several entry points ... First, because the method of directly forming metal silicide must be chemically reacted The metal silicide is formed, so the by-products and pollution generated by the reaction process are unavoidable. Therefore, the influence of reactants / contamination must always be controlled by modifying the reaction chamber or forming a barrier layer on the wafer. Second, first form metal and then penetrate the heat

475239 V. Description of the invention (4) In order to form the metal silicide, in addition to the metal must be evenly distributed on the wafer to ensure that the metal silicide can be reliably formed, the metal teeth must be controlled to penetrate into the wafer. In order to ensure that the metal fossil compound does not take a photo to change (make it worse) the properties of the semiconductor structure below it. Thirdly, the method on the wafer can be adjusted arbitrarily, the only limitation is the quality of the formed metal. According to these points, the inventor of the present invention proposes a method for forming a metal oxide semi-electric crystal: firstly, metal particles (metal atoms or metal ions are formed on a wafer surface using an implantation method with a mature technology) Or in the surface layer), and then perform a heat treatment process to form a metal silicide. Since the metal silicide is not directly formed by a chemical reaction, the occurrence of by-products and pollution can be avoided; the implantation method can accurately control the incorporation of the mixed metal particles Energy, doping concentration and doping orientation can therefore ensure the uniform distribution of the metal and the uniform distribution of the metal silicide; furthermore, the energy use efficiency of the implantation method will not be as low as sputtering, so the present invention will not cause the entire transistor The output of the process is reduced throughout.

A preferred embodiment of the present invention is a method for forming a metal oxide semi-electric crystal of a kind of stone oxide, which is formed on the source and the electrode and has at least the following steps: Gold is shown in the first A diagram, and 1 1 is on a silicon substrate. On the material 10, the first silicon substrate 10 is formed here and a first dielectric layer is formed—the dielectric layer 11 can serve at least as the second gate &

475239 V. Description of the invention (5) For electric layer. The first dielectric layer 11 is usually an oxide layer, and a typical thickness is about 50 to 300 angstroms. As shown in the first B diagram, a conductor layer 12 is formed on the first dielectric layer 11 and a second dielectric layer 13 is formed on the conductor layer 12. The conductor layer 12 can be used as at least a gate conductor layer. The conductor layer 12 can be one of the following: a metal layer, a polycrystalline silicon layer, and a polycrystalline silicon silicide layer, and its typical thickness is about 5 0 Angstroms to 3 5 0 0 Angstroms. The second dielectric layer 13 may be one of the following: a silicon dioxide layer, a silicon nitride layer, a combination of a silicon dioxide layer and a silicon nitride layer, and a silicon oxynitride compound layer (S i 0 XN y), And the typical thickness of the second dielectric layer 13 is about 300 Angstroms to 2000 Angstroms. As shown in FIG. 1C, a pattern transfer step is performed to remove a portion of the second dielectric layer 13, a portion of the conductor layer 12, and a portion of the first dielectric layer 11 to form a gate structure. Then, a partition wall 14 is formed on the side wall of the gate structure as shown in the first D diagram, and a plurality of metal particles 15 are doped with an ion implantation (i ο nimp 1 antati ο η) technique or other conventional techniques, such as Metal ions or metal atoms, up to 10 on silicon substrate. Of course, unless covered with a photoresist, part of the metal particles 15 will also be doped to the spacer 14 and the second dielectric layer 13. As shown in the first figure E, a heat treatment process is performed to make the metal particles

475239 V. Description of the invention (6) ^ ~, 15 reacts with the silicon substrate 10 to form a metal silicide layer 16. When iron contacts the silicon substrate 10, a part of the metal particles 丨 5 "," Time layer 16 (these unreacted metal particles, 5 and 5 will not form a metal silicide at this time the conductor layer 12 is superimposed on the second dielectric layer to simplify the illustration). By object 1 6 It will only be formed on the silicon substrate i 0 (that is, complex silicon, so metal silicidation will not be formed on the top of the gate structure. On the source drain of a crystal), the physical layer 16 is one of the following: Titanium bismuth: Generally speaking, metal silicide platinum disilicide, manganese disilicide, disilicide button: Cobalt silicide, tungsten disilicide, silicide layer 16 The type depends on the metal f Palladium silicide and metalworking Types of Uncle Gou Hun 1 5

The subsequent steps are followed by multiple phenomena. Of course, part of the metal scrap is to remove unreacted metal interconnects, etc. This step can also expand the layer 16. In some metal particles, the process occurred to remove the particles. 15 To avoid abnormal short circuit, connect with silicon substrate

It must be mentioned that the first (: graph $ p is not jealous in the step of pattern transfer ~ brother ^ — the step of E diagram can also be repaired by E. The advantage of this operation is to divide in the subsequent process t! Dielectric layer ". As a subsequent formation of other structures of _di-dielectric negative layer 1 1 can be used; the gate dielectric layer of the leisure. But must ;;: 卩 2, such as !! is Subsequent formation of the second and second dielectric layers 1 3 and > f, =, the effect of the first dielectric layer. In the process of particles 15, metal particles. Will be doped to the conductor layer 12 = 15 will only be doped "bottom" 10;

Page 9 475239 V. Description of the invention (7) The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others that are completed without departing from the spirit disclosed by the present invention Equivalent changes or modifications should be included in the scope of patent application described below.

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Claims (1)

475239 6. Scope of patent application1. A method for forming a gold-oxygen semi-electric crystal with a metal silicide on a source drain electrode, including at least: providing a silicon substrate; forming a first dielectric layer on the silicon substrate The first dielectric layer can be used as at least a gate dielectric layer; forming a conductor layer on the first dielectric layer; the conductor layer can be used as at least a gate conductor layer; forming a second dielectric layer An electric substance layer is on the conductor layer; A pattern transfer step is performed to remove a portion of the second dielectric layer, a portion of the conductor layer, and a portion of the first dielectric layer to form a gate structure; forming a gap wall on the gate A plurality of metal particles are doped on the silicon substrate; a heat treatment process is performed to form a metal silicide layer on the silicon substrate; and an unreacted part of the metal particles is removed. 2. The method according to item 1 of the scope of patent application, wherein the first dielectric layer is an oxide layer. 3. The method according to item 1 of the scope of patent application, wherein the thickness of the first dielectric layer is about 50 angstroms to 300 angstroms. Page 12 475239 6. Scope of patent application 4 · The method described in item 1 of the scope of patent application, wherein the thickness of the above-mentioned conductor layer is about 500 angstroms to 3 500 angstroms. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned conductor layer is one of the following: a metal layer, a polycrystalline layer, and a polycrystalline layer. 6. The method according to item 1 of the scope of patent application, wherein the thickness of the second dielectric layer is about 300 Angstroms to 2000 Angstroms. 7. The method according to item 1 of the scope of patent application, wherein the second dielectric layer is one of the following: a silicon dioxide layer, a silicon nitride layer, a combination of a silicon dioxide layer and a silicon nitride layer, and Silicon oxynitride layer (S i 0 XN y). 8. The method according to item 1 of the scope of patent application, wherein the above-mentioned metal particles are one of the following: metal ions and metal atoms. 9. The method according to item 1 of the scope of patent application, wherein the above-mentioned metal particles are doped to the substrate by ion implantation technology. 10. The method according to item 1 of the scope of the patent application, wherein the above-mentioned metal silicide layer is one of the following: titanium disilicide, cobalt disilicide, tungsten disilicide, platinum dilithium, and dilithium Meng, Ershixi tantalum, and the disilicide. 11. The method described in item 1 of the scope of patent application, further comprising removing 475239 6. Scope of patent application Part of the metal silicide layer in contact with the silicon substrate. 1 2. A method for forming a gold-oxygen semi-electric crystal with a metal silicide on a source drain, at least comprising: providing a broken substrate; forming a first dielectric layer on the silicon substrate, the first The dielectric layer can be at least a gate dielectric layer; a conductor layer is formed on the first dielectric layer, and the conductor layer can be at least a gate conductor layer; a second dielectric layer is formed on the first dielectric layer; On the conductor layer; performing a pattern transfer step to remove a portion of the second dielectric layer and a portion of the conductor layer to form a gate structure; forming a gap wall on a side wall of the gate structure; Doping a plurality of metal particles to the silicon substrate, where the metal particles can penetrate the first dielectric layer to the silicon substrate but cannot penetrate the second dielectric layer to the conductor layer; A heat treatment process is performed to form a metal stone oxide layer on the stone substrate; and an unreacted part of the metal particles is removed. 1 3. The method as described in item 12 of the scope of patent application, wherein the first dielectric layer is an oxide layer. 14. The method according to item 12 of the scope of patent application, wherein the first 475239 6. Scope of patent application The thickness of the dielectric layer is about 50 angstroms to 300 angstroms. 15. The method according to item 12 of the scope of patent application, wherein the thickness of the above-mentioned conductor layer is about 500 angstroms to 3 500 angstroms. 16. The method according to item 12 of the scope of patent application, wherein the conductor layer is one of the following: a metal layer, a polycrystalline silicon layer, and a polycrystalline silicon silicide layer. 17. The method according to item 12 of the scope of the patent application, wherein the thickness of the second dielectric layer is about 300 angstroms to 2000 angstroms. 18. The method as described in item 12 of the scope of patent application, wherein the second dielectric layer is one of the following: a silicon dioxide layer, a silicon nitride layer, a silicon dioxide layer, and a silicon nitride layer. Combination and oxynitride compound layer (S i 0 XN y). 19. The method according to item 12 of the scope of patent application, wherein the above-mentioned metal particles are one of the following: metal ions and metal atoms. 20. The method according to item 12 of the scope of the patent application, wherein the above-mentioned metal particles are doped to the substrate by an ion implantation technique. 2 1. The method as described in item 12 of the scope of the patent application, wherein the metal silicide layer is one of the following: titanium disilicide, cobalt disilicide, tungsten disilicide, platinum disilicide, disilicide, two Siliconized group and two siliconized handles. Page 15 475239 VI. Patent Application Scope 2. The method described in item 12 of the patent application scope further includes removing a portion of the metal silicide layer that is not in direct contact with the silicon substrate.