JPH01266745A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To stably reduce sheet resistance of silicide wiring within a wafer by implanting boron or silicon ion into a polysilicon layer covered with a mask. CONSTITUTION:Silicide conversion is performed by a high melt-point metal using the solid phase-reaction for a polysilicon layer 6 formed at a specified area on a semiconductor substrate 1 so that a contact layer is owned. In that case, before starting silicide conversion process, the area of the polysilicon layer 6 for the n-type semiconductor area 3 among the contact area is covered with a mask 20 and boron or silicon ion is implanted in the polysilicon layer 6 covered with the mask 20. Thus, it stably reduces sheet resistance of silicide wiring within a wafer.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, particularly, a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device using a solid phase reaction for a polysilicon layer formed to have an SN region. Regarding the technology of forming silicide wiring using high-melting point metal, the aim is to reduce the sheet resistance of silicide wiring in a stable state within the wafer. The method includes a step of covering a portion of the polysilicon layer corresponding to the n-type semiconductor region in the region I with a mask, and a step of implanting boron or silicon ions into the polysilicon layer covered with the mask. or (2) a step of implanting silicon ions into the above-mentioned polysilicon layer.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device using a high melting point metal using a solid phase reaction on a polysilicon (Poly-3i) layer formed to have a contact region in a predetermined region on a semiconductor substrate. The present invention relates to a technique for forming silicide wiring by siliciding.

[Prior art and problems to be solved by the invention]

Aluminum (AI) commonly used as wiring material
It is known that it becomes difficult to perform etching in the process when the size becomes submicron during miniaturization. On the other hand, Po1y-3i, which is widely used as an electrode material for gates, etc., can be easily etched even at a submicron level compared to AI, and is therefore suitable for miniaturization. Therefore, in view of the demand for higher integration or higher density and from a process standpoint, attempts have been made to use Poly-5t as a wiring material. However, since Po1y-St has a relatively high sheet resistance, when forming a Po1y-Si wiring layer, the Po1y-5t is silicided with a high melting point metal using a solid phase reaction. As a result, silicide wiring having low sheet resistance and high heat resistance is formed. Titanium (Ti) is generally used as the high melting point metal because it can achieve the lowest sheet resistance among silicide compounds.

In this silicidation (TiSi, formation) by solid phase reaction, Ti is deposited on the surface of Po1y-5i or St and reacted with Si, and silicide is formed by increasing the reaction temperature. ing. In this case, the silicide is selectively
It is formed only on the surface of 5i or St, and silicon dioxide (S
It is necessary to take care in the process so that it is not formed on an insulating layer such as a tow. For this purpose, for example, it is necessary to appropriately select the pretreatment when depositing Ti, the sputtering conditions, the purity of Ti, etc. The standard varies depending on the quality of the insulating layer. In this case, if the selection is not appropriate, there will be problems such as fluctuations in sheet resistance or peeling off of Ti that should have been deposited.

Thus, in conventional TiSi, formation, the silicide is P
It is carried out under unstable conditions where it is not possible to clearly distinguish between conditions in which silicide is formed only on the surface of o1y-Si or Si and conditions in which silicide is not formed on an insulating layer such as SiO2. was.

For this reason, due to the unstable process, it is difficult to stabilize the sheet resistance of silicide interconnects within the wafer, which in turn makes it impossible to maintain a low sheet resistance value, resulting in the disadvantage that the resistance value varies. Ta.

The present invention was created in view of the problems in the prior art described above, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can stably reduce the sheet resistance of silicide wiring within a wafer.

[Means for Solving the Problems and Effects] According to one form of the present invention, the problems in the above-mentioned prior art are solved by:
A method for manufacturing a semiconductor device including a step of silicidating a polysilicon layer formed to have a contact region in a predetermined region on a semiconductor substrate with a high melting point metal using a solid phase reaction, the silicidation step Prior to this, a step of covering a portion of the polysilicon layer corresponding to the n-type semiconductor region in the contact region with a mask;
The problem is solved by providing a method for manufacturing a semiconductor device, which includes a step of implanting boron or silicon ions into the polysilicon layer covered with the mask.

According to another aspect of the present invention, a polysilicon layer formed to have a contact region in a predetermined region on a semiconductor substrate is silicided with a high melting point metal using a solid phase reaction. There is provided a method of manufacturing a semiconductor device comprising the step of implanting silicon ions into the polysilicon layer prior to the silicidation step.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the configuration of a semiconductor device as an embodiment of the present invention. In the figure, (a) shows a cross-sectional view of the main parts of a device with a complementary metal-oxide-semiconductor (hereinafter referred to as CMO3) structure, specifically, a p-channel MoS transistor Q and an n-channel MO3). Ranjistor Qn
This figure shows a state in which each drain is connected by a silicide wiring. (b) shows the equivalent circuit, and in the figure, a portion D indicated by a dashed line corresponds to the portion (a).

In FIG. 1(a), 1 is an n-type semiconductor (silicon (St) in this example) substrate (n-5OB), 2 is a p-type well (p-WELL) formed in the substrate, and 3 is a an n-type diffusion region formed in the well and corresponding to the drain of the n-channel MOS transistor Q7;
is a p-type diffusion region formed in the substrate and corresponds to the drain of the p-channel MOS transistor Q;
5 is a gate insulating layer made of 5iOz, 6 is Poly-S
A wiring layer consisting of i, 7 is titanium silicide (TiSix
) layer, 8 is an insulating layer consisting of 5i (h), 9 is a boron (B
) an insulating layer made of phosphorus glass (BPSG), 10
2A and 2B respectively show wiring layers made of AI for connecting the wiring layer 6 to the outside via the TiSix layer 7.

Next, FIGS. 2(a) to 2(a) show a manufacturing method for the device shown in FIG. 1.
This will be explained with reference to the process diagram (f).

First, in step (a), a p-type well 2 is formed in a predetermined region of an n-type semiconductor substrate 1 using a commonly known process, and then an n-type diffusion region 3, A p-type diffusion region 4 is formed. Further, after forming a Si02 layer by thermal oxidation, windows for contact with the diffusion regions 3 and 4 are opened using photolithography, and an insulating layer 5 is formed. Next, chemical vapor deposition (CVD)
) method to deposit Poly-3i over approximately 3000 deposited surfaces to form Poly-Si Jl 6.

In the next step (b), by photolithography, Poly-
A resist 20 is formed on the 3i layer, and boron (B') ions are implanted using the resist as a mask. In this case, the acceleration energy is 35keV and the dose is 3X1
0′″′/cfi!

In step (c), after removing the resist 20 by 0□ ashing, Poly-3iN is formed using photolithography.
6 is patterned into a predetermined shape to form a wiring layer 6.

The next step (d) shows a silicidation step. In this example, 1000 Ti layers are deposited by two rapid thermal annealing (PTA) processes. First, the first PTA was performed at a temperature of 675°C for 60 seconds, and then at 60°C
After immersing it in NH4OH.H,O for about one degree, a second RTA is performed at a temperature of 800° C. for 30 seconds.

In this case, it is preferable to perform PTA at a high temperature all at once in order to lower the resistance of the Ti5iX layer, but if the temperature is too high in the first PTA, it will damage areas that would otherwise be undesirable to be silicided, that is, the 5iOz layer 5. Silicide is also formed on top. In order to prevent this, in this example, PTA was performed twice. As a result, the TiSix layer 7
can be formed only on Po1y-Si@6, and the Ti5iX layer can be maintained at low resistance.

In the next step (e), 5i02 is first deposited over approximately 1000 deposited surfaces by CVD to form an insulating layer 8. Then melted BPSG (8% boron; 5% phosphorus)
%) over approximately 6,000 deposits,
It is melted under conditions of a temperature of 900°C and a time of 15 minutes. As a result, the insulating layer 9 is formed into a flat shape.

In the final step Cf>, a window for contact with the TiSi layer 7 is opened using photolithography, and after AI is deposited over the entire surface, it is patterned into a predetermined shape to form the wiring layer 10. After this, Lingaras (
PSG) is deposited to an appropriate thickness to form a passivation film (not shown in Figures 1 and 2).
.

FIGS. 3(a) to 3(d) show other manufacturing steps for the apparatus shown in FIG.

The manufacturing process shown in Figure 3 differs from the manufacturing process shown in Figure 2 in that in step (b) of Figure 3, Si'' ions are implanted over the entire surface without using a resist. It is. In the process shown in FIG. 2, when B' is introduced into the n-type diffusion region 3, a contact failure occurs with the Poly-St layer 6. To avoid this, B' is introduced into the n-type diffusion region 3.
4 prior to the implantation of Po1y-S corresponding to the n-type region.
It was necessary to cover the tN portion with the resist 20, but according to the process shown in FIG. 3, even if St'' is introduced into the n-type diffusion region 3, the contact failure as described above will not occur.
There is no need to cover the corresponding part with resist. Therefore, the manufacturing process is simplified to the extent that the masking process can be omitted.

However, it goes without saying that St+ ion implantation may be performed while covered with resist (the state shown in FIG. 2(b)).

The other steps are the same as those in FIG. 2, that is, the step in FIG. 3(a) corresponds to the step in FIG. 2(a), and the steps in FIG. 3(c) and (d). are shown in Figure 2(c)-(
Since this corresponds to step f), its explanation will be omitted.

Figure 4 shows a method for measuring the sheet resistance of silicide wiring. In the figure, 41 is a constant current source, 42 is a voltmeter, and the hunting part is a pattern of the Po1y-Si layer to be measured when viewed from above. represents. This pattern represents, in one form, the TiSix layer 7 shown in FIG. 2(d). The size of the pattern to be measured is 100
μm x 10 μm, and the measurement conditions were as follows: After ion implantation into the Poly-St layer as illustrated, and TiSi formation, a constant current was supplied from the constant current source 41. The sheet resistance is measured by measuring the potential difference with a voltmeter 42. An example of data measured in this manner is shown in FIG.

In Fig. 5, (Case 1) When B+ is ion-implanted with an acceleration energy of 35 keν and a dose of 13 x 1014/cXli, the measured value is 21Ω, and the sheet resistance is 2.1Ω/unit. (Case 2) Acceleration of B Energy 35keV, dose 13
The measured value when ion implanted with Xl01S/c+4 is 1
5Ω, sheet resistance is 1.5Ω/mouth, (Case 3) As
+ acceleration energy 35 keV, dose 3XIQ”
The measured value when ions were implanted at /cal was 48Ω, and the sheet resistance was 4.8Ω/mouth. (Case 4) When ions were implanted at P゛ acceleration energy of 35keV and dose of 3XIQ”/cJ, the measured value was 37Ω. So, the sheet resistance is 3.7Ω
/ (Case 5) The measured value without impurity doping is 36Ω, and the sheet resistance is 3.6Ω / (Case 6) Si” is accelerated with an energy of 35 keV and a dose of 3.
The measured value when ions were implanted at X10''/cj was 23Ω, and the sheet resistance was 2.3Ω/hole.

Here, case 2 corresponds to the sheet resistance of the TiSix layer formed based on the process shown in FIG.
This corresponds to the sheet resistance of the Ti5iX layer formed based on the process shown in the figure. As shown in FIG. 5, the sheet resistance can be reduced by implanting B' or St' compared to the case where ion implantation is not performed or the case where As' or P' is implanted.

〔Effect of the invention〕

As explained above, according to the method of manufacturing a semiconductor device of the present invention, the sheet resistance of silicide wiring can be stably reduced within the wafer.

[Brief explanation of the drawing]

1(a) and Cb> are diagrams showing the configuration of a semiconductor device as an embodiment of the present invention, in which (a) is a sectional view, (b) is an equivalent circuit diagram, and FIG. 2(a) - (f) are process diagrams showing one method of manufacturing the device shown in Figure 1, Figures 3 (a) to (d) are process diagrams showing another method of manufacturing the device shown in Figure 1, and Figure 4 is a process diagram showing the sheet resistance. FIG. 5 is a diagram for explaining the measurement method. FIG. 5 is a diagram showing the relationship of sheet resistance for each ion species actually measured based on the measurement method of FIG. 4. (Explanation of symbols) 1... Semiconductor substrate, 3... N-type semiconductor region (diffusion region), 6... Polysilicon (Poly-St) layer, 7... Titanium silicide (TiSi, ) layer, 20...Mask (resist)
. Cross-sectional view (Q) Equivalent circuit diagram (b) Diagrams 1 and 3 showing the configuration of a semiconductor device as an embodiment of the present invention. Type diffusion region 8...Insulating layer (SiO□
) (a) (b) (C) Figure 1: One of the manufacturing steps of the device (d) (e) Process diagram showing the method Si'' () 1111.ILL (b) Figure 1: Other manufacturing step of the device (C) (d) 3 process diagrams showing the folding method

Claims (1)

[Claims] 1. A polysilicon layer (6) formed to have a contact region in a predetermined region on a semiconductor substrate (1).
In a method for manufacturing a semiconductor device including a step of performing silicidation (7) with a high melting point metal using a solid phase reaction, prior to the silicidation step, a portion of the contact region corresponding to the n-type semiconductor region (3) is formed. manufacturing a semiconductor device comprising the steps of: covering a portion of a polysilicon layer with a mask (20); and implanting boron or silicon ions into the polysilicon layer covered with the mask. Method. 2. A polysilicon layer (6) formed to have a contact region in a predetermined region on the semiconductor substrate (1)
A method for manufacturing a semiconductor device including a step of performing silicidation (7) with a high-melting point metal using a solid phase reaction, the step of implanting silicon ions into the polysilicon layer prior to the silicidation step. A method of manufacturing a semiconductor device, comprising: