JPH10233371A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of stable electrode parts contacting a semiconductor substrate without reaction with silicon of the substrate, even in the course of and after growth of a metallic film to be formed on the electrode parts by a selective metal technique. SOLUTION: A cobalt(Co) film is formed on an entire surface of a silicon substrate 1 by a sputtering process. After formation of the cobalt film, the substrate is subjected, e.g. to a lamp annealing profess at 550 deg.C for 30 seconds to cause cobalt(Co) to react with silicon(Si) in source and drain regions 19a and 19b and in a gate electrode 14a respectively. This causes low-resistance cobalt silicide(CoSi2 ) films 21a, 21b and 21c to be selectively formed only on the source and drain regions 19a and 19b and on the gate electrode 14a. Subsequently tungsten(W) films 22a, 22b and 22c are formed by a selective tungsten CVD technique only on the cobalt silicide films 21a, 21b and 21c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a refractory metal silicide layer, and more particularly to a MOS (Metal Ox
The present invention relates to a method for manufacturing a semiconductor device applied to forming an electrode portion such as an ide semiconductor type semiconductor device.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have been miniaturized in accordance with the so-called scaling law in semiconductor manufacturing, the gate length of a transistor has become shorter and the resistance during driving has been decreasing year by year. However, a parasitic resistance such as an increase in contact resistance due to a reduction in the contact diameter of a MOS transistor and a shallow junction of a diffusion layer (a source region and a drain region) are rather increased. Due to this parasitic resistance, the current driving capability of the MOS transistor is reduced. That is, there is a problem that the response speed of the MOS transistor is deteriorated. Accordingly, a self-aligned silicide (salicide) technique has been proposed as a measure to reduce the parasitic resistance. In this self-aligned silicide technique, a high-melting metal is deposited on a semiconductor substrate, and the high-melting metal reacts with the semiconductor in the electrode portion (source region and drain region). A low-resistance metal silicide is formed only on the portion. In addition, selective metal CVD (Chem) for selectively growing a metal only on these electrode portions.
ical Vapor Deposition (chemical vapor deposition) technology is also attracting attention.

Here, referring to FIGS. 5 (a) to 5 (c),
MOS LSI with a conventional salicide structure (Large Sc
ale Integrated circuit) An example of the process will be described.

In this process, first, as shown in FIG. 5A, for example, a LOCOS (Local
Oxidation of Silicon) method for thick device isolation film (SiO ₂ )
A gate electrode 114 made of a polycrystalline silicon film is formed in a region surrounded by the element isolation film 112 via a gate insulating film (SiO ₂ ) 113. Subsequently, after an oxide film (SiO ₂ ) is formed on the entire surface of the silicon substrate 111 by, for example, the CVD method, a gate side wall (side wall) 115 is formed on the side surface of the gate electrode 114 by dry etching (etch back). I do. continue,
Using the element isolation film 112 and the gate electrode 114 as a mask, an impurity of the opposite conductivity type to the substrate is introduced into the silicon substrate 111, and the source region 116 and the drain region 117 are formed in a self-aligned manner, thereby forming a MOS transistor. .

Next, as shown in FIG. 5B, an etching process using hydrogen fluoride (HF) is performed to
After completely removing the native oxide film on each of the gate region 16 and the drain region 117, a titanium (Ti) film is formed on the entire surface by, for example, a sputtering method. After that, heat treatment is performed so that the source region 116 and the drain region 1 are formed.
By reacting silicon (Si) and titanium (Ti) in 17, a low-resistance silicide (TiSi ₂ ) film 118 is selectively formed on each of the source region 116 and the drain region 117. After that, titanium (Ti) on the element isolation film 112 is selectively removed by immersion in an etching solution such as ammonia peroxide.

Next, as shown in FIG. 5C, an interlayer insulating film 119 such as an oxide film (SiO ₂ ) is formed by, for example, a CVD method, and the drain region 11 of the interlayer insulating film 119 is formed.
A connection hole (contact hole) 120 reaching the silicide film 118 is formed in a region opposed to. Further, a laminated film (TiN / Ti) 121 composed of a thin titanium nitride (TiN) film and a titanium (Ti) film is selectively formed on the inner wall and the bottom of the connection hole 120 (that is, the surface of the silicide film 118). After that, the inside of the connection hole 120 is tungsten (W).
The layer 122 is embedded. Subsequently, a titanium (Ti) film 123 is formed on the silicon substrate 111 including the connection hole 120, and an aluminum alloy such as aluminum (Al) including silicon (Si) is formed on the titanium film 123, By patterning, a wiring layer 124 electrically connected to the tungsten (W) layer 122 is formed.

In this way, a MOS transistor having a silicide film 118 as an electrode on the source region 116 and the drain region 117 can be formed in a self-aligned manner. Thereby, the shallow source region 11 is formed.
6 and the drain resistance in the drain region 117 can be reduced by about one digit as compared with the conventional MOS transistor having no silicide film.

[0008]

However, according to the recent technology, in order to suppress the short channel effect with the advance of the integration degree of the semiconductor integrated circuit, the junction of the electrode portion (source region and drain region) of the MOS transistor is reduced. Need to be shallower. However, in the self-aligned silicide technology, as the junction between the source region and the drain region becomes shallower, the refractory metal silicide layer formed on the surface layer of each of the source region and the drain region penetrates the semiconductor substrate, and the refractory metal Leakage current between the silicide layer and the semiconductor substrate increases. In order to prevent this leakage current, a thin silicide film must be formed. That is, there is a problem that the sheet resistance of the refractory metal silicide layer increases with the progress of integration.
Further, the selective metal CVD technique has a characteristic of consuming silicon crystals in a silicon substrate during an initial growth process of a metal film, and has a problem that a junction between a source region and a drain region is easily broken. Furthermore, the grown metal film,
For example, when a high temperature is applied to a tungsten (W) film, a silicon crystal is absorbed and a junction between a source region and a drain region is destroyed, so that there is a problem that a manufacturing process after the growth of the tungsten (W) layer is greatly restricted. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device in which a metal film formed on an electrode portion by using a selective metal technique comes into contact with a semiconductor substrate even during a growth process and after the growth. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a stable electrode portion without reacting with silicon constituting a substrate.

According to the present invention, a plurality of electrode portions can be simultaneously silicided even if the device is miniaturized.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing parasitic resistance at a junction of a shallow electrode portion and expanding a process margin for forming a contact.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a refractory metal silicide film in a self-aligned manner only in a region where an electrode is to be formed on a semiconductor substrate formed of a silicon material; Forming a metal film by selectively growing a metal only on the refractory metal silicide film.

According to another method of manufacturing a semiconductor device according to the present invention, an element isolation film is formed on a semiconductor substrate formed of a silicon material and a polycrystalline silicon film is formed in a region surrounded by the element isolation film. Forming a first insulating film on the polycrystalline silicon film together with the polycrystalline silicon film and the first insulating film, forming the polycrystalline silicon film and the first insulating film into an electrode shape; Forming a side wall made of a second insulating film around the side surface of the insulating film; forming the side wall; forming an etching protection film on the entire surface of the semiconductor substrate; and protecting the etching protection film from the upper surface by etching. Selectively removing the film so that the film covers at least the element isolation film and exposing at least the first insulating film; and exposing the polycrystalline silicon film by etching the first insulating film. Forming a polycrystalline silicon electrode and an impurity layer by introducing impurities into the polycrystalline silicon film and the semiconductor substrate using the side walls and the element isolation film as a mask after removing the etching protection film. Forming a polycrystalline silicon electrode and an impurity layer, and then depositing a refractory metal over the entire surface of the semiconductor substrate and performing a heat treatment to selectively form a silicide film on the polycrystalline silicon electrode and the impurity layer, respectively. And a step of selectively forming a metal film on each of the plurality of silicide films.

In the method of manufacturing a semiconductor device according to the present invention,
A refractory metal silicide film is formed in a self-aligned manner only in a region where an electrode is to be formed on a semiconductor substrate (silicon substrate), and a metal is grown only on the refractory metal silicide film to form a metal film. Thus, the metal film does not come into contact with the semiconductor substrate even during the growth process and after the growth, and does not react with silicon constituting the semiconductor substrate.

In another method for manufacturing a semiconductor device according to the present invention, in the step of exposing the polycrystalline silicon film by etching the first insulating film, the element isolation film is covered with the etching protection film. The element isolation film is not etched together with the first insulating film, and the polycrystalline silicon electrode (gate electrode) and the impurity layer region (source / drain region) are simultaneously silicided. Thereafter, a metal is grown only on these silicide films to form a metal film. Thereby, the metal film does not come into contact with the semiconductor substrate even during the growth process and after the growth, and does not react with silicon constituting the semiconductor substrate.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

1 to 4 show a method of manufacturing a MOS transistor having a salicide structure according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 1 (a), for example, on a P-type silicon substrate 11, for example a thick isolation layer using a LOCOS method after forming a (SiO ₂₎ 12, the element isolation film (SiO ₂ ) Impurity implantation for forming a well region and the like is performed on the silicon substrate 11 using the mask 12 as a mask. Then, gate oxidation is performed by thermal oxidation on a region surrounded by the element isolation film (SiO ₂ ) 12 to form a gate insulating film (SiO ₂ ) 13 having a thickness of, for example, 5 nm.
Subsequently, after a polycrystalline silicon film 14 having a thickness of, for example, 200 nm is formed on the gate insulating film (SiO ₂ ) 13 serving as a first insulating film by, for example, the CVD method, the silicon film having a thickness of, for example, 150 nm is formed by the same CVD method. An oxide film 15 is formed. Here, the silicon oxide film 15 is appropriately doped with an impurity such as phosphorus in order to change the etching rate. Thereafter, a resist film (not shown) having a gate pattern is formed by using a photolithography technique, and the silicon oxide film 15 and the polycrystalline silicon film 14 are sequentially etched by anisotropic etching using the resist film as a mask.

Next, as shown in FIG. 1B, ion implantation (LDD implantation) of impurities for the extension electrodes of the source electrode and the drain electrode is performed using the element isolation film 12 and the silicon oxide film 15 as a mask. LDD (Lightly Doped D
rain) Regions 13a and 13b are formed. Subsequently, a silicon oxide film 16 having a thickness of 20 nm and a silicon nitride film 17 having a thickness of 150 nm to be a second insulating film are formed by, for example, a CVD method. Next, FIG.
As shown in FIG. 7, the silicon oxide film 16 and the silicon nitride film 17 are anisotropically etched to form the polycrystalline silicon film 1.
Etching is performed leaving only the side surface portion of No. 4 to form a wide gate side wall (side wall) 17a.

Next, as shown in FIG. 2A, a resist film 18 having a thickness of, for example, 500 nm is formed as an etching protection film, and thereafter, as shown in FIG. By, for example, 300 n by anisotropic etching.
Etching is performed to expose the upper portion of the gate side wall 17a. Further, as shown in FIG.
The anisotropic etching is performed under such a condition that the etching rate of the silicon oxide film 15 doped with phosphorus is, for example, 30 times as large as that of a. Further, the silicon oxide film 15 on the polycrystalline silicon film 14 is etched by a dilute hydrofluoric acid solution.
Is removed. The etching with the diluted hydrofluoric acid solution is performed, for example, with a solution of water: hydrofluoric acid = 10: 1 for 60 seconds.

Next, after removing the resist film 18, FIG.
As shown in FIG. 3A, the source region 19a and the drain region 19b are formed by performing ion implantation of an N-type impurity, for example, phosphorus (P) using the gate side wall 17a and the element isolation film 12 as a mask. The silicon film 14 is doped with impurities to form a gate electrode 14a. Subsequently, heat treatment (annealing) is performed for a short time, for example, at 1000 ° C. to activate the impurities introduced by the implantation.
Is performed for 10 seconds.

Next, as shown in FIG. 3B, after the natural oxide film on each of the source region 19a and the drain region 19b is completely removed, a high melting point is formed on the entire surface of the silicon substrate 11 by, for example, a sputtering method. A metal film, for example, a cobalt (Co) film 20 having a thickness of 20 nm is formed. After the formation of the cobalt film 20, for example, lamp annealing at 550 ° C. is performed for 30 seconds to react silicon (Si) and cobalt (Co) in the source region 19a, the drain region 19b, and the gate electrode 14a. Thereby, the source region 19a and the drain region 1
9b and a low-resistance cobalt silicide (CoSi ₂ ) film 21a, 21b, 2 only on respective regions of the gate electrode 14a.
1c is selectively formed. Further, as shown in FIG. 3C, unreacted cobalt (Co) on a region other than the source region 19a, the drain region 19b and the gate electrode 14a is formed by a wet etching method using sulfuric acid and hydrogen peroxide. The film 20 is selectively removed.

Subsequently, as shown in FIG. 4, for example, a cobalt silicide film 2 is formed by selective tungsten CVD technique.
Tungsten (W) films 22a, 22b, 22c having a thickness of 100 nm are formed only on 1a, 21b, 21c. Thereafter, although not shown, the interlayer insulating film (S
iO ₂ ) is formed, and anisotropic etching is performed under the condition that the etching rate of the interlayer insulating film is, for example, 30 times as large as that of the gate side wall 17a, thereby forming the source region 19a and the drain region of the interlayer insulating film. A connection hole (contact hole) reaching the tungsten films 22a and 22b is formed in a region opposed to 19b. Further, selectively thin titanium nitride (TiN) is formed on the inner wall and the bottom of the connection hole (that is, the surfaces of the tungsten films 22a and 22b).
) Film and titanium (Ti) film (TiN / Ti)
Is formed, and then the connection holes are filled with a tungsten (W) layer. Subsequently, a titanium (Ti) film is formed on the silicon substrate 11 including the connection holes, and a silicon (S) film is further formed on the titanium film.
A wiring layer electrically connected to the tungsten (W) layer is formed by depositing and patterning an aluminum-based alloy such as aluminum (Al) containing i).

As described above, in the present embodiment, thick cobalt silicide films 21a, 21b, 21c are collectively formed on the source region 19a, the drain region 19b, and the gate electrode 14a.
Tungsten films 22a, 22 only on a, 21b, 21c
b, 22c are grown, the tungsten film 22
The a, 22b, and 22c do not directly contact the silicon substrate 11, do not react with the silicon substrate 11 in the initial growth process, do not consume silicon by a reduction reaction, and do not break the junction of the electrode portion. Also, in the heat treatment after the growth of the tungsten films 22a, 22b and 22c, the tungsten films 22a, 22b and 22c and the silicon substrate 11 are not in direct contact with each other.
2a, 22b, and 22c do not absorb the silicon of the silicon substrate 11 and break the junction of the electrode portions.

Further, in the present embodiment, in addition to the above effects, as described in the steps of FIGS. 2B and 2C, the insulating film (silicon oxide film 15) on the polycrystalline silicon film 14 At the time of etching, a gate side wall 17a is formed by a silicon nitride film 17 having a different etching rate, and a resist film 18 is coated and formed on the entire surface as an etching protection film, and then anisotropic etching is performed until the silicon oxide film 15 is exposed. After that, the insulating film (silicon oxide film 15) on the polycrystalline silicon film 14 is selectively removed. Therefore, when the insulating film on the polycrystalline silicon film 14 is removed, even the element isolation film 12 is removed. It will not be etched. Therefore, the source regions 19a,
Thick cobalt silicide films 21a, 21b, and 21c can be collectively formed on the drain region 19b and the gate electrode 14a, respectively, and a high-performance MOS transistor with small parasitic resistance can be formed. Further, since the process margin for forming the contact hole is increased, the yield rate is also improved.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and can be variously modified within an equivalent range. For example, a method other than a sputtering method, for example, a CVD method may be used as a method for forming a film of a high melting point metal.

In the above embodiment, the structure and the manufacturing process of the MOS transistor have been described.
The present invention can be applied to devices other than the S device (bipolar transistor, CCD (Charge Coupled Device), etc.). Further, in the above embodiment, cobalt (Co) is used as the refractory metal to be a silicide film, but other refractory metals such as titanium (Ti), nickel (Ni), molybdenum (Mo), and platinum are used. (Pt) or the like may be used. Since the reaction temperature for silicidation of any of these metals is in the range of 400 ° C. to 900 ° C., a silicidation step which is well compatible with other semiconductor manufacturing steps can be performed.

[0026]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a refractory metal silicide film is formed in a self-aligned manner only in a region where an electrode is to be formed on a semiconductor substrate (silicon substrate). Since the metal film is formed only by growing the metal on the refractory metal silicide film, the metal film does not come into direct contact with the semiconductor substrate. It does not react with the silicon of the substrate. Therefore, consumption of silicon of the semiconductor substrate can be reduced, and breakage of the junction of the electrode portion can be prevented.

Further, according to the method of manufacturing a semiconductor device of the present invention, in the step of exposing the polycrystalline silicon film by etching the first insulating film, the element isolation film is covered with the etching protection film. After the element isolation film is prevented from being etched together with the first insulating film and the polycrystalline silicon electrode (gate electrode) and the impurity layer region (source / drain region) are collectively silicided, these silicide films are formed. Since a metal film is formed by growing a metal only on the metal layer, it is possible to suppress the reaction between the metal and silicon in the electrode portion on the impurity layer,
Simultaneous silicidation of a plurality of electrode parts can improve the performance by reducing the parasitic resistance at the junction of the shallow electrode parts, and the yield rate can be improved by stabilizing the manufacturing process of the electrode part formation. To play.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process of a MOS transistor having a salicide structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing step following FIG. 1;

FIG. 3 is a cross-sectional view for explaining a manufacturing step following FIG. 2;

FIG. 4 is a cross-sectional view for explaining a manufacturing step following FIG. 3;

FIG. 5 is a cross-sectional view for explaining a manufacturing process of a MOS transistor having a conventional salicide structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12 ... Element isolation film, 13 ... Gate insulating film, 13a, 13b ... LDD area, 14 ... Polycrystalline silicon film, 14a ... Gate electrode, 15, 16 ... Silicon oxide film, 17 ... Silicon nitride film, 18 ... resist film, 1
9a: source region, 19b: drain region, 20: cobalt film, 21a, 21b, 21c: cobalt silicide film, 22a, 22b, 22c: tungsten film

Claims (6)

[Claims] A step of forming a refractory metal silicide film in a self-aligned manner only in a region where an electrode is to be formed on a semiconductor substrate formed of a silicon material; and selectively growing a metal only on the refractory metal silicide film. Forming a metal film by performing the method. 2. An element isolation film is formed on a semiconductor substrate formed of a silicon material, a polycrystalline silicon film is formed in a region surrounded by the element isolation film, and a first film is formed on the polycrystalline silicon film. Forming the insulating film, and processing the polycrystalline silicon film and the first insulating film into an electrode shape; and forming the polycrystalline silicon film and the first insulating film into the electrode shape.
Forming a side wall made of a second insulating film around the side surface of the insulating film; and, after forming the side wall, forming an etching protection film on the entire surface of the semiconductor substrate. A step of selectively removing the etching protection film at least so as to cover the device isolation film and at least exposing the first insulating film; and etching the first insulating film to remove the polycrystalline silicon film. And exposing the polysilicon electrode and the impurity layer by introducing impurities into the polycrystalline silicon film and the semiconductor substrate using the side walls and the element isolation film as masks after removing the etching protection film. Forming a polycrystalline silicon electrode and an impurity layer, and then depositing a refractory metal on the entire surface of the semiconductor substrate. A step of selectively forming a silicide film on each of the polycrystalline silicon electrode and the impurity layer by performing a heat treatment; and a step of selectively forming a metal film on each of the plurality of silicide films. A method for manufacturing a semiconductor device, comprising: 3. The refractory metal silicide film is formed by using any one of titanium (Ti), cobalt (Co), molybdenum (Mo), nickel (Ni) and platinum (Pt). The method for manufacturing a semiconductor device according to claim 1. 4. The method according to claim 1, wherein the metal film is formed using tungsten (W). 5. The method according to claim 2, wherein the first insulating film is formed of an insulating material having a higher etching rate than the second insulating film. 6. The method according to claim 5, wherein the first insulating film is a silicon oxide film to which a predetermined concentration of phosphorus ions is added or not, and the second insulating film is a silicon nitride film. A method for manufacturing a semiconductor device.